source/src/vm/fmr50/scsi.cpp

   1 /*
   2         FUJITSU FMR-50 Emulator 'eFMR-50'
   3         FUJITSU FMR-60 Emulator 'eFMR-60'
   4
   5         Author : Takeda.Toshiya
   6         Date   : 2008.05.02 -
   7
   8         [ scsi ]
   9 */
  10
  11 #include "scsi.h"
  12 #include "../../fileio.h"
  13
  14 // phase
  15 #define PHASE_BUSFREE           0
  16 #define PHASE_ARBITRATION       1
  17 #define PHASE_SELECTION         2
  18 #define PHASE_RESELECTION       3
  19 #define PHASE_COMMAND           4
  20 #define PHASE_EXECUTE           5
  21 #define PHASE_MSG_IN            6
  22 #define PHASE_MSG_OUT           7
  23 #define PHASE_DATA_IN           8
  24 #define PHASE_DATA_OUT          9
  25 #define PHASE_STATUS            10
  26
  27 // control register
  28 #define CTRL_WEN        0x80
  29 #define CTRL_IMSK       0x40
  30 #define CTRL_ATN        0x10
  31 #define CTRL_SEL        0x04
  32 #define CTRL_DMAE       0x02
  33 #define CTRL_RST        0x01
  34
  35 // status register
  36 #define STAT_REQ        0x80
  37 #define STAT_IO         0x40
  38 #define STAT_MSG        0x20
  39 #define STAT_CD         0x10
  40 #define STAT_BUSY       0x08
  41 #define STAT_INT        0x02
  42 #define STAT_PERR       0x01
  43
  44 // DMA: SIG_UPD71071_CH1
  45 // IRQ: SIG_I8259_CHIP1 | SIG_I8259_IR0
  46
  47 void SCSI::initialize()
  48 {
  49         phase = PHASE_BUSFREE;
  50         ctrlreg = datareg = statreg = 0;
  51 }
  52
  53 void SCSI::write_io8(uint32 addr, uint32 data)
  54 {
  55         switch(addr & 0xffff) {
  56         case 0xc30:
  57                 // data register
  58                 datareg = data;
  59                 break;
  60         case 0xc32:
  61                 // control register
  62                 if((ctrlreg & CTRL_RST) && ~(data & CTRL_RST)) {
  63                         // reset
  64                         statreg = 0;
  65                 }
  66                 if(~(ctrlreg & CTRL_SEL) && (data & CTRL_SEL)) {
  67                         // sel
  68 //                      statreg |= 8;
  69 //                      datareg = 0x80;
  70                 }
  71                 ctrlreg = data;
  72                 break;
  73         }
  74 }
  75
  76 uint32 SCSI::read_io8(uint32 addr)
  77 {
  78 //      uint32 val;
  79
  80         switch(addr & 0xffff) {
  81         case 0xc30:
  82                 // data register
  83                 return 0;
  84         case 0xc32:
  85                 // status register
  86                 return 0;
  87 //              val = statreg;
  88 //              statreg &= ~8;
  89 //              return val;
  90         }
  91         return 0xff;
  92 }
  93
  94 void SCSI::write_dma_io8(uint32 addr, uint32 data)
  95 {
  96         write_io8(0xc30, data);
  97 }
  98
  99 uint32 SCSI::read_dma_io8(uint32 addr)
 100 {
 101         return read_io8(0xc30);
 102 }
 103