2 Skelton for retropc emulator
4 Author : Kyuma Ohta <whatisthis.sowhat _at_ gmail.com>
8 History: 2016.12.28 Initial.
11 #ifndef _TOWNS_VRAM_H_
12 #define _TOWNS_VRAM_H_
19 #define TOWNS_VRAM_ADDR_MASK 0x7ffff
20 // VRAM DIRECT ACCESS: For Sprite. You should access with 16bit
21 // You can write raw data, drawing with colorkey is automatically.
22 #define SIG_TOWNS_TRANSFER_SPRITE_DATA 0x100000
23 #define SIG_TOWNS_SET_SPRITE_BANK 0x140000
24 #define SIG_TOWNS_CLEAR_SPRITE_BUFFER 0x140001
25 // Do render with any mode. You should set vline to arg.
26 #define SIG_TOWNS_RENDER_RASTER 0x01
27 #define SIG_TOWNS_RENDER_FULL 0x02
28 #define SIG_TOWNS_VRAM_VSTART 0x03
29 #define SIG_TOWNS_VRAM_VBLANK 0x04
30 #define SIG_TOWNS_VRAM_VSYNC 0x05
31 #define SIG_TOWNS_VRAM_HSYNC 0x06
32 #define SIG_TOWNS_VRAM_SET_VLINE 0x07
33 #define SIG_TOWNS_RENDER_FLAG 0x08
35 class TOWNS_VRAM : public DEVICE
38 uint32_t page_modes[4];
39 bool line_rendered[2][TOWNS_CRTC_MAX_LINES];
41 scrntype_t *framebuffer0[2]; // Frame Buffer Layer 0. Not saved.
42 scrntype_t *framebuffer1[2]; // Frame Buffer Layer 1. Not saved.
44 int framebuffer_width[2];
45 int framebuffer_height[2];
47 uint16_t *vram_ptr[2]; // Layer [01] address.
48 uint32_t vram_size[2]; // Layer [01] size [bytes].
49 uint32_t vram_offset[2]; // Layer [01] address offset.
51 scrntype_t table_32768c[65536];
53 uint32_t layer_virtual_width[2];
54 uint32_t layer_virtual_height[2];
55 uint32_t layer_display_width[2];
56 uint32_t layer_display_height[2];
59 uint32_t write_plane_mask; // for plane-access.
60 uint8_t packed_access_mask_lo;
61 uint8_t packed_access_mask_hi;
64 uint8_t vram[0x80000]; // Related by machine.
65 // FMR50 Compatible registers. They are mostly dummy.
66 // Digital paletts. I/O FD98H - FD9FH.
67 uint8_t r50_digital_palette[8];
68 bool layer_display_flags[2]; // I/O FDA0H (WO) : bit3-2 (Layer1) or bit1-0 (Layer0).Not 0 is true.
70 bool r50_dpalette_updated; // I/O 044CH (RO) : bit7
72 bool sprite_busy; // I/O 044CH (RO) : bit1. Must update from write_signal().
73 bool splite_disp_page; // I/O 044CH (RO) : bit0. Must update from write_signal().
75 // Around Analog palette.
76 uint8_t apalette_code; // I/O FD90H (RW). 16 or 256 colors.
77 uint8_t apalette_b; // I/O FD92H (RW).
78 uint8_t apalette_r; // I/O FD94H (RW).
79 uint8_t apalette_g; // I/O FD96H (RW).
80 uint16_t apalette_16_rgb[2][16]; // R * 256 + G * 16 + B
81 scrntype_t apalette_16_pixel[2][16]; // Not saved. Must be calculated.
82 uint32_t apalette_256_rgb[256]; // R * 65536 + G * 256 + B
83 scrntype_t apalette_256_pixel[256]; // Not saved. Must be calculated.
84 // Accessing VRAM. Will be separated.
85 // Memory description:
86 // All of accessing must be little endian.
87 // 000C:00000 - 000C:07fff : Plane accessing window(->FM-R50 features?). Access to Layer #0 (8000:00000).
88 // 000C:08000 - 000C:0ffff : I/O CVRAM
89 // 000D:00000 - 000E:0ffff : Reserved (Window for KANJI, DIC etc).
90 // 8000:00000 - 8000:3ffff : Plane accessing Layer #0.
91 // 8000:40000 - 8000:7ffff : Plane accessing Layer #1.
92 // 8010:00000 - 8010:7ffff : Plane accessing with one layer.
93 // 8100:00000 - 8100:1ffff : Sprite (and text vram).
94 // I/O 0458H (RW) : VRAM ACCESS CONTROLLER reg address.
95 // I/O 045AH (RW) : VRAM ACCESS CONTROLLER reg data (LOW).
96 // I/O 045BH (RW) : VRAM ACCESS CONTROLLER reg data (HIGH).
97 pair_t packed_pixel_mask_reg; // '1' = Write. I/O 0458H - 045BH.
100 uint32_t layer_offset[4];
101 uint8_t text_vram[4096]; // 4096bytes
102 uint8_t kanji_vram[4096]; // 4096bytes
105 // Flags related by host renderer. Not saved.
106 bool has_hardware_rendering;
107 bool has_hardware_blending;
110 TOWNS_VRAM(VM* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)
112 memset(vram, 0x00, sizeof(vram));
113 render_buffer = NULL;
114 page_modes[0] = page_modes[1] = page_modes[2] = page_modes[3] = 0;
115 packed_access_mask_hi = packed_access_mask_lo = 0xff;
116 write_plane_mask = 0xffffffff;
120 uint32_t read_data8(uint32_t addr);
121 uint32_t read_data16(uint32_t addr);
122 uint32_t read_data32(uint32_t addr);
123 void write_data8(uint32_t addr, uint32_t data);
124 void write_data16(uint32_t addr, uint32_t data);
125 void write_data32(uint32_t addr, uint32_t data);
127 uint32_t read_io8(uint32_t addr);
128 void write_io8(uint32_t addr, uint32_t data);
130 void write_signal(int id, uint32_t data, uint32_t mask); // Do render
133 uint32_t read_plane_data8(uint32_t addr);
134 uint32_t read_plane_data16(uint32_t addr);
135 uint32_t read_plane_data32(uint32_t addr);
137 void write_plane_data8(uint32_t addr, uint32_t data);
138 void write_plane_data16(uint32_t addr, uint32_t data);
139 void write_plane_data32(uint32_t addr, uint32_t data);
141 void set_frame_buffer(int layer, bool buffer1, scrntype_t *framebuffer, int width, int height);
142 scrntype_t *get_frame_buffer_ptr(int layer);
143 int get_frame_buffer_width(int layer);
144 int get_frame_buffer_height(int layer);
145 bool is_display(int layer);
146 bool is_updated(int layer, int line_num);
147 void lock_frame_buffer(int layer);
148 void unlock_frame_buffer(int layer);
149 void set_render_features(bool blending_from_buffer, bool rendering_framebuffer);
152 void set_context_renderbuffer(scrntype_t *p, uint32_t size){