source/src/vm/huc6280_base.cpp

   1 /*
   2         Skelton for retropc emulator
   3
   4         Origin : MESS 0.147
   5         Author : Takeda.Toshiya
   6         Date   : 2012.10.23-
   7
   8         [ HuC6280 ]
   9 */
  10
  11 #include "huc6280.h"
  12 //#ifdef USE_DEBUGGER
  13 #include "debugger.h"
  14 //#endif
  15
  16 /* ----------------------------------------------------------------------------
  17         MAME h6280
  18 ---------------------------------------------------------------------------- */
  19
  20 #define INLINE inline
  21 #define PAIR pair_t
  22 #define offs_t UINT16
  23
  24 /*****************************************************************************/
  25 /* src/emu/devcpu.h */
  26
  27 // CPU interface functions
  28 #define CPU_INIT_NAME(name)                     cpu_init_##name
  29 #define CPU_INIT(name)                          void* CPU_INIT_NAME(name)()
  30 #define CPU_INIT_CALL(name)                     CPU_INIT_NAME(name)()
  31
  32 #define CPU_RESET_NAME(name)                    cpu_reset_##name
  33 #define CPU_RESET(name)                         void CPU_RESET_NAME(name)(h6280_Regs *cpustate)
  34 #define CPU_RESET_CALL(name)                    CPU_RESET_NAME(name)(cpustate)
  35
  36 #define CPU_EXECUTE_NAME(name)                  cpu_execute_##name
  37 #define CPU_EXECUTE(name)                       int CPU_EXECUTE_NAME(name)(h6280_Regs *cpustate)
  38 #define CPU_EXECUTE_CALL(name)                  CPU_EXECUTE_NAME(name)(cpustate)
  39
  40 #define CPU_DISASSEMBLE_NAME(name)              cpu_disassemble_##name
  41 #define CPU_DISASSEMBLE(name)                   int CPU_DISASSEMBLE_NAME(name)(_TCHAR *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, symbol_t *first_symbol)
  42 #define CPU_DISASSEMBLE_CALL(name)              CPU_DISASSEMBLE_NAME(name)(buffer, pc, oprom, oprom, d_debugger->first_symbol)
  43
  44 #define READ8_HANDLER(name)                     UINT8 name(h6280_Regs *cpustate, offs_t offset)
  45 #define WRITE8_HANDLER(name)                    void name(h6280_Regs *cpustate, offs_t offset, UINT8 data)
  46
  47 /*****************************************************************************/
  48 /* src/emu/didisasm.h */
  49
  50 // Disassembler constants
  51 const UINT32 DASMFLAG_SUPPORTED     = 0x80000000;   // are disassembly flags supported?
  52 const UINT32 DASMFLAG_STEP_OUT      = 0x40000000;   // this instruction should be the end of a step out sequence
  53 const UINT32 DASMFLAG_STEP_OVER     = 0x20000000;   // this instruction should be stepped over by setting a breakpoint afterwards
  54 const UINT32 DASMFLAG_OVERINSTMASK  = 0x18000000;   // number of extra instructions to skip when stepping over
  55 const UINT32 DASMFLAG_OVERINSTSHIFT = 27;           // bits to shift after masking to get the value
  56 const UINT32 DASMFLAG_LENGTHMASK    = 0x0000ffff;   // the low 16-bits contain the actual length
  57
  58 /*****************************************************************************/
  59 /* src/emu/diexec.h */
  60
  61 // I/O line states
  62 enum line_state
  63 {
  64         CLEAR_LINE = 0,                         // clear (a fired or held) line
  65         ASSERT_LINE,                            // assert an interrupt immediately
  66         HOLD_LINE,                              // hold interrupt line until acknowledged
  67         PULSE_LINE                              // pulse interrupt line instantaneously (only for NMI, RESET)
  68 };
  69
  70 enum
  71 {
  72         INPUT_LINE_IRQ1 = 0,
  73         INPUT_LINE_IRQ2 = 1,
  74         INPUT_LINE_TIRQ = 2,
  75         INPUT_LINE_NMI
  76 };
  77
  78 #define logerror(...)
  79
  80 #include "mame/emu/cpu/h6280/h6280.c"
  81 //#ifdef USE_DEBUGGER
  82 #include "mame/emu/cpu/h6280/6280dasm.c"
  83 //#endif
  84
  85 // main
  86
  87 void HUC6280_BASE::initialize()
  88 {
  89         DEVICE::initialize();
  90         opaque = CPU_INIT_CALL(h6280);
  91
  92         h6280_Regs *cpustate = (h6280_Regs *)opaque;
  93         cpustate->program = d_mem;
  94         cpustate->io = d_io;
  95
  96 }
  97 void HUC6280_BASE::release()
  98 {
  99 }
 100
 101 void HUC6280_BASE::reset()
 102 {
 103         h6280_Regs *cpustate = (h6280_Regs *)opaque;
 104
 105         CPU_RESET_CALL(h6280);
 106
 107         cpustate->program = d_mem;
 108         cpustate->io = d_io;
 109         icount = 0;
 110         busreq = false;
 111 }
 112
 113 int HUC6280_BASE::run(int clocks)
 114 {
 115         return 0;
 116 }
 117
 118 int HUC6280_BASE::exec_call(void)
 119 {
 120         h6280_Regs *cpustate = (h6280_Regs *)opaque;
 121         return CPU_EXECUTE_CALL(h6280);
 122 }
 123
 124 int HUC6280_BASE::exec_call_debug(void)
 125 {
 126         h6280_Regs *cpustate = (h6280_Regs *)opaque;
 127         return CPU_EXECUTE_CALL(h6280_debug);
 128 }
 129
 130 void HUC6280_BASE::write_signal(int id, uint32_t data, uint32_t mask)
 131 {
 132         if(id == SIG_CPU_BUSREQ) {
 133                 busreq = ((data & mask) != 0);
 134         } else {
 135                 h6280_Regs *cpustate = (h6280_Regs *)opaque;
 136                 set_irq_line(cpustate, id, data);
 137         }
 138 }
 139
 140 uint32_t HUC6280_BASE::get_pc()
 141 {
 142         h6280_Regs *cpustate = (h6280_Regs *)opaque;
 143         return cpustate->ppc.w.l;
 144 }
 145
 146 uint32_t HUC6280_BASE::get_next_pc()
 147 {
 148         h6280_Regs *cpustate = (h6280_Regs *)opaque;
 149         return cpustate->pc.w.l;
 150 }
 151
 152 uint8_t HUC6280_BASE::irq_status_r(uint16_t offset)
 153 {
 154         h6280_Regs *cpustate = (h6280_Regs *)opaque;
 155         return h6280_irq_status_r(cpustate, offset);
 156 }
 157
 158 void HUC6280_BASE::irq_status_w(uint16_t offset, uint8_t data)
 159 {
 160         h6280_Regs *cpustate = (h6280_Regs *)opaque;
 161         h6280_irq_status_w(cpustate, offset, data);
 162 }
 163
 164 uint8_t HUC6280_BASE::timer_r(uint16_t offset)
 165 {
 166         h6280_Regs *cpustate = (h6280_Regs *)opaque;
 167         return h6280_timer_r(cpustate, offset);
 168 }
 169
 170 void HUC6280_BASE::timer_w(uint16_t offset, uint8_t data)
 171 {
 172         h6280_Regs *cpustate = (h6280_Regs *)opaque;
 173         h6280_timer_w(cpustate, offset, data);
 174 }
 175
 176 //#ifdef USE_DEBUGGER
 177 void HUC6280_BASE::write_debug_data8(uint32_t addr, uint32_t data)
 178 {
 179         int wait;
 180         d_mem->write_data8w(addr, data, &wait);
 181 }
 182
 183 uint32_t HUC6280_BASE::read_debug_data8(uint32_t addr)
 184 {
 185         int wait;
 186         return d_mem->read_data8w(addr, &wait);
 187 }
 188
 189 void HUC6280_BASE::write_debug_io8(uint32_t addr, uint32_t data)
 190 {
 191         int wait;
 192         d_io->write_io8w(addr, data, &wait);
 193 }
 194
 195 uint32_t HUC6280_BASE::read_debug_io8(uint32_t addr) {
 196         int wait;
 197         return d_io->read_io8w(addr, &wait);
 198 }
 199
 200 bool HUC6280_BASE::write_debug_reg(const _TCHAR *reg, uint32_t data)
 201 {
 202         h6280_Regs *cpustate = (h6280_Regs *)opaque;
 203         if(_tcsicmp(reg, _T("PC")) == 0) {
 204                 cpustate->pc.w.l = data;
 205         } if(_tcsicmp(reg, _T("SP")) == 0) {
 206                 cpustate->sp.w.l = data;
 207         } if(_tcsicmp(reg, _T("ZP")) == 0) {
 208                 cpustate->zp.w.l = data;
 209         } if(_tcsicmp(reg, _T("EA")) == 0) {
 210                 cpustate->ea.w.l = data;
 211         } if(_tcsicmp(reg, _T("A")) == 0) {
 212                 cpustate->a = data;
 213         } if(_tcsicmp(reg, _T("X")) == 0) {
 214                 cpustate->x = data;
 215         } if(_tcsicmp(reg, _T("Y")) == 0) {
 216                 cpustate->y = data;
 217         } if(_tcsicmp(reg, _T("P")) == 0) {
 218                 cpustate->p = data;
 219         } else {
 220                 return false;
 221         }
 222         return true;
 223 }
 224
 225 void HUC6280_BASE::get_debug_regs_info(_TCHAR *buffer, size_t buffer_len)
 226 {
 227         h6280_Regs *cpustate = (h6280_Regs *)opaque;
 228         my_stprintf_s(buffer, buffer_len,
 229         _T("PC = %04X SP = %04X ZP = %04X EA = %04X A = %02X X = %02X Y = %02X P = %02X"),
 230         cpustate->pc.w.l, cpustate->sp.w.l, cpustate->zp.w.l, cpustate->ea.w.l, cpustate->a, cpustate->x, cpustate->y, cpustate->p);
 231 }
 232
 233 // disassembler
 234
 235 int HUC6280_BASE::debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len)
 236 {
 237         uint8_t oprom[8];
 238         uint8_t *opram = oprom;
 239
 240         for(int i = 0; i < 8; i++) {
 241                 int wait;
 242                 oprom[i] = d_mem->read_data8w(pc + i, &wait);
 243         }
 244         return CPU_DISASSEMBLE_CALL(h6280) & DASMFLAG_LENGTHMASK;
 245 }
 246 //#endif
 247
 248 void HUC6280_BASE::save_state_registers(FILEIO* state_fio)
 249 {
 250         h6280_Regs *cpustate = (h6280_Regs *)opaque;
 251
 252         state_fio->FputInt32(cpustate->ICount);
 253         state_fio->Fwrite(&(cpustate->ppc), sizeof(PAIR), 1);
 254         state_fio->Fwrite(&(cpustate->pc), sizeof(PAIR), 1);
 255         state_fio->Fwrite(&(cpustate->sp), sizeof(PAIR), 1);
 256         state_fio->Fwrite(&(cpustate->zp), sizeof(PAIR), 1);
 257         state_fio->Fwrite(&(cpustate->ea), sizeof(PAIR), 1);
 258         state_fio->FputUint8(cpustate->a);
 259         state_fio->FputUint8(cpustate->x);
 260         state_fio->FputUint8(cpustate->y);
 261         state_fio->FputUint8(cpustate->p);
 262         state_fio->Fwrite(&(cpustate->mmr), sizeof(uint8_t) * 8, 1);
 263         state_fio->FputUint8(cpustate->irq_mask);
 264         state_fio->FputUint8(cpustate->timer_status);
 265         state_fio->FputUint8(cpustate->timer_ack);
 266         state_fio->FputUint8(cpustate->clocks_per_cycle);
 267         state_fio->FputInt32(cpustate->timer_value);
 268         state_fio->FputInt32(cpustate->timer_load);
 269         state_fio->FputUint8(cpustate->nmi_state);
 270         state_fio->Fwrite(&(cpustate->irq_state), sizeof(uint8_t) * 3, 1);
 271         state_fio->FputUint8(cpustate->irq_pending);
 272 }
 273
 274 void HUC6280_BASE::load_state_registers(FILEIO* state_fio)
 275 {
 276         h6280_Regs *cpustate = (h6280_Regs *)opaque;
 277         cpustate->ICount = state_fio->FgetInt32();
 278         state_fio->Fread(&(cpustate->ppc), sizeof(PAIR), 1);
 279         state_fio->Fread(&(cpustate->pc), sizeof(PAIR), 1);
 280         state_fio->Fread(&(cpustate->sp), sizeof(PAIR), 1);
 281         state_fio->Fread(&(cpustate->zp), sizeof(PAIR), 1);
 282         state_fio->Fread(&(cpustate->ea), sizeof(PAIR), 1);
 283         cpustate->a = state_fio->FgetUint8();
 284         cpustate->x = state_fio->FgetUint8();
 285         cpustate->y = state_fio->FgetUint8();
 286         cpustate->p = state_fio->FgetUint8();
 287         state_fio->Fread(&(cpustate->mmr), sizeof(uint8_t) * 8, 1);
 288         cpustate->irq_mask = state_fio->FgetUint8();
 289         cpustate->timer_status = state_fio->FgetUint8();
 290         cpustate->timer_ack = state_fio->FgetUint8();
 291         cpustate->clocks_per_cycle = state_fio->FgetUint8();
 292         cpustate->timer_value = state_fio->FgetInt32();
 293         cpustate->timer_load = state_fio->FgetInt32();
 294         cpustate->nmi_state = state_fio->FgetUint8();
 295         state_fio->Fread(&(cpustate->irq_state), sizeof(uint8_t) * 3, 1);
 296         cpustate->irq_pending = state_fio->FgetUint8();
 297 }
 298
 299