source/src/vm/libcpu_newdev/libcpu_i386/i386_opdef.h

   1
   2 #ifndef __LIB_I386_OPDEF_H__
   3 #define __LIB_I386_OPDEF_H__
   4
   5 #include "../../../common.h"
   6 #ifndef __BIG_ENDIAN__
   7 #define LSB_FIRST
   8 #endif
   9 #include "../../../fileio.h"
  10 #include "../device.h"
  11 #include "./i386priv.h"
  12 #include "./i386ops.h"
  13 #include "./vtlb.h"
  14
  15 #ifndef INLINE
  16 #define INLINE inline
  17 #endif
  18
  19 #define U64(v) UINT64(v)
  20
  21 //#define fatalerror(...) exit(1)
  22 #define fatalerror(...)
  23 #define logerror(...)
  24 #define popmessage(...)
  25
  26 #define X86_NUM_CPUS        4
  27 #define CPU_CYCLES_I386         0
  28 #define CPU_CYCLES_I486         1
  29 #define CPU_CYCLES_PENTIUM      2
  30 #define CPU_CYCLES_MEDIAGX      3
  31
  32 enum X86_CYCLES
  33 {
  34         CYCLES_MOV_REG_REG,
  35         CYCLES_MOV_REG_MEM,
  36         CYCLES_MOV_MEM_REG,
  37         CYCLES_MOV_IMM_REG,
  38         CYCLES_MOV_IMM_MEM,
  39         CYCLES_MOV_ACC_MEM,
  40         CYCLES_MOV_MEM_ACC,
  41         CYCLES_MOV_REG_SREG,
  42         CYCLES_MOV_MEM_SREG,
  43         CYCLES_MOV_SREG_REG,
  44         CYCLES_MOV_SREG_MEM,
  45         CYCLES_MOVSX_REG_REG,
  46         CYCLES_MOVSX_MEM_REG,
  47         CYCLES_MOVZX_REG_REG,
  48         CYCLES_MOVZX_MEM_REG,
  49         CYCLES_PUSH_RM,
  50         CYCLES_PUSH_REG_SHORT,
  51         CYCLES_PUSH_SREG,
  52         CYCLES_PUSH_IMM,
  53         CYCLES_PUSHA,
  54         CYCLES_POP_RM,
  55         CYCLES_POP_REG_SHORT,
  56         CYCLES_POP_SREG,
  57         CYCLES_POPA,
  58         CYCLES_XCHG_REG_REG,
  59         CYCLES_XCHG_REG_MEM,
  60         CYCLES_IN,
  61         CYCLES_IN_VAR,
  62         CYCLES_OUT,
  63         CYCLES_OUT_VAR,
  64         CYCLES_LEA,
  65         CYCLES_LDS,
  66         CYCLES_LES,
  67         CYCLES_LFS,
  68         CYCLES_LGS,
  69         CYCLES_LSS,
  70         CYCLES_CLC,
  71         CYCLES_CLD,
  72         CYCLES_CLI,
  73         CYCLES_CLTS,
  74         CYCLES_CMC,
  75         CYCLES_LAHF,
  76         CYCLES_POPF,
  77         CYCLES_PUSHF,
  78         CYCLES_SAHF,
  79         CYCLES_STC,
  80         CYCLES_STD,
  81         CYCLES_STI,
  82         CYCLES_ALU_REG_REG,
  83         CYCLES_ALU_REG_MEM,
  84         CYCLES_ALU_MEM_REG,
  85         CYCLES_ALU_IMM_REG,
  86         CYCLES_ALU_IMM_MEM,
  87         CYCLES_ALU_IMM_ACC,
  88         CYCLES_INC_REG,
  89         CYCLES_INC_MEM,
  90         CYCLES_DEC_REG,
  91         CYCLES_DEC_MEM,
  92         CYCLES_CMP_REG_REG,
  93         CYCLES_CMP_REG_MEM,
  94         CYCLES_CMP_MEM_REG,
  95         CYCLES_CMP_IMM_REG,
  96         CYCLES_CMP_IMM_MEM,
  97         CYCLES_CMP_IMM_ACC,
  98         CYCLES_TEST_REG_REG,
  99         CYCLES_TEST_REG_MEM,
 100         CYCLES_TEST_IMM_REG,
 101         CYCLES_TEST_IMM_MEM,
 102         CYCLES_TEST_IMM_ACC,
 103         CYCLES_NEG_REG,
 104         CYCLES_NEG_MEM,
 105         CYCLES_AAA,
 106         CYCLES_AAS,
 107         CYCLES_DAA,
 108         CYCLES_DAS,
 109         CYCLES_MUL8_ACC_REG,
 110         CYCLES_MUL8_ACC_MEM,
 111         CYCLES_MUL16_ACC_REG,
 112         CYCLES_MUL16_ACC_MEM,
 113         CYCLES_MUL32_ACC_REG,
 114         CYCLES_MUL32_ACC_MEM,
 115         CYCLES_IMUL8_ACC_REG,
 116         CYCLES_IMUL8_ACC_MEM,
 117         CYCLES_IMUL16_ACC_REG,
 118         CYCLES_IMUL16_ACC_MEM,
 119         CYCLES_IMUL32_ACC_REG,
 120         CYCLES_IMUL32_ACC_MEM,
 121         CYCLES_IMUL8_REG_REG,
 122         CYCLES_IMUL8_REG_MEM,
 123         CYCLES_IMUL16_REG_REG,
 124         CYCLES_IMUL16_REG_MEM,
 125         CYCLES_IMUL32_REG_REG,
 126         CYCLES_IMUL32_REG_MEM,
 127         CYCLES_IMUL16_REG_IMM_REG,
 128         CYCLES_IMUL16_MEM_IMM_REG,
 129         CYCLES_IMUL32_REG_IMM_REG,
 130         CYCLES_IMUL32_MEM_IMM_REG,
 131         CYCLES_DIV8_ACC_REG,
 132         CYCLES_DIV8_ACC_MEM,
 133         CYCLES_DIV16_ACC_REG,
 134         CYCLES_DIV16_ACC_MEM,
 135         CYCLES_DIV32_ACC_REG,
 136         CYCLES_DIV32_ACC_MEM,
 137         CYCLES_IDIV8_ACC_REG,
 138         CYCLES_IDIV8_ACC_MEM,
 139         CYCLES_IDIV16_ACC_REG,
 140         CYCLES_IDIV16_ACC_MEM,
 141         CYCLES_IDIV32_ACC_REG,
 142         CYCLES_IDIV32_ACC_MEM,
 143         CYCLES_AAD,
 144         CYCLES_AAM,
 145         CYCLES_CBW,
 146         CYCLES_CWD,
 147         CYCLES_ROTATE_REG,
 148         CYCLES_ROTATE_MEM,
 149         CYCLES_ROTATE_CARRY_REG,
 150         CYCLES_ROTATE_CARRY_MEM,
 151         CYCLES_SHLD_REG,
 152         CYCLES_SHLD_MEM,
 153         CYCLES_SHRD_REG,
 154         CYCLES_SHRD_MEM,
 155         CYCLES_NOT_REG,
 156         CYCLES_NOT_MEM,
 157         CYCLES_CMPS,
 158         CYCLES_INS,
 159         CYCLES_LODS,
 160         CYCLES_MOVS,
 161         CYCLES_OUTS,
 162         CYCLES_SCAS,
 163         CYCLES_STOS,
 164         CYCLES_XLAT,
 165         CYCLES_REP_CMPS_BASE,
 166         CYCLES_REP_INS_BASE,
 167         CYCLES_REP_LODS_BASE,
 168         CYCLES_REP_MOVS_BASE,
 169         CYCLES_REP_OUTS_BASE,
 170         CYCLES_REP_SCAS_BASE,
 171         CYCLES_REP_STOS_BASE,
 172         CYCLES_REP_CMPS,
 173         CYCLES_REP_INS,
 174         CYCLES_REP_LODS,
 175         CYCLES_REP_MOVS,
 176         CYCLES_REP_OUTS,
 177         CYCLES_REP_SCAS,
 178         CYCLES_REP_STOS,
 179         CYCLES_BSF_BASE,
 180         CYCLES_BSF,
 181         CYCLES_BSR_BASE,
 182         CYCLES_BSR,
 183         CYCLES_BT_IMM_REG,
 184         CYCLES_BT_IMM_MEM,
 185         CYCLES_BT_REG_REG,
 186         CYCLES_BT_REG_MEM,
 187         CYCLES_BTC_IMM_REG,
 188         CYCLES_BTC_IMM_MEM,
 189         CYCLES_BTC_REG_REG,
 190         CYCLES_BTC_REG_MEM,
 191         CYCLES_BTR_IMM_REG,
 192         CYCLES_BTR_IMM_MEM,
 193         CYCLES_BTR_REG_REG,
 194         CYCLES_BTR_REG_MEM,
 195         CYCLES_BTS_IMM_REG,
 196         CYCLES_BTS_IMM_MEM,
 197         CYCLES_BTS_REG_REG,
 198         CYCLES_BTS_REG_MEM,
 199         CYCLES_CALL,                // E8
 200         CYCLES_CALL_REG,            // FF /2
 201         CYCLES_CALL_MEM,            // FF /2
 202         CYCLES_CALL_INTERSEG,       // 9A
 203         CYCLES_CALL_REG_INTERSEG,   // FF /3
 204         CYCLES_CALL_MEM_INTERSEG,   // FF /3
 205         CYCLES_JMP_SHORT,           // EB
 206         CYCLES_JMP,                 // E9
 207         CYCLES_JMP_REG,             // FF /4
 208         CYCLES_JMP_MEM,             // FF /4
 209         CYCLES_JMP_INTERSEG,        // EA
 210         CYCLES_JMP_REG_INTERSEG,    // FF /5
 211         CYCLES_JMP_MEM_INTERSEG,    // FF /5
 212         CYCLES_RET,                 // C3
 213         CYCLES_RET_IMM,             // C2
 214         CYCLES_RET_INTERSEG,        // CB
 215         CYCLES_RET_IMM_INTERSEG,    // CA
 216         CYCLES_JCC_DISP8,
 217         CYCLES_JCC_FULL_DISP,
 218         CYCLES_JCC_DISP8_NOBRANCH,
 219         CYCLES_JCC_FULL_DISP_NOBRANCH,
 220         CYCLES_JCXZ,
 221         CYCLES_JCXZ_NOBRANCH,
 222         CYCLES_LOOP,
 223         CYCLES_LOOPZ,
 224         CYCLES_LOOPNZ,
 225         CYCLES_SETCC_REG,
 226         CYCLES_SETCC_MEM,
 227         CYCLES_ENTER,
 228         CYCLES_LEAVE,
 229         CYCLES_INT,
 230         CYCLES_INT3,
 231         CYCLES_INTO_OF1,
 232         CYCLES_INTO_OF0,
 233         CYCLES_BOUND_IN_RANGE,
 234         CYCLES_BOUND_OUT_RANGE,
 235         CYCLES_IRET,
 236         CYCLES_HLT,
 237         CYCLES_MOV_REG_CR0,
 238         CYCLES_MOV_REG_CR2,
 239         CYCLES_MOV_REG_CR3,
 240         CYCLES_MOV_CR_REG,
 241         CYCLES_MOV_REG_DR0_3,
 242         CYCLES_MOV_REG_DR6_7,
 243         CYCLES_MOV_DR6_7_REG,
 244         CYCLES_MOV_DR0_3_REG,
 245         CYCLES_MOV_REG_TR6_7,
 246         CYCLES_MOV_TR6_7_REG,
 247         CYCLES_NOP,
 248         CYCLES_WAIT,
 249         CYCLES_ARPL_REG,
 250         CYCLES_ARPL_MEM,
 251         CYCLES_LAR_REG,
 252         CYCLES_LAR_MEM,
 253         CYCLES_LGDT,
 254         CYCLES_LIDT,
 255         CYCLES_LLDT_REG,
 256         CYCLES_LLDT_MEM,
 257         CYCLES_LMSW_REG,
 258         CYCLES_LMSW_MEM,
 259         CYCLES_LSL_REG,
 260         CYCLES_LSL_MEM,
 261         CYCLES_LTR_REG,
 262         CYCLES_LTR_MEM,
 263         CYCLES_SGDT,
 264         CYCLES_SIDT,
 265         CYCLES_SLDT_REG,
 266         CYCLES_SLDT_MEM,
 267         CYCLES_SMSW_REG,
 268         CYCLES_SMSW_MEM,
 269         CYCLES_STR_REG,
 270         CYCLES_STR_MEM,
 271         CYCLES_VERR_REG,
 272         CYCLES_VERR_MEM,
 273         CYCLES_VERW_REG,
 274         CYCLES_VERW_MEM,
 275         CYCLES_LOCK,
 276
 277         CYCLES_BSWAP,
 278         CYCLES_CMPXCHG8B,
 279         CYCLES_CMPXCHG,
 280         CYCLES_CPUID,
 281         CYCLES_CPUID_EAX1,
 282         CYCLES_INVD,
 283         CYCLES_XADD,
 284         CYCLES_RDTSC,
 285         CYCLES_RSM,
 286         CYCLES_RDMSR,
 287
 288         CYCLES_FABS,
 289         CYCLES_FADD,
 290         CYCLES_FBLD,
 291         CYCLES_FBSTP,
 292         CYCLES_FCHS,
 293         CYCLES_FCLEX,
 294         CYCLES_FCOM,
 295         CYCLES_FCOS,
 296         CYCLES_FDECSTP,
 297         CYCLES_FDISI,
 298         CYCLES_FDIV,
 299         CYCLES_FDIVR,
 300         CYCLES_FENI,
 301         CYCLES_FFREE,
 302         CYCLES_FIADD,
 303         CYCLES_FICOM,
 304         CYCLES_FIDIV,
 305         CYCLES_FILD,
 306         CYCLES_FIMUL,
 307         CYCLES_FINCSTP,
 308         CYCLES_FINIT,
 309         CYCLES_FIST,
 310         CYCLES_FISUB,
 311         CYCLES_FLD,
 312         CYCLES_FLDZ,
 313         CYCLES_FLD1,
 314         CYCLES_FLDL2E,
 315         CYCLES_FLDL2T,
 316         CYCLES_FLDLG2,
 317         CYCLES_FLDLN2,
 318         CYCLES_FLDPI,
 319         CYCLES_FLDCW,
 320         CYCLES_FLDENV,
 321         CYCLES_FMUL,
 322         CYCLES_FNOP,
 323         CYCLES_FPATAN,
 324         CYCLES_FPREM,
 325         CYCLES_FPREM1,
 326         CYCLES_FPTAN,
 327         CYCLES_FRNDINT,
 328         CYCLES_FRSTOR,
 329         CYCLES_FSAVE,
 330         CYCLES_FSCALE,
 331         CYCLES_FSETPM,
 332         CYCLES_FSIN,
 333         CYCLES_FSINCOS,
 334         CYCLES_FSQRT,
 335         CYCLES_FST,
 336         CYCLES_FSTCW,
 337         CYCLES_FSTENV,
 338         CYCLES_FSTSW,
 339         CYCLES_FSUB,
 340         CYCLES_FSUBR,
 341         CYCLES_FTST,
 342         CYCLES_FUCOM,
 343         CYCLES_FXAM,
 344         CYCLES_FXCH,
 345         CYCLES_FXTRACT,
 346         CYCLES_FYL2X,
 347         CYCLES_FYL2XPI,
 348         CYCLES_CMPXCHG_REG_REG_T,
 349         CYCLES_CMPXCHG_REG_REG_F,
 350         CYCLES_CMPXCHG_REG_MEM_T,
 351         CYCLES_CMPXCHG_REG_MEM_F,
 352         CYCLES_XADD_REG_REG,
 353         CYCLES_XADD_REG_MEM,
 354
 355         CYCLES_NUM_OPCODES
 356 };
 357
 358 struct X86_CYCLE_TABLE
 359 {
 360         X86_CYCLES op;
 361         UINT8 cpu_cycles[X86_NUM_CPUS][2];
 362 };
 363
 364 /*************************************
 365  *
 366  * Defines
 367  *
 368  *************************************/
 369
 370 #define X87_SW_IE               0x0001
 371 #define X87_SW_DE               0x0002
 372 #define X87_SW_ZE               0x0004
 373 #define X87_SW_OE               0x0008
 374 #define X87_SW_UE               0x0010
 375 #define X87_SW_PE               0x0020
 376 #define X87_SW_SF               0x0040
 377 #define X87_SW_ES               0x0080
 378 #define X87_SW_C0               0x0100
 379 #define X87_SW_C1               0x0200
 380 #define X87_SW_C2               0x0400
 381 #define X87_SW_TOP_SHIFT        11
 382 #define X87_SW_TOP_MASK         7
 383 #define X87_SW_C3               0x4000
 384 #define X87_SW_BUSY             0x8000
 385
 386 #define X87_CW_IM               0x0001
 387 #define X87_CW_DM               0x0002
 388 #define X87_CW_ZM               0x0004
 389 #define X87_CW_OM               0x0008
 390 #define X87_CW_UM               0x0010
 391 #define X87_CW_PM               0x0020
 392 #define X87_CW_PC_SHIFT         8
 393 #define X87_CW_PC_MASK          3
 394 #define X87_CW_PC_SINGLE        0
 395 #define X87_CW_PC_DOUBLE        2
 396 #define X87_CW_PC_EXTEND        3
 397 #define X87_CW_RC_SHIFT         10
 398 #define X87_CW_RC_MASK          3
 399 #define X87_CW_RC_NEAREST       0
 400 #define X87_CW_RC_DOWN          1
 401 #define X87_CW_RC_UP            2
 402 #define X87_CW_RC_ZERO          3
 403
 404 #define X87_TW_MASK             3
 405 #define X87_TW_VALID            0
 406 #define X87_TW_ZERO             1
 407 #define X87_TW_SPECIAL          2
 408 #define X87_TW_EMPTY            3
 409
 410
 411 /*************************************
 412  *
 413  * Macros
 414  *
 415  *************************************/
 416
 417 #define ST_TO_PHYS(x)           (((cpustate->x87_sw >> X87_SW_TOP_SHIFT) + (x)) & X87_SW_TOP_MASK)
 418 #define ST(x)                   (cpustate->x87_reg[ST_TO_PHYS(x)])
 419 #define X87_TW_FIELD_SHIFT(x)   ((x) << 1)
 420 #define X87_TAG(x)              ((cpustate->x87_tw >> X87_TW_FIELD_SHIFT(x)) & X87_TW_MASK)
 421 #define X87_RC                  ((cpustate->x87_cw >> X87_CW_RC_SHIFT) & X87_CW_RC_MASK)
 422 #define X87_IS_ST_EMPTY(x)      (X87_TAG(ST_TO_PHYS(x)) == X87_TW_EMPTY)
 423 #define X87_SW_C3_0             X87_SW_C0
 424
 425 #define UNIMPLEMENTED           fatalerror("Unimplemented x87 op: %s (PC:%x)\n", __FUNCTION__, cpustate->pc)
 426
 427 /*****************************************************************************/
 428 /* src/emu/devcpu.h */
 429
 430 // CPU interface functions
 431 #define CPU_INIT_NAME(name)                     I386_OPS_BASE::cpu_init_##name
 432 #define CPU_INIT(name)                          void* CPU_INIT_NAME(name)()
 433 #define CPU_INIT_CALL_NAME(name)        cpu_init_##name
 434 #define CPU_INIT_CALL(name)                     CPU_INIT_CALL_NAME(name)()
 435
 436 #define CPU_RESET_NAME(name)            I386_OPS_BASE::cpu_reset_##name
 437 #define CPU_RESET(name)                         void CPU_RESET_NAME(name)()
 438 #define CPU_RESET_CALL_NAME(name)       cpu_reset_##name
 439 #define CPU_RESET_CALL(name)            CPU_RESET_CALL_NAME(name)()
 440
 441 #define CPU_EXECUTE_NAME(name)          I386_OPS_BASE::cpu_execute_##name
 442 #define CPU_EXECUTE(name)                       int CPU_EXECUTE_NAME(name)(int cycles)
 443 #define CPU_EXECUTE_CALL_NAME(name)     cpu_execute_##name
 444 #define CPU_EXECUTE_CALL(name)          CPU_EXECUTE_CALL_NAME(name)(cycles)
 445
 446 #define CPU_TRANSLATE_NAME(name)        I386_OPS_BASE::cpu_translate_##name
 447 #define CPU_TRANSLATE(name)                     int CPU_TRANSLATE_NAME(name)(void *cpudevice, address_spacenum space, int intention, offs_t *address)
 448 #define CPU_TRANSLATE_CALL_NAME(name)   cpu_translate_##name
 449 #define CPU_TRANSLATE_CALL(name)        CPU_TRANSLATE_CALL_NAME(name)(cpudevice, space, intention, address)
 450
 451 #define CPU_DISASSEMBLE_NAME(name)      I386_OPS_BASE::cpu_disassemble_##name
 452 #define CPU_DISASSEMBLE(name)           int CPU_DISASSEMBLE_NAME(name)(_TCHAR *buffer, offs_t eip, const UINT8 *oprom)
 453 #define CPU_DISASSEMBLE_CALL_NAME(name) cpu_disassemble_##name
 454 #define CPU_DISASSEMBLE_CALL(name)      CPU_DISASSEMBLE_CALL_NAME(name)(buffer, eip, oprom)
 455
 456 /*****************************************************************************/
 457 /* src/emu/didisasm.h */
 458
 459 // Disassembler constants
 460 const UINT32 DASMFLAG_SUPPORTED     = 0x80000000;   // are disassembly flags supported?
 461 const UINT32 DASMFLAG_STEP_OUT      = 0x40000000;   // this instruction should be the end of a step out sequence
 462 const UINT32 DASMFLAG_STEP_OVER     = 0x20000000;   // this instruction should be stepped over by setting a breakpoint afterwards
 463 const UINT32 DASMFLAG_OVERINSTMASK  = 0x18000000;   // number of extra instructions to skip when stepping over
 464 const UINT32 DASMFLAG_OVERINSTSHIFT = 27;           // bits to shift after masking to get the value
 465 const UINT32 DASMFLAG_LENGTHMASK    = 0x0000ffff;   // the low 16-bits contain the actual length
 466
 467 /*****************************************************************************/
 468 /* src/emu/diexec.h */
 469
 470 // I/O line states
 471 enum line_state
 472 {
 473         CLEAR_LINE = 0,                         // clear (a fired or held) line
 474         ASSERT_LINE,                            // assert an interrupt immediately
 475         HOLD_LINE,                              // hold interrupt line until acknowledged
 476         PULSE_LINE                              // pulse interrupt line instantaneously (only for NMI, RESET)
 477 };
 478
 479 enum
 480 {
 481         INPUT_LINE_IRQ = 0,
 482         INPUT_LINE_NMI
 483 };
 484
 485 /*****************************************************************************/
 486 /* src/emu/dimemory.h */
 487
 488 enum {
 489         I386_OPS_CPUTYPE_I386 = 0,
 490         I386_OPS_CPUTYPE_I486,
 491         I386_OPS_CPUTYPE_PENTIUM,
 492         I386_OPS_CPUTYPE_MEDIAGX,
 493         I386_OPS_CPUTYPE_PENTIUM_PRO,
 494         I386_OPS_CPUTYPE_PENTIUM_MMX,
 495         I386_OPS_CPUTYPE_PENTIUM2,
 496         I386_OPS_CPUTYPE_PENTIUM3,
 497         I386_OPS_CPUTYPE_PENTIUM4,
 498         I386_OPS_CPUTYPE_IX87FPU,
 499         I386_OPS_CPUTYPE_END
 500 };
 501
 502 /************************************** vtlb.h ***************************************/
 503
 504 class DEBUG;
 505 class I386_OPS_BASE {
 506 protected:
 507         i386_state *cpustate;
 508         int _cputype;
 509 // Parameters.
 510         //const X86_CYCLE_TABLE *x86_cycle_table;
 511         //const X86_OPCODE *x86_opcode_table;
 512         //X86_OPCODE x86_opcode_table[];
 513
 514         int i386_parity_table[256];
 515         MODRM_TABLE i386_MODRM_table[256];
 516         i386_state __cpustate;
 517         UINT8 cycle_table_rm[X86_NUM_CPUS][CYCLES_NUM_OPCODES];
 518         UINT8 cycle_table_pm[X86_NUM_CPUS][CYCLES_NUM_OPCODES];
 519         const floatx80 fx80_zero =   { 0x0000, U64(0x0000000000000000) };
 520         const floatx80 fx80_one =    { 0x3fff, U64(0x8000000000000000) };
 521         const floatx80 fx80_ninf =   { 0xffff, U64(0x8000000000000000) };
 522         const floatx80 fx80_inan =   { 0xffff, U64(0xc000000000000000) };
 523 /* Maps x87 round modes to SoftFloat round modes */
 524         const int x87_to_sf_rc[4] = {
 525                 float_round_nearest_even,
 526                 float_round_down,
 527                 float_round_up,
 528                 float_round_to_zero,
 529         };
 530         DEVICE *d_mem;
 531         DEVICE *d_io;
 532         DEVICE *d_pic;
 533         DEVICE *d_bios;
 534         DEVICE *d_dma;
 535
 536         UINT32 i386_escape_ea;   // hack around GCC 4.6 error because we need the side effects of GetEA()
 537 public:
 538         I386_OPS_BASE(int cputypes = I386_OPS_CPUTYPE_I386)
 539         {
 540                 cpustate = NULL;
 541                 _cputype = cputypes;
 542         }
 543         ~I386_OPS_BASE() {}
 544         virtual void I386OP_D(decode_opcode)();
 545
 546         int i386_translate_address(int intention, offs_t *address, vtlb_entry *entry);
 547         virtual int cpu_translate_i386(void *cpudevice, address_spacenum space, int intention, offs_t *address);
 548         virtual int cpu_execute_i386(int cycles);
 549         virtual void i386_trap(int irq, int irq_gate, int trap_level);
 550         virtual void i386_trap_with_error(int irq, int irq_gate, int trap_level, UINT32 error);
 551         void i386_set_irq_line(int irqline, int state);
 552         void i386_set_a20_line(int state);
 553         int i386_limit_check( int seg, UINT32 offset);
 554         void i386_vtlb_free(void);
 555         void i386_free_state(void);
 556
 557         i386_state *get_cpu_state(void) { return cpustate; }
 558         int get_extra_clock() { return cpustate->extra_cycles; }
 559         void set_extra_clock(int n) { cpustate->extra_cycles += n; }
 560
 561         uint32_t get_pc() { return cpustate->pc; }
 562         uint32_t get_prev_pc() { return cpustate->prev_pc; }
 563         void set_address_mask(uint32_t mask) { cpustate->a20_mask = mask; }
 564         uint32_t get_address_mask() { return cpustate->a20_mask; }
 565         void  set_shutdown_flag(int n) { cpustate->shutdown = n; }
 566         int get_shutdown_flag() { return cpustate->shutdown; }
 567
 568         void set_busreq(bool n) { cpustate->busreq = n ? 1 : 0; }
 569         bool get_busreq() { return cpustate->busreq; }
 570         INLINE void check_ioperm( offs_t port, UINT8 mask);
 571
 572         void set_context_pic(DEVICE *dev) {
 573                 cpustate->pic = dev;
 574                 d_pic = dev;
 575         }
 576         virtual void set_context_progmem_stored(DEVICE *dev) {
 577                 //cpustate->program_stored = dev;
 578         }
 579         void set_context_progmem(DEVICE *dev) {
 580                 cpustate->program = dev;
 581                 d_mem = dev;
 582         }
 583
 584         virtual void set_context_pseudo_bios(DEVICE *dev) {
 585                 //cpustate->bios = dev;
 586                 //d_bios = dev;
 587         }
 588
 589         virtual void set_context_dma(DEVICE *dev) {
 590                 //cpustate->dma = dev;
 591                 //d_dma = dev;
 592         }
 593
 594         void set_context_io(DEVICE *dev) {
 595                 cpustate->io = dev;
 596                 d_io = dev;
 597         }
 598
 599         virtual void set_context_io_stored(DEVICE *dev) {
 600                 //cpustate->io_stored = dev;
 601
 602         }
 603
 604         virtual void set_context_emu(EMU *p_emu) {
 605                 //cpustate->emu = p_emu;
 606         }
 607
 608         virtual void set_context_debugger(DEBUGGER *debugger) {
 609                 //cpustate->debugger = dev;
 610         }
 611
 612         virtual bool write_debug_reg(const _TCHAR *reg, uint32_t data) { return false; }
 613
 614         virtual int debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len) { return 0;}
 615         void vtlb_flush_dynamic(void) { vtlb_flush_dynamic(cpustate->vtlb); }
 616
 617         void save_state(FILEIO *state_fio);
 618         bool load_state(FILEIO *state_fio);
 619
 620 protected:
 621         // Utilities
 622         void build_cycle_table();
 623         virtual i386_state *i386_common_init(int tlbsize);
 624         void build_opcode_table( UINT32 features);
 625         void zero_state();
 626         void pentium_smi();
 627
 628         UINT32 i386_load_protected_mode_segment( I386_SREG *seg, UINT64 *desc );
 629         void i386_load_call_gate(I386_CALL_GATE *gate);
 630         void i386_set_descriptor_accessed( UINT16 selector);
 631         void i386_load_segment_descriptor( int segment );
 632         UINT32 i386_get_stack_segment(UINT8 privilege);
 633         UINT32 i386_get_stack_ptr(UINT8 privilege);
 634
 635         UINT32 get_flags();
 636         void set_flags( UINT32 f );
 637
 638         void sib_byte(UINT8 mod, UINT32* out_ea, UINT8* out_segment);
 639         void modrm_to_EA(UINT8 mod_rm, UINT32* out_ea, UINT8* out_segment);
 640
 641         UINT32 GetNonTranslatedEA(UINT8 modrm,UINT8 *seg);
 642         UINT32 GetEA(UINT8 modrm, int rwn);
 643
 644         //
 645         void i386_check_sreg_validity(int reg);
 646         void i386_sreg_load( UINT16 selector, UINT8 reg, bool *fault);
 647         void i286_task_switch( UINT16 selector, UINT8 nested);
 648         void i386_task_switch( UINT16 selector, UINT8 nested);
 649         void i386_check_irq_line();
 650
 651         void i386_protected_mode_jump( UINT16 seg, UINT32 off, int indirect, int operand32);
 652         void i386_protected_mode_call( UINT16 seg, UINT32 off, int indirect, int operand32);
 653         void i386_protected_mode_retf(UINT8 count, UINT8 operand32);
 654         void i386_protected_mode_iret(int operand32);
 655
 656         // Reporter.
 657         void report_invalid_opcode();
 658         void report_invalid_modrm(const char* opcode, UINT8 modrm);
 659
 660         //LINES
 661         void i386_postload();
 662
 663         /* ----- initialization/teardown ----- */
 664         /* allocate a new VTLB for the given CPU */
 665         vtlb_state *vtlb_alloc(void *cpu, address_spacenum space, int fixed_entries, int dynamic_entries);
 666         /* free an allocated VTLB */
 667         void vtlb_free(vtlb_state *vtlb);
 668
 669         /* called by the CPU core in response to an unmapped access */
 670         int vtlb_fill(vtlb_state *vtlb, offs_t address, int intention);
 671         /* load a fixed VTLB entry */
 672         void vtlb_load(vtlb_state *vtlb, int entrynum, int numpages, offs_t address, vtlb_entry value);
 673         /* load a dynamic VTLB entry */
 674         void vtlb_dynload(vtlb_state *vtlb, UINT32 index, offs_t address, vtlb_entry value);
 675         /* ----- flushing ----- */
 676         /* flush all knowledge from the dynamic part of the VTLB */
 677         void vtlb_flush_dynamic(vtlb_state *vtlb);
 678         /* flush knowledge of a particular address from the VTLB */
 679         void vtlb_flush_address(vtlb_state *vtlb, offs_t address);
 680         /* ----- accessors ----- */
 681         /* return a pointer to the base of the linear VTLB lookup table */
 682         const vtlb_entry *vtlb_table(vtlb_state *vtlb);
 683
 684         virtual int cpu_disassemble_x86_16(_TCHAR *buffer, UINT64 eip, const UINT8 *oprom) { return 0; }
 685         virtual int cpu_disassemble_x86_32(_TCHAR *buffer, UINT64 eip, const UINT8 *oprom) { return 0; }
 686         virtual int cpu_disassemble_x86_64(_TCHAR *buffer, UINT64 eip, const UINT8 *oprom) { return 0; }
 687 public:
 688         // Init per vm..
 689         void *cpu_init_i386(void);
 690         void *cpu_init_i486(void);
 691         void *cpu_init_pentium(void);
 692         void *cpu_init_mediagx(void);
 693         void *cpu_init_pentium_pro(void);
 694         void *cpu_init_pentium_mmx(void);
 695         void *cpu_init_pentium2(void);
 696         void *cpu_init_pentium3(void);
 697         void *cpu_init_pentium4(void);
 698         // Reset pewr type.
 699         void cpu_reset_i386(void);
 700         void cpu_reset_i486(void);
 701         void cpu_reset_pentium(void);
 702         void cpu_reset_mediagx(void);
 703         void cpu_reset_pentium_pro(void);
 704         void cpu_reset_pentium_mmx(void);
 705         void cpu_reset_pentium2(void);
 706         void cpu_reset_pentium3(void);
 707         void cpu_reset_pentium4(void);
 708
 709         // INSNs.
 710         // i386/op16
 711         void I386OP_D(adc_rm16_r16)();      // Opcode 0x11
 712         void I386OP_D(adc_r16_rm16)();      // Opcode 0x13
 713         void I386OP_D(adc_ax_i16)();        // Opcode 0x15
 714         void I386OP_D(add_rm16_r16)();      // Opcode 0x01
 715         void I386OP_D(add_r16_rm16)();      // Opcode 0x03
 716         void I386OP_D(add_ax_i16)();        // Opcode 0x05
 717         void I386OP_D(and_rm16_r16)();      // Opcode 0x21
 718         void I386OP_D(and_r16_rm16)();      // Opcode 0x23
 719         void I386OP_D(and_ax_i16)();        // Opcode 0x25
 720         void I386OP_D(bsf_r16_rm16)();      // Opcode 0x0f bc
 721         void I386OP_D(bsr_r16_rm16)();      // Opcode 0x0f bd
 722         void I386OP_D(bt_rm16_r16)();       // Opcode 0x0f a3
 723         void I386OP_D(btc_rm16_r16)();      // Opcode 0x0f bb
 724         void I386OP_D(btr_rm16_r16)();      // Opcode 0x0f b3
 725         void I386OP_D(bts_rm16_r16)();      // Opcode 0x0f ab
 726         virtual void I386OP_D(call_abs16)();        // Opcode 0x9a
 727         virtual void I386OP_D(call_rel16)();        // Opcode 0xe8
 728         void I386OP_D(cbw)();               // Opcode 0x98
 729         void I386OP_D(cmp_rm16_r16)();      // Opcode 0x39
 730         void I386OP_D(cmp_r16_rm16)();      // Opcode 0x3b
 731         void I386OP_D(cmp_ax_i16)();        // Opcode 0x3d
 732         void I386OP_D(cmpsw)();             // Opcode 0xa7
 733         void I386OP_D(cwd)();               // Opcode 0x99
 734         void I386OP_D(dec_ax)();            // Opcode 0x48
 735         void I386OP_D(dec_cx)();            // Opcode 0x49
 736         void I386OP_D(dec_dx)();            // Opcode 0x4a
 737         void I386OP_D(dec_bx)();            // Opcode 0x4b
 738         void I386OP_D(dec_sp)();            // Opcode 0x4c
 739         void I386OP_D(dec_bp)();            // Opcode 0x4d
 740         void I386OP_D(dec_si)();            // Opcode 0x4e
 741         void I386OP_D(dec_di)();            // Opcode 0x4f
 742         void I386OP_D(imul_r16_rm16)();     // Opcode 0x0f af
 743         void I386OP_D(imul_r16_rm16_i16)(); // Opcode 0x69
 744         void I386OP_D(imul_r16_rm16_i8)();  // Opcode 0x6b
 745         void I386OP_D(in_ax_i8)();          // Opcode 0xe5
 746         void I386OP_D(in_ax_dx)();          // Opcode 0xed
 747         void I386OP_D(inc_ax)();            // Opcode 0x40
 748         void I386OP_D(inc_cx)();            // Opcode 0x41
 749         void I386OP_D(inc_dx)();            // Opcode 0x42
 750         void I386OP_D(inc_bx)();            // Opcode 0x43
 751         void I386OP_D(inc_sp)();            // Opcode 0x44
 752         void I386OP_D(inc_bp)();            // Opcode 0x45
 753         void I386OP_D(inc_si)();            // Opcode 0x46
 754         void I386OP_D(inc_di)();            // Opcode 0x47
 755         void I386OP_D(iret16)();            // Opcode 0xcf
 756         void I386OP_D(ja_rel16)();          // Opcode 0x0f 87
 757         void I386OP_D(jbe_rel16)();         // Opcode 0x0f 86
 758         void I386OP_D(jc_rel16)();          // Opcode 0x0f 82
 759         void I386OP_D(jg_rel16)();          // Opcode 0x0f 8f
 760         void I386OP_D(jge_rel16)();         // Opcode 0x0f 8d
 761         void I386OP_D(jl_rel16)();          // Opcode 0x0f 8c
 762         void I386OP_D(jle_rel16)();         // Opcode 0x0f 8e
 763         void I386OP_D(jnc_rel16)();         // Opcode 0x0f 83
 764         void I386OP_D(jno_rel16)();         // Opcode 0x0f 81
 765         void I386OP_D(jnp_rel16)();         // Opcode 0x0f 8b
 766         void I386OP_D(jns_rel16)();         // Opcode 0x0f 89
 767         void I386OP_D(jnz_rel16)();         // Opcode 0x0f 85
 768         void I386OP_D(jo_rel16)();          // Opcode 0x0f 80
 769         void I386OP_D(jp_rel16)();          // Opcode 0x0f 8a
 770         void I386OP_D(js_rel16)();          // Opcode 0x0f 88
 771         void I386OP_D(jz_rel16)();          // Opcode 0x0f 84
 772         void I386OP_D(jcxz16)();            // Opcode 0xe3
 773         void I386OP_D(jmp_rel16)();         // Opcode 0xe9
 774         void I386OP_D(jmp_abs16)();         // Opcode 0xea
 775         void I386OP_D(lea16)();             // Opcode 0x8d
 776         void I386OP_D(enter16)();           // Opcode 0xc8
 777         void I386OP_D(leave16)();           // Opcode 0xc9
 778         void I386OP_D(lodsw)();             // Opcode 0xad
 779         void I386OP_D(loop16)();            // Opcode 0xe2
 780         void I386OP_D(loopne16)();          // Opcode 0xe0
 781         void I386OP_D(loopz16)();           // Opcode 0xe1
 782         void I386OP_D(mov_rm16_r16)();      // Opcode 0x89
 783         void I386OP_D(mov_r16_rm16)();      // Opcode 0x8b
 784         void I386OP_D(mov_rm16_i16)();      // Opcode 0xc7
 785         void I386OP_D(mov_ax_m16)();        // Opcode 0xa1
 786         void I386OP_D(mov_m16_ax)();        // Opcode 0xa3
 787         void I386OP_D(mov_ax_i16)();        // Opcode 0xb8
 788         void I386OP_D(mov_cx_i16)();        // Opcode 0xb9
 789         void I386OP_D(mov_dx_i16)();        // Opcode 0xba
 790         void I386OP_D(mov_bx_i16)();        // Opcode 0xbb
 791         void I386OP_D(mov_sp_i16)();        // Opcode 0xbc
 792         void I386OP_D(mov_bp_i16)();        // Opcode 0xbd
 793         void I386OP_D(mov_si_i16)();        // Opcode 0xbe
 794         void I386OP_D(mov_di_i16)();        // Opcode 0xbf
 795         void I386OP_D(movsw)();             // Opcode 0xa5
 796         void I386OP_D(movsx_r16_rm8)();     // Opcode 0x0f be
 797         void I386OP_D(movzx_r16_rm8)();     // Opcode 0x0f b6
 798         void I386OP_D(or_rm16_r16)();       // Opcode 0x09
 799         void I386OP_D(or_r16_rm16)();       // Opcode 0x0b
 800         void I386OP_D(or_ax_i16)();         // Opcode 0x0d
 801         void I386OP_D(out_ax_i8)();         // Opcode 0xe7
 802         void I386OP_D(out_ax_dx)();         // Opcode 0xef
 803         void I386OP_D(pop_ax)();            // Opcode 0x58
 804         void I386OP_D(pop_cx)();            // Opcode 0x59
 805         void I386OP_D(pop_dx)();            // Opcode 0x5a
 806         void I386OP_D(pop_bx)();            // Opcode 0x5b
 807         void I386OP_D(pop_sp)();            // Opcode 0x5c
 808         void I386OP_D(pop_bp)();            // Opcode 0x5d
 809         void I386OP_D(pop_si)();            // Opcode 0x5e
 810         void I386OP_D(pop_di)();            // Opcode 0x5f
 811         void I386OP_D(pop_ds16)();          // Opcode 0x1f
 812         void I386OP_D(pop_es16)();          // Opcode 0x07
 813         void I386OP_D(pop_fs16)();          // Opcode 0x0f a1
 814         void I386OP_D(pop_gs16)();          // Opcode 0x0f a9
 815         void I386OP_D(pop_ss16)();          // Opcode 0x17
 816         void I386OP_D(pop_rm16)();          // Opcode 0x8f
 817         void I386OP_D(popa)();              // Opcode 0x61
 818         void I386OP_D(popf)();              // Opcode 0x9d
 819         void I386OP_D(push_ax)();           // Opcode 0x50
 820         void I386OP_D(push_cx)();           // Opcode 0x51
 821         void I386OP_D(push_dx)();           // Opcode 0x52
 822         void I386OP_D(push_bx)();           // Opcode 0x53
 823         void I386OP_D(push_sp)();           // Opcode 0x54
 824         void I386OP_D(push_bp)();           // Opcode 0x55
 825         void I386OP_D(push_si)();           // Opcode 0x56
 826         void I386OP_D(push_di)();           // Opcode 0x57
 827         void I386OP_D(push_cs16)();         // Opcode 0x0e
 828         void I386OP_D(push_ds16)();         // Opcode 0x1e
 829         void I386OP_D(push_es16)();         // Opcode 0x06
 830         void I386OP_D(push_fs16)();         // Opcode 0x0f a0
 831         void I386OP_D(push_gs16)();         // Opcode 0x0f a8
 832         void I386OP_D(push_ss16)();         // Opcode 0x16
 833         void I386OP_D(push_i16)();          // Opcode 0x68
 834         void I386OP_D(pusha)();             // Opcode 0x60
 835         void I386OP_D(pushf)();             // Opcode 0x9c
 836         void I386OP_D(ret_near16_i16)();    // Opcode 0xc2
 837         void I386OP_D(ret_near16)();        // Opcode 0xc3
 838         void I386OP_D(sbb_rm16_r16)();      // Opcode 0x19
 839         void I386OP_D(sbb_r16_rm16)();      // Opcode 0x1b
 840         void I386OP_D(sbb_ax_i16)();        // Opcode 0x1d
 841         void I386OP_D(scasw)();             // Opcode 0xaf
 842         void I386OP_D(shld16_i8)();         // Opcode 0x0f a4
 843         void I386OP_D(shld16_cl)();         // Opcode 0x0f a5
 844         void I386OP_D(shrd16_i8)();         // Opcode 0x0f ac
 845         void I386OP_D(shrd16_cl)();         // Opcode 0x0f ad
 846         void I386OP_D(stosw)();             // Opcode 0xab
 847         void I386OP_D(sub_rm16_r16)();      // Opcode 0x29
 848         void I386OP_D(sub_r16_rm16)();      // Opcode 0x2b
 849         void I386OP_D(sub_ax_i16)();        // Opcode 0x2d
 850         void I386OP_D(test_ax_i16)();       // Opcode 0xa9
 851         void I386OP_D(test_rm16_r16)();     // Opcode 0x85
 852         void I386OP_D(xchg_ax_cx)();        // Opcode 0x91
 853         void I386OP_D(xchg_ax_dx)();        // Opcode 0x92
 854         void I386OP_D(xchg_ax_bx)();        // Opcode 0x93
 855         void I386OP_D(xchg_ax_sp)();        // Opcode 0x94
 856         void I386OP_D(xchg_ax_bp)();        // Opcode 0x95
 857         void I386OP_D(xchg_ax_si)();        // Opcode 0x96
 858         void I386OP_D(xchg_ax_di)();        // Opcode 0x97
 859         void I386OP_D(xchg_r16_rm16)();     // Opcode 0x87
 860         void I386OP_D(xor_rm16_r16)();      // Opcode 0x31
 861         void I386OP_D(xor_r16_rm16)();      // Opcode 0x33
 862         void I386OP_D(xor_ax_i16)();        // Opcode 0x35
 863         void I386OP_D(group81_16)();        // Opcode 0x81
 864         void I386OP_D(group83_16)();        // Opcode 0x83
 865         void I386OP_D(groupC1_16)();        // Opcode 0xc1
 866         void I386OP_D(groupD1_16)();        // Opcode 0xd1
 867         void I386OP_D(groupD3_16)();        // Opcode 0xd3
 868         void I386OP_D(groupF7_16)();        // Opcode 0xf7
 869         virtual void I386OP_D(groupFF_16)();        // Opcode 0xff
 870         void I386OP_D(group0F00_16)();          // Opcode 0x0f 00
 871         void I386OP_D(group0F01_16)();      // Opcode 0x0f 01
 872         void I386OP_D(group0FBA_16)();      // Opcode 0x0f ba
 873         void I386OP_D(lar_r16_rm16)();  // Opcode 0x0f 0x02
 874         void I386OP_D(lsl_r16_rm16)();  // Opcode 0x0f 0x03
 875         void I386OP_D(bound_r16_m16_m16)(); // Opcode 0x62
 876         void I386OP_D(retf16)();            // Opcode 0xcb
 877         void I386OP_D(retf_i16)();          // Opcode 0xca
 878         void I386OP_D(lds16)();             // Opcode 0xc5
 879         void I386OP_D(lss16)();             // Opcode 0x0f 0xb2
 880         void I386OP_D(les16)();             // Opcode 0xc4
 881         void I386OP_D(lfs16)();             // Opcode 0x0f 0xb4
 882         void I386OP_D(lgs16)();             // Opcode 0x0f 0xb5
 883         UINT16 I386OP_D(shift_rotate16)( UINT8 modrm, UINT32 value, UINT8 shift);
 884         UINT8 I386OP_D(shift_rotate8)( UINT8 modrm, UINT32 value, UINT8 shift);
 885         //i386/op32
 886         void I386OP_D(adc_rm32_r32)();      // Opcode 0x11
 887         void I386OP_D(adc_r32_rm32)();      // Opcode 0x13
 888         void I386OP_D(adc_eax_i32)();       // Opcode 0x15
 889         void I386OP_D(add_rm32_r32)();      // Opcode 0x01
 890         void I386OP_D(add_r32_rm32)();      // Opcode 0x03
 891         void I386OP_D(add_eax_i32)();       // Opcode 0x05
 892         void I386OP_D(and_rm32_r32)();      // Opcode 0x21
 893         void I386OP_D(and_r32_rm32)();      // Opcode 0x23
 894         void I386OP_D(and_eax_i32)();       // Opcode 0x25
 895         void I386OP_D(bsf_r32_rm32)();      // Opcode 0x0f bc
 896         void I386OP_D(bsr_r32_rm32)();      // Opcode 0x0f bd
 897         void I386OP_D(bt_rm32_r32)();       // Opcode 0x0f a3
 898         void I386OP_D(btc_rm32_r32)();      // Opcode 0x0f bb
 899         void I386OP_D(btr_rm32_r32)();      // Opcode 0x0f b3
 900         void I386OP_D(bts_rm32_r32)();      // Opcode 0x0f ab
 901         void I386OP_D(call_abs32)();        // Opcode 0x9a
 902         void I386OP_D(call_rel32)();        // Opcode 0xe8
 903         void I386OP_D(cdq)();               // Opcode 0x99
 904         void I386OP_D(cmp_rm32_r32)();      // Opcode 0x39
 905         void I386OP_D(cmp_r32_rm32)();      // Opcode 0x3b
 906         void I386OP_D(cmp_eax_i32)();       // Opcode 0x3d
 907         void I386OP_D(cmpsd)();             // Opcode 0xa7
 908         void I386OP_D(cwde)();              // Opcode 0x98
 909         void I386OP_D(dec_eax)();           // Opcode 0x48
 910         void I386OP_D(dec_ecx)();           // Opcode 0x49
 911         void I386OP_D(dec_edx)();           // Opcode 0x4a
 912         void I386OP_D(dec_ebx)();           // Opcode 0x4b
 913         void I386OP_D(dec_esp)();           // Opcode 0x4c
 914         void I386OP_D(dec_ebp)();           // Opcode 0x4d
 915         void I386OP_D(dec_esi)();           // Opcode 0x4e
 916         void I386OP_D(dec_edi)();           // Opcode 0x4f
 917         void I386OP_D(imul_r32_rm32)();     // Opcode 0x0f af
 918         void I386OP_D(imul_r32_rm32_i32)(); // Opcode 0x69
 919         void I386OP_D(imul_r32_rm32_i8)();  // Opcode 0x6b
 920         void I386OP_D(in_eax_i8)();         // Opcode 0xe5
 921         void I386OP_D(in_eax_dx)();         // Opcode 0xed
 922         void I386OP_D(inc_eax)();           // Opcode 0x40
 923         void I386OP_D(inc_ecx)();           // Opcode 0x41
 924         void I386OP_D(inc_edx)();           // Opcode 0x42
 925         void I386OP_D(inc_ebx)();           // Opcode 0x43
 926         void I386OP_D(inc_esp)();           // Opcode 0x44
 927         void I386OP_D(inc_ebp)();           // Opcode 0x45
 928         void I386OP_D(inc_esi)();           // Opcode 0x46
 929         void I386OP_D(inc_edi)();           // Opcode 0x47
 930         void I386OP_D(iret32)();            // Opcode 0xcf
 931         void I386OP_D(ja_rel32)();          // Opcode 0x0f 87
 932         void I386OP_D(jbe_rel32)();         // Opcode 0x0f 86
 933         void I386OP_D(jc_rel32)();          // Opcode 0x0f 82
 934         void I386OP_D(jg_rel32)();          // Opcode 0x0f 8f
 935         void I386OP_D(jge_rel32)();         // Opcode 0x0f 8d
 936         void I386OP_D(jl_rel32)();          // Opcode 0x0f 8c
 937         void I386OP_D(jle_rel32)();         // Opcode 0x0f 8e
 938         void I386OP_D(jnc_rel32)();         // Opcode 0x0f 83
 939         void I386OP_D(jno_rel32)();         // Opcode 0x0f 81
 940         void I386OP_D(jnp_rel32)();         // Opcode 0x0f 8b
 941         void I386OP_D(jns_rel32)();         // Opcode 0x0f 89
 942         void I386OP_D(jnz_rel32)();         // Opcode 0x0f 85
 943         void I386OP_D(jo_rel32)();          // Opcode 0x0f 80
 944         void I386OP_D(jp_rel32)();          // Opcode 0x0f 8a
 945         void I386OP_D(js_rel32)();          // Opcode 0x0f 88
 946         void I386OP_D(jz_rel32)();          // Opcode 0x0f 84
 947         void I386OP_D(jcxz32)();            // Opcode 0xe3
 948         void I386OP_D(jmp_rel32)();         // Opcode 0xe9
 949         void I386OP_D(jmp_abs32)();         // Opcode 0xea
 950         void I386OP_D(lea32)();             // Opcode 0x8d
 951         void I386OP_D(enter32)();           // Opcode 0xc8
 952         void I386OP_D(leave32)();           // Opcode 0xc9
 953         void I386OP_D(lodsd)();             // Opcode 0xad
 954         void I386OP_D(loop32)();            // Opcode 0xe2
 955         void I386OP_D(loopne32)();          // Opcode 0xe0
 956         void I386OP_D(loopz32)();           // Opcode 0xe1
 957         void I386OP_D(mov_rm32_r32)();      // Opcode 0x89
 958         void I386OP_D(mov_r32_rm32)();      // Opcode 0x8b
 959         void I386OP_D(mov_rm32_i32)();      // Opcode 0xc7
 960         void I386OP_D(mov_eax_m32)();       // Opcode 0xa1
 961         void I386OP_D(mov_m32_eax)();       // Opcode 0xa3
 962         void I386OP_D(mov_eax_i32)();       // Opcode 0xb8
 963         void I386OP_D(mov_ecx_i32)();       // Opcode 0xb9
 964         void I386OP_D(mov_edx_i32)();       // Opcode 0xba
 965         void I386OP_D(mov_ebx_i32)();       // Opcode 0xbb
 966         void I386OP_D(mov_esp_i32)();       // Opcode 0xbc
 967         void I386OP_D(mov_ebp_i32)();       // Opcode 0xbd
 968         void I386OP_D(mov_esi_i32)();       // Opcode 0xbe
 969         void I386OP_D(mov_edi_i32)();       // Opcode 0xbf
 970         void I386OP_D(movsd)();             // Opcode 0xa5
 971         void I386OP_D(movsx_r32_rm8)();     // Opcode 0x0f be
 972         void I386OP_D(movsx_r32_rm16)();    // Opcode 0x0f bf
 973         void I386OP_D(movzx_r32_rm8)();     // Opcode 0x0f b6
 974         void I386OP_D(movzx_r32_rm16)();    // Opcode 0x0f b7
 975         void I386OP_D(or_rm32_r32)();       // Opcode 0x09
 976         void I386OP_D(or_r32_rm32)();       // Opcode 0x0b
 977         void I386OP_D(or_eax_i32)();        // Opcode 0x0d
 978         void I386OP_D(out_eax_i8)();        // Opcode 0xe7
 979         void I386OP_D(out_eax_dx)();        // Opcode 0xef
 980         void I386OP_D(pop_eax)();           // Opcode 0x58
 981         void I386OP_D(pop_ecx)();           // Opcode 0x59
 982         void I386OP_D(pop_edx)();           // Opcode 0x5a
 983         void I386OP_D(pop_ebx)();           // Opcode 0x5b
 984         void I386OP_D(pop_esp)();           // Opcode 0x5c
 985         void I386OP_D(pop_ebp)();           // Opcode 0x5d
 986         void I386OP_D(pop_esi)();           // Opcode 0x5e
 987         void I386OP_D(pop_edi)();           // Opcode 0x5f
 988         void I386OP_D(pop_ds32)();          // Opcode 0x1f
 989         void I386OP_D(pop_es32)();          // Opcode 0x07
 990         void I386OP_D(pop_fs32)();          // Opcode 0x0f a1
 991         void I386OP_D(pop_gs32)();          // Opcode 0x0f a9
 992         void I386OP_D(pop_ss32)();          // Opcode 0x17
 993         void I386OP_D(pop_rm32)();          // Opcode 0x8f
 994         void I386OP_D(popad)();             // Opcode 0x61
 995         void I386OP_D(popfd)();             // Opcode 0x9d
 996         void I386OP_D(push_eax)();          // Opcode 0x50
 997         void I386OP_D(push_ecx)();          // Opcode 0x51
 998         void I386OP_D(push_edx)();          // Opcode 0x52
 999         void I386OP_D(push_ebx)();          // Opcode 0x53
1000         void I386OP_D(push_esp)();          // Opcode 0x54
1001         void I386OP_D(push_ebp)();          // Opcode 0x55
1002         void I386OP_D(push_esi)();          // Opcode 0x56
1003         void I386OP_D(push_edi)();          // Opcode 0x57
1004         void I386OP_D(push_cs32)();         // Opcode 0x0e
1005         void I386OP_D(push_ds32)();         // Opcode 0x1e
1006         void I386OP_D(push_es32)();         // Opcode 0x06
1007         void I386OP_D(push_fs32)();         // Opcode 0x0f a0
1008         void I386OP_D(push_gs32)();         // Opcode 0x0f a8
1009         void I386OP_D(push_ss32)();         // Opcode 0x16
1010         void I386OP_D(push_i32)();          // Opcode 0x68
1011         void I386OP_D(pushad)();            // Opcode 0x60
1012         void I386OP_D(pushfd)();            // Opcode 0x9c
1013         void I386OP_D(ret_near32_i16)();    // Opcode 0xc2
1014         void I386OP_D(ret_near32)();        // Opcode 0xc3
1015         void I386OP_D(sbb_rm32_r32)();      // Opcode 0x19
1016         void I386OP_D(sbb_r32_rm32)();      // Opcode 0x1b
1017         void I386OP_D(sbb_eax_i32)();       // Opcode 0x1d
1018         void I386OP_D(scasd)();             // Opcode 0xaf
1019         void I386OP_D(shld32_i8)();         // Opcode 0x0f a4
1020         void I386OP_D(shld32_cl)();         // Opcode 0x0f a5
1021         void I386OP_D(shrd32_i8)();         // Opcode 0x0f ac
1022         void I386OP_D(shrd32_cl)();         // Opcode 0x0f ad
1023         void I386OP_D(stosd)();             // Opcode 0xab
1024         void I386OP_D(sub_rm32_r32)();      // Opcode 0x29
1025         void I386OP_D(sub_r32_rm32)();      // Opcode 0x2b
1026         void I386OP_D(sub_eax_i32)();       // Opcode 0x2d
1027         void I386OP_D(test_eax_i32)();      // Opcode 0xa9
1028         void I386OP_D(test_rm32_r32)();     // Opcode 0x85
1029         void I386OP_D(xchg_eax_ecx)();      // Opcode 0x91
1030         void I386OP_D(xchg_eax_edx)();      // Opcode 0x92
1031         void I386OP_D(xchg_eax_ebx)();      // Opcode 0x93
1032         void I386OP_D(xchg_eax_esp)();      // Opcode 0x94
1033         void I386OP_D(xchg_eax_ebp)();      // Opcode 0x95
1034         void I386OP_D(xchg_eax_esi)();      // Opcode 0x96
1035         void I386OP_D(xchg_eax_edi)();      // Opcode 0x97
1036         void I386OP_D(xchg_r32_rm32)();     // Opcode 0x87
1037         void I386OP_D(xor_rm32_r32)();      // Opcode 0x31
1038         void I386OP_D(xor_r32_rm32)();      // Opcode 0x33
1039         void I386OP_D(xor_eax_i32)();       // Opcode 0x35
1040         void I386OP_D(group81_32)();        // Opcode 0x81
1041         void I386OP_D(group83_32)();        // Opcode 0x83
1042         void I386OP_D(groupC1_32)();        // Opcode 0xc1
1043         void I386OP_D(groupD1_32)();        // Opcode 0xd1
1044         void I386OP_D(groupD3_32)();        // Opcode 0xd3
1045         void I386OP_D(groupF7_32)();        // Opcode 0xf7
1046         void I386OP_D(groupFF_32)();        // Opcode 0xff
1047         void I386OP_D(group0F00_32)();          // Opcode 0x0f 00
1048         void I386OP_D(group0F01_32)();      // Opcode 0x0f 01
1049         void I386OP_D(group0FBA_32)();      // Opcode 0x0f ba
1050         void I386OP_D(lar_r32_rm32)();  // Opcode 0x0f 0x02
1051         void I386OP_D(lsl_r32_rm32)();  // Opcode 0x0f 0x03
1052         void I386OP_D(bound_r32_m32_m32)(); // Opcode 0x62
1053         void I386OP_D(retf32)();            // Opcode 0xcb
1054         void I386OP_D(retf_i32)();          // Opcode 0xca
1055         void I386OP_D(load_far_pointer32)( int s);
1056         void I386OP_D(lds32)();             // Opcode 0xc5
1057         void I386OP_D(lss32)();             // Opcode 0x0f 0xb2
1058         void I386OP_D(les32)();             // Opcode 0xc4
1059         void I386OP_D(lfs32)();             // Opcode 0x0f 0xb4
1060         void I386OP_D(lgs32)();             // Opcode 0x0f 0xb5
1061 // i386 other OPS.
1062         void I386OP_D(adc_rm8_r8)();        // Opcode 0x10
1063         void I386OP_D(adc_r8_rm8)();        // Opcode 0x12
1064         void I386OP_D(adc_al_i8)();     // Opcode 0x14
1065         void I386OP_D(add_rm8_r8)();        // Opcode 0x00
1066         void I386OP_D(add_r8_rm8)();        // Opcode 0x02
1067         void I386OP_D(add_al_i8)();     // Opcode 0x04
1068         void I386OP_D(and_rm8_r8)();        // Opcode 0x20
1069         void I386OP_D(and_r8_rm8)();        // Opcode 0x22
1070         void I386OP_D(and_al_i8)();         // Opcode 0x24
1071         void I386OP_D(clc)();               // Opcode 0xf8
1072         void I386OP_D(cld)();               // Opcode 0xfc
1073         void I386OP_D(cli)();               // Opcode 0xfa
1074         void I386OP_D(cmc)();               // Opcode 0xf5
1075         void I386OP_D(cmp_rm8_r8)();        // Opcode 0x38
1076         void I386OP_D(cmp_r8_rm8)();        // Opcode 0x3a
1077         void I386OP_D(cmp_al_i8)();         // Opcode 0x3c
1078         void I386OP_D(cmpsb)();             // Opcode 0xa6
1079         void I386OP_D(in_al_i8)();          // Opcode 0xe4
1080         void I386OP_D(in_al_dx)();          // Opcode 0xec
1081         void I386OP_D(ja_rel8)();           // Opcode 0x77
1082         void I386OP_D(jbe_rel8)();          // Opcode 0x76
1083         void I386OP_D(jc_rel8)();           // Opcode 0x72
1084         void I386OP_D(jg_rel8)();           // Opcode 0x7f
1085         void I386OP_D(jge_rel8)();          // Opcode 0x7d
1086         void I386OP_D(jl_rel8)();           // Opcode 0x7c
1087         void I386OP_D(jle_rel8)();      // Opcode 0x7e
1088         void I386OP_D(jnc_rel8)();          // Opcode 0x73
1089         void I386OP_D(jno_rel8)();          // Opcode 0x71
1090         void I386OP_D(jnp_rel8)();          // Opcode 0x7b
1091         void I386OP_D(jns_rel8)();          // Opcode 0x79
1092         void I386OP_D(jnz_rel8)();          // Opcode 0x75
1093         void I386OP_D(jo_rel8)();           // Opcode 0x70
1094         void I386OP_D(jp_rel8)();           // Opcode 0x7a
1095         void I386OP_D(js_rel8)();           // Opcode 0x78
1096         void I386OP_D(jz_rel8)();           // Opcode 0x74
1097         void I386OP_D(jmp_rel8)();          // Opcode 0xeb
1098         void I386OP_D(lahf)();              // Opcode 0x9f
1099         void I386OP_D(lodsb)();             // Opcode 0xac
1100         void I386OP_D(mov_rm8_r8)();        // Opcode 0x88
1101         void I386OP_D(mov_r8_rm8)();        // Opcode 0x8a
1102         void I386OP_D(mov_rm8_i8)();        // Opcode 0xc6
1103         void I386OP_D(mov_r32_cr)();        // Opcode 0x0f 20
1104         void I386OP_D(mov_r32_dr)();        // Opcode 0x0f 21
1105         void I386OP_D(mov_cr_r32)();        // Opcode 0x0f 22
1106         void I386OP_D(mov_dr_r32)();        // Opcode 0x0f 23
1107         void I386OP_D(mov_al_m8)();         // Opcode 0xa0
1108         void I386OP_D(mov_m8_al)();         // Opcode 0xa2
1109         void I386OP_D(mov_rm16_sreg)();     // Opcode 0x8c
1110         void I386OP_D(mov_sreg_rm16)();     // Opcode 0x8e
1111         void I386OP_D(mov_al_i8)();         // Opcode 0xb0
1112         void I386OP_D(mov_cl_i8)();         // Opcode 0xb1
1113         void I386OP_D(mov_dl_i8)();         // Opcode 0xb2
1114         void I386OP_D(mov_bl_i8)();         // Opcode 0xb3
1115         void I386OP_D(mov_ah_i8)();         // Opcode 0xb4
1116         void I386OP_D(mov_ch_i8)();         // Opcode 0xb5
1117         void I386OP_D(mov_dh_i8)();         // Opcode 0xb6
1118         void I386OP_D(mov_bh_i8)();         // Opcode 0xb7
1119         void I386OP_D(movsb)();             // Opcode 0xa4
1120         void I386OP_D(or_rm8_r8)();         // Opcode 0x08
1121         void I386OP_D(or_r8_rm8)();         // Opcode 0x0a
1122         void I386OP_D(or_al_i8)();          // Opcode 0x0c
1123         void I386OP_D(out_al_i8)();         // Opcode 0xe6
1124         void I386OP_D(out_al_dx)();         // Opcode 0xee
1125         void I386OP_D(arpl)();           // Opcode 0x63
1126         void I386OP_D(push_i8)();           // Opcode 0x6a
1127         void I386OP_D(ins_generic)( int size);
1128         void I386OP_D(insb)();              // Opcode 0x6c
1129         void I386OP_D(insw)();              // Opcode 0x6d
1130         void I386OP_D(insd)();              // Opcode 0x6d
1131         void I386OP_D(outs_generic)( int size);
1132         void I386OP_D(outsb)();             // Opcode 0x6e
1133         void I386OP_D(outsw)();             // Opcode 0x6f
1134         void I386OP_D(outsd)();             // Opcode 0x6f
1135         void I386OP_D(repeat)( int invert_flag);
1136         void I386OP_D(rep)();               // Opcode 0xf3
1137         void I386OP_D(repne)();             // Opcode 0xf2
1138         void I386OP_D(sahf)();              // Opcode 0x9e
1139         void I386OP_D(sbb_rm8_r8)();        // Opcode 0x18
1140         void I386OP_D(sbb_r8_rm8)();        // Opcode 0x1a
1141         void I386OP_D(sbb_al_i8)();         // Opcode 0x1c
1142         void I386OP_D(scasb)();             // Opcode 0xae
1143         void I386OP_D(setalc)();            // Opcode 0xd6 (undocumented)
1144         void I386OP_D(seta_rm8)();          // Opcode 0x0f 97
1145         void I386OP_D(setbe_rm8)();         // Opcode 0x0f 96
1146         void I386OP_D(setc_rm8)();          // Opcode 0x0f 92
1147         void I386OP_D(setg_rm8)();          // Opcode 0x0f 9f
1148         void I386OP_D(setge_rm8)();         // Opcode 0x0f 9d
1149         void I386OP_D(setl_rm8)();          // Opcode 0x0f 9c
1150         void I386OP_D(setle_rm8)();         // Opcode 0x0f 9e
1151         void I386OP_D(setnc_rm8)();         // Opcode 0x0f 93
1152         void I386OP_D(setno_rm8)();         // Opcode 0x0f 91
1153         void I386OP_D(setnp_rm8)();         // Opcode 0x0f 9b
1154         void I386OP_D(setns_rm8)();         // Opcode 0x0f 99
1155         void I386OP_D(setnz_rm8)();         // Opcode 0x0f 95
1156         void I386OP_D(seto_rm8)();          // Opcode 0x0f 90
1157         void I386OP_D(setp_rm8)();          // Opcode 0x0f 9a
1158         void I386OP_D(sets_rm8)();          // Opcode 0x0f 98
1159         void I386OP_D(setz_rm8)();          // Opcode 0x0f 94
1160         void I386OP_D(stc)();               // Opcode 0xf9
1161         void I386OP_D(std)();               // Opcode 0xfd
1162         void I386OP_D(sti)();               // Opcode 0xfb
1163         void I386OP_D(stosb)();             // Opcode 0xaa
1164         void I386OP_D(sub_rm8_r8)();        // Opcode 0x28
1165         void I386OP_D(sub_r8_rm8)();        // Opcode 0x2a
1166         void I386OP_D(sub_al_i8)();         // Opcode 0x2c
1167         void I386OP_D(test_al_i8)();        // Opcode 0xa8
1168         void I386OP_D(test_rm8_r8)();       // Opcode 0x84
1169         void I386OP_D(xchg_r8_rm8)();       // Opcode 0x86
1170         void I386OP_D(xor_rm8_r8)();        // Opcode 0x30
1171         void I386OP_D(xor_r8_rm8)();        // Opcode 0x32
1172         void I386OP_D(xor_al_i8)();         // Opcode 0x34
1173         void I386OP_D(group80_8)();         // Opcode 0x80
1174         void I386OP_D(groupC0_8)();         // Opcode 0xc0
1175         void I386OP_D(groupD0_8)();         // Opcode 0xd0
1176         void I386OP_D(groupD2_8)();         // Opcode 0xd2
1177         void I386OP_D(groupF6_8)();         // Opcode 0xf6
1178         void I386OP_D(groupFE_8)();         // Opcode 0xfe
1179         void I386OP_D(segment_CS)();        // Opcode 0x2e
1180         void I386OP_D(segment_DS)();        // Opcode 0x3e
1181         void I386OP_D(segment_ES)();        // Opcode 0x26
1182         void I386OP_D(segment_FS)();        // Opcode 0x64
1183         void I386OP_D(segment_GS)();        // Opcode 0x65
1184         void I386OP_D(segment_SS)();        // Opcode 0x36
1185         void I386OP_D(operand_size)();      // Opcode prefix 0x66
1186         void I386OP_D(address_size)();      // Opcode 0x67
1187         void I386OP_D(nop)();               // Opcode 0x90
1188         void I386OP_D(int3)();              // Opcode 0xcc
1189         void I386OP_D(int)();               // Opcode 0xcd
1190         void I386OP_D(into)();              // Opcode 0xce
1191         void I386OP_D(escape)();            // Opcodes 0xd8 - 0xdf
1192         void I386OP_D(hlt)();               // Opcode 0xf4
1193         void I386OP_D(decimal_adjust)(int direction);
1194         void I386OP_D(daa)();               // Opcode 0x27
1195         void I386OP_D(das)();               // Opcode 0x2f
1196         void I386OP_D(aaa)();               // Opcode 0x37
1197         void I386OP_D(aas)();               // Opcode 0x3f
1198         void I386OP_D(aad)();               // Opcode 0xd5
1199         void I386OP_D(aam)();               // Opcode 0xd4
1200         void I386OP_D(clts)();              // Opcode 0x0f 0x06
1201         void I386OP_D(wait)();              // Opcode 0x9B
1202         void I386OP_D(lock)();              // Opcode 0xf0
1203         void I386OP_D(mov_r32_tr)();        // Opcode 0x0f 24
1204         void I386OP_D(mov_tr_r32)();        // Opcode 0x0f 26
1205         void I386OP_D(loadall)();       // Opcode 0x0f 0x07 (0x0f 0x05 on 80286), undocumented
1206         void I386OP_D(invalid)();
1207         void I386OP_D(xlat)();          // Opcode 0xd7
1208         bool I386OP_D(pop_seg16)( int segment);
1209         bool I386OP_D(load_far_pointer16)(int s);
1210         bool I386OP_D(pop_seg32)( int segment);
1211 //i486
1212         void I486OP_D(cpuid)();             // Opcode 0x0F A2
1213         void I486OP_D(invd)();              // Opcode 0x0f 08
1214         void I486OP_D(wbinvd)();            // Opcode 0x0f 09
1215         void I486OP_D(cmpxchg_rm8_r8)();    // Opcode 0x0f b0
1216         void I486OP_D(cmpxchg_rm16_r16)();  // Opcode 0x0f b1
1217         void I486OP_D(cmpxchg_rm32_r32)();  // Opcode 0x0f b1
1218         void I486OP_D(xadd_rm8_r8)();   // Opcode 0x0f c0
1219         void I486OP_D(xadd_rm16_r16)(); // Opcode 0x0f c1
1220         void I486OP_D(xadd_rm32_r32)(); // Opcode 0x0f c1
1221         void I486OP_D(group0F01_16)();      // Opcode 0x0f 01
1222         void I486OP_D(group0F01_32)();      // Opcode 0x0f 01
1223         void I486OP_D(bswap_eax)();     // Opcode 0x0f 38
1224         void I486OP_D(bswap_ecx)();     // Opcode 0x0f 39
1225         void I486OP_D(bswap_edx)();     // Opcode 0x0f 3A
1226         void I486OP_D(bswap_ebx)();     // Opcode 0x0f 3B
1227         void I486OP_D(bswap_esp)();     // Opcode 0x0f 3C
1228         void I486OP_D(bswap_ebp)();     // Opcode 0x0f 3D
1229         void I486OP_D(bswap_esi)();     // Opcode 0x0f 3E
1230         void I486OP_D(bswap_edi)();     // Opcode 0x0f 3F
1231         void I486OP_D(mov_cr_r32)();        // Opcode 0x0f 22
1232 //Pentium, MMX, SSE.
1233         void PENTIUMOP_D(rdmsr)();          // Opcode 0x0f 32
1234         void PENTIUMOP_D(wrmsr)();          // Opcode 0x0f 30
1235         void PENTIUMOP_D(rdtsc)();          // Opcode 0x0f 31
1236         void PENTIUMOP_D(ud2)();    // Opcode 0x0f 0b
1237         void PENTIUMOP_D(rsm)();
1238         void PENTIUMOP_D(prefetch_m8)();    // Opcode 0x0f 18
1239         void PENTIUMOP_D(cmovo_r16_rm16)();    // Opcode 0x0f 40
1240         void PENTIUMOP_D(cmovo_r32_rm32)();    // Opcode 0x0f 40
1241         void PENTIUMOP_D(cmovno_r16_rm16)();    // Opcode 0x0f 41
1242         void PENTIUMOP_D(cmovno_r32_rm32)();    // Opcode 0x0f 41
1243         void PENTIUMOP_D(cmovb_r16_rm16)();    // Opcode 0x0f 42
1244         void PENTIUMOP_D(cmovb_r32_rm32)();    // Opcode 0x0f 42
1245         void PENTIUMOP_D(cmovae_r16_rm16)();    // Opcode 0x0f 43
1246         void PENTIUMOP_D(cmovae_r32_rm32)();    // Opcode 0x0f 43
1247         void PENTIUMOP_D(cmove_r16_rm16)();    // Opcode 0x0f 44
1248         void PENTIUMOP_D(cmove_r32_rm32)();    // Opcode 0x0f 44
1249         void PENTIUMOP_D(cmovne_r16_rm16)();    // Opcode 0x0f 45
1250         void PENTIUMOP_D(cmovne_r32_rm32)();    // Opcode 0x0f 45
1251         void PENTIUMOP_D(cmovbe_r16_rm16)();    // Opcode 0x0f 46
1252         void PENTIUMOP_D(cmovbe_r32_rm32)();    // Opcode 0x0f 46
1253         void PENTIUMOP_D(cmova_r16_rm16)();    // Opcode 0x0f 47
1254         void PENTIUMOP_D(cmova_r32_rm32)();    // Opcode 0x0f 47
1255         void PENTIUMOP_D(cmovs_r16_rm16)();    // Opcode 0x0f 48
1256         void PENTIUMOP_D(cmovs_r32_rm32)();    // Opcode 0x0f 48
1257         void PENTIUMOP_D(cmovns_r16_rm16)();    // Opcode 0x0f 49
1258         void PENTIUMOP_D(cmovns_r32_rm32)();    // Opcode 0x0f 49
1259         void PENTIUMOP_D(cmovp_r16_rm16)();    // Opcode 0x0f 4a
1260         void PENTIUMOP_D(cmovp_r32_rm32)();    // Opcode 0x0f 4a
1261         void PENTIUMOP_D(cmovnp_r16_rm16)();    // Opcode 0x0f 4b
1262         void PENTIUMOP_D(cmovnp_r32_rm32)();    // Opcode 0x0f 4b
1263         void PENTIUMOP_D(cmovl_r16_rm16)();    // Opcode 0x0f 4c
1264         void PENTIUMOP_D(cmovl_r32_rm32)();    // Opcode 0x0f 4c
1265         void PENTIUMOP_D(cmovge_r16_rm16)();    // Opcode 0x0f 4d
1266         void PENTIUMOP_D(cmovge_r32_rm32)();    // Opcode 0x0f 4d
1267         void PENTIUMOP_D(cmovle_r16_rm16)();    // Opcode 0x0f 4e
1268         void PENTIUMOP_D(cmovle_r32_rm32)();    // Opcode 0x0f 4e
1269         void PENTIUMOP_D(cmovg_r16_rm16)();    // Opcode 0x0f 4f
1270         void PENTIUMOP_D(cmovg_r32_rm32)();    // Opcode 0x0f 4f
1271         void PENTIUMOP_D(movnti_m16_r16)(); // Opcode 0f c3
1272         void PENTIUMOP_D(movnti_m32_r32)(); // Opcode 0f c3
1273         void PENTIUMOP_D(cmpxchg8b_m64)();  // Opcode 0x0f c7
1274         void PENTIUMOP_D(movntq_m64_r64)(); // Opcode 0f e7
1275         void PENTIUMOP_D(maskmovq_r64_r64)();  // Opcode 0f f7
1276         void SSEOP_D(maskmovdqu_r128_r128)();  // Opcode 66 0f f7
1277         void PENTIUMOP_D(popcnt_r16_rm16)();    // Opcode f3 0f b8
1278         void PENTIUMOP_D(popcnt_r32_rm32)();    // Opcode f3 0f b8
1279         void PENTIUMOP_D(tzcnt_r16_rm16)();
1280         void PENTIUMOP_D(tzcnt_r32_rm32)();
1281         void I386OP_D(cyrix_special)();
1282         void I386OP_D(cyrix_unknown)();
1283         void I386OP_D(cyrix_svdc)();
1284         void I386OP_D(cyrix_rsdc)();
1285         void I386OP_D(cyrix_svldt)();
1286         void I386OP_D(cyrix_rsldt)();
1287         void I386OP_D(cyrix_svts)();
1288         void I386OP_D(cyrix_rsts)();
1289
1290         void MMXOP_D(group_0f71)();  // Opcode 0f 71
1291         void SSEOP_D(group_660f71)();  // Opcode 66 0f 71
1292         void MMXOP_D(group_0f72)();  // Opcode 0f 72
1293         void SSEOP_D(group_660f72)();  // Opcode 66 0f 72
1294         void MMXOP_D(group_0f73)();  // Opcode 0f 73
1295         void SSEOP_D(group_660f73)();  // Opcode 66 0f 73
1296         void MMXOP_D(psrlw_r64_rm64)();  // Opcode 0f d1
1297         void MMXOP_D(psrld_r64_rm64)();  // Opcode 0f d2
1298         void MMXOP_D(psrlq_r64_rm64)();  // Opcode 0f d3
1299         void MMXOP_D(paddq_r64_rm64)();  // Opcode 0f d4
1300         void MMXOP_D(pmullw_r64_rm64)();  // Opcode 0f d5
1301         void MMXOP_D(psubusb_r64_rm64)();  // Opcode 0f d8
1302         void MMXOP_D(psubusw_r64_rm64)();  // Opcode 0f d9
1303         void MMXOP_D(pand_r64_rm64)();  // Opcode 0f db
1304         void MMXOP_D(paddusb_r64_rm64)();  // Opcode 0f dc
1305         void MMXOP_D(paddusw_r64_rm64)();  // Opcode 0f dd
1306         void MMXOP_D(pandn_r64_rm64)();  // Opcode 0f df
1307         void MMXOP_D(psraw_r64_rm64)();  // Opcode 0f e1
1308         void MMXOP_D(psrad_r64_rm64)();  // Opcode 0f e2
1309         void MMXOP_D(pmulhw_r64_rm64)();  // Opcode 0f e5
1310         void MMXOP_D(psubsb_r64_rm64)();  // Opcode 0f e8
1311         void MMXOP_D(psubsw_r64_rm64)();  // Opcode 0f e9
1312         void MMXOP_D(por_r64_rm64)();  // Opcode 0f eb
1313         void MMXOP_D(paddsb_r64_rm64)();  // Opcode 0f ec
1314         void MMXOP_D(paddsw_r64_rm64)();  // Opcode 0f ed
1315         void MMXOP_D(pxor_r64_rm64)();  // Opcode 0f ef
1316         void MMXOP_D(psllw_r64_rm64)();  // Opcode 0f f1
1317         void MMXOP_D(pslld_r64_rm64)();  // Opcode 0f f2
1318         void MMXOP_D(psllq_r64_rm64)();  // Opcode 0f f3
1319         void MMXOP_D(pmaddwd_r64_rm64)();  // Opcode 0f f5
1320         void MMXOP_D(psubb_r64_rm64)();  // Opcode 0f f8
1321         void MMXOP_D(psubw_r64_rm64)();  // Opcode 0f f9
1322         void MMXOP_D(psubd_r64_rm64)();  // Opcode 0f fa
1323         void MMXOP_D(paddb_r64_rm64)();  // Opcode 0f fc
1324         void MMXOP_D(paddw_r64_rm64)();  // Opcode 0f fd
1325         void MMXOP_D(paddd_r64_rm64)();  // Opcode 0f fe
1326         void MMXOP_D(emms)(); // Opcode 0f 77
1327         void MMXOP_D(movd_r64_rm32)(); // Opcode 0f 6e
1328         void MMXOP_D(movq_r64_rm64)(); // Opcode 0f 6f
1329         void MMXOP_D(movd_rm32_r64)(); // Opcode 0f 7e
1330         void MMXOP_D(movq_rm64_r64)(); // Opcode 0f 7f
1331         void MMXOP_D(pcmpeqb_r64_rm64)(); // Opcode 0f 74
1332         void MMXOP_D(pcmpeqw_r64_rm64)(); // Opcode 0f 75
1333         void MMXOP_D(pcmpeqd_r64_rm64)(); // Opcode 0f 76
1334         void MMXOP_D(pshufw_r64_rm64_i8)(); // Opcode 0f 70
1335         void SSEOP_D(punpcklbw_r128_rm128)(); // Opcode 66 0f 60
1336         void SSEOP_D(punpcklwd_r128_rm128)();
1337         void SSEOP_D(punpckldq_r128_rm128)();
1338         void SSEOP_D(punpcklqdq_r128_rm128)();
1339         void MMXOP_D(punpcklbw_r64_r64m32)(); // Opcode 0f 60
1340         void MMXOP_D(punpcklwd_r64_r64m32)(); // Opcode 0f 61
1341         void MMXOP_D(punpckldq_r64_r64m32)(); // Opcode 0f 62
1342         void MMXOP_D(packsswb_r64_rm64)(); // Opcode 0f 63
1343         void MMXOP_D(pcmpgtb_r64_rm64)(); // Opcode 0f 64
1344         void MMXOP_D(pcmpgtw_r64_rm64)(); // Opcode 0f 65
1345         void MMXOP_D(pcmpgtd_r64_rm64)(); // Opcode 0f 66
1346         void MMXOP_D(packuswb_r64_rm64)(); // Opcode 0f 67
1347         void MMXOP_D(punpckhbw_r64_rm64)(); // Opcode 0f 68
1348         void MMXOP_D(punpckhwd_r64_rm64)(); // Opcode 0f 69
1349         void MMXOP_D(punpckhdq_r64_rm64)(); // Opcode 0f 6a
1350         void MMXOP_D(packssdw_r64_rm64)(); // Opcode 0f 6b
1351         void SSEOP_D(group_0fae)();  // Opcode 0f ae
1352         void SSEOP_D(cvttps2dq_r128_rm128)(); // Opcode f3 0f 5b
1353         void SSEOP_D(cvtss2sd_r128_r128m32)(); // Opcode f3 0f 5a
1354         void SSEOP_D(cvttss2si_r32_r128m32)(); // Opcode f3 0f 2c
1355         void SSEOP_D(cvtss2si_r32_r128m32)(); // Opcode f3 0f 2d
1356         void SSEOP_D(cvtsi2ss_r128_rm32)(); // Opcode f3 0f 2a
1357         void SSEOP_D(cvtpi2ps_r128_rm64)(); // Opcode 0f 2a
1358         void SSEOP_D(cvttps2pi_r64_r128m64)(); // Opcode 0f 2c
1359         void SSEOP_D(cvtps2pi_r64_r128m64)(); // Opcode 0f 2d
1360         void SSEOP_D(cvtps2pd_r128_r128m64)(); // Opcode 0f 5a
1361         void SSEOP_D(cvtdq2ps_r128_rm128)(); // Opcode 0f 5b
1362         void SSEOP_D(cvtdq2pd_r128_r128m64)(); // Opcode f3 0f e6
1363         void SSEOP_D(movss_r128_rm128)(); // Opcode f3 0f 10
1364         void SSEOP_D(movss_rm128_r128)(); // Opcode f3 0f 11
1365         void SSEOP_D(movsldup_r128_rm128)(); // Opcode f3 0f 12
1366         void SSEOP_D(movshdup_r128_rm128)(); // Opcode f3 0f 16
1367         void SSEOP_D(movaps_r128_rm128)(); // Opcode 0f 28
1368         void SSEOP_D(movaps_rm128_r128)(); // Opcode 0f 29
1369         void SSEOP_D(movups_r128_rm128)(); // Opcode 0f 10
1370         void SSEOP_D(movupd_r128_rm128)(); // Opcode 66 0f 10
1371         void SSEOP_D(movups_rm128_r128)(); // Opcode 0f 11
1372         void SSEOP_D(movupd_rm128_r128)(); // Opcode 66 0f 11
1373         void SSEOP_D(movlps_r128_m64)(); // Opcode 0f 12
1374         void SSEOP_D(movlpd_r128_m64)(); // Opcode 66 0f 12
1375         void SSEOP_D(movlps_m64_r128)(); // Opcode 0f 13
1376         void SSEOP_D(movlpd_m64_r128)(); // Opcode 66 0f 13
1377         void SSEOP_D(movhps_r128_m64)(); // Opcode 0f 16
1378         void SSEOP_D(movhpd_r128_m64)(); // Opcode 66 0f 16
1379         void SSEOP_D(movhps_m64_r128)(); // Opcode 0f 17
1380         void SSEOP_D(movhpd_m64_r128)(); // Opcode 66 0f 17
1381         void SSEOP_D(movntps_m128_r128)(); // Opcode 0f 2b
1382         void SSEOP_D(movmskps_r16_r128)(); // Opcode 0f 50
1383         void SSEOP_D(movmskps_r32_r128)(); // Opcode 0f 50
1384         void SSEOP_D(movmskpd_r32_r128)(); // Opcode 66 0f 50
1385         void SSEOP_D(movq2dq_r128_r64)(); // Opcode f3 0f d6
1386         void SSEOP_D(movdqu_r128_rm128)(); // Opcode f3 0f 6f
1387         void SSEOP_D(movdqu_rm128_r128)(); // Opcode f3 0f 7f
1388         void SSEOP_D(movd_m128_rm32)(); // Opcode 66 0f 6e
1389         void SSEOP_D(movdqa_m128_rm128)(); // Opcode 66 0f 6f
1390         void SSEOP_D(movq_r128_r128m64)(); // Opcode f3 0f 7e
1391         void SSEOP_D(movd_rm32_r128)(); // Opcode 66 0f 7e
1392         void SSEOP_D(movdqa_rm128_r128)(); // Opcode 66 0f 7f
1393         void SSEOP_D(pmovmskb_r16_r64)(); // Opcode 0f d7
1394         void SSEOP_D(pmovmskb_r32_r64)(); // Opcode 0f d7
1395         void SSEOP_D(pmovmskb_r32_r128)(); // Opcode 66 0f d7
1396         void SSEOP_D(xorps)(); // Opcode 0f 57
1397         void SSEOP_D(xorpd_r128_rm128)(); // Opcode 66 0f 57
1398         void SSEOP_D(addps)(); // Opcode 0f 58
1399         void SSEOP_D(sqrtps_r128_rm128)(); // Opcode 0f 51
1400         void SSEOP_D(rsqrtps_r128_rm128)(); // Opcode 0f 52
1401         void SSEOP_D(rcpps_r128_rm128)(); // Opcode 0f 53
1402         void SSEOP_D(andps_r128_rm128)(); // Opcode 0f 54
1403         void SSEOP_D(andpd_r128_rm128)(); // Opcode 66 0f 54
1404         void SSEOP_D(andnps_r128_rm128)(); // Opcode 0f 55
1405         void SSEOP_D(andnpd_r128_rm128)(); // Opcode 66 0f 55
1406         void SSEOP_D(orps_r128_rm128)(); // Opcode 0f 56
1407         void SSEOP_D(orpd_r128_rm128)(); // Opcode 66 0f 56
1408         void SSEOP_D(mulps)(); // Opcode 0f 59 ????
1409         void SSEOP_D(subps)(); // Opcode 0f 5c
1410         void SSEOP_D(minps)(); // Opcode 0f 5d
1411         void SSEOP_D(divps)(); // Opcode 0f 5e
1412         void SSEOP_D(maxps)(); // Opcode 0f 5f
1413         void SSEOP_D(maxss_r128_r128m32)(); // Opcode f3 0f 5f
1414         void SSEOP_D(addss)(); // Opcode f3 0f 58
1415         void SSEOP_D(subss)(); // Opcode f3 0f 5c
1416         void SSEOP_D(mulss)(); // Opcode f3 0f 5e
1417         void SSEOP_D(divss)(); // Opcode 0f 59
1418         void SSEOP_D(rcpss_r128_r128m32)(); // Opcode f3 0f 53
1419         void SSEOP_D(sqrtss_r128_r128m32)(); // Opcode f3 0f 51
1420         void SSEOP_D(rsqrtss_r128_r128m32)(); // Opcode f3 0f 52
1421         void SSEOP_D(minss_r128_r128m32)(); // Opcode f3 0f 5d
1422         void SSEOP_D(comiss_r128_r128m32)(); // Opcode 0f 2f
1423         void SSEOP_D(comisd_r128_r128m64)(); // Opcode 66 0f 2f
1424         void SSEOP_D(ucomiss_r128_r128m32)(); // Opcode 0f 2e
1425         void SSEOP_D(ucomisd_r128_r128m64)(); // Opcode 66 0f 2e
1426         void SSEOP_D(shufps)(); // Opcode 0f c6
1427         void SSEOP_D(shufpd_r128_rm128_i8)(); // Opcode 66 0f c6
1428         void SSEOP_D(unpcklps_r128_rm128)(); // Opcode 0f 14
1429         void SSEOP_D(unpcklpd_r128_rm128)(); // Opcode 66 0f 14
1430         void SSEOP_D(unpckhps_r128_rm128)(); // Opcode 0f 15
1431         void SSEOP_D(unpckhpd_r128_rm128)(); // Opcode 66 0f 15
1432         void SSEOP_D(predicate_compare_single)(UINT8 imm8, XMM_REG d, XMM_REG s);
1433         void SSEOP_D(predicate_compare_double)(UINT8 imm8, XMM_REG d, XMM_REG s);
1434         void SSEOP_D(predicate_compare_single_scalar)(UINT8 imm8, XMM_REG d, XMM_REG s);
1435         void SSEOP_D(predicate_compare_double_scalar)(UINT8 imm8, XMM_REG d, XMM_REG s);
1436         void SSEOP_D(cmpps_r128_rm128_i8)(); // Opcode 0f c2
1437         void SSEOP_D(cmppd_r128_rm128_i8)(); // Opcode 66 0f c2
1438         void SSEOP_D(cmpss_r128_r128m32_i8)(); // Opcode f3 0f c2
1439         void SSEOP_D(pinsrw_r64_r16m16_i8)(); // Opcode 0f c4, 16bit register
1440         void SSEOP_D(pinsrw_r64_r32m16_i8)(); // Opcode 0f c4, 32bit register
1441         void SSEOP_D(pinsrw_r128_r32m16_i8)(); // Opcode 66 0f c4
1442         void SSEOP_D(pextrw_r16_r64_i8)(); // Opcode 0f c5
1443         void SSEOP_D(pextrw_r32_r64_i8)(); // Opcode 0f c5
1444         void SSEOP_D(pextrw_reg_r128_i8)(); // Opcode 66 0f c5
1445         void SSEOP_D(pminub_r64_rm64)(); // Opcode 0f da
1446         void SSEOP_D(pminub_r128_rm128)(); // Opcode 66 0f da
1447         void SSEOP_D(pmaxub_r64_rm64)(); // Opcode 0f de
1448         void SSEOP_D(pavgb_r64_rm64)(); // Opcode 0f e0
1449         void SSEOP_D(pavgw_r64_rm64)(); // Opcode 0f e3
1450         void SSEOP_D(pmulhuw_r64_rm64)();  // Opcode 0f e4
1451         void SSEOP_D(pminsw_r64_rm64)(); // Opcode 0f ea
1452         void SSEOP_D(pmaxsw_r64_rm64)(); // Opcode 0f ee
1453         void SSEOP_D(pmuludq_r64_rm64)(); // Opcode 0f f4
1454         void SSEOP_D(pmuludq_r128_rm128)(); // Opcode 66 0f f4
1455         void SSEOP_D(psadbw_r64_rm64)(); // Opcode 0f f6
1456         void SSEOP_D(psubq_r64_rm64)();  // Opcode 0f fb
1457         void SSEOP_D(psubq_r128_rm128)();  // Opcode 66 0f fb
1458         void SSEOP_D(pshufd_r128_rm128_i8)(); // Opcode 66 0f 70
1459         void SSEOP_D(pshuflw_r128_rm128_i8)(); // Opcode f2 0f 70
1460         void SSEOP_D(pshufhw_r128_rm128_i8)(); // Opcode f3 0f 70
1461         void SSEOP_D(packsswb_r128_rm128)(); // Opcode 66 0f 63
1462         void SSEOP_D(packssdw_r128_rm128)(); // Opcode 66 0f 6b
1463         void SSEOP_D(pcmpgtb_r128_rm128)(); // Opcode 66 0f 64
1464         void SSEOP_D(pcmpgtw_r128_rm128)(); // Opcode 66 0f 65
1465         void SSEOP_D(pcmpgtd_r128_rm128)(); // Opcode 66 0f 66
1466         void SSEOP_D(packuswb_r128_rm128)(); // Opcode 66 0f 67
1467         void SSEOP_D(punpckhbw_r128_rm128)(); // Opcode 66 0f 68
1468         void SSEOP_D(punpckhwd_r128_rm128)(); // Opcode 66 0f 69
1469         void SSEOP_D(unpckhdq_r128_rm128)(); // Opcode 66 0f 6a
1470         void SSEOP_D(punpckhqdq_r128_rm128)(); // Opcode 66 0f 6d
1471         void SSEOP_D(pcmpeqb_r128_rm128)(); // Opcode 66 0f 74
1472         void SSEOP_D(pcmpeqw_r128_rm128)(); // Opcode 66 0f 75
1473         void SSEOP_D(pcmpeqd_r128_rm128)(); // Opcode 66 0f 76
1474         void SSEOP_D(paddq_r128_rm128)();  // Opcode 66 0f d4
1475         void SSEOP_D(pmullw_r128_rm128)();  // Opcode 66 0f d5
1476         void SSEOP_D(paddb_r128_rm128)();  // Opcode 66 0f fc
1477         void SSEOP_D(paddw_r128_rm128)();  // Opcode 66 0f fd
1478         void SSEOP_D(paddd_r128_rm128)();  // Opcode 66 0f fe
1479         void SSEOP_D(psubusb_r128_rm128)();  // Opcode 66 0f d8
1480         void SSEOP_D(psubusw_r128_rm128)();  // Opcode 66 0f d9
1481         void SSEOP_D(pand_r128_rm128)();  // Opcode 66 0f db
1482         void SSEOP_D(pandn_r128_rm128)();  // Opcode 66 0f df
1483         void SSEOP_D(paddusb_r128_rm128)();  // Opcode 66 0f dc
1484         void SSEOP_D(paddusw_r128_rm128)();  // Opcode 66 0f dd
1485         void SSEOP_D(pmaxub_r128_rm128)(); // Opcode 66 0f de
1486         void SSEOP_D(pmulhuw_r128_rm128)();  // Opcode 66 0f e4
1487         void SSEOP_D(pmulhw_r128_rm128)();  // Opcode 66 0f e5
1488         void SSEOP_D(psubsb_r128_rm128)();  // Opcode 66 0f e8
1489         void SSEOP_D(psubsw_r128_rm128)();  // Opcode 66 0f e9
1490         void SSEOP_D(pminsw_r128_rm128)(); // Opcode 66 0f ea
1491         void SSEOP_D(pmaxsw_r128_rm128)(); // Opcode 66 0f ee
1492         void SSEOP_D(paddsb_r128_rm128)();  // Opcode 66 0f ec
1493         void SSEOP_D(paddsw_r128_rm128)();  // Opcode 66 0f ed
1494         void SSEOP_D(por_r128_rm128)();  // Opcode 66 0f eb
1495         void SSEOP_D(pxor_r128_rm128)();  // Opcode 66 0f ef
1496         void SSEOP_D(pmaddwd_r128_rm128)();  // Opcode 66 0f f5
1497         void SSEOP_D(psubb_r128_rm128)();  // Opcode 66 0f f8
1498         void SSEOP_D(psubw_r128_rm128)();  // Opcode 66 0f f9
1499         void SSEOP_D(psubd_r128_rm128)();  // Opcode 66 0f fa
1500         void SSEOP_D(psadbw_r128_rm128)(); // Opcode 66 0f f6
1501         void SSEOP_D(pavgb_r128_rm128)(); // Opcode 66 0f e0
1502         void SSEOP_D(pavgw_r128_rm128)(); // Opcode 66 0f e3
1503         void SSEOP_D(psrlw_r128_rm128)();  // Opcode 66 0f d1
1504         void SSEOP_D(psrld_r128_rm128)();  // Opcode 66 0f d2
1505         void SSEOP_D(psrlq_r128_rm128)();  // Opcode 66 0f d3
1506         void SSEOP_D(psllw_r128_rm128)();  // Opcode 66 0f f1
1507         void SSEOP_D(pslld_r128_rm128)();  // Opcode 66 0f f2
1508         void SSEOP_D(psllq_r128_rm128)();  // Opcode 66 0f f3
1509         void SSEOP_D(psraw_r128_rm128)();  // Opcode 66 0f e1
1510         void SSEOP_D(psrad_r128_rm128)();  // Opcode 66 0f e2
1511         void SSEOP_D(movntdq_m128_r128)();  // Opcode 66 0f e7
1512         void SSEOP_D(cvttpd2dq_r128_rm128)();  // Opcode 66 0f e6
1513         void SSEOP_D(movq_r128m64_r128)();  // Opcode 66 0f d6
1514         void SSEOP_D(addsubpd_r128_rm128)();  // Opcode 66 0f d0
1515         void SSEOP_D(haddpd_r128_rm128)();  // Opcode 66 0f 7c
1516         void SSEOP_D(hsubpd_r128_rm128)();  // Opcode 66 0f 7d
1517         void SSEOP_D(sqrtpd_r128_rm128)();  // Opcode 66 0f 51
1518         void SSEOP_D(cvtpi2pd_r128_rm64)();  // Opcode 66 0f 2a
1519         void SSEOP_D(cvttpd2pi_r64_rm128)();  // Opcode 66 0f 2c
1520         void SSEOP_D(cvtpd2pi_r64_rm128)();  // Opcode 66 0f 2d
1521         void SSEOP_D(cvtpd2ps_r128_rm128)();  // Opcode 66 0f 5a
1522         void SSEOP_D(cvtps2dq_r128_rm128)();  // Opcode 66 0f 5b
1523         void SSEOP_D(addpd_r128_rm128)();  // Opcode 66 0f 58
1524         void SSEOP_D(mulpd_r128_rm128)();  // Opcode 66 0f 59
1525         void SSEOP_D(subpd_r128_rm128)();  // Opcode 66 0f 5c
1526         void SSEOP_D(minpd_r128_rm128)();  // Opcode 66 0f 5d
1527         void SSEOP_D(divpd_r128_rm128)();  // Opcode 66 0f 5e
1528         void SSEOP_D(maxpd_r128_rm128)();  // Opcode 66 0f 5f
1529         void SSEOP_D(movntpd_m128_r128)();  // Opcode 66 0f 2b
1530         void SSEOP_D(movapd_r128_rm128)();  // Opcode 66 0f 28
1531         void SSEOP_D(movapd_rm128_r128)();  // Opcode 66 0f 29
1532         void SSEOP_D(movsd_r128_r128m64)(); // Opcode f2 0f 10
1533         void SSEOP_D(movsd_r128m64_r128)(); // Opcode f2 0f 11
1534         void SSEOP_D(movddup_r128_r128m64)(); // Opcode f2 0f 12
1535         void SSEOP_D(cvtsi2sd_r128_rm32)(); // Opcode f2 0f 2a
1536         void SSEOP_D(cvttsd2si_r32_r128m64)(); // Opcode f2 0f 2c
1537         void SSEOP_D(cvtsd2si_r32_r128m64)(); // Opcode f2 0f 2d
1538         void SSEOP_D(sqrtsd_r128_r128m64)(); // Opcode f2 0f 51
1539         void SSEOP_D(addsd_r128_r128m64)(); // Opcode f2 0f 58
1540         void SSEOP_D(mulsd_r128_r128m64)(); // Opcode f2 0f 59
1541         void SSEOP_D(cvtsd2ss_r128_r128m64)(); // Opcode f2 0f 5a
1542         void SSEOP_D(subsd_r128_r128m64)(); // Opcode f2 0f 5c
1543         void SSEOP_D(minsd_r128_r128m64)(); // Opcode f2 0f 5d
1544         void SSEOP_D(divsd_r128_r128m64)(); // Opcode f2 0f 5e
1545         void SSEOP_D(maxsd_r128_r128m64)(); // Opcode f2 0f 5f
1546         void SSEOP_D(haddps_r128_rm128)(); // Opcode f2 0f 7c
1547         void SSEOP_D(hsubps_r128_rm128)(); // Opcode f2 0f 7d
1548         void SSEOP_D(cmpsd_r128_r128m64_i8)(); // Opcode f2 0f c2
1549         void SSEOP_D(addsubps_r128_rm128)(); // Opcode f2 0f d0
1550         void SSEOP_D(movdq2q_r64_r128)(); // Opcode f2 0f d6
1551         void SSEOP_D(cvtpd2dq_r128_rm128)(); // Opcode f2 0f e6
1552         void SSEOP_D(lddqu_r128_m128)(); // Opcode f2 0f f0
1553         // x87 FPU
1554         void x87_write_stack( int i, floatx80 value, int update_tag);
1555         void x87_reset();
1556         void x87_fadd_m32real(UINT8 modrm);
1557         void x87_fadd_m64real(UINT8 modrm);
1558         void x87_fadd_st_sti(UINT8 modrm);
1559         void x87_fadd_sti_st(UINT8 modrm);
1560         void x87_faddp(UINT8 modrm);
1561         void x87_fiadd_m32int(UINT8 modrm);
1562         void x87_fiadd_m16int(UINT8 modrm);
1563         void x87_fsub_m32real(UINT8 modrm);
1564         void x87_fsub_m64real(UINT8 modrm);
1565         void x87_fsub_st_sti(UINT8 modrm);
1566         void x87_fsub_sti_st( UINT8 modrm);
1567         void x87_fsubp(UINT8 modrm);
1568         void x87_fisub_m32int(UINT8 modrm);
1569         void x87_fisub_m16int(UINT8 modrm);
1570         void x87_fsubr_m32real(UINT8 modrm);
1571         void x87_fsubr_m64real(UINT8 modrm);
1572         void x87_fsubr_st_sti(UINT8 modrm);
1573         void x87_fsubr_sti_st(UINT8 modrm);
1574         void x87_fsubrp(UINT8 modrm);
1575         void x87_fisubr_m32int(UINT8 modrm);
1576         void x87_fisubr_m16int(UINT8 modrm);
1577         void x87_fdiv_m32real(UINT8 modrm);
1578         void x87_fdiv_m64real(UINT8 modrm);
1579         void x87_fdiv_st_sti(UINT8 modrm);
1580         void x87_fdiv_sti_st(UINT8 modrm);
1581         void x87_fdivp(UINT8 modrm);
1582         void x87_fidiv_m32int(UINT8 modrm);
1583         void x87_fidiv_m16int(UINT8 modrm);
1584         void x87_fdivr_m32real(UINT8 modrm);
1585         void x87_fdivr_m64real(UINT8 modrm);
1586         void x87_fdivr_st_sti(UINT8 modrm);
1587         void x87_fdivr_sti_st(UINT8 modrm);
1588         void x87_fdivrp(UINT8 modrm);
1589         void x87_fidivr_m32int( UINT8 modrm);
1590         void x87_fidivr_m16int( UINT8 modrm);
1591         void x87_fmul_m32real( UINT8 modrm);
1592         void x87_fmul_m64real( UINT8 modrm);
1593         void x87_fmul_st_sti( UINT8 modrm);
1594         void x87_fmul_sti_st( UINT8 modrm);
1595         void x87_fmulp( UINT8 modrm);
1596         void x87_fimul_m32int( UINT8 modrm);
1597         void x87_fimul_m16int( UINT8 modrm);
1598         void x87_fcmovb_sti( UINT8 modrm);
1599         void x87_fcmove_sti( UINT8 modrm);
1600         void x87_fcmovbe_sti( UINT8 modrm);
1601         void x87_fcmovu_sti( UINT8 modrm);
1602         void x87_fcmovnb_sti( UINT8 modrm);
1603         void x87_fcmovne_sti( UINT8 modrm);
1604         void x87_fcmovnbe_sti( UINT8 modrm);
1605         void x87_fcmovnu_sti( UINT8 modrm);
1606         void x87_fprem( UINT8 modrm);
1607         void x87_fprem1( UINT8 modrm);
1608         void x87_fsqrt( UINT8 modrm);
1609         void x87_f2xm1( UINT8 modrm);
1610         void x87_fyl2x( UINT8 modrm);
1611         void x87_fyl2xp1( UINT8 modrm);
1612         void x87_fptan( UINT8 modrm);
1613         void x87_fpatan( UINT8 modrm);
1614         void x87_fsin( UINT8 modrm);
1615         void x87_fcos( UINT8 modrm);
1616         void x87_fsincos( UINT8 modrm);
1617         void x87_fld_m32real( UINT8 modrm);
1618         void x87_fld_m64real( UINT8 modrm);
1619         void x87_fld_m80real( UINT8 modrm);
1620         void x87_fld_sti( UINT8 modrm);
1621         void x87_fild_m16int( UINT8 modrm);
1622         void x87_fild_m32int( UINT8 modrm);
1623         void x87_fild_m64int( UINT8 modrm);
1624         void x87_fbld( UINT8 modrm);
1625         void x87_fst_m32real( UINT8 modrm);
1626         void x87_fst_m64real( UINT8 modrm);
1627         void x87_fst_sti( UINT8 modrm);
1628         void x87_fstp_m32real( UINT8 modrm);
1629         void x87_fstp_m64real( UINT8 modrm);
1630         void x87_fstp_m80real( UINT8 modrm);
1631         void x87_fstp_sti( UINT8 modrm);
1632         void x87_fist_m16int( UINT8 modrm);
1633         void x87_fist_m32int( UINT8 modrm);
1634         void x87_fistp_m16int( UINT8 modrm);
1635         void x87_fistp_m32int( UINT8 modrm);
1636         void x87_fistp_m64int( UINT8 modrm);
1637         void x87_fbstp( UINT8 modrm);
1638         void x87_fld1( UINT8 modrm);
1639         void x87_fldl2t( UINT8 modrm);
1640         void x87_fldl2e( UINT8 modrm);
1641         void x87_fldpi( UINT8 modrm);
1642         void x87_fldlg2( UINT8 modrm);
1643         void x87_fldln2( UINT8 modrm);
1644         void x87_fldz( UINT8 modrm);
1645         void x87_fnop( UINT8 modrm);
1646         void x87_fchs( UINT8 modrm);
1647         void x87_fabs( UINT8 modrm);
1648         void x87_fscale( UINT8 modrm);
1649         void x87_frndint( UINT8 modrm);
1650         void x87_fxtract( UINT8 modrm);
1651         void x87_ftst( UINT8 modrm);
1652         void x87_fxam( UINT8 modrm);
1653         void x87_ficom_m16int( UINT8 modrm);
1654         void x87_ficom_m32int( UINT8 modrm);
1655         void x87_ficomp_m16int( UINT8 modrm);
1656         void x87_ficomp_m32int( UINT8 modrm);
1657         void x87_fcom_m32real( UINT8 modrm);
1658         void x87_fcom_m64real( UINT8 modrm);
1659         void x87_fcom_sti( UINT8 modrm);
1660         void x87_fcomp_m32real( UINT8 modrm);
1661         void x87_fcomp_m64real( UINT8 modrm);
1662         void x87_fcomp_sti( UINT8 modrm);
1663         void x87_fcomi_sti( UINT8 modrm);
1664         void x87_fcomip_sti( UINT8 modrm);
1665         void x87_fucomi_sti( UINT8 modrm);
1666         void x87_fucomip_sti( UINT8 modrm);
1667         void x87_fcompp( UINT8 modrm);
1668         void x87_fucom_sti( UINT8 modrm);
1669         void x87_fucomp_sti( UINT8 modrm);
1670         void x87_fucompp( UINT8 modrm);
1671         void x87_fdecstp( UINT8 modrm);
1672         void x87_fincstp( UINT8 modrm);
1673         void x87_fclex( UINT8 modrm);
1674         void x87_ffree( UINT8 modrm);
1675         void x87_finit( UINT8 modrm);
1676         void x87_fldcw( UINT8 modrm);
1677         void x87_fstcw( UINT8 modrm);
1678         void x87_fldenv( UINT8 modrm);
1679         void x87_fstenv( UINT8 modrm);
1680         void x87_fsave( UINT8 modrm);
1681         void x87_frstor( UINT8 modrm);
1682         void x87_fxch( UINT8 modrm);
1683         void x87_fxch_sti( UINT8 modrm);
1684         void x87_fstsw_ax( UINT8 modrm);
1685         void x87_fstsw_m2byte( UINT8 modrm);
1686         void x87_invalid( UINT8 modrm);
1687         void I386OP_D(x87_group_d8)();
1688         void I386OP_D(x87_group_d9)();
1689         void I386OP_D(x87_group_da)();
1690         void I386OP_D(x87_group_db)();
1691         void I386OP_D(x87_group_dc)();
1692         void I386OP_D(x87_group_dd)();
1693         void I386OP_D(x87_group_de)();
1694         void I386OP_D(x87_group_df)();
1695         void build_x87_opcode_table_d8();
1696         void build_x87_opcode_table_d9();
1697         void build_x87_opcode_table_da();
1698         void build_x87_opcode_table_db();
1699         void build_x87_opcode_table_dc();
1700         void build_x87_opcode_table_dd();
1701         void build_x87_opcode_table_de();
1702         void build_x87_opcode_table_df();
1703         void build_x87_opcode_table();
1704
1705         floatx80 x87_add( floatx80 a, floatx80 b);
1706         floatx80 x87_sub( floatx80 a, floatx80 b);
1707         floatx80 x87_mul( floatx80 a, floatx80 b);
1708         floatx80 x87_div( floatx80 a, floatx80 b);
1709
1710         void I386OP_D(decode_two_byte)();
1711         void I386OP_D(decode_three_byte38)();
1712         void I386OP_D(decode_three_byte3a)();
1713         void I386OP_D(decode_three_byte66)();
1714         void I386OP_D(decode_three_bytef2)();
1715         void I386OP_D(decode_three_bytef3)();
1716         void I386OP_D(decode_four_byte3866)();
1717         void I386OP_D(decode_four_byte3a66)();
1718         void I386OP_D(decode_four_byte3af2)();
1719         void I386OP_D(decode_four_byte38f2)();
1720         void I386OP_D(decode_four_byte38f3)();
1721 protected:
1722
1723         // Inline Utilities.
1724         INLINE INT8 SaturatedSignedWordToSignedByte(INT16 word);
1725         INLINE UINT8 SaturatedSignedWordToUnsignedByte(INT16 word);
1726         INLINE INT16 SaturatedSignedDwordToSignedWord(INT32 dword);
1727         INLINE UINT16 SaturatedSignedDwordToUnsignedWord(INT32 dword);
1728         //
1729         INLINE vtlb_entry get_permissions(UINT32 pte, int wp);
1730         INLINE int translate_address(int pl, int type, UINT32 *address, UINT32 *error);
1731         INLINE UINT32 i386_translate(int segment, UINT32 ip, int rwn);
1732
1733         INLINE UINT8 FETCH();
1734         INLINE UINT16 FETCH16();
1735         INLINE UINT32 FETCH32();
1736
1737         INLINE UINT8 READ8(UINT32 ea);
1738         INLINE UINT8 READ8PL0(UINT32 ea);
1739         INLINE UINT16 READ16(UINT32 ea);
1740         INLINE UINT16 READ16PL0(UINT32 ea);
1741         INLINE UINT32 READ32(UINT32 ea);
1742         INLINE UINT32 READ32PL0(UINT32 ea);
1743         INLINE UINT64 READ64(UINT32 ea);
1744
1745         INLINE void WRITE8(UINT32 ea, UINT8 value);
1746         INLINE void WRITE16(UINT32 ea, UINT16 value);
1747         INLINE void WRITE32(UINT32 ea, UINT32 value);
1748         INLINE void WRITE64(UINT32 ea, UINT64 value);
1749         INLINE void WRITE_TEST(UINT32 ea);
1750
1751         INLINE void WRITEPORT8(offs_t port, UINT8 value);
1752         INLINE void WRITEPORT16(offs_t port, UINT16 value);
1753         INLINE void WRITEPORT32(offs_t port, UINT32 value);
1754         INLINE UINT8 READPORT8( offs_t port);
1755         INLINE UINT16 READPORT16( offs_t port);
1756         INLINE UINT32 READPORT32( offs_t port);
1757
1758         INLINE void PUSH8(UINT8 value);
1759         INLINE UINT8 POP8();
1760         INLINE void PUSH16(UINT16 value);
1761         INLINE UINT16 POP16();
1762         INLINE void PUSH32(UINT32 value);
1763         INLINE void PUSH32SEG(UINT32 value);
1764         INLINE UINT32 POP32();
1765
1766         INLINE UINT8 OR8(UINT8 dst, UINT8 src);
1767         INLINE UINT8 AND8(UINT8 dst, UINT8 src);
1768         INLINE UINT8 XOR8(UINT8 dst, UINT8 src);
1769         INLINE UINT8 SBB8(UINT8 dst, UINT8 src, UINT8 b);
1770         INLINE UINT8 ADC8(UINT8 dst, UINT8 src, UINT8 c);
1771         INLINE UINT8 INC8(UINT8 dst);
1772         INLINE UINT8 DEC8(UINT8 dst);
1773
1774         INLINE UINT16 OR16(UINT16 dst, UINT16 src);
1775         INLINE UINT16 AND16(UINT16 dst, UINT16 src);
1776         INLINE UINT16 XOR16(UINT16 dst, UINT16 src);
1777         INLINE UINT16 SBB16(UINT16 dst, UINT16 src, UINT16 b);
1778         INLINE UINT16 ADC16(UINT16 dst, UINT16 src, UINT8 c);
1779         INLINE UINT16 INC16(UINT16 dst);
1780         INLINE UINT16 DEC16(UINT16 dst);
1781
1782         INLINE UINT32 OR32(UINT32 dst, UINT32 src);
1783         INLINE UINT32 AND32(UINT32 dst, UINT32 src);
1784         INLINE UINT32 XOR32(UINT32 dst, UINT32 src);
1785         INLINE UINT32 SBB32(UINT32 dst, UINT32 src, UINT32 b);
1786         INLINE UINT32 ADC32(UINT32 dst, UINT32 src, UINT32 c);
1787         INLINE UINT32 INC32(UINT32 dst);
1788         INLINE UINT32 DEC32(UINT32 dst);
1789
1790         INLINE UINT64 MSR_READ(UINT32 offset,UINT8 *valid_msr);
1791         INLINE void MSR_WRITE(UINT32 offset, UINT64 data, UINT8 *valid_msr);
1792
1793         INLINE void CHANGE_PC(UINT32 pc);
1794         INLINE void NEAR_BRANCH(INT32 offs);
1795         INLINE void BUMP_SI(int adjustment);
1796         INLINE void BUMP_DI(int adjustment);
1797         INLINE void CYCLES(int x);
1798         INLINE void CYCLES_RM(int modrm, int r, int m);
1799
1800         INLINE void MMXPROLOG();
1801         INLINE void READMMX(UINT32 ea,MMX_REG &r);
1802         INLINE void WRITEMMX(UINT32 ea,MMX_REG &r);
1803         INLINE void READXMM(UINT32 ea,XMM_REG &r);
1804         INLINE void WRITEXMM(UINT32 ea,XMM_REG &r);
1805         INLINE void READXMM_LO64(UINT32 ea,XMM_REG &r);
1806         INLINE void WRITEXMM_LO64(UINT32 ea,XMM_REG &r);
1807         INLINE void READXMM_HI64(UINT32 ea,XMM_REG &r);
1808         INLINE void WRITEXMM_HI64(UINT32 ea,XMM_REG &r);
1809
1810         INLINE flag floatx80_is_quiet_nan(floatx80 a);
1811         INLINE int floatx80_is_zero(floatx80 fx);
1812         INLINE int floatx80_is_inf(floatx80 fx);
1813         INLINE int floatx80_is_denormal(floatx80 fx);
1814         INLINE floatx80 floatx80_abs(floatx80 fx);
1815         INLINE double fx80_to_double(floatx80 fx);
1816         INLINE floatx80 double_to_fx80(double in);
1817         INLINE floatx80 READ80( UINT32 ea);
1818         INLINE void WRITE80( UINT32 ea, floatx80 t);
1819         INLINE void x87_set_stack_top(int top);
1820         INLINE void x87_set_tag(int reg, int tag);
1821         INLINE void x87_set_stack_underflow();
1822         INLINE void x87_set_stack_overflow();
1823         INLINE void x87_write_cw( UINT16 cw);
1824
1825         UINT32 I386OP_D(shift_rotate32)(UINT8 modrm, UINT32 value, UINT8 shift);
1826
1827         UINT64 pentium_msr_read(UINT32 offset,UINT8 *valid_msr);;
1828         void pentium_msr_write(UINT32 offset, UINT64 data, UINT8 *valid_msr);
1829         UINT64 p6_msr_read(UINT32 offset,UINT8 *valid_msr);;
1830         void p6_msr_write(UINT32 offset, UINT64 data, UINT8 *valid_msr);
1831         UINT64 piv_msr_read(UINT32 offset,UINT8 *valid_msr);;
1832         void piv_msr_write(UINT32 offset, UINT64 data, UINT8 *valid_msr);
1833
1834         int x87_inc_stack();
1835         int x87_dec_stack();
1836         int x87_check_exceptions();
1837 };
1838 extern const X86_OPCODE x86_opcode_table[];
1839 extern const X86_CYCLE_TABLE x86_cycle_table[];
1840
1841 /***********************************************************************************/
1842
1843 #define CYCLES_NUM(x)   (cpustate->cycles -= (x))
1844
1845 INLINE void I386_OPS_BASE::CYCLES(int x)
1846 {
1847         if (PROTECTED_MODE)
1848         {
1849                 cpustate->cycles -= cpustate->cycle_table_pm[x];
1850         }
1851         else
1852         {
1853                 cpustate->cycles -= cpustate->cycle_table_rm[x];
1854         }
1855 }
1856
1857 INLINE void I386_OPS_BASE::CYCLES_RM(int modrm, int r, int m)
1858 {
1859         if (modrm >= 0xc0)
1860         {
1861                 if (PROTECTED_MODE)
1862                 {
1863                         cpustate->cycles -= cpustate->cycle_table_pm[r];
1864                 }
1865                 else
1866                 {
1867                         cpustate->cycles -= cpustate->cycle_table_rm[r];
1868                 }
1869         }
1870         else
1871         {
1872                 if (PROTECTED_MODE)
1873                 {
1874                         cpustate->cycles -= cpustate->cycle_table_pm[m];
1875                 }
1876                 else
1877                 {
1878                         cpustate->cycles -= cpustate->cycle_table_rm[m];
1879                 }
1880         }
1881 }
1882
1883
1884 INLINE UINT32 I386_OPS_BASE::i386_translate(int segment, UINT32 ip, int rwn)
1885 {
1886         // TODO: segment limit access size, execution permission, handle exception thrown from exception handler
1887         if(PROTECTED_MODE && !V8086_MODE && (rwn != -1))
1888         {
1889                 if(!(cpustate->sreg[segment].valid))
1890                         FAULT_THROW((segment==SS)?FAULT_SS:FAULT_GP, 0);
1891                 if(i386_limit_check(segment, ip))
1892                         FAULT_THROW((segment==SS)?FAULT_SS:FAULT_GP, 0);
1893                 if((rwn == 0) && ((cpustate->sreg[segment].flags & 8) && !(cpustate->sreg[segment].flags & 2)))
1894                         FAULT_THROW(FAULT_GP, 0);
1895                 if((rwn == 1) && ((cpustate->sreg[segment].flags & 8) || !(cpustate->sreg[segment].flags & 2)))
1896                         FAULT_THROW(FAULT_GP, 0);
1897         }
1898         return cpustate->sreg[segment].base + ip;
1899 }
1900
1901 #define VTLB_FLAG_DIRTY 0x100
1902
1903 INLINE vtlb_entry I386_OPS_BASE::get_permissions(UINT32 pte, int wp)
1904 {
1905         vtlb_entry ret = VTLB_READ_ALLOWED | ((pte & 4) ? VTLB_USER_READ_ALLOWED : 0);
1906         if(!wp)
1907                 ret |= VTLB_WRITE_ALLOWED;
1908         if(pte & 2)
1909                 ret |= VTLB_WRITE_ALLOWED | ((pte & 4) ? VTLB_USER_WRITE_ALLOWED : 0);
1910         return ret;
1911 }
1912
1913 //#define TEST_TLB
1914
1915 INLINE int I386_OPS_BASE::translate_address(int pl, int type, UINT32 *address, UINT32 *error)
1916 {
1917         if(!(cpustate->cr[0] & 0x80000000)) // Some (very few) old OS's won't work with this
1918                 return TRUE;
1919
1920         const vtlb_entry *table = vtlb_table(cpustate->vtlb);
1921         UINT32 index = *address >> 12;
1922         vtlb_entry entry = table[index];
1923         if(type == TRANSLATE_FETCH)
1924                 type = TRANSLATE_READ;
1925         if(pl == 3)
1926                 type |= TRANSLATE_USER_MASK;
1927 #ifdef TEST_TLB
1928         UINT32 test_addr = *address;
1929 #endif
1930
1931         if(!(entry & VTLB_FLAG_VALID) || ((type & TRANSLATE_WRITE) && !(entry & VTLB_FLAG_DIRTY)))
1932         {
1933                 if(!i386_translate_address( type, address, &entry))
1934                 {
1935                         *error = ((type & TRANSLATE_WRITE) ? 2 : 0) | ((cpustate->CPL == 3) ? 4 : 0);
1936                         if(entry)
1937                                 *error |= 1;
1938                         return FALSE;
1939                 }
1940                 vtlb_dynload(cpustate->vtlb, index, *address, entry);
1941                 return TRUE;
1942         }
1943         if(!(entry & (1 << type)))
1944         {
1945                 *error = ((type & TRANSLATE_WRITE) ? 2 : 0) | ((cpustate->CPL == 3) ? 4 : 0) | 1;
1946                 return FALSE;
1947         }
1948         *address = (entry & 0xfffff000) | (*address & 0xfff);
1949 #ifdef TEST_TLB
1950         int test_ret = i386_translate_address( type | TRANSLATE_DEBUG_MASK, &test_addr, NULL);
1951         if(!test_ret || (test_addr != *address))
1952                 logerror("TLB-PTE mismatch! %06X %06X %06x\n", *address, test_addr, cpustate->pc);
1953 #endif
1954         return TRUE;
1955 }
1956
1957 INLINE void I386_OPS_BASE::CHANGE_PC(UINT32 pc)
1958 {
1959         cpustate->pc = i386_translate(CS, pc, -1 );
1960 }
1961
1962 INLINE void I386_OPS_BASE::NEAR_BRANCH(INT32 offs)
1963 {
1964         /* TODO: limit */
1965         cpustate->eip += offs;
1966         cpustate->pc += offs;
1967 }
1968
1969 INLINE UINT8 I386_OPS_BASE::FETCH()
1970 {
1971         UINT8 value;
1972         UINT32 address = cpustate->pc, error;
1973
1974         if(!translate_address(cpustate->CPL,TRANSLATE_FETCH,&address,&error))
1975                 PF_THROW(error);
1976
1977         value = cpustate->program->read_data8(address & cpustate->a20_mask);
1978 #ifdef DEBUG_MISSING_OPCODE
1979         cpustate->opcode_bytes[cpustate->opcode_bytes_length] = value;
1980         cpustate->opcode_bytes_length = (cpustate->opcode_bytes_length + 1) & 15;
1981 #endif
1982         cpustate->eip++;
1983         cpustate->pc++;
1984         return value;
1985 }
1986
1987 INLINE UINT16 I386_OPS_BASE::FETCH16()
1988 {
1989         UINT16 value;
1990         UINT32 address = cpustate->pc, error;
1991
1992         if( !WORD_ALIGNED(address) ) {       /* Unaligned read */
1993                 value = (FETCH() << 0);
1994                 value |= (FETCH() << 8);
1995         } else {
1996                 if(!translate_address(cpustate->CPL,TRANSLATE_FETCH,&address,&error))
1997                         PF_THROW(error);
1998                 address &= cpustate->a20_mask;
1999                 value = cpustate->program->read_data16(address);
2000                 cpustate->eip += 2;
2001                 cpustate->pc += 2;
2002         }
2003         return value;
2004 }
2005 INLINE UINT32 I386_OPS_BASE::FETCH32()
2006 {
2007         UINT32 value;
2008         UINT32 address = cpustate->pc, error;
2009
2010         if( !DWORD_ALIGNED(cpustate->pc) ) {      /* Unaligned read */
2011                 value = (FETCH() << 0);
2012                 value |= (FETCH() << 8);
2013                 value |= (FETCH() << 16);
2014                 value |= (FETCH() << 24);
2015         } else {
2016                 if(!translate_address(cpustate->CPL,TRANSLATE_FETCH,&address,&error))
2017                         PF_THROW(error);
2018
2019                 address &= cpustate->a20_mask;
2020                 value = cpustate->program->read_data32(address);
2021                 cpustate->eip += 4;
2022                 cpustate->pc += 4;
2023         }
2024         return value;
2025 }
2026
2027 INLINE UINT8 I386_OPS_BASE::READ8(UINT32 ea)
2028 {
2029         UINT32 address = ea, error;
2030
2031         if(!translate_address(cpustate->CPL,TRANSLATE_READ,&address, &error))
2032                 PF_THROW(error);
2033
2034         address &= cpustate->a20_mask;
2035         return cpustate->program->read_data8(address);
2036 }
2037
2038 INLINE UINT16 I386_OPS_BASE::READ16(UINT32 ea)
2039 {
2040         UINT16 value;
2041         UINT32 address = ea, error;
2042
2043         if( !WORD_ALIGNED(ea) ) {      /* Unaligned read */
2044                 value = (READ8(address+0) << 0);
2045                 value |= (READ8(address+1) << 8);
2046         } else {
2047                 if(!translate_address(cpustate->CPL,TRANSLATE_READ,&address,&error))
2048                         PF_THROW(error);
2049
2050                 address &= cpustate->a20_mask;
2051                 value = cpustate->program->read_data16( address );
2052         }
2053         return value;
2054 }
2055 INLINE UINT32 I386_OPS_BASE::READ32(UINT32 ea)
2056 {
2057         UINT32 value;
2058         UINT32 address = ea, error;
2059
2060         if( !DWORD_ALIGNED(ea) ) {      /* Unaligned read */
2061                 value = (READ8(address+0) << 0);
2062                 value |= (READ8(address+1) << 8);
2063                 value |= (READ8(address+2) << 16),
2064                 value |= (READ8(address+3) << 24);
2065         } else {
2066                 if(!translate_address(cpustate->CPL,TRANSLATE_READ,&address,&error))
2067                         PF_THROW(error);
2068
2069                 address &= cpustate->a20_mask;
2070                 value = cpustate->program->read_data32( address );
2071         }
2072         return value;
2073 }
2074
2075 INLINE UINT64 I386_OPS_BASE::READ64(UINT32 ea)
2076 {
2077         UINT64 value;
2078         UINT32 address = ea, error;
2079
2080         if( !QWORD_ALIGNED(ea) ) {      /* Unaligned read */
2081                 value = (((UINT64) READ8( address+0 )) << 0);
2082                 value |= (((UINT64) READ8( address+1 )) << 8);
2083                 value |= (((UINT64) READ8( address+2 )) << 16);
2084                 value |= (((UINT64) READ8( address+3 )) << 24);
2085                 value |= (((UINT64) READ8( address+4 )) << 32);
2086                 value |= (((UINT64) READ8( address+5 )) << 40);
2087                 value |= (((UINT64) READ8( address+6 )) << 48);
2088                 value |= (((UINT64) READ8( address+7 )) << 56);
2089         } else {
2090                 if(!translate_address(cpustate->CPL,TRANSLATE_READ,&address,&error))
2091                         PF_THROW(error);
2092
2093                 address &= cpustate->a20_mask;
2094                 value = (((UINT64) cpustate->program->read_data32( address+0 )) << 0);
2095                 value |= (((UINT64) cpustate->program->read_data32( address+4 )) << 32);
2096         }
2097         return value;
2098 }
2099
2100 INLINE UINT8 I386_OPS_BASE::READ8PL0(UINT32 ea)
2101 {
2102         UINT32 address = ea, error;
2103
2104         if(!translate_address(0,TRANSLATE_READ,&address,&error))
2105                 PF_THROW(error);
2106
2107         address &= cpustate->a20_mask;
2108         return cpustate->program->read_data8(address);
2109 }
2110
2111 INLINE UINT16 I386_OPS_BASE::READ16PL0(UINT32 ea)
2112 {
2113         UINT16 value;
2114         UINT32 address = ea, error;
2115
2116         if( !WORD_ALIGNED(ea) ) {      /* Unaligned read */
2117                 value = (READ8PL0( address+0 ) << 0);
2118                 value |= (READ8PL0( address+1 ) << 8);
2119         } else {
2120                 if(!translate_address(0,TRANSLATE_READ,&address,&error))
2121                         PF_THROW(error);
2122
2123                 address &= cpustate->a20_mask;
2124                 value = cpustate->program->read_data16( address );
2125         }
2126         return value;
2127 }
2128
2129 INLINE UINT32 I386_OPS_BASE::READ32PL0(UINT32 ea)
2130 {
2131         UINT32 value;
2132         UINT32 address = ea, error;
2133
2134         if( !DWORD_ALIGNED(ea) ) {      /* Unaligned read */
2135                 value = (READ8PL0( address+0 ) << 0);
2136                 value |= (READ8PL0( address+1 ) << 8);
2137                 value |= (READ8PL0( address+2 ) << 16);
2138                 value |= (READ8PL0( address+3 ) << 24);
2139         } else {
2140                 if(!translate_address(0,TRANSLATE_READ,&address,&error))
2141                         PF_THROW(error);
2142
2143                 address &= cpustate->a20_mask;
2144                 value = cpustate->program->read_data32( address );
2145         }
2146         return value;
2147 }
2148
2149 INLINE void I386_OPS_BASE::WRITE_TEST(UINT32 ea)
2150 {
2151         UINT32 address = ea, error;
2152         if(!translate_address(cpustate->CPL,TRANSLATE_WRITE,&address,&error))
2153                 PF_THROW(error);
2154 }
2155
2156 INLINE void I386_OPS_BASE::WRITE8(UINT32 ea, UINT8 value)
2157 {
2158         UINT32 address = ea, error;
2159
2160         if(!translate_address(cpustate->CPL,TRANSLATE_WRITE,&address,&error))
2161                 PF_THROW(error);
2162
2163         address &= cpustate->a20_mask;
2164         cpustate->program->write_data8(address, value);
2165 }
2166
2167 INLINE void I386_OPS_BASE::WRITE16(UINT32 ea, UINT16 value)
2168 {
2169         UINT32 address = ea, error;
2170
2171         if( !WORD_ALIGNED(ea) ) {      /* Unaligned write */
2172                 WRITE8( address+0, value & 0xff );
2173                 WRITE8( address+1, (value >> 8) & 0xff );
2174         } else {
2175                 if(!translate_address(cpustate->CPL,TRANSLATE_WRITE,&address,&error))
2176                         PF_THROW(error);
2177
2178                 address &= cpustate->a20_mask;
2179                 cpustate->program->write_data16(address, value);
2180         }
2181 }
2182
2183 INLINE void I386_OPS_BASE::WRITE32(UINT32 ea, UINT32 value)
2184 {
2185         UINT32 address = ea, error;
2186
2187         if( !DWORD_ALIGNED(ea) ) {      /* Unaligned write */
2188                 WRITE8( address+0, value & 0xff );
2189                 WRITE8( address+1, (value >> 8) & 0xff );
2190                 WRITE8( address+2, (value >> 16) & 0xff );
2191                 WRITE8( address+3, (value >> 24) & 0xff );
2192         } else {
2193                 if(!translate_address(cpustate->CPL,TRANSLATE_WRITE,&address,&error))
2194                         PF_THROW(error);
2195
2196                 ea &= cpustate->a20_mask;
2197                 cpustate->program->write_data32(address, value);
2198         }
2199 }
2200
2201 INLINE void I386_OPS_BASE::WRITE64(UINT32 ea, UINT64 value)
2202 {
2203         UINT32 address = ea, error;
2204
2205         if( !QWORD_ALIGNED(ea) ) {      /* Unaligned write */
2206                 WRITE8( address+0, value & 0xff );
2207                 WRITE8( address+1, (value >> 8) & 0xff );
2208                 WRITE8( address+2, (value >> 16) & 0xff );
2209                 WRITE8( address+3, (value >> 24) & 0xff );
2210                 WRITE8( address+4, (value >> 32) & 0xff );
2211                 WRITE8( address+5, (value >> 40) & 0xff );
2212                 WRITE8( address+6, (value >> 48) & 0xff );
2213                 WRITE8( address+7, (value >> 56) & 0xff );
2214         } else {
2215                 if(!translate_address(cpustate->CPL,TRANSLATE_WRITE,&address,&error))
2216                         PF_THROW(error);
2217
2218                 ea &= cpustate->a20_mask;
2219                 cpustate->program->write_data32(address+0, value & 0xffffffff);
2220                 cpustate->program->write_data32(address+4, (value >> 32) & 0xffffffff);
2221         }
2222 }
2223
2224 /***********************************************************************************/
2225
2226 INLINE UINT8 I386_OPS_BASE::OR8(UINT8 dst, UINT8 src)
2227 {
2228         UINT8 res = dst | src;
2229         cpustate->CF = cpustate->OF = 0;
2230         SetSZPF8(res);
2231         return res;
2232 }
2233
2234 INLINE UINT16 I386_OPS_BASE::OR16(UINT16 dst, UINT16 src)
2235 {
2236         UINT16 res = dst | src;
2237         cpustate->CF = cpustate->OF = 0;
2238         SetSZPF16(res);
2239         return res;
2240 }
2241
2242 INLINE UINT32 I386_OPS_BASE::OR32(UINT32 dst, UINT32 src)
2243 {
2244         UINT32 res = dst | src;
2245         cpustate->CF = cpustate->OF = 0;
2246         SetSZPF32(res);
2247         return res;
2248 }
2249
2250 INLINE UINT8 I386_OPS_BASE::AND8(UINT8 dst, UINT8 src)
2251 {
2252         UINT8 res = dst & src;
2253         cpustate->CF = cpustate->OF = 0;
2254         SetSZPF8(res);
2255         return res;
2256 }
2257 INLINE UINT16 I386_OPS_BASE::AND16(UINT16 dst, UINT16 src)
2258 {
2259         UINT16 res = dst & src;
2260         cpustate->CF = cpustate->OF = 0;
2261         SetSZPF16(res);
2262         return res;
2263 }
2264 INLINE UINT32 I386_OPS_BASE::AND32(UINT32 dst, UINT32 src)
2265 {
2266         UINT32 res = dst & src;
2267         cpustate->CF = cpustate->OF = 0;
2268         SetSZPF32(res);
2269         return res;
2270 }
2271
2272 INLINE UINT8 I386_OPS_BASE::XOR8(UINT8 dst, UINT8 src)
2273 {
2274         UINT8 res = dst ^ src;
2275         cpustate->CF = cpustate->OF = 0;
2276         SetSZPF8(res);
2277         return res;
2278 }
2279 INLINE UINT16 I386_OPS_BASE::XOR16(UINT16 dst, UINT16 src)
2280 {
2281         UINT16 res = dst ^ src;
2282         cpustate->CF = cpustate->OF = 0;
2283         SetSZPF16(res);
2284         return res;
2285 }
2286 INLINE UINT32 I386_OPS_BASE::XOR32(UINT32 dst, UINT32 src)
2287 {
2288         UINT32 res = dst ^ src;
2289         cpustate->CF = cpustate->OF = 0;
2290         SetSZPF32(res);
2291         return res;
2292 }
2293
2294 #define SUB8(dst, src) SBB8(dst, src, 0)
2295 INLINE UINT8 I386_OPS_BASE::SBB8(UINT8 dst, UINT8 src, UINT8 b)
2296 {
2297         UINT16 res = (UINT16)dst - (UINT16)src - (UINT8)b;
2298         SetCF8(res);
2299         SetOF_Sub8(res,src,dst);
2300         SetAF(res,src,dst);
2301         SetSZPF8(res);
2302         return (UINT8)res;
2303 }
2304
2305 #define SUB16(dst, src) SBB16(dst, src, 0)
2306 INLINE UINT16 I386_OPS_BASE::SBB16(UINT16 dst, UINT16 src, UINT16 b)
2307 {
2308         UINT32 res = (UINT32)dst - (UINT32)src - (UINT32)b;
2309         SetCF16(res);
2310         SetOF_Sub16(res,src,dst);
2311         SetAF(res,src,dst);
2312         SetSZPF16(res);
2313         return (UINT16)res;
2314 }
2315
2316 #define SUB32(dst, src) SBB32(dst, src, 0)
2317 INLINE UINT32 I386_OPS_BASE::SBB32(UINT32 dst, UINT32 src, UINT32 b)
2318 {
2319         UINT64 res = (UINT64)dst - (UINT64)src - (UINT64) b;
2320         SetCF32(res);
2321         SetOF_Sub32(res,src,dst);
2322         SetAF(res,src,dst);
2323         SetSZPF32(res);
2324         return (UINT32)res;
2325 }
2326
2327 #define ADD8(dst, src) ADC8(dst, src, 0)
2328 INLINE UINT8 I386_OPS_BASE::ADC8(UINT8 dst, UINT8 src, UINT8 c)
2329 {
2330         UINT16 res = (UINT16)dst + (UINT16)src + (UINT16)c;
2331         SetCF8(res);
2332         SetOF_Add8(res,src,dst);
2333         SetAF(res,src,dst);
2334         SetSZPF8(res);
2335         return (UINT8)res;
2336 }
2337
2338 #define ADD16(dst, src) ADC16(dst, src, 0)
2339 INLINE UINT16 I386_OPS_BASE::ADC16(UINT16 dst, UINT16 src, UINT8 c)
2340 {
2341         UINT32 res = (UINT32)dst + (UINT32)src + (UINT32)c;
2342         SetCF16(res);
2343         SetOF_Add16(res,src,dst);
2344         SetAF(res,src,dst);
2345         SetSZPF16(res);
2346         return (UINT16)res;
2347 }
2348
2349 #define ADD32(dst, src) ADC32(dst, src, 0)
2350 INLINE UINT32 I386_OPS_BASE::ADC32(UINT32 dst, UINT32 src, UINT32 c)
2351 {
2352         UINT64 res = (UINT64)dst + (UINT64)src + (UINT64) c;
2353         SetCF32(res);
2354         SetOF_Add32(res,src,dst);
2355         SetAF(res,src,dst);
2356         SetSZPF32(res);
2357         return (UINT32)res;
2358 }
2359
2360 INLINE UINT8 I386_OPS_BASE::INC8(UINT8 dst)
2361 {
2362         UINT16 res = (UINT16)dst + 1;
2363         SetOF_Add8(res,1,dst);
2364         SetAF(res,1,dst);
2365         SetSZPF8(res);
2366         return (UINT8)res;
2367 }
2368 INLINE UINT16 I386_OPS_BASE::INC16(UINT16 dst)
2369 {
2370         UINT32 res = (UINT32)dst + 1;
2371         SetOF_Add16(res,1,dst);
2372         SetAF(res,1,dst);
2373         SetSZPF16(res);
2374         return (UINT16)res;
2375 }
2376 INLINE UINT32 I386_OPS_BASE::INC32(UINT32 dst)
2377 {
2378         UINT64 res = (UINT64)dst + 1;
2379         SetOF_Add32(res,1,dst);
2380         SetAF(res,1,dst);
2381         SetSZPF32(res);
2382         return (UINT32)res;
2383 }
2384
2385 INLINE UINT8 I386_OPS_BASE::DEC8(UINT8 dst)
2386 {
2387         UINT16 res = (UINT16)dst - 1;
2388         SetOF_Sub8(res,1,dst);
2389         SetAF(res,1,dst);
2390         SetSZPF8(res);
2391         return (UINT8)res;
2392 }
2393 INLINE UINT16 I386_OPS_BASE::DEC16(UINT16 dst)
2394 {
2395         UINT32 res = (UINT32)dst - 1;
2396         SetOF_Sub16(res,1,dst);
2397         SetAF(res,1,dst);
2398         SetSZPF16(res);
2399         return (UINT16)res;
2400 }
2401 INLINE UINT32 I386_OPS_BASE::DEC32(UINT32 dst)
2402 {
2403         UINT64 res = (UINT64)dst - 1;
2404         SetOF_Sub32(res,1,dst);
2405         SetAF(res,1,dst);
2406         SetSZPF32(res);
2407         return (UINT32)res;
2408 }
2409
2410
2411
2412 INLINE void I386_OPS_BASE::PUSH16(UINT16 value)
2413 {
2414         UINT32 ea, new_esp;
2415         if( STACK_32BIT ) {
2416                 new_esp = REG32(ESP) - 2;
2417                 ea = i386_translate( SS, new_esp, 1);
2418                 WRITE16( ea, value );
2419                 REG32(ESP) = new_esp;
2420         } else {
2421                 new_esp = (REG16(SP) - 2) & 0xffff;
2422                 ea = i386_translate( SS, new_esp, 1);
2423                 WRITE16( ea, value );
2424                 REG16(SP) = new_esp;
2425         }
2426 }
2427 INLINE void I386_OPS_BASE::PUSH32(UINT32 value)
2428 {
2429         UINT32 ea, new_esp;
2430         if( STACK_32BIT ) {
2431                 new_esp = REG32(ESP) - 4;
2432                 ea = i386_translate( SS, new_esp, 1);
2433                 WRITE32( ea, value );
2434                 REG32(ESP) = new_esp;
2435         } else {
2436                 new_esp = (REG16(SP) - 4) & 0xffff;
2437                 ea = i386_translate( SS, new_esp, 1);
2438                 WRITE32( ea, value );
2439                 REG16(SP) = new_esp;
2440         }
2441 }
2442
2443 INLINE void I386_OPS_BASE::PUSH32SEG(UINT32 value)
2444 {
2445         UINT32 ea, new_esp;
2446         if( STACK_32BIT ) {
2447                 new_esp = REG32(ESP) - 4;
2448                 ea = i386_translate(SS, new_esp, 1);
2449                 ((cpustate->cpu_version & 0xf00) == 0x300) ? WRITE16(ea, value) : WRITE32(ea, value ); // 486 also?
2450                 REG32(ESP) = new_esp;
2451         } else {
2452                 new_esp = (REG16(SP) - 4) & 0xffff;
2453                 ea = i386_translate(SS, new_esp, 1);
2454                 ((cpustate->cpu_version & 0xf00) == 0x300) ? WRITE16(ea, value) : WRITE32(ea, value );
2455                 REG16(SP) = new_esp;
2456         }
2457 }
2458
2459 INLINE void I386_OPS_BASE::PUSH8(UINT8 value)
2460 {
2461         if( cpustate->operand_size ) {
2462                 PUSH32((INT32)(INT8)value);
2463         } else {
2464                 PUSH16((INT16)(INT8)value);
2465         }
2466 }
2467
2468 INLINE UINT8 I386_OPS_BASE::POP8()
2469 {
2470         UINT8 value;
2471         UINT32 ea, new_esp;
2472         if( STACK_32BIT ) {
2473                 new_esp = REG32(ESP) + 1;
2474                 ea = i386_translate( SS, new_esp - 1, 0);
2475                 value = READ8( ea );
2476                 REG32(ESP) = new_esp;
2477         } else {
2478                 new_esp = REG16(SP) + 1;
2479                 ea = i386_translate( SS, (new_esp - 1) & 0xffff, 0);
2480                 value = READ8( ea );
2481                 REG16(SP) = new_esp;
2482         }
2483         return value;
2484 }
2485
2486 INLINE UINT16 I386_OPS_BASE::POP16()
2487 {
2488         UINT16 value;
2489         UINT32 ea, new_esp;
2490         if( STACK_32BIT ) {
2491                 new_esp = REG32(ESP) + 2;
2492                 ea = i386_translate( SS, new_esp - 2, 0);
2493                 value = READ16( ea );
2494                 REG32(ESP) = new_esp;
2495         } else {
2496                 new_esp = REG16(SP) + 2;
2497                 ea = i386_translate( SS, (new_esp - 2) & 0xffff, 0);
2498                 value = READ16( ea );
2499                 REG16(SP) = new_esp;
2500         }
2501         return value;
2502 }
2503 INLINE UINT32 I386_OPS_BASE::POP32()
2504 {
2505         UINT32 value;
2506         UINT32 ea, new_esp;
2507         if( STACK_32BIT ) {
2508                 new_esp = REG32(ESP) + 4;
2509                 ea = i386_translate( SS, new_esp - 4, 0);
2510                 value = READ32( ea );
2511                 REG32(ESP) = new_esp;
2512         } else {
2513                 new_esp = REG16(SP) + 4;
2514                 ea = i386_translate( SS, (new_esp - 4) & 0xffff, 0);
2515                 value = READ32( ea );
2516                 REG16(SP) = new_esp;
2517         }
2518         return value;
2519 }
2520
2521 INLINE void I386_OPS_BASE::BUMP_SI(int adjustment)
2522 {
2523         if ( cpustate->address_size )
2524                 REG32(ESI) += ((cpustate->DF) ? -adjustment : +adjustment);
2525         else
2526                 REG16(SI) += ((cpustate->DF) ? -adjustment : +adjustment);
2527 }
2528
2529 INLINE void I386_OPS_BASE::BUMP_DI(int adjustment)
2530 {
2531         if ( cpustate->address_size )
2532                 REG32(EDI) += ((cpustate->DF) ? -adjustment : +adjustment);
2533         else
2534                 REG16(DI) += ((cpustate->DF) ? -adjustment : +adjustment);
2535 }
2536
2537
2538
2539 /***********************************************************************************
2540     I/O ACCESS
2541 ***********************************************************************************/
2542
2543 INLINE void I386_OPS_BASE::check_ioperm( offs_t port, UINT8 mask)
2544 {
2545         UINT8 IOPL, map;
2546         UINT16 IOPB;
2547         UINT32 address;
2548
2549         if(!PROTECTED_MODE)
2550                 return;
2551
2552         IOPL = cpustate->IOP1 | (cpustate->IOP2 << 1);
2553         if(!V8086_MODE && (cpustate->CPL <= IOPL))
2554                 return;
2555
2556         if((cpustate->task.limit < 0x67) || ((cpustate->task.flags & 0xd) != 9))
2557                 FAULT_THROW(FAULT_GP,0);
2558
2559         address = cpustate->task.base;
2560         IOPB = READ16PL0( address+0x66);
2561         if((IOPB+(port/8)) > cpustate->task.limit)
2562                 FAULT_THROW(FAULT_GP,0);
2563
2564         map = READ8PL0( address+IOPB+(port/8));
2565         map >>= (port%8);
2566         if(map & mask)
2567                 FAULT_THROW(FAULT_GP,0);
2568 }
2569
2570 INLINE UINT8 I386_OPS_BASE::READPORT8( offs_t port)
2571 {
2572         check_ioperm( port, 1);
2573         return cpustate->io->read_io8(port);
2574 }
2575
2576 INLINE void I386_OPS_BASE::WRITEPORT8( offs_t port, UINT8 value)
2577 {
2578         check_ioperm( port, 1);
2579         cpustate->io->write_io8(port, value);
2580 }
2581
2582 INLINE UINT16 I386_OPS_BASE::READPORT16( offs_t port)
2583 {
2584         if (port & 1)
2585         {
2586                 UINT16 value = READPORT8( port);
2587                 value |= (READPORT8( port + 1) << 8);
2588                 return value;
2589         }
2590         else
2591         {
2592                 check_ioperm( port, 3);
2593                 return cpustate->io->read_io16(port);
2594         }
2595 }
2596
2597 INLINE void I386_OPS_BASE::WRITEPORT16( offs_t port, UINT16 value)
2598 {
2599         if (port & 1)
2600         {
2601                 WRITEPORT8( port, value & 0xff);
2602                 WRITEPORT8( port + 1, (value >> 8) & 0xff);
2603         }
2604         else
2605         {
2606                 check_ioperm( port, 3);
2607                 cpustate->io->write_io16(port, value);
2608         }
2609 }
2610
2611 INLINE UINT32 I386_OPS_BASE::READPORT32( offs_t port)
2612 {
2613         if (port & 3)
2614         {
2615                 UINT32 value = READPORT8( port);
2616                 value |= (READPORT8( port + 1) << 8);
2617                 value |= (READPORT8( port + 2) << 16);
2618                 value |= (READPORT8( port + 3) << 24);
2619                 return value;
2620         }
2621         else
2622         {
2623                 check_ioperm( port, 0xf);
2624                 return cpustate->io->read_io32(port);
2625         }
2626 }
2627
2628 INLINE void I386_OPS_BASE::WRITEPORT32( offs_t port, UINT32 value)
2629 {
2630         if (port & 3)
2631         {
2632                 WRITEPORT8( port, value & 0xff);
2633                 WRITEPORT8( port + 1, (value >> 8) & 0xff);
2634                 WRITEPORT8( port + 2, (value >> 16) & 0xff);
2635                 WRITEPORT8( port + 3, (value >> 24) & 0xff);
2636         }
2637         else
2638         {
2639                 check_ioperm( port, 0xf);
2640                 cpustate->io->write_io32(port, value);
2641         }
2642 }
2643
2644
2645 INLINE UINT64 I386_OPS_BASE::MSR_READ(UINT32 offset,UINT8 *valid_msr)
2646 {
2647         UINT64 res;
2648         UINT8 cpu_type = (cpustate->cpu_version >> 8) & 0x0f;
2649
2650         *valid_msr = 0;
2651
2652         switch(cpu_type)
2653         {
2654         case 5:  // Pentium
2655                 res = pentium_msr_read(offset,valid_msr);
2656                 break;
2657         case 6:  // Pentium Pro, Pentium II, Pentium III
2658                 res = p6_msr_read(offset,valid_msr);
2659                 break;
2660         case 15:  // Pentium 4+
2661                 res = piv_msr_read(offset,valid_msr);
2662                 break;
2663         default:
2664                 res = 0;
2665                 break;
2666         }
2667
2668         return res;
2669 }
2670
2671 INLINE void I386_OPS_BASE::MSR_WRITE(UINT32 offset, UINT64 data, UINT8 *valid_msr)
2672 {
2673         *valid_msr = 0;
2674         UINT8 cpu_type = (cpustate->cpu_version >> 8) & 0x0f;
2675
2676         switch(cpu_type)
2677         {
2678         case 5:  // Pentium
2679                 pentium_msr_write(offset,data,valid_msr);
2680                 break;
2681         case 6:  // Pentium Pro, Pentium II, Pentium III
2682                 p6_msr_write(offset,data,valid_msr);
2683                 break;
2684         case 15:  // Pentium 4+
2685                 piv_msr_write(offset,data,valid_msr);
2686                 break;
2687         }
2688 }
2689
2690 INLINE INT8 I386_OPS_BASE::SaturatedSignedWordToSignedByte(INT16 word)
2691 {
2692         if (word > 127)
2693                 return 127;
2694         if (word < -128)
2695                 return -128;
2696         return (INT8)word;
2697 }
2698
2699 INLINE UINT8 I386_OPS_BASE::SaturatedSignedWordToUnsignedByte(INT16 word)
2700 {
2701         if (word > 255)
2702                 return 255;
2703         if (word < 0)
2704                 return 0;
2705         return (UINT8)word;
2706 }
2707
2708 INLINE INT16 I386_OPS_BASE::SaturatedSignedDwordToSignedWord(INT32 dword)
2709 {
2710         if (dword > 32767)
2711                 return 32767;
2712         if (dword < -32768)
2713                 return -32768;
2714         return (INT16)dword;
2715 }
2716
2717 INLINE UINT16 I386_OPS_BASE::SaturatedSignedDwordToUnsignedWord(INT32 dword)
2718 {
2719         if (dword > 65535)
2720                 return 65535;
2721         if (dword < 0)
2722                 return 0;
2723         return (UINT16)dword;
2724 }
2725
2726 INLINE void I386_OPS_BASE::MMXPROLOG()
2727 {
2728         //cpustate->x87_sw &= ~(X87_SW_TOP_MASK << X87_SW_TOP_SHIFT); // top = 0
2729         cpustate->x87_tw = 0; // tag word = 0
2730 }
2731
2732 INLINE void I386_OPS_BASE::READMMX(UINT32 ea,MMX_REG &r)
2733 {
2734         r.q=READ64( ea);
2735 }
2736
2737 INLINE void I386_OPS_BASE::WRITEMMX(UINT32 ea,MMX_REG &r)
2738 {
2739         WRITE64( ea, r.q);
2740 }
2741
2742 INLINE void I386_OPS_BASE::READXMM(UINT32 ea,XMM_REG &r)
2743 {
2744         r.q[0]=READ64( ea);
2745         r.q[1]=READ64( ea+8);
2746 }
2747
2748 INLINE void I386_OPS_BASE::WRITEXMM(UINT32 ea,XMM_REG &r)
2749 {
2750         WRITE64( ea, r.q[0]);
2751         WRITE64( ea+8, r.q[1]);
2752 }
2753
2754 INLINE void I386_OPS_BASE::READXMM_LO64(UINT32 ea,XMM_REG &r)
2755 {
2756         r.q[0]=READ64( ea);
2757 }
2758
2759 INLINE void I386_OPS_BASE::WRITEXMM_LO64(UINT32 ea,XMM_REG &r)
2760 {
2761         WRITE64( ea, r.q[0]);
2762 }
2763
2764 INLINE void I386_OPS_BASE::READXMM_HI64(UINT32 ea,XMM_REG &r)
2765 {
2766         r.q[1]=READ64( ea);
2767 }
2768
2769 INLINE void I386_OPS_BASE::WRITEXMM_HI64(UINT32 ea,XMM_REG &r)
2770 {
2771         WRITE64( ea, r.q[1]);
2772 }
2773
2774 INLINE flag I386_OPS_BASE::floatx80_is_quiet_nan(floatx80 a)
2775 {
2776         bits64 aLow;
2777
2778         aLow = a.low & ~LIT64(0x4000000000000000);
2779         return
2780                 ((a.high & 0x7FFF) == 0x7FFF)
2781                 && (bits64)(aLow << 1)
2782                 && (a.low != aLow);
2783 }
2784
2785 INLINE int I386_OPS_BASE::floatx80_is_zero(floatx80 fx)
2786 {
2787         return (((fx.high & 0x7fff) == 0) && ((fx.low << 1) == 0));
2788 }
2789
2790 INLINE int I386_OPS_BASE::floatx80_is_inf(floatx80 fx)
2791 {
2792         return (((fx.high & 0x7fff) == 0x7fff) && ((fx.low << 1) == 0));
2793 }
2794
2795 INLINE int I386_OPS_BASE::floatx80_is_denormal(floatx80 fx)
2796 {
2797         return (((fx.high & 0x7fff) == 0) &&
2798                         ((fx.low & U64(0x8000000000000000)) == 0) &&
2799                         ((fx.low << 1) != 0));
2800 }
2801
2802 INLINE floatx80 I386_OPS_BASE::floatx80_abs(floatx80 fx)
2803 {
2804         fx.high &= 0x7fff;
2805         return fx;
2806 }
2807
2808 INLINE double I386_OPS_BASE::fx80_to_double(floatx80 fx)
2809 {
2810         UINT64 d = floatx80_to_float64(fx);
2811         return *(double*)&d;
2812 }
2813
2814 INLINE floatx80 I386_OPS_BASE::double_to_fx80(double in)
2815 {
2816         return float64_to_floatx80(*(UINT64*)&in);
2817 }
2818
2819 INLINE floatx80 I386_OPS_BASE::READ80( UINT32 ea)
2820 {
2821         floatx80 t;
2822
2823         t.low = READ64( ea);
2824         t.high = READ16( ea + 8);
2825
2826         return t;
2827 }
2828
2829 INLINE void I386_OPS_BASE::WRITE80( UINT32 ea, floatx80 t)
2830 {
2831         WRITE64( ea, t.low);
2832         WRITE16( ea + 8, t.high);
2833 }
2834
2835 /*************************************
2836  *
2837  * x87 stack handling
2838  *
2839  *************************************/
2840
2841 INLINE void I386_OPS_BASE::x87_set_stack_top(int top)
2842 {
2843         cpustate->x87_sw &= ~(X87_SW_TOP_MASK << X87_SW_TOP_SHIFT);
2844         cpustate->x87_sw |= (top << X87_SW_TOP_SHIFT);
2845 }
2846
2847 INLINE void I386_OPS_BASE::x87_set_tag(int reg, int tag)
2848 {
2849         int shift = X87_TW_FIELD_SHIFT(reg);
2850
2851         cpustate->x87_tw &= ~(X87_TW_MASK << shift);
2852         cpustate->x87_tw |= (tag << shift);
2853 }
2854
2855 INLINE void I386_OPS_BASE::x87_set_stack_underflow()
2856 {
2857         cpustate->x87_sw &= ~X87_SW_C1;
2858         cpustate->x87_sw |= X87_SW_IE | X87_SW_SF;
2859 }
2860
2861 INLINE void I386_OPS_BASE::x87_set_stack_overflow()
2862 {
2863         cpustate->x87_sw |= X87_SW_C1 | X87_SW_IE | X87_SW_SF;
2864 }
2865
2866 INLINE void I386_OPS_BASE::x87_write_cw( UINT16 cw)
2867 {
2868         cpustate->x87_cw = cw;
2869
2870         /* Update the SoftFloat rounding mode */
2871         float_rounding_mode = x87_to_sf_rc[(cpustate->x87_cw >> X87_CW_RC_SHIFT) & X87_CW_RC_MASK];
2872 }
2873
2874 #endif