source/src/vm/mc6801.cpp

   1 /*
   2         Skelton for retropc emulator
   3
   4         Origin : MAME 0.142
   5         Author : Takeda.Toshiya
   6         Date  : 2011.04.23-
   7
   8         [ MC6801 ]
   9 */
  10 #if defined(_MSC_VER) && (_MSC_VER >= 1400)
  11 #pragma warning( disable : 4996 )
  12 #endif
  13
  14 #include "mc6801.h"
  15 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
  16 #include "../fifo.h"
  17 //#endif
  18 //#ifdef USE_DEBUGGER
  19 #include "debugger.h"
  20 #include "mc6800_consts.h"
  21 #include "mc6801_consts.h"
  22 //#endif
  23 /****************************************************************************/
  24 /* memory                                                                   */
  25 /****************************************************************************/
  26
  27 uint32_t MC6801::RM(uint32_t Addr)
  28 {
  29 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
  30         if(Addr < 0x20) {
  31                 return mc6801_io_r(Addr);
  32         } else if(Addr >= 0x80 && Addr < 0x100 && (ram_ctrl & 0x40)) {
  33                 return ram[Addr & 0x7f];
  34         }
  35 //#endif
  36         return d_mem->read_data8(Addr);
  37 }
  38
  39 void MC6801::WM(uint32_t Addr, uint32_t Value)
  40 {
  41 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
  42         if(Addr < 0x20) {
  43                 mc6801_io_w(Addr, Value);
  44         } else if(Addr >= 0x80 && Addr < 0x100 && (ram_ctrl & 0x40)) {
  45                 ram[Addr & 0x7f] = Value;
  46         } else
  47 //#endif
  48         d_mem->write_data8(Addr, Value);
  49 }
  50 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
  51
  52 uint32_t MC6801::mc6801_io_r(uint32_t offset)
  53 {
  54         switch (offset) {
  55         case 0x00:
  56                 // port1 data direction register
  57                 return port[0].ddr;
  58         case 0x01:
  59                 // port2 data direction register
  60                 return port[1].ddr;
  61         case 0x02:
  62                 // port1 data register
  63                 return (port[0].rreg & ~port[0].ddr) | (port[0].wreg & port[0].ddr);
  64         case 0x03:
  65                 // port2 data register
  66                 return (port[1].rreg & ~port[1].ddr) | (port[1].wreg & port[1].ddr);
  67         case 0x04:
  68                 // port3 data direction register (write only???)
  69                 return port[2].ddr;
  70         case 0x05:
  71                 // port4 data direction register
  72                 return port[3].ddr;
  73         case 0x06:
  74                 // port3 data register
  75                 if(p3csr_is3_flag_read) {
  76                         p3csr_is3_flag_read = false;
  77                         p3csr &= ~P3CSR_IS3_FLAG;
  78                 }
  79                 if(port[2].latched) {
  80                         port[2].latched = false;
  81                         return (port[2].latched_data & ~port[2].ddr) | (port[2].wreg & port[2].ddr);
  82                 }
  83                 return (port[2].rreg & ~port[2].ddr) | (port[2].wreg & port[2].ddr);
  84         case 0x07:
  85                 // port4 data register
  86                 return (port[3].rreg & ~port[3].ddr) | (port[3].wreg & port[3].ddr);
  87         case 0x08:
  88                 // timer control register
  89                 pending_tcsr = 0;
  90                 return tcsr;
  91         case 0x09:
  92                 // free running counter (msb)
  93                 if(!(pending_tcsr & TCSR_TOF)) {
  94                         tcsr &= ~TCSR_TOF;
  95                 }
  96                 return counter.b.h;
  97         case 0x0a:
  98                 // free running counter (lsb)
  99                 return counter.b.l;
 100         case 0x0b:
 101                 // output compare register (msb)
 102                 if(!(pending_tcsr & TCSR_OCF)) {
 103                         tcsr &= ~TCSR_OCF;
 104                 }
 105                 return output_compare.b.h;
 106         case 0x0c:
 107                 // output compare register (lsb)
 108                 if(!(pending_tcsr & TCSR_OCF)) {
 109                         tcsr &= ~TCSR_OCF;
 110                 }
 111                 return output_compare.b.l;
 112         case 0x0d:
 113                 // input capture register (msb)
 114                 if(!(pending_tcsr & TCSR_ICF)) {
 115                         tcsr &= ~TCSR_ICF;
 116                 }
 117                 return (input_capture >> 0) & 0xff;
 118         case 0x0e:
 119                 // input capture register (lsb)
 120                 return (input_capture >> 8) & 0xff;
 121         case 0x0f:
 122                 // port3 control/status register
 123                 p3csr_is3_flag_read = true;
 124                 return p3csr;
 125         case 0x10:
 126                 // rate and mode control register
 127                 return rmcr;
 128         case 0x11:
 129                 if(trcsr & TRCSR_TDRE) {
 130                         trcsr_read_tdre = true;
 131                 }
 132                 if(trcsr & TRCSR_ORFE) {
 133                         trcsr_read_orfe = true;
 134                 }
 135                 if(trcsr & TRCSR_RDRF) {
 136                         trcsr_read_rdrf = true;
 137                 }
 138                 return trcsr;
 139         case 0x12:
 140                 // receive data register
 141                 if(trcsr_read_orfe) {
 142                         trcsr_read_orfe = false;
 143                         trcsr &= ~TRCSR_ORFE;
 144                 }
 145                 if(trcsr_read_rdrf) {
 146                         trcsr_read_rdrf = false;
 147                         trcsr &= ~TRCSR_RDRF;
 148                 }
 149                 return rdr;
 150         case 0x13:
 151                 // transmit data register
 152                 return tdr;
 153         case 0x14:
 154                 // ram control register
 155                 return (ram_ctrl & 0x40) | 0x3f;
 156         }
 157         return 0;
 158 }
 159
 160 void MC6801::mc6801_io_w(uint32_t offset, uint32_t data)
 161 {
 162         switch(offset) {
 163         case 0x00:
 164                 // port1 data direction register
 165                 port[0].ddr = data;
 166                 break;
 167         case 0x01:
 168                 // port2 data direction register
 169                 port[1].ddr = data;
 170                 break;
 171         case 0x02:
 172                 // port1 data register
 173                 if(port[0].wreg != data || port[0].first_write) {
 174                         write_signals(&port[0].outputs, data);
 175                         port[0].wreg = data;
 176                         port[0].first_write = false;
 177                 }
 178                 break;
 179         case 0x03:
 180                 // port2 data register
 181                 if(port[1].wreg != data || port[1].first_write) {
 182                         write_signals(&port[1].outputs, data);
 183                         port[1].wreg = data;
 184                         port[1].first_write = false;
 185                 }
 186                 break;
 187         case 0x04:
 188                 // port3 data direction register
 189                 port[2].ddr = data;
 190                 break;
 191         case 0x05:
 192                 // port4 data direction register
 193                 port[3].ddr = data;
 194                 break;
 195         case 0x06:
 196                 // port3 data register
 197                 if(p3csr_is3_flag_read) {
 198                         p3csr_is3_flag_read = false;
 199                         p3csr &= ~P3CSR_IS3_FLAG;
 200                 }
 201                 if(port[2].wreg != data || port[2].first_write) {
 202                         write_signals(&port[2].outputs, data);
 203                         port[2].wreg = data;
 204                         port[2].first_write = false;
 205                 }
 206                 break;
 207         case 0x07:
 208                 // port4 data register
 209                 if(port[3].wreg != data || port[3].first_write) {
 210                         write_signals(&port[3].outputs, data);
 211                         port[3].wreg = data;
 212                         port[3].first_write = false;
 213                 }
 214                 break;
 215         case 0x08:
 216                 // timer control/status register
 217                 tcsr = data;
 218                 pending_tcsr &= tcsr;
 219                 break;
 220         case 0x09:
 221                 // free running counter (msb)
 222 //#ifdef HAS_HD6301
 223 //              latch09 = data & 0xff;
 224 //#endif
 225                 CT = 0xfff8;
 226                 TOH = CTH;
 227                 MODIFIED_counters;
 228                 break;
 229 //#ifdef HAS_HD6301
 230 //      case 0x0a:
 231 //              // free running counter (lsb)
 232 //              CT = (latch09 << 8) | (data & 0xff);
 233 //              TOH = CTH;
 234 //              MODIFIED_counters;
 235 ///             break;
 236 //#endif
 237         case 0x0b:
 238                 // output compare register (msb)
 239                 if(output_compare.b.h != data) {
 240                         output_compare.b.h = data;
 241                         MODIFIED_counters;
 242                 }
 243         tcsr &=~TCSR_OCF;
 244                 break;
 245         case 0x0c:
 246                 // output compare register (lsb)
 247                 if(output_compare.b.l != data) {
 248                         output_compare.b.l = data;
 249                         MODIFIED_counters;
 250                 }
 251         tcsr &=~TCSR_OCF;
 252                 break;
 253         case 0x0f:
 254                 // port3 control/status register
 255                 p3csr = (p3csr & P3CSR_IS3_FLAG) | (data & ~P3CSR_IS3_FLAG);
 256                 break;
 257         case 0x10:
 258                 // rate and mode control register
 259                 rmcr = data;
 260                 break;
 261         case 0x11:
 262                 // transmit/receive control/status register
 263                 trcsr = (trcsr & 0xe0) | (data & 0x1f);
 264                 break;
 265         case 0x13:
 266                 // transmit data register
 267                 if(trcsr_read_tdre) {
 268                         trcsr_read_tdre = false;
 269                         trcsr &= ~TRCSR_TDRE;
 270                 }
 271                 tdr = data;
 272                 break;
 273         case 0x14:
 274                 // ram control register
 275                 ram_ctrl = data;
 276                 break;
 277         }
 278 }
 279
 280 void MC6801::increment_counter(int amount)
 281 {
 282         total_icount += amount;
 283         icount -= amount;
 284
 285         // timer
 286         if((CTD += amount) >= timer_next) {
 287                 /* OCI */
 288                 if( CTD >= OCD) {
 289                         OCH++;  // next IRQ point
 290                         tcsr |= TCSR_OCF;
 291                         pending_tcsr |= TCSR_OCF;
 292                 }
 293                 /* TOI */
 294                 if( CTD >= TOD) {
 295                         TOH++;  // next IRQ point
 296                         tcsr |= TCSR_TOF;
 297                         pending_tcsr |= TCSR_TOF;
 298                 }
 299                 /* set next event */
 300                 SET_TIMER_EVENT;
 301         }
 302
 303         // serial i/o
 304         if((sio_counter -= amount) <= 0) {
 305                 if((trcsr & TRCSR_TE) && !(trcsr & TRCSR_TDRE)) {
 306                         write_signals(&outputs_sio, tdr);
 307                         trcsr |= TRCSR_TDRE;
 308                 }
 309                 if((trcsr & TRCSR_RE) && !recv_buffer->empty()) {
 310                         if(trcsr & TRCSR_WU) {
 311                                 // skip 10 bits
 312                                 trcsr &= ~TRCSR_WU;
 313                                 recv_buffer->read();
 314                         } else if(!(trcsr & TRCSR_RDRF)) {
 315                                 // note: wait reveived data is read by cpu, so overrun framing error never occurs
 316                                 rdr = recv_buffer->read();
 317                                 trcsr |= TRCSR_RDRF;
 318                         }
 319                 }
 320                 sio_counter += RMCR_SS[rmcr & 3];
 321         }
 322 }
 323 //#else
 324
 325
 326 void MC6801::initialize()
 327 {
 328         MC6800::initialize();
 329
 330 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 331         recv_buffer = new FIFO(0x10000);
 332         ram_ctrl = 0xc0;
 333 //#endif
 334 //#ifdef USE_DEBUGGER
 335         if(__USE_DEBUGGER) {
 336                 d_mem_stored = d_mem;
 337                 d_debugger->set_context_mem(d_mem);
 338         }
 339 //#endif
 340 }
 341 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 342 void MC6801::release()
 343 {
 344         recv_buffer->release();
 345         delete recv_buffer;
 346 }
 347 //#endif
 348
 349 void MC6801::reset()
 350 {
 351         CC = 0xc0;
 352         SEI; /* IRQ disabled */
 353         PCD = RM16(0xfffe);
 354         S = X = D = EA = 0;
 355
 356         wai_state = 0;
 357         int_state = 0;
 358
 359         icount = 0;
 360
 361 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 362         for(int i = 0; i < 4; i++) {
 363                 port[i].ddr = 0x00;
 364                 port[i].first_write = true;
 365                 port[i].latched = false;
 366         }
 367         p3csr = 0x00;
 368         p3csr_is3_flag_read = false;
 369         sc1_state = sc2_state = false;
 370
 371         tcsr = pending_tcsr = 0x00;
 372         CTD = 0x0000;
 373         OCD = 0xffff;
 374         TOD = 0xffff;
 375
 376         recv_buffer->clear();
 377         trcsr = TRCSR_TDRE;
 378         trcsr_read_tdre = trcsr_read_orfe = trcsr_read_rdrf = false;
 379         rmcr = 0x00;
 380         sio_counter = RMCR_SS[rmcr & 3];
 381
 382         ram_ctrl |= 0x40;
 383 //#endif
 384 }
 385
 386 void MC6801::write_signal(int id, uint32_t data, uint32_t mask)
 387 {
 388         switch(id) {
 389         case SIG_CPU_IRQ:
 390                 if(data & mask) {
 391                         int_state |= INT_REQ_BIT;
 392                 } else {
 393                         int_state &= ~INT_REQ_BIT;
 394                 }
 395                 break;
 396         case SIG_CPU_NMI:
 397                 if(data & mask) {
 398                         int_state |= NMI_REQ_BIT;
 399                 } else {
 400                         int_state &= ~NMI_REQ_BIT;
 401                 }
 402                 break;
 403 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 404         case SIG_MC6801_PORT_1:
 405                 port[0].rreg = (port[0].rreg & ~mask) | (data & mask);
 406                 break;
 407         case SIG_MC6801_PORT_2:
 408                 if((mask & 1) && (port[1].rreg & 1) != (data & 1) && (tcsr & 2) == ((data << 1) & 2)) {
 409                         // active TIN edge in
 410                         tcsr |= TCSR_ICF;
 411                         pending_tcsr |= TCSR_ICF;
 412                         input_capture = CT;
 413                 }
 414                 port[1].rreg = (port[1].rreg & ~mask) | (data & mask);
 415                 break;
 416         case SIG_MC6801_PORT_3:
 417                 port[2].rreg = (port[2].rreg & ~mask) | (data & mask);
 418                 break;
 419         case SIG_MC6801_PORT_4:
 420                 port[3].rreg = (port[3].rreg & ~mask) | (data & mask);
 421                 break;
 422         case SIG_MC6801_PORT_3_SC1:
 423                 if(sc1_state && !(data & mask)) {
 424                         // SC1: H -> L
 425                         if(!port[2].latched && (p3csr & P3CSR_LE)) {
 426                                 port[2].latched_data = port[2].rreg;
 427                                 port[2].latched = true;
 428                                 p3csr |= P3CSR_IS3_FLAG;
 429                         }
 430                 }
 431                 sc1_state = ((data & mask) != 0);
 432                 break;
 433         case SIG_MC6801_PORT_3_SC2:
 434                 sc2_state = ((data & mask) != 0);
 435                 break;
 436         case SIG_MC6801_SIO_RECV:
 437                 recv_buffer->write(data & mask);
 438                 break;
 439 //#endif
 440         }
 441 }
 442
 443 int MC6801::run(int clock)
 444 {
 445         // run cpu
 446         if(clock == -1) {
 447                 // run only one opcode
 448
 449                 CLEANUP_COUNTERS();
 450
 451                 icount = 0;
 452                 run_one_opecode();
 453                 return -icount;
 454         } else {
 455                 /* run cpu while given clocks */
 456
 457                 CLEANUP_COUNTERS();
 458
 459                 icount += clock;
 460                 int first_icount = icount;
 461
 462                 while(icount > 0) {
 463                         run_one_opecode();
 464                 }
 465                 return first_icount - icount;
 466         }
 467 }
 468
 469 void MC6801::run_one_opecode()
 470 {
 471         if(wai_state & (MC6800_WAI | HD6301_SLP)) {
 472                 increment_counter(1);
 473         } else {
 474                 do {
 475                         one_more_insn = false;
 476                         if(__USE_DEBUGGER) {
 477                                 bool now_debugging = d_debugger->now_debugging;
 478                                 if(now_debugging) {
 479                                         d_debugger->check_break_points(PC);
 480                                         if(d_debugger->now_suspended) {
 481                                                 emu->mute_sound();
 482                                                 d_debugger->now_waiting = true;
 483                                                 while(d_debugger->now_debugging && d_debugger->now_suspended) {
 484                                                         emu->sleep(10);
 485                                                 }
 486                                                 d_debugger->now_waiting = false;
 487                                         }
 488                                         if(d_debugger->now_debugging) {
 489                                                 d_mem = d_debugger;
 490                                         } else {
 491                                                 now_debugging = false;
 492                                         }
 493
 494                                         d_debugger->add_cpu_trace(PC);
 495                                         uint8_t ireg = M_RDOP(PCD);
 496                                         prevpc = PC;
 497                                         PC++;
 498                                         insn(ireg);
 499                                         increment_counter(cycles[ireg]);
 500
 501                                         if(now_debugging) {
 502                                                 if(!d_debugger->now_going) {
 503                                                         d_debugger->now_suspended = true;
 504                                                 }
 505                                                 d_mem = d_mem_stored;
 506                                         }
 507                                 } else {
 508                                         if(__USE_DEBUGGER) d_debugger->add_cpu_trace(PC);
 509                                         uint8_t ireg = M_RDOP(PCD);
 510                                         prevpc = PC;
 511                                         PC++;
 512                                         insn(ireg);
 513                                         increment_counter(cycles[ireg]);
 514                                 }
 515                         } else {
 516                                 uint8_t ireg = M_RDOP(PCD);
 517                                 prevpc = PC;
 518                                 PC++;
 519                                 insn(ireg);
 520                                 increment_counter(cycles[ireg]);
 521                         }
 522                 } while(one_more_insn);
 523         }
 524
 525         // check interrupt
 526         if(int_state & NMI_REQ_BIT) {
 527                 wai_state &= ~HD6301_SLP;
 528                 int_state &= ~NMI_REQ_BIT;
 529                 enter_interrupt(0xfffc);
 530         } else if(int_state & INT_REQ_BIT) {
 531                 wai_state &= ~HD6301_SLP;
 532                 if(!(CC & 0x10)) {
 533                         int_state &= ~INT_REQ_BIT;
 534                         enter_interrupt(0xfff8);
 535                 }
 536 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 537         } else if((tcsr & (TCSR_EICI | TCSR_ICF)) == (TCSR_EICI | TCSR_ICF)) {
 538                 wai_state &= ~HD6301_SLP;
 539                 if(!(CC & 0x10)) {
 540                         TAKE_ICI;
 541                 }
 542         } else if((tcsr & (TCSR_EOCI | TCSR_OCF)) == (TCSR_EOCI | TCSR_OCF)) {
 543                 wai_state &= ~HD6301_SLP;
 544                 if(!(CC & 0x10)) {
 545                         TAKE_OCI;
 546                 }
 547         } else if((tcsr & (TCSR_ETOI | TCSR_TOF)) == (TCSR_ETOI | TCSR_TOF)) {
 548                 wai_state &= ~HD6301_SLP;
 549                 if(!(CC & 0x10)) {
 550                         TAKE_TOI;
 551                 }
 552         } else if(((trcsr & (TRCSR_RIE | TRCSR_RDRF)) == (TRCSR_RIE | TRCSR_RDRF)) ||
 553                   ((trcsr & (TRCSR_RIE | TRCSR_ORFE)) == (TRCSR_RIE | TRCSR_ORFE)) ||
 554                   ((trcsr & (TRCSR_TIE | TRCSR_TDRE)) == (TRCSR_TIE | TRCSR_TDRE))) {
 555                 wai_state &= ~HD6301_SLP;
 556                 if(!(CC & 0x10)) {
 557                         TAKE_SCI;
 558                 }
 559 //#endif
 560         }
 561 }
 562
 563 int MC6801::debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len)
 564 {
 565         uint8_t ops[4];
 566         for(int i = 0; i < 4; i++) {
 567                 int wait;
 568                 ops[i] = d_mem_stored->read_data8w(pc + i, &wait);
 569         }
 570         return Dasm680x(6801, buffer, pc, ops, ops, d_debugger->first_symbol);
 571         return 0;
 572 }
 573
 574 void MC6801::insn(uint8_t code)
 575 {
 576         switch(code) {
 577         case 0x00: illegal(); break;
 578         case 0x01: nop(); break;
 579         case 0x02: illegal(); break;
 580         case 0x03: illegal(); break;
 581 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 582         case 0x04: lsrd(); break;
 583         case 0x05: asld(); break;
 584 //#else
 585 //      case 0x04: illegal(); break;
 586 //      case 0x05: illegal(); break;
 587 //#endif
 588         case 0x06: tap(); break;
 589         case 0x07: tpa(); break;
 590         case 0x08: inx(); break;
 591         case 0x09: dex(); break;
 592         case 0x0a: clv(); break;
 593         case 0x0b: sev(); break;
 594         case 0x0c: clc(); break;
 595         case 0x0d: sec(); break;
 596         case 0x0e: cli(); break;
 597         case 0x0f: sei(); break;
 598         case 0x10: sba(); break;
 599         case 0x11: cba(); break;
 600 //#if defined(HAS_HD6301)
 601 //      case 0x12: undoc1(); break;
 602 //      case 0x13: undoc2(); break;
 603 //#else
 604         case 0x12: illegal(); break;
 605         case 0x13: illegal(); break;
 606 //#endif
 607         case 0x14: illegal(); break;
 608         case 0x15: illegal(); break;
 609         case 0x16: tab(); break;
 610         case 0x17: tba(); break;
 611 //#if defined(HAS_HD6301)
 612 //      case 0x18: xgdx(); break;
 613 //#else
 614         case 0x18: illegal(); break;
 615 //#endif
 616         case 0x19: daa(); break;
 617 //#if defined(HAS_HD6301)
 618 //      case 0x1a: slp(); break;
 619 //#else
 620         case 0x1a: illegal(); break;
 621 //#endif
 622         case 0x1b: aba(); break;
 623         case 0x1c: illegal(); break;
 624         case 0x1d: illegal(); break;
 625         case 0x1e: illegal(); break;
 626         case 0x1f: illegal(); break;
 627         case 0x20: bra(); break;
 628         case 0x21: brn(); break;
 629         case 0x22: bhi(); break;
 630         case 0x23: bls(); break;
 631         case 0x24: bcc(); break;
 632         case 0x25: bcs(); break;
 633         case 0x26: bne(); break;
 634         case 0x27: beq(); break;
 635         case 0x28: bvc(); break;
 636         case 0x29: bvs(); break;
 637         case 0x2a: bpl(); break;
 638         case 0x2b: bmi(); break;
 639         case 0x2c: bge(); break;
 640         case 0x2d: blt(); break;
 641         case 0x2e: bgt(); break;
 642         case 0x2f: ble(); break;
 643         case 0x30: tsx(); break;
 644         case 0x31: ins(); break;
 645         case 0x32: pula(); break;
 646         case 0x33: pulb(); break;
 647         case 0x34: des(); break;
 648         case 0x35: txs(); break;
 649         case 0x36: psha(); break;
 650         case 0x37: pshb(); break;
 651 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 652         case 0x38: pulx(); break;
 653 //#else
 654 //      case 0x38: illegal(); break;
 655 //#endif
 656         case 0x39: rts(); break;
 657 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 658         case 0x3a: abx(); break;
 659 //#else
 660 //      case 0x3a: illegal(); break;
 661 //#endif
 662         case 0x3b: rti(); break;
 663 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 664         case 0x3c: pshx(); break;
 665         case 0x3d: mul(); break;
 666 //#else
 667 //      case 0x3c: illegal(); break;
 668 //      case 0x3d: illegal(); break;
 669 //#endif
 670         case 0x3e: wai(); break;
 671         case 0x3f: swi(); break;
 672         case 0x40: nega(); break;
 673         case 0x41: illegal(); break;
 674         case 0x42: illegal(); break;
 675         case 0x43: coma(); break;
 676         case 0x44: lsra(); break;
 677         case 0x45: illegal(); break;
 678         case 0x46: rora(); break;
 679         case 0x47: asra(); break;
 680         case 0x48: asla(); break;
 681         case 0x49: rola(); break;
 682         case 0x4a: deca(); break;
 683         case 0x4b: illegal(); break;
 684         case 0x4c: inca(); break;
 685         case 0x4d: tsta(); break;
 686         case 0x4e: illegal(); break;
 687         case 0x4f: clra(); break;
 688         case 0x50: negb(); break;
 689         case 0x51: illegal(); break;
 690         case 0x52: illegal(); break;
 691         case 0x53: comb(); break;
 692         case 0x54: lsrb(); break;
 693         case 0x55: illegal(); break;
 694         case 0x56: rorb(); break;
 695         case 0x57: asrb(); break;
 696         case 0x58: aslb(); break;
 697         case 0x59: rolb(); break;
 698         case 0x5a: decb(); break;
 699         case 0x5b: illegal(); break;
 700         case 0x5c: incb(); break;
 701         case 0x5d: tstb(); break;
 702         case 0x5e: illegal(); break;
 703         case 0x5f: clrb(); break;
 704         case 0x60: neg_ix(); break;
 705 //#if defined(HAS_HD6301)
 706 //      case 0x61: aim_ix(); break;
 707 //      case 0x62: oim_ix(); break;
 708 //#else
 709         case 0x61: illegal(); break;
 710         case 0x62: illegal(); break;
 711 //#endif
 712         case 0x63: com_ix(); break;
 713         case 0x64: lsr_ix(); break;
 714 //#if defined(HAS_HD6301)
 715 //      case 0x65: eim_ix(); break;
 716 //#else
 717         case 0x65: illegal(); break;
 718 //#endif
 719         case 0x66: ror_ix(); break;
 720         case 0x67: asr_ix(); break;
 721         case 0x68: asl_ix(); break;
 722         case 0x69: rol_ix(); break;
 723         case 0x6a: dec_ix(); break;
 724 //#if defined(HAS_HD6301)
 725 //      case 0x6b: tim_ix(); break;
 726 //#else
 727         case 0x6b: illegal(); break;
 728 //#endif
 729         case 0x6c: inc_ix(); break;
 730         case 0x6d: tst_ix(); break;
 731         case 0x6e: jmp_ix(); break;
 732         case 0x6f: clr_ix(); break;
 733         case 0x70: neg_ex(); break;
 734 //#if defined(HAS_HD6301)
 735 //      case 0x71: aim_di(); break;
 736 //      case 0x72: oim_di(); break;
 737 //#elif defined(HAS_MB8861)
 738 //      case 0x71: nim_ix(); break;
 739 //      case 0x72: oim_ix_mb8861(); break;
 740 //#else
 741         case 0x71: illegal(); break;
 742         case 0x72: illegal(); break;
 743 //#endif
 744         case 0x73: com_ex(); break;
 745         case 0x74: lsr_ex(); break;
 746 //#if defined(HAS_HD6301)
 747 //      case 0x75: eim_di(); break;
 748 //#elif defined(HAS_MB8861)
 749 //      case 0x75: xim_ix(); break;
 750 //#else
 751         case 0x75: illegal(); break;
 752 //#endif
 753         case 0x76: ror_ex(); break;
 754         case 0x77: asr_ex(); break;
 755         case 0x78: asl_ex(); break;
 756         case 0x79: rol_ex(); break;
 757         case 0x7a: dec_ex(); break;
 758 //#if defined(HAS_HD6301)
 759 //      case 0x7b: tim_di(); break;
 760 //#elif defined(HAS_MB8861)
 761 //      case 0x7b: tmm_ix(); break;
 762 //#else
 763         case 0x7b: illegal(); break;
 764 //#endif
 765         case 0x7c: inc_ex(); break;
 766         case 0x7d: tst_ex(); break;
 767         case 0x7e: jmp_ex(); break;
 768         case 0x7f: clr_ex(); break;
 769         case 0x80: suba_im(); break;
 770         case 0x81: cmpa_im(); break;
 771         case 0x82: sbca_im(); break;
 772 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 773         case 0x83: subd_im(); break;
 774 //#else
 775 //      case 0x83: illegal(); break;
 776 //#endif
 777         case 0x84: anda_im(); break;
 778         case 0x85: bita_im(); break;
 779         case 0x86: lda_im(); break;
 780         case 0x87: sta_im(); break;
 781         case 0x88: eora_im(); break;
 782         case 0x89: adca_im(); break;
 783         case 0x8a: ora_im(); break;
 784         case 0x8b: adda_im(); break;
 785 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 786         case 0x8c: cpx_im (); break;
 787 //#else
 788 //      case 0x8c: cmpx_im(); break;
 789 //#endif
 790         case 0x8d: bsr(); break;
 791         case 0x8e: lds_im(); break;
 792         case 0x8f: sts_im(); break;
 793         case 0x90: suba_di(); break;
 794         case 0x91: cmpa_di(); break;
 795         case 0x92: sbca_di(); break;
 796 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 797         case 0x93: subd_di(); break;
 798 //#else
 799 //      case 0x93: illegal(); break;
 800 //#endif
 801         case 0x94: anda_di(); break;
 802         case 0x95: bita_di(); break;
 803         case 0x96: lda_di(); break;
 804         case 0x97: sta_di(); break;
 805         case 0x98: eora_di(); break;
 806         case 0x99: adca_di(); break;
 807         case 0x9a: ora_di(); break;
 808         case 0x9b: adda_di(); break;
 809 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 810         case 0x9c: cpx_di (); break;
 811 //#else
 812 //      case 0x9c: cmpx_di(); break;
 813 //#endif
 814         case 0x9d: jsr_di(); break;
 815         case 0x9e: lds_di(); break;
 816         case 0x9f: sts_di(); break;
 817         case 0xa0: suba_ix(); break;
 818         case 0xa1: cmpa_ix(); break;
 819         case 0xa2: sbca_ix(); break;
 820 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 821         case 0xa3: subd_ix(); break;
 822 //#else
 823 //      case 0xa3: illegal(); break;
 824 //#endif
 825         case 0xa4: anda_ix(); break;
 826         case 0xa5: bita_ix(); break;
 827         case 0xa6: lda_ix(); break;
 828         case 0xa7: sta_ix(); break;
 829         case 0xa8: eora_ix(); break;
 830         case 0xa9: adca_ix(); break;
 831         case 0xaa: ora_ix(); break;
 832         case 0xab: adda_ix(); break;
 833 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 834         case 0xac: cpx_ix (); break;
 835 //#else
 836 //      case 0xac: cmpx_ix(); break;
 837 //#endif
 838         case 0xad: jsr_ix(); break;
 839         case 0xae: lds_ix(); break;
 840         case 0xaf: sts_ix(); break;
 841         case 0xb0: suba_ex(); break;
 842         case 0xb1: cmpa_ex(); break;
 843         case 0xb2: sbca_ex(); break;
 844 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 845         case 0xb3: subd_ex(); break;
 846 //#else
 847 //      case 0xb3: illegal(); break;
 848 //#endif
 849         case 0xb4: anda_ex(); break;
 850         case 0xb5: bita_ex(); break;
 851         case 0xb6: lda_ex(); break;
 852         case 0xb7: sta_ex(); break;
 853         case 0xb8: eora_ex(); break;
 854         case 0xb9: adca_ex(); break;
 855         case 0xba: ora_ex(); break;
 856         case 0xbb: adda_ex(); break;
 857 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 858         case 0xbc: cpx_ex (); break;
 859 //#else
 860 //      case 0xbc: cmpx_ex(); break;
 861 //#endif
 862         case 0xbd: jsr_ex(); break;
 863         case 0xbe: lds_ex(); break;
 864         case 0xbf: sts_ex(); break;
 865         case 0xc0: subb_im(); break;
 866         case 0xc1: cmpb_im(); break;
 867         case 0xc2: sbcb_im(); break;
 868 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 869         case 0xc3: addd_im(); break;
 870 //#else
 871 //      case 0xc3: illegal(); break;
 872 //#endif
 873         case 0xc4: andb_im(); break;
 874         case 0xc5: bitb_im(); break;
 875         case 0xc6: ldb_im(); break;
 876         case 0xc7: stb_im(); break;
 877         case 0xc8: eorb_im(); break;
 878         case 0xc9: adcb_im(); break;
 879         case 0xca: orb_im(); break;
 880         case 0xcb: addb_im(); break;
 881 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 882         case 0xcc: ldd_im(); break;
 883         case 0xcd: std_im(); break;
 884 //#else
 885 //      case 0xcc: illegal(); break;
 886 //      case 0xcd: illegal(); break;
 887 //#endif
 888         case 0xce: ldx_im(); break;
 889         case 0xcf: stx_im(); break;
 890         case 0xd0: subb_di(); break;
 891         case 0xd1: cmpb_di(); break;
 892         case 0xd2: sbcb_di(); break;
 893 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 894         case 0xd3: addd_di(); break;
 895 //#else
 896 //      case 0xd3: illegal(); break;
 897 //#endif
 898         case 0xd4: andb_di(); break;
 899         case 0xd5: bitb_di(); break;
 900         case 0xd6: ldb_di(); break;
 901         case 0xd7: stb_di(); break;
 902         case 0xd8: eorb_di(); break;
 903         case 0xd9: adcb_di(); break;
 904         case 0xda: orb_di(); break;
 905         case 0xdb: addb_di(); break;
 906 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 907         case 0xdc: ldd_di(); break;
 908         case 0xdd: std_di(); break;
 909 //#else
 910 //      case 0xdc: illegal(); break;
 911 //      case 0xdd: illegal(); break;
 912 //#endif
 913         case 0xde: ldx_di(); break;
 914         case 0xdf: stx_di(); break;
 915         case 0xe0: subb_ix(); break;
 916         case 0xe1: cmpb_ix(); break;
 917         case 0xe2: sbcb_ix(); break;
 918 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 919         case 0xe3: addd_ix(); break;
 920 //#else
 921 //      case 0xe3: illegal(); break;
 922 //#endif
 923         case 0xe4: andb_ix(); break;
 924         case 0xe5: bitb_ix(); break;
 925         case 0xe6: ldb_ix(); break;
 926         case 0xe7: stb_ix(); break;
 927         case 0xe8: eorb_ix(); break;
 928         case 0xe9: adcb_ix(); break;
 929         case 0xea: orb_ix(); break;
 930         case 0xeb: addb_ix(); break;
 931 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 932         case 0xec: ldd_ix(); break;
 933         case 0xed: std_ix(); break;
 934 //#elif defined(HAS_MB8861)
 935 //      case 0xec: adx_im(); break;
 936 //      case 0xed: illegal(); break;
 937 //#else
 938 //      case 0xec: illegal(); break;
 939 //      case 0xed: illegal(); break;
 940 //#endif
 941         case 0xee: ldx_ix(); break;
 942         case 0xef: stx_ix(); break;
 943         case 0xf0: subb_ex(); break;
 944         case 0xf1: cmpb_ex(); break;
 945         case 0xf2: sbcb_ex(); break;
 946 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 947         case 0xf3: addd_ex(); break;
 948 //#else
 949 //      case 0xf3: illegal(); break;
 950 //#endif
 951         case 0xf4: andb_ex(); break;
 952         case 0xf5: bitb_ex(); break;
 953         case 0xf6: ldb_ex(); break;
 954         case 0xf7: stb_ex(); break;
 955         case 0xf8: eorb_ex(); break;
 956         case 0xf9: adcb_ex(); break;
 957         case 0xfa: orb_ex(); break;
 958         case 0xfb: addb_ex(); break;
 959 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
 960         case 0xfc: ldd_ex(); break;
 961         case 0xfd: std_ex(); break;
 962 //#elif defined(HAS_MB8861)
 963 //      case 0xfc: adx_ex(); break;
 964 //      case 0xfd: illegal(); break;
 965 //#else
 966 //      case 0xfc: illegal(); break;
 967 //      case 0xfd: illegal(); break;
 968 //#endif
 969         case 0xfe: ldx_ex(); break;
 970         case 0xff: stx_ex(); break;
 971 #if defined(_MSC_VER) && (_MSC_VER >= 1200)
 972         default: __assume(0);
 973 #endif
 974         }
 975 }
 976
 977 /* $04 LSRD inherent -0*-* */
 978 void MC6801::lsrd()
 979 {
 980         uint16_t t;
 981         CLR_NZC;
 982         t = D;
 983         CC |= (t & 0x0001);
 984         t >>= 1;
 985         SET_Z16(t);
 986         D = t;
 987 }
 988
 989 /* $05 ASLD inherent ?**** */
 990 void MC6801::asld()
 991 {
 992         int r;
 993         uint16_t t;
 994         t = D;
 995         r = t << 1;
 996         CLR_NZVC;
 997         SET_FLAGS16(t, t, r);
 998         D = r;
 999 }
1000 /* $38 PULX inherent ----- */
1001 void MC6801::pulx()
1002 {
1003         PULLWORD(pX);
1004 }
1005
1006 /* $3a ABX inherent ----- */
1007 void MC6801::abx()
1008 {
1009         X += B;
1010 }
1011 /* $3c PSHX inherent ----- */
1012 void MC6801::pshx()
1013 {
1014         PUSHWORD(pX);
1015 }
1016
1017 /* $3d MUL inherent --*-@ */
1018 void MC6801::mul()
1019 {
1020         uint16_t t;
1021         t = A*B;
1022         CLR_C;
1023         if(t & 0x80) SEC;
1024         D = t;
1025 }
1026 /* $83 SUBD immediate -**** */
1027 void MC6801::subd_im()
1028 {
1029         uint32_t r, d;
1030         pair_t b;
1031         IMMWORD(b);
1032         d = D;
1033         r = d - b.d;
1034         CLR_NZVC;
1035         SET_FLAGS16(d, b.d, r);
1036         D = r;
1037 }
1038
1039 /* $8c CPX immediate -**** (6801) */
1040 void MC6801::cpx_im()
1041 {
1042         uint32_t r, d;
1043         pair_t b;
1044         IMMWORD(b);
1045         d = X;
1046         r = d - b.d;
1047         CLR_NZVC;
1048         SET_FLAGS16(d, b.d, r);
1049 }
1050
1051 /* $93 SUBD direct -**** */
1052 void MC6801::subd_di()
1053 {
1054         uint32_t r, d;
1055         pair_t b;
1056         DIRWORD(b);
1057         d = D;
1058         r = d - b.d;
1059         CLR_NZVC;
1060         SET_FLAGS16(d, b.d, r);
1061         D = r;
1062 }
1063
1064 /* $9c CPX direct -**** (6801) */
1065 void MC6801::cpx_di()
1066 {
1067         uint32_t r, d;
1068         pair_t b;
1069         DIRWORD(b);
1070         d = X;
1071         r = d - b.d;
1072         CLR_NZVC;
1073         SET_FLAGS16(d, b.d, r);
1074 }
1075 /* $a3 SUBD indexed -**** */
1076 void MC6801::subd_ix()
1077 {
1078         uint32_t r, d;
1079         pair_t b;
1080         IDXWORD(b);
1081         d = D;
1082         r = d - b.d;
1083         CLR_NZVC;
1084         SET_FLAGS16(d, b.d, r);
1085         D = r;
1086 }
1087
1088 /* $ac CPX indexed -**** (6801)*/
1089 void MC6801::cpx_ix()
1090 {
1091         uint32_t r, d;
1092         pair_t b;
1093         IDXWORD(b);
1094         d = X;
1095         r = d - b.d;
1096         CLR_NZVC;
1097         SET_FLAGS16(d, b.d, r);
1098 }
1099
1100 /* $b3 SUBD extended -**** */
1101 void MC6801::subd_ex()
1102 {
1103         uint32_t r, d;
1104         pair_t b;
1105         EXTWORD(b);
1106         d = D;
1107         r = d - b.d;
1108         CLR_NZVC;
1109         SET_FLAGS16(d, b.d, r);
1110         D = r;
1111 }
1112
1113 /* $bc CPX extended -**** (6801) */
1114 void MC6801::cpx_ex()
1115 {
1116         uint32_t r, d;
1117         pair_t b;
1118         EXTWORD(b);
1119         d = X;
1120         r = d - b.d;
1121         CLR_NZVC;
1122         SET_FLAGS16(d, b.d, r);
1123 }
1124
1125 /* $c3 ADDD immediate -**** */
1126 void MC6801::addd_im()
1127 {
1128         uint32_t r, d;
1129         pair_t b;
1130         IMMWORD(b);
1131         d = D;
1132         r = d + b.d;
1133         CLR_NZVC;
1134         SET_FLAGS16(d, b.d, r);
1135         D = r;
1136 }
1137
1138 /* $CC LDD immediate -**0- */
1139 void MC6801::ldd_im()
1140 {
1141         IMMWORD(pD);
1142         CLR_NZV;
1143         SET_NZ16(D);
1144 }
1145
1146 /* is this a legal instruction? */
1147 /* $cd STD immediate -**0- */
1148 void MC6801::std_im()
1149 {
1150         IMM16;
1151         CLR_NZV;
1152         SET_NZ16(D);
1153         WM16(EAD, &pD);
1154 }
1155
1156 /* $d3 ADDD direct -**** */
1157 void MC6801::addd_di()
1158 {
1159         uint32_t r, d;
1160         pair_t b;
1161         DIRWORD(b);
1162         d = D;
1163         r = d + b.d;
1164         CLR_NZVC;
1165         SET_FLAGS16(d, b.d, r);
1166         D = r;
1167 }
1168
1169 /* $dc LDD direct -**0- */
1170 void MC6801::ldd_di()
1171 {
1172         DIRWORD(pD);
1173         CLR_NZV;
1174         SET_NZ16(D);
1175 }
1176
1177 /* $dd STD direct -**0- */
1178 void MC6801::std_di()
1179 {
1180         DIRECT;
1181         CLR_NZV;
1182         SET_NZ16(D);
1183         WM16(EAD, &pD);
1184 }
1185
1186 /* $e3 ADDD indexed -**** */
1187 void MC6801::addd_ix()
1188 {
1189         uint32_t r, d;
1190         pair_t b;
1191         IDXWORD(b);
1192         d = D;
1193         r = d + b.d;
1194         CLR_NZVC;
1195         SET_FLAGS16(d, b.d, r);
1196         D = r;
1197 }
1198
1199 /* $ec LDD indexed -**0- */
1200 void MC6801::ldd_ix()
1201 {
1202         IDXWORD(pD);
1203         CLR_NZV;
1204         SET_NZ16(D);
1205 }
1206
1207 /* $ed STD indexed -**0- */
1208 void MC6801::std_ix()
1209 {
1210         INDEXED;
1211         CLR_NZV;
1212         SET_NZ16(D);
1213         WM16(EAD, &pD);
1214 }
1215
1216 /* $f3 ADDD extended -**** */
1217 void MC6801::addd_ex()
1218 {
1219         uint32_t r, d;
1220         pair_t b;
1221         EXTWORD(b);
1222         d = D;
1223         r = d + b.d;
1224         CLR_NZVC;
1225         SET_FLAGS16(d, b.d, r);
1226         D = r;
1227 }
1228
1229 /* $fc LDD extended -**0- */
1230 void MC6801::ldd_ex()
1231 {
1232         EXTWORD(pD);
1233         CLR_NZV;
1234         SET_NZ16(D);
1235 }
1236
1237 /* $fd STD extended -**0- */
1238 void MC6801::std_ex()
1239 {
1240         EXTENDED;
1241         CLR_NZV;
1242         SET_NZ16(D);
1243         WM16(EAD, &pD);
1244 }
1245
1246 #define STATE_VERSION   3
1247
1248 #include "../statesub.h"
1249
1250 void MC6801::decl_state()
1251 {
1252         enter_decl_state(STATE_VERSION);
1253
1254         DECL_STATE_ENTRY_PAIR(pc);
1255         DECL_STATE_ENTRY_UINT16(prevpc);
1256         DECL_STATE_ENTRY_PAIR(sp);
1257         DECL_STATE_ENTRY_PAIR(ix);
1258         DECL_STATE_ENTRY_PAIR(acc_d);
1259         DECL_STATE_ENTRY_PAIR(ea);
1260         DECL_STATE_ENTRY_UINT8(cc);
1261         DECL_STATE_ENTRY_INT32(wai_state);
1262         DECL_STATE_ENTRY_INT32(int_state);
1263         if(__USE_DEBUGGER) {
1264                 DECL_STATE_ENTRY_UINT64(total_icount);
1265         }
1266         DECL_STATE_ENTRY_INT32(icount);
1267 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
1268         for(int i = 0; i < 4; i++) {
1269                 DECL_STATE_ENTRY_UINT8_MEMBER(port[i].wreg, i);
1270                 DECL_STATE_ENTRY_UINT8_MEMBER(port[i].rreg, i);
1271                 DECL_STATE_ENTRY_UINT8_MEMBER(port[i].ddr, i);
1272                 DECL_STATE_ENTRY_UINT8_MEMBER(port[i].latched_data, i);
1273                 DECL_STATE_ENTRY_BOOL_MEMBER(port[i].latched, i);
1274                 DECL_STATE_ENTRY_BOOL_MEMBER(port[i].first_write, i);
1275         }
1276         DECL_STATE_ENTRY_UINT8(p3csr);
1277         DECL_STATE_ENTRY_BOOL(p3csr_is3_flag_read);
1278         DECL_STATE_ENTRY_BOOL(sc1_state);
1279         DECL_STATE_ENTRY_BOOL(sc2_state);
1280         DECL_STATE_ENTRY_PAIR(counter);
1281         DECL_STATE_ENTRY_PAIR(output_compare);
1282         DECL_STATE_ENTRY_PAIR(timer_over);
1283         DECL_STATE_ENTRY_UINT8(tcsr);
1284         DECL_STATE_ENTRY_UINT8(pending_tcsr);
1285         DECL_STATE_ENTRY_UINT16(input_capture);
1286         DECL_STATE_ENTRY_UINT32(timer_next);
1287         DECL_STATE_ENTRY_FIFO(recv_buffer);
1288
1289         DECL_STATE_ENTRY_UINT8(trcsr);
1290         DECL_STATE_ENTRY_UINT8(rdr);
1291         DECL_STATE_ENTRY_UINT8(tdr);
1292         DECL_STATE_ENTRY_BOOL(trcsr_read_tdre);
1293         DECL_STATE_ENTRY_BOOL(trcsr_read_orfe);
1294         DECL_STATE_ENTRY_BOOL(trcsr_read_rdrf);
1295         DECL_STATE_ENTRY_UINT8(rmcr);
1296         DECL_STATE_ENTRY_INT32(sio_counter);
1297         DECL_STATE_ENTRY_UINT8(ram_ctrl);
1298         DECL_STATE_ENTRY_1D_ARRAY(ram, sizeof(ram));
1299 //#endif
1300
1301
1302         leave_decl_state();
1303 }
1304
1305 void MC6801::save_state(FILEIO* state_fio)
1306 {
1307         if(state_entry != NULL) {
1308                 state_entry->save_state(state_fio);
1309         }
1310 //      state_fio->FputUint32(STATE_VERSION);
1311 //      state_fio->FputInt32(this_device_id);
1312
1313 //      state_fio->FputUint32(pc.d);
1314 //      state_fio->FputUint16(prevpc);
1315 //      state_fio->FputUint32(sp.d);
1316 //      state_fio->FputUint32(ix.d);
1317 //      state_fio->FputUint32(acc_d.d);
1318 //      state_fio->FputUint32(ea.d);
1319 //      state_fio->FputUint8(cc);
1320 //      state_fio->FputInt32(wai_state);
1321 //      state_fio->FputInt32(int_state);
1322 //      if(__USE_DEBUGGER) state_fio->FputUint64(total_icount);
1323 //      state_fio->FputInt32(icount);
1324 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
1325 //      for(int i = 0; i < 4; i++) {
1326 //              state_fio->FputUint8(port[i].wreg);
1327 //              state_fio->FputUint8(port[i].rreg);
1328 //              state_fio->FputUint8(port[i].ddr);
1329 //              state_fio->FputUint8(port[i].latched_data);
1330 //              state_fio->FputBool(port[i].latched);
1331 //              state_fio->FputBool(port[i].first_write);
1332 //      }
1333 //      state_fio->FputUint8(p3csr);
1334 //      state_fio->FputBool(p3csr_is3_flag_read);
1335 //      state_fio->FputBool(sc1_state);
1336 //      state_fio->FputBool(sc2_state);
1337 //      state_fio->FputUint32(counter.d);
1338 //      state_fio->FputUint32(output_compare.d);
1339 //      state_fio->FputUint32(timer_over.d);
1340 //      state_fio->FputUint8(tcsr);
1341 //      state_fio->FputUint8(pending_tcsr);
1342 //      state_fio->FputUint16(input_capture);
1343 //      state_fio->FputUint32(timer_next);
1344 //      recv_buffer->save_state((void *)state_fio);
1345 //      state_fio->FputUint8(trcsr);
1346 //      state_fio->FputUint8(rdr);
1347 //      state_fio->FputUint8(tdr);
1348 //      state_fio->FputBool(trcsr_read_tdre);
1349 //      state_fio->FputBool(trcsr_read_orfe);
1350 //      state_fio->FputBool(trcsr_read_rdrf);
1351 //      state_fio->FputUint8(rmcr);
1352 //      state_fio->FputInt32(sio_counter);
1353 //      state_fio->FputUint8(ram_ctrl);
1354 //      state_fio->Fwrite(ram, sizeof(ram), 1);
1355 //#endif
1356 }
1357
1358 bool MC6801::load_state(FILEIO* state_fio)
1359 {
1360         bool mb = false;
1361         if(state_entry != NULL) {
1362                 mb = state_entry->load_state(state_fio);
1363         }
1364         if(!mb) return false;
1365 //      if(state_fio->FgetUint32() != STATE_VERSION) {
1366 //              return false;
1367 //      }
1368 //      if(state_fio->FgetInt32() != this_device_id) {
1369 //              return false;
1370 //      }
1371 //      pc.d = state_fio->FgetUint32();
1372 //      prevpc = state_fio->FgetUint16();
1373 //      sp.d = state_fio->FgetUint32();
1374 //      ix.d = state_fio->FgetUint32();
1375 //      acc_d.d = state_fio->FgetUint32();
1376 //      ea.d = state_fio->FgetUint32();
1377 //      cc = state_fio->FgetUint8();
1378 //      wai_state = state_fio->FgetInt32();
1379 //      int_state = state_fio->FgetInt32();
1380 //      if(__USE_DEBUGGER) { total_icount = prev_total_icount = state_fio->FgetUint64(); }
1381 //      icount = state_fio->FgetInt32();
1382 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
1383 //      for(int i = 0; i < 4; i++) {
1384 //              port[i].wreg = state_fio->FgetUint8();
1385 //              port[i].rreg = state_fio->FgetUint8();
1386 //              port[i].ddr = state_fio->FgetUint8();
1387 //              port[i].latched_data = state_fio->FgetUint8();
1388 //              port[i].latched = state_fio->FgetBool();
1389 //              port[i].first_write = state_fio->FgetBool();
1390 //      }
1391 //      p3csr = state_fio->FgetUint8();
1392 //      p3csr_is3_flag_read = state_fio->FgetBool();
1393 //      sc1_state = state_fio->FgetBool();
1394 //      sc2_state = state_fio->FgetBool();
1395 //      counter.d = state_fio->FgetUint32();
1396 //      output_compare.d = state_fio->FgetUint32();
1397 //      timer_over.d = state_fio->FgetUint32();
1398 //      tcsr = state_fio->FgetUint8();
1399 //      pending_tcsr = state_fio->FgetUint8();
1400 //      input_capture = state_fio->FgetUint16();
1401 //#ifdef HAS_HD6301
1402 //      latch09 = state_fio->FgetUint16();
1403 //#endif
1404 //      timer_next = state_fio->FgetUint32();
1405         if(__USE_DEBUGGER) {
1406                 prev_total_icount = total_icount;
1407         }
1408 //      if(!recv_buffer->load_state((void *)state_fio)) {
1409 //              return false;
1410 //      }
1411 //      trcsr = state_fio->FgetUint8();
1412 //      rdr = state_fio->FgetUint8();
1413 //      tdr = state_fio->FgetUint8();
1414 //      trcsr_read_tdre = state_fio->FgetBool();
1415 //      trcsr_read_orfe = state_fio->FgetBool();
1416 //      trcsr_read_rdrf = state_fio->FgetBool();
1417 //      rmcr = state_fio->FgetUint8();
1418 //      sio_counter = state_fio->FgetInt32();
1419 //      ram_ctrl = state_fio->FgetUint8();
1420 //      state_fio->Fread(ram, sizeof(ram), 1);
1421 //#endif
1422         return true;
1423 }