2 Skelton for retropc emulator
5 Author : Takeda.Toshiya
10 #if defined(_MSC_VER) && (_MSC_VER >= 1400)
11 #pragma warning( disable : 4996 )
15 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
20 #include "mc6800_consts.h"
21 #include "mc6801_consts.h"
23 /****************************************************************************/
25 /****************************************************************************/
27 uint32_t MC6801::RM(uint32_t Addr)
29 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
31 return mc6801_io_r(Addr);
32 } else if(Addr >= 0x80 && Addr < 0x100 && (ram_ctrl & 0x40)) {
33 return ram[Addr & 0x7f];
36 return d_mem->read_data8(Addr);
39 void MC6801::WM(uint32_t Addr, uint32_t Value)
41 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
43 mc6801_io_w(Addr, Value);
44 } else if(Addr >= 0x80 && Addr < 0x100 && (ram_ctrl & 0x40)) {
45 ram[Addr & 0x7f] = Value;
48 d_mem->write_data8(Addr, Value);
50 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
52 uint32_t MC6801::mc6801_io_r(uint32_t offset)
56 // port1 data direction register
59 // port2 data direction register
62 // port1 data register
63 return (port[0].rreg & ~port[0].ddr) | (port[0].wreg & port[0].ddr);
65 // port2 data register
66 return (port[1].rreg & ~port[1].ddr) | (port[1].wreg & port[1].ddr);
68 // port3 data direction register (write only???)
71 // port4 data direction register
74 // port3 data register
75 if(p3csr_is3_flag_read) {
76 p3csr_is3_flag_read = false;
77 p3csr &= ~P3CSR_IS3_FLAG;
80 port[2].latched = false;
81 return (port[2].latched_data & ~port[2].ddr) | (port[2].wreg & port[2].ddr);
83 return (port[2].rreg & ~port[2].ddr) | (port[2].wreg & port[2].ddr);
85 // port4 data register
86 return (port[3].rreg & ~port[3].ddr) | (port[3].wreg & port[3].ddr);
88 // timer control register
92 // free running counter (msb)
93 if(!(pending_tcsr & TCSR_TOF)) {
98 // free running counter (lsb)
101 // output compare register (msb)
102 if(!(pending_tcsr & TCSR_OCF)) {
105 return output_compare.b.h;
107 // output compare register (lsb)
108 if(!(pending_tcsr & TCSR_OCF)) {
111 return output_compare.b.l;
113 // input capture register (msb)
114 if(!(pending_tcsr & TCSR_ICF)) {
117 return (input_capture >> 0) & 0xff;
119 // input capture register (lsb)
120 return (input_capture >> 8) & 0xff;
122 // port3 control/status register
123 p3csr_is3_flag_read = true;
126 // rate and mode control register
129 if(trcsr & TRCSR_TDRE) {
130 trcsr_read_tdre = true;
132 if(trcsr & TRCSR_ORFE) {
133 trcsr_read_orfe = true;
135 if(trcsr & TRCSR_RDRF) {
136 trcsr_read_rdrf = true;
140 // receive data register
141 if(trcsr_read_orfe) {
142 trcsr_read_orfe = false;
143 trcsr &= ~TRCSR_ORFE;
145 if(trcsr_read_rdrf) {
146 trcsr_read_rdrf = false;
147 trcsr &= ~TRCSR_RDRF;
151 // transmit data register
154 // ram control register
155 return (ram_ctrl & 0x40) | 0x3f;
160 void MC6801::mc6801_io_w(uint32_t offset, uint32_t data)
164 // port1 data direction register
168 // port2 data direction register
172 // port1 data register
173 if(port[0].wreg != data || port[0].first_write) {
174 write_signals(&port[0].outputs, data);
176 port[0].first_write = false;
180 // port2 data register
181 if(port[1].wreg != data || port[1].first_write) {
182 write_signals(&port[1].outputs, data);
184 port[1].first_write = false;
188 // port3 data direction register
192 // port4 data direction register
196 // port3 data register
197 if(p3csr_is3_flag_read) {
198 p3csr_is3_flag_read = false;
199 p3csr &= ~P3CSR_IS3_FLAG;
201 if(port[2].wreg != data || port[2].first_write) {
202 write_signals(&port[2].outputs, data);
204 port[2].first_write = false;
208 // port4 data register
209 if(port[3].wreg != data || port[3].first_write) {
210 write_signals(&port[3].outputs, data);
212 port[3].first_write = false;
216 // timer control/status register
218 pending_tcsr &= tcsr;
221 // free running counter (msb)
223 // latch09 = data & 0xff;
231 // // free running counter (lsb)
232 // CT = (latch09 << 8) | (data & 0xff);
234 // MODIFIED_counters;
238 // output compare register (msb)
239 if(output_compare.b.h != data) {
240 output_compare.b.h = data;
246 // output compare register (lsb)
247 if(output_compare.b.l != data) {
248 output_compare.b.l = data;
254 // port3 control/status register
255 p3csr = (p3csr & P3CSR_IS3_FLAG) | (data & ~P3CSR_IS3_FLAG);
258 // rate and mode control register
262 // transmit/receive control/status register
263 trcsr = (trcsr & 0xe0) | (data & 0x1f);
266 // transmit data register
267 if(trcsr_read_tdre) {
268 trcsr_read_tdre = false;
269 trcsr &= ~TRCSR_TDRE;
274 // ram control register
280 void MC6801::increment_counter(int amount)
282 total_icount += amount;
286 if((CTD += amount) >= timer_next) {
289 OCH++; // next IRQ point
291 pending_tcsr |= TCSR_OCF;
295 TOH++; // next IRQ point
297 pending_tcsr |= TCSR_TOF;
304 if((sio_counter -= amount) <= 0) {
305 if((trcsr & TRCSR_TE) && !(trcsr & TRCSR_TDRE)) {
306 write_signals(&outputs_sio, tdr);
309 if((trcsr & TRCSR_RE) && !recv_buffer->empty()) {
310 if(trcsr & TRCSR_WU) {
314 } else if(!(trcsr & TRCSR_RDRF)) {
315 // note: wait reveived data is read by cpu, so overrun framing error never occurs
316 rdr = recv_buffer->read();
320 sio_counter += RMCR_SS[rmcr & 3];
326 void MC6801::initialize()
328 MC6800::initialize();
330 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
331 recv_buffer = new FIFO(0x10000);
334 //#ifdef USE_DEBUGGER
336 d_mem_stored = d_mem;
337 d_debugger->set_context_mem(d_mem);
341 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
342 void MC6801::release()
344 recv_buffer->release();
352 SEI; /* IRQ disabled */
361 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
362 for(int i = 0; i < 4; i++) {
364 port[i].first_write = true;
365 port[i].latched = false;
368 p3csr_is3_flag_read = false;
369 sc1_state = sc2_state = false;
371 tcsr = pending_tcsr = 0x00;
376 recv_buffer->clear();
378 trcsr_read_tdre = trcsr_read_orfe = trcsr_read_rdrf = false;
380 sio_counter = RMCR_SS[rmcr & 3];
386 void MC6801::write_signal(int id, uint32_t data, uint32_t mask)
391 int_state |= INT_REQ_BIT;
393 int_state &= ~INT_REQ_BIT;
398 int_state |= NMI_REQ_BIT;
400 int_state &= ~NMI_REQ_BIT;
403 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
404 case SIG_MC6801_PORT_1:
405 port[0].rreg = (port[0].rreg & ~mask) | (data & mask);
407 case SIG_MC6801_PORT_2:
408 if((mask & 1) && (port[1].rreg & 1) != (data & 1) && (tcsr & 2) == ((data << 1) & 2)) {
409 // active TIN edge in
411 pending_tcsr |= TCSR_ICF;
414 port[1].rreg = (port[1].rreg & ~mask) | (data & mask);
416 case SIG_MC6801_PORT_3:
417 port[2].rreg = (port[2].rreg & ~mask) | (data & mask);
419 case SIG_MC6801_PORT_4:
420 port[3].rreg = (port[3].rreg & ~mask) | (data & mask);
422 case SIG_MC6801_PORT_3_SC1:
423 if(sc1_state && !(data & mask)) {
425 if(!port[2].latched && (p3csr & P3CSR_LE)) {
426 port[2].latched_data = port[2].rreg;
427 port[2].latched = true;
428 p3csr |= P3CSR_IS3_FLAG;
431 sc1_state = ((data & mask) != 0);
433 case SIG_MC6801_PORT_3_SC2:
434 sc2_state = ((data & mask) != 0);
436 case SIG_MC6801_SIO_RECV:
437 recv_buffer->write(data & mask);
443 int MC6801::run(int clock)
447 // run only one opcode
455 /* run cpu while given clocks */
460 int first_icount = icount;
465 return first_icount - icount;
469 void MC6801::run_one_opecode()
471 if(wai_state & (MC6800_WAI | HD6301_SLP)) {
472 increment_counter(1);
475 one_more_insn = false;
477 bool now_debugging = d_debugger->now_debugging;
479 d_debugger->check_break_points(PC);
480 if(d_debugger->now_suspended) {
482 d_debugger->now_waiting = true;
483 while(d_debugger->now_debugging && d_debugger->now_suspended) {
486 d_debugger->now_waiting = false;
488 if(d_debugger->now_debugging) {
491 now_debugging = false;
494 d_debugger->add_cpu_trace(PC);
495 uint8_t ireg = M_RDOP(PCD);
499 increment_counter(cycles[ireg]);
502 if(!d_debugger->now_going) {
503 d_debugger->now_suspended = true;
505 d_mem = d_mem_stored;
508 if(__USE_DEBUGGER) d_debugger->add_cpu_trace(PC);
509 uint8_t ireg = M_RDOP(PCD);
513 increment_counter(cycles[ireg]);
516 uint8_t ireg = M_RDOP(PCD);
520 increment_counter(cycles[ireg]);
522 } while(one_more_insn);
526 if(int_state & NMI_REQ_BIT) {
527 wai_state &= ~HD6301_SLP;
528 int_state &= ~NMI_REQ_BIT;
529 enter_interrupt(0xfffc);
530 } else if(int_state & INT_REQ_BIT) {
531 wai_state &= ~HD6301_SLP;
533 int_state &= ~INT_REQ_BIT;
534 enter_interrupt(0xfff8);
536 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
537 } else if((tcsr & (TCSR_EICI | TCSR_ICF)) == (TCSR_EICI | TCSR_ICF)) {
538 wai_state &= ~HD6301_SLP;
542 } else if((tcsr & (TCSR_EOCI | TCSR_OCF)) == (TCSR_EOCI | TCSR_OCF)) {
543 wai_state &= ~HD6301_SLP;
547 } else if((tcsr & (TCSR_ETOI | TCSR_TOF)) == (TCSR_ETOI | TCSR_TOF)) {
548 wai_state &= ~HD6301_SLP;
552 } else if(((trcsr & (TRCSR_RIE | TRCSR_RDRF)) == (TRCSR_RIE | TRCSR_RDRF)) ||
553 ((trcsr & (TRCSR_RIE | TRCSR_ORFE)) == (TRCSR_RIE | TRCSR_ORFE)) ||
554 ((trcsr & (TRCSR_TIE | TRCSR_TDRE)) == (TRCSR_TIE | TRCSR_TDRE))) {
555 wai_state &= ~HD6301_SLP;
563 int MC6801::debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len)
566 for(int i = 0; i < 4; i++) {
568 ops[i] = d_mem_stored->read_data8w(pc + i, &wait);
570 return Dasm680x(6801, buffer, pc, ops, ops, d_debugger->first_symbol);
574 void MC6801::insn(uint8_t code)
577 case 0x00: illegal(); break;
578 case 0x01: nop(); break;
579 case 0x02: illegal(); break;
580 case 0x03: illegal(); break;
581 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
582 case 0x04: lsrd(); break;
583 case 0x05: asld(); break;
585 // case 0x04: illegal(); break;
586 // case 0x05: illegal(); break;
588 case 0x06: tap(); break;
589 case 0x07: tpa(); break;
590 case 0x08: inx(); break;
591 case 0x09: dex(); break;
592 case 0x0a: clv(); break;
593 case 0x0b: sev(); break;
594 case 0x0c: clc(); break;
595 case 0x0d: sec(); break;
596 case 0x0e: cli(); break;
597 case 0x0f: sei(); break;
598 case 0x10: sba(); break;
599 case 0x11: cba(); break;
600 //#if defined(HAS_HD6301)
601 // case 0x12: undoc1(); break;
602 // case 0x13: undoc2(); break;
604 case 0x12: illegal(); break;
605 case 0x13: illegal(); break;
607 case 0x14: illegal(); break;
608 case 0x15: illegal(); break;
609 case 0x16: tab(); break;
610 case 0x17: tba(); break;
611 //#if defined(HAS_HD6301)
612 // case 0x18: xgdx(); break;
614 case 0x18: illegal(); break;
616 case 0x19: daa(); break;
617 //#if defined(HAS_HD6301)
618 // case 0x1a: slp(); break;
620 case 0x1a: illegal(); break;
622 case 0x1b: aba(); break;
623 case 0x1c: illegal(); break;
624 case 0x1d: illegal(); break;
625 case 0x1e: illegal(); break;
626 case 0x1f: illegal(); break;
627 case 0x20: bra(); break;
628 case 0x21: brn(); break;
629 case 0x22: bhi(); break;
630 case 0x23: bls(); break;
631 case 0x24: bcc(); break;
632 case 0x25: bcs(); break;
633 case 0x26: bne(); break;
634 case 0x27: beq(); break;
635 case 0x28: bvc(); break;
636 case 0x29: bvs(); break;
637 case 0x2a: bpl(); break;
638 case 0x2b: bmi(); break;
639 case 0x2c: bge(); break;
640 case 0x2d: blt(); break;
641 case 0x2e: bgt(); break;
642 case 0x2f: ble(); break;
643 case 0x30: tsx(); break;
644 case 0x31: ins(); break;
645 case 0x32: pula(); break;
646 case 0x33: pulb(); break;
647 case 0x34: des(); break;
648 case 0x35: txs(); break;
649 case 0x36: psha(); break;
650 case 0x37: pshb(); break;
651 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
652 case 0x38: pulx(); break;
654 // case 0x38: illegal(); break;
656 case 0x39: rts(); break;
657 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
658 case 0x3a: abx(); break;
660 // case 0x3a: illegal(); break;
662 case 0x3b: rti(); break;
663 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
664 case 0x3c: pshx(); break;
665 case 0x3d: mul(); break;
667 // case 0x3c: illegal(); break;
668 // case 0x3d: illegal(); break;
670 case 0x3e: wai(); break;
671 case 0x3f: swi(); break;
672 case 0x40: nega(); break;
673 case 0x41: illegal(); break;
674 case 0x42: illegal(); break;
675 case 0x43: coma(); break;
676 case 0x44: lsra(); break;
677 case 0x45: illegal(); break;
678 case 0x46: rora(); break;
679 case 0x47: asra(); break;
680 case 0x48: asla(); break;
681 case 0x49: rola(); break;
682 case 0x4a: deca(); break;
683 case 0x4b: illegal(); break;
684 case 0x4c: inca(); break;
685 case 0x4d: tsta(); break;
686 case 0x4e: illegal(); break;
687 case 0x4f: clra(); break;
688 case 0x50: negb(); break;
689 case 0x51: illegal(); break;
690 case 0x52: illegal(); break;
691 case 0x53: comb(); break;
692 case 0x54: lsrb(); break;
693 case 0x55: illegal(); break;
694 case 0x56: rorb(); break;
695 case 0x57: asrb(); break;
696 case 0x58: aslb(); break;
697 case 0x59: rolb(); break;
698 case 0x5a: decb(); break;
699 case 0x5b: illegal(); break;
700 case 0x5c: incb(); break;
701 case 0x5d: tstb(); break;
702 case 0x5e: illegal(); break;
703 case 0x5f: clrb(); break;
704 case 0x60: neg_ix(); break;
705 //#if defined(HAS_HD6301)
706 // case 0x61: aim_ix(); break;
707 // case 0x62: oim_ix(); break;
709 case 0x61: illegal(); break;
710 case 0x62: illegal(); break;
712 case 0x63: com_ix(); break;
713 case 0x64: lsr_ix(); break;
714 //#if defined(HAS_HD6301)
715 // case 0x65: eim_ix(); break;
717 case 0x65: illegal(); break;
719 case 0x66: ror_ix(); break;
720 case 0x67: asr_ix(); break;
721 case 0x68: asl_ix(); break;
722 case 0x69: rol_ix(); break;
723 case 0x6a: dec_ix(); break;
724 //#if defined(HAS_HD6301)
725 // case 0x6b: tim_ix(); break;
727 case 0x6b: illegal(); break;
729 case 0x6c: inc_ix(); break;
730 case 0x6d: tst_ix(); break;
731 case 0x6e: jmp_ix(); break;
732 case 0x6f: clr_ix(); break;
733 case 0x70: neg_ex(); break;
734 //#if defined(HAS_HD6301)
735 // case 0x71: aim_di(); break;
736 // case 0x72: oim_di(); break;
737 //#elif defined(HAS_MB8861)
738 // case 0x71: nim_ix(); break;
739 // case 0x72: oim_ix_mb8861(); break;
741 case 0x71: illegal(); break;
742 case 0x72: illegal(); break;
744 case 0x73: com_ex(); break;
745 case 0x74: lsr_ex(); break;
746 //#if defined(HAS_HD6301)
747 // case 0x75: eim_di(); break;
748 //#elif defined(HAS_MB8861)
749 // case 0x75: xim_ix(); break;
751 case 0x75: illegal(); break;
753 case 0x76: ror_ex(); break;
754 case 0x77: asr_ex(); break;
755 case 0x78: asl_ex(); break;
756 case 0x79: rol_ex(); break;
757 case 0x7a: dec_ex(); break;
758 //#if defined(HAS_HD6301)
759 // case 0x7b: tim_di(); break;
760 //#elif defined(HAS_MB8861)
761 // case 0x7b: tmm_ix(); break;
763 case 0x7b: illegal(); break;
765 case 0x7c: inc_ex(); break;
766 case 0x7d: tst_ex(); break;
767 case 0x7e: jmp_ex(); break;
768 case 0x7f: clr_ex(); break;
769 case 0x80: suba_im(); break;
770 case 0x81: cmpa_im(); break;
771 case 0x82: sbca_im(); break;
772 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
773 case 0x83: subd_im(); break;
775 // case 0x83: illegal(); break;
777 case 0x84: anda_im(); break;
778 case 0x85: bita_im(); break;
779 case 0x86: lda_im(); break;
780 case 0x87: sta_im(); break;
781 case 0x88: eora_im(); break;
782 case 0x89: adca_im(); break;
783 case 0x8a: ora_im(); break;
784 case 0x8b: adda_im(); break;
785 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
786 case 0x8c: cpx_im (); break;
788 // case 0x8c: cmpx_im(); break;
790 case 0x8d: bsr(); break;
791 case 0x8e: lds_im(); break;
792 case 0x8f: sts_im(); break;
793 case 0x90: suba_di(); break;
794 case 0x91: cmpa_di(); break;
795 case 0x92: sbca_di(); break;
796 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
797 case 0x93: subd_di(); break;
799 // case 0x93: illegal(); break;
801 case 0x94: anda_di(); break;
802 case 0x95: bita_di(); break;
803 case 0x96: lda_di(); break;
804 case 0x97: sta_di(); break;
805 case 0x98: eora_di(); break;
806 case 0x99: adca_di(); break;
807 case 0x9a: ora_di(); break;
808 case 0x9b: adda_di(); break;
809 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
810 case 0x9c: cpx_di (); break;
812 // case 0x9c: cmpx_di(); break;
814 case 0x9d: jsr_di(); break;
815 case 0x9e: lds_di(); break;
816 case 0x9f: sts_di(); break;
817 case 0xa0: suba_ix(); break;
818 case 0xa1: cmpa_ix(); break;
819 case 0xa2: sbca_ix(); break;
820 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
821 case 0xa3: subd_ix(); break;
823 // case 0xa3: illegal(); break;
825 case 0xa4: anda_ix(); break;
826 case 0xa5: bita_ix(); break;
827 case 0xa6: lda_ix(); break;
828 case 0xa7: sta_ix(); break;
829 case 0xa8: eora_ix(); break;
830 case 0xa9: adca_ix(); break;
831 case 0xaa: ora_ix(); break;
832 case 0xab: adda_ix(); break;
833 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
834 case 0xac: cpx_ix (); break;
836 // case 0xac: cmpx_ix(); break;
838 case 0xad: jsr_ix(); break;
839 case 0xae: lds_ix(); break;
840 case 0xaf: sts_ix(); break;
841 case 0xb0: suba_ex(); break;
842 case 0xb1: cmpa_ex(); break;
843 case 0xb2: sbca_ex(); break;
844 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
845 case 0xb3: subd_ex(); break;
847 // case 0xb3: illegal(); break;
849 case 0xb4: anda_ex(); break;
850 case 0xb5: bita_ex(); break;
851 case 0xb6: lda_ex(); break;
852 case 0xb7: sta_ex(); break;
853 case 0xb8: eora_ex(); break;
854 case 0xb9: adca_ex(); break;
855 case 0xba: ora_ex(); break;
856 case 0xbb: adda_ex(); break;
857 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
858 case 0xbc: cpx_ex (); break;
860 // case 0xbc: cmpx_ex(); break;
862 case 0xbd: jsr_ex(); break;
863 case 0xbe: lds_ex(); break;
864 case 0xbf: sts_ex(); break;
865 case 0xc0: subb_im(); break;
866 case 0xc1: cmpb_im(); break;
867 case 0xc2: sbcb_im(); break;
868 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
869 case 0xc3: addd_im(); break;
871 // case 0xc3: illegal(); break;
873 case 0xc4: andb_im(); break;
874 case 0xc5: bitb_im(); break;
875 case 0xc6: ldb_im(); break;
876 case 0xc7: stb_im(); break;
877 case 0xc8: eorb_im(); break;
878 case 0xc9: adcb_im(); break;
879 case 0xca: orb_im(); break;
880 case 0xcb: addb_im(); break;
881 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
882 case 0xcc: ldd_im(); break;
883 case 0xcd: std_im(); break;
885 // case 0xcc: illegal(); break;
886 // case 0xcd: illegal(); break;
888 case 0xce: ldx_im(); break;
889 case 0xcf: stx_im(); break;
890 case 0xd0: subb_di(); break;
891 case 0xd1: cmpb_di(); break;
892 case 0xd2: sbcb_di(); break;
893 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
894 case 0xd3: addd_di(); break;
896 // case 0xd3: illegal(); break;
898 case 0xd4: andb_di(); break;
899 case 0xd5: bitb_di(); break;
900 case 0xd6: ldb_di(); break;
901 case 0xd7: stb_di(); break;
902 case 0xd8: eorb_di(); break;
903 case 0xd9: adcb_di(); break;
904 case 0xda: orb_di(); break;
905 case 0xdb: addb_di(); break;
906 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
907 case 0xdc: ldd_di(); break;
908 case 0xdd: std_di(); break;
910 // case 0xdc: illegal(); break;
911 // case 0xdd: illegal(); break;
913 case 0xde: ldx_di(); break;
914 case 0xdf: stx_di(); break;
915 case 0xe0: subb_ix(); break;
916 case 0xe1: cmpb_ix(); break;
917 case 0xe2: sbcb_ix(); break;
918 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
919 case 0xe3: addd_ix(); break;
921 // case 0xe3: illegal(); break;
923 case 0xe4: andb_ix(); break;
924 case 0xe5: bitb_ix(); break;
925 case 0xe6: ldb_ix(); break;
926 case 0xe7: stb_ix(); break;
927 case 0xe8: eorb_ix(); break;
928 case 0xe9: adcb_ix(); break;
929 case 0xea: orb_ix(); break;
930 case 0xeb: addb_ix(); break;
931 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
932 case 0xec: ldd_ix(); break;
933 case 0xed: std_ix(); break;
934 //#elif defined(HAS_MB8861)
935 // case 0xec: adx_im(); break;
936 // case 0xed: illegal(); break;
938 // case 0xec: illegal(); break;
939 // case 0xed: illegal(); break;
941 case 0xee: ldx_ix(); break;
942 case 0xef: stx_ix(); break;
943 case 0xf0: subb_ex(); break;
944 case 0xf1: cmpb_ex(); break;
945 case 0xf2: sbcb_ex(); break;
946 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
947 case 0xf3: addd_ex(); break;
949 // case 0xf3: illegal(); break;
951 case 0xf4: andb_ex(); break;
952 case 0xf5: bitb_ex(); break;
953 case 0xf6: ldb_ex(); break;
954 case 0xf7: stb_ex(); break;
955 case 0xf8: eorb_ex(); break;
956 case 0xf9: adcb_ex(); break;
957 case 0xfa: orb_ex(); break;
958 case 0xfb: addb_ex(); break;
959 //#if defined(HAS_MC6801) || defined(HAS_HD6301)
960 case 0xfc: ldd_ex(); break;
961 case 0xfd: std_ex(); break;
962 //#elif defined(HAS_MB8861)
963 // case 0xfc: adx_ex(); break;
964 // case 0xfd: illegal(); break;
966 // case 0xfc: illegal(); break;
967 // case 0xfd: illegal(); break;
969 case 0xfe: ldx_ex(); break;
970 case 0xff: stx_ex(); break;
971 #if defined(_MSC_VER) && (_MSC_VER >= 1200)
972 default: __assume(0);
977 /* $04 LSRD inherent -0*-* */
989 /* $05 ASLD inherent ?**** */
997 SET_FLAGS16(t, t, r);
1000 /* $38 PULX inherent ----- */
1006 /* $3a ABX inherent ----- */
1011 /* $3c PSHX inherent ----- */
1017 /* $3d MUL inherent --*-@ */
1026 /* $83 SUBD immediate -**** */
1027 void MC6801::subd_im()
1035 SET_FLAGS16(d, b.d, r);
1039 /* $8c CPX immediate -**** (6801) */
1040 void MC6801::cpx_im()
1048 SET_FLAGS16(d, b.d, r);
1051 /* $93 SUBD direct -**** */
1052 void MC6801::subd_di()
1060 SET_FLAGS16(d, b.d, r);
1064 /* $9c CPX direct -**** (6801) */
1065 void MC6801::cpx_di()
1073 SET_FLAGS16(d, b.d, r);
1075 /* $a3 SUBD indexed -**** */
1076 void MC6801::subd_ix()
1084 SET_FLAGS16(d, b.d, r);
1088 /* $ac CPX indexed -**** (6801)*/
1089 void MC6801::cpx_ix()
1097 SET_FLAGS16(d, b.d, r);
1100 /* $b3 SUBD extended -**** */
1101 void MC6801::subd_ex()
1109 SET_FLAGS16(d, b.d, r);
1113 /* $bc CPX extended -**** (6801) */
1114 void MC6801::cpx_ex()
1122 SET_FLAGS16(d, b.d, r);
1125 /* $c3 ADDD immediate -**** */
1126 void MC6801::addd_im()
1134 SET_FLAGS16(d, b.d, r);
1138 /* $CC LDD immediate -**0- */
1139 void MC6801::ldd_im()
1146 /* is this a legal instruction? */
1147 /* $cd STD immediate -**0- */
1148 void MC6801::std_im()
1156 /* $d3 ADDD direct -**** */
1157 void MC6801::addd_di()
1165 SET_FLAGS16(d, b.d, r);
1169 /* $dc LDD direct -**0- */
1170 void MC6801::ldd_di()
1177 /* $dd STD direct -**0- */
1178 void MC6801::std_di()
1186 /* $e3 ADDD indexed -**** */
1187 void MC6801::addd_ix()
1195 SET_FLAGS16(d, b.d, r);
1199 /* $ec LDD indexed -**0- */
1200 void MC6801::ldd_ix()
1207 /* $ed STD indexed -**0- */
1208 void MC6801::std_ix()
1216 /* $f3 ADDD extended -**** */
1217 void MC6801::addd_ex()
1225 SET_FLAGS16(d, b.d, r);
1229 /* $fc LDD extended -**0- */
1230 void MC6801::ldd_ex()
1237 /* $fd STD extended -**0- */
1238 void MC6801::std_ex()
1246 #define STATE_VERSION 2
1248 bool MC6801::process_state(FILEIO* state_fio, bool loading)
1250 if(!state_fio->StateCheckUint32(STATE_VERSION)) {
1253 if(!state_fio->StateCheckInt32(this_device_id)) {
1256 state_fio->StateUint32(pc.d);
1257 state_fio->StateUint16(prevpc);
1258 state_fio->StateUint32(sp.d);
1259 state_fio->StateUint32(ix.d);
1260 state_fio->StateUint32(acc_d.d);
1261 state_fio->StateUint32(ea.d);
1262 state_fio->StateUint8(cc);
1263 state_fio->StateInt32(wai_state);
1264 state_fio->StateInt32(int_state);
1265 if(__USE_DEBUGGER) {
1266 state_fio->StateUint64(total_icount);
1268 state_fio->StateInt32(icount);
1269 // #if defined(HAS_MC6801) || defined(HAS_HD6301)
1270 for(int i = 0; i < 4; i++) {
1271 state_fio->StateUint8(port[i].wreg);
1272 state_fio->StateUint8(port[i].rreg);
1273 state_fio->StateUint8(port[i].ddr);
1274 state_fio->StateUint8(port[i].latched_data);
1275 state_fio->StateBool(port[i].latched);
1276 state_fio->StateBool(port[i].first_write);
1278 state_fio->StateUint8(p3csr);
1279 state_fio->StateBool(p3csr_is3_flag_read);
1280 state_fio->StateBool(sc1_state);
1281 state_fio->StateBool(sc2_state);
1282 state_fio->StateUint32(counter.d);
1283 state_fio->StateUint32(output_compare.d);
1284 state_fio->StateUint32(timer_over.d);
1285 state_fio->StateUint8(tcsr);
1286 state_fio->StateUint8(pending_tcsr);
1287 state_fio->StateUint16(input_capture);
1288 state_fio->StateUint32(timer_next);
1289 if(!recv_buffer->process_state((void *)state_fio, loading)) {
1292 state_fio->StateUint8(trcsr);
1293 state_fio->StateUint8(rdr);
1294 state_fio->StateUint8(tdr);
1295 state_fio->StateBool(trcsr_read_tdre);
1296 state_fio->StateBool(trcsr_read_orfe);
1297 state_fio->StateBool(trcsr_read_rdrf);
1298 state_fio->StateUint8(rmcr);
1299 state_fio->StateInt32(sio_counter);
1300 state_fio->StateUint8(ram_ctrl);
1301 state_fio->StateBuffer(ram, sizeof(ram), 1);
1305 if(__USE_DEBUGGER) {
1307 prev_total_icount = total_icount;