2 Skelton for retropc emulator
5 Author : Takeda.Toshiya
9 Notes from K.Ohta <whatisthis.sowhat _at_ gmail.com> at Jan 16, 2015:
10 All of undocumented instructions (i.e. ngc, flag16) of MC6809(not HD6309) are written by me.
11 These behaviors of undocumented insns are refered from "vm/cpu_x86.asm" (ia32 assembly codefor nasm) within XM7
12 written by Ryu Takegami , and older article wrote in magazine, "I/O" at 1985.
13 But, these C implements are written from scratch by me , and I tested many years at XM7/SDL.
14 Perhaps, these insns. are not implement MAME/MESS yet.
17 // Fixed IRQ/FIRQ by Mr.Sasaji at 2011.06.17
20 #include "mc6809_consts.h"
26 #define OP_HANDLER(_name) void MC6809::_name (void)
28 /* macros for branch instructions */
29 inline void MC6809::BRANCH(bool cond)
38 inline void MC6809::LBRANCH(bool cond)
48 /* macros for setting/getting registers in TFR/EXG instructions */
50 inline pair_t MC6809::RM16_PAIR(uint32_t addr)
59 inline void MC6809::WM16(uint32_t Addr, pair_t *p)
66 static const uint8_t flags8i[256] = {
67 CC_Z,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
68 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
69 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
70 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
71 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
72 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
73 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
74 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
75 CC_N|CC_V,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
76 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
77 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
78 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
79 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
80 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
81 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
82 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N
86 static const uint8_t flags8d[256] = {
87 CC_Z,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
88 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
89 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
90 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
91 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
92 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
93 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
94 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,CC_V,
95 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
96 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
97 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
98 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
99 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
100 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
101 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
102 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N
105 /* FIXME: Cycles differ slighly from hd6309 emulation */
106 static const int index_cycle_em[256] = { /* Index Loopup cycle counts */
107 /* 0xX0, 0xX1, 0xX2, 0xX3, 0xX4, 0xX5, 0xX6, 0xX7, 0xX8, 0xX9, 0xXA, 0xXB, 0xXC, 0xXD, 0xXE, 0xXF */
109 /* 0x0X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
110 /* 0x1X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
111 /* 0x2X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
112 /* 0x3X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
113 /* 0x4X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
114 /* 0x5X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
115 /* 0x6X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
116 /* 0x7X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
117 /* 0x8X */ 2, 3, 2, 3, 0, 1, 1, 1, 1, 4, 0, 4, 1, 5, 0, 2,
118 /* 0x9X */ 5, 6, 5, 6, 3, 4, 4, 4, 4, 7, 3, 7, 4, 8, 3, 3,
119 /* 0xAX */ 2, 3, 2, 3, 0, 1, 1, 1, 1, 4, 0, 4, 1, 5, 0, 2,
120 /* 0xBX */ 5, 6, 5, 6, 3, 4, 4, 4, 4, 7, 3, 7, 4, 8, 3, 5,
121 /* 0xCX */ 2, 3, 2, 3, 0, 1, 1, 1, 1, 4, 0, 4, 1, 5, 0, 2,
122 /* 0xDX */ 5, 6, 5, 6, 3, 4, 4, 4, 4, 7, 3, 7, 4, 8, 3, 5,
123 /* 0xEX */ 2, 3, 2, 3, 0, 1, 1, 1, 1, 4, 0, 4, 1, 5, 0, 2,
124 /* 0xFX */ 4, 6, 5, 6, 3, 4, 4, 4, 4, 7, 3, 7, 4, 8, 3, 5
127 /* timings for 1-byte opcodes */
128 /* 20100731 Fix to XM7 */
129 static const int cycles1[] = {
130 /* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
131 /*0 */ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 3, 6,
132 /*1 */ 0, 0, 2, 2, 0, 0, 5, 9, 3, 2, 3, 2, 3, 2, 8, 6,
133 /*2 */ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
134 /*3 */ 4, 4, 4, 4, 5, 5, 5, 5, 4, 5, 3, 6, 20, 11, 1, 19,
135 /*4 */ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
136 /*5 */ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
137 /*6 */ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 3, 6,
138 /*7 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 4, 7,
139 /*8 */ 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 2, 4, 7, 3, 3,
140 /*9 */ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 6, 7, 5, 5,
141 /*A*/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 6, 7, 5, 5,
142 /*B*/ 5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 5, 7, 8, 6, 6,
143 /*C*/ 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 2, 3, 0, 3, 3,
144 /*D*/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
145 /*E*/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
146 /*F*/ 5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6
150 static void (MC6809::*m6809_main[0x100]) (void) = {
151 /* 0xX0, 0xX1, 0xX2, 0xX3, 0xX4, 0xX5, 0xX6, 0xX7,
152 0xX8, 0xX9, 0xXA, 0xXB, 0xXC, 0xXD, 0xXE, 0xXF */
155 &MC6809::neg_di, &MC6809::neg_di, &MC6809::ngc_di, &MC6809::com_di,
156 &MC6809::lsr_di, &MC6809::lsr_di, &MC6809::ror_di, &MC6809::asr_di,
157 &MC6809::asl_di, &MC6809::rol_di, &MC6809::dec_di, &MC6809::dcc_di,
158 &MC6809::inc_di, &MC6809::tst_di, &MC6809::jmp_di, &MC6809::clr_di,
160 &MC6809::pref10, &MC6809::pref11, &MC6809::nop, &MC6809::sync_09,
161 &MC6809::trap, &MC6809::trap, &MC6809::lbra, &MC6809::lbsr,
162 &MC6809::aslcc_in, &MC6809::daa, &MC6809::orcc, &MC6809::nop,
163 &MC6809::andcc, &MC6809::sex, &MC6809::exg, &MC6809::tfr,
165 &MC6809::bra, &MC6809::brn, &MC6809::bhi, &MC6809::bls,
166 &MC6809::bcc, &MC6809::bcs, &MC6809::bne, &MC6809::beq,
167 &MC6809::bvc, &MC6809::bvs, &MC6809::bpl, &MC6809::bmi,
168 &MC6809::bge, &MC6809::blt, &MC6809::bgt, &MC6809::ble,
170 &MC6809::leax, &MC6809::leay, &MC6809::leas, &MC6809::leau,
171 &MC6809::pshs, &MC6809::puls, &MC6809::pshu, &MC6809::pulu,
172 &MC6809::andcc, &MC6809::rts, &MC6809::abx, &MC6809::rti,
173 &MC6809::cwai, &MC6809::mul, &MC6809::rst, &MC6809::swi,
175 &MC6809::nega, &MC6809::nega, &MC6809::ngca, &MC6809::coma,
176 &MC6809::lsra, &MC6809::lsra, &MC6809::rora, &MC6809::asra,
177 &MC6809::asla, &MC6809::rola, &MC6809::deca, &MC6809::dcca,
178 &MC6809::inca, &MC6809::tsta, &MC6809::clca, &MC6809::clra,
180 &MC6809::negb, &MC6809::negb, &MC6809::ngcb, &MC6809::comb,
181 &MC6809::lsrb, &MC6809::lsrb, &MC6809::rorb, &MC6809::asrb,
182 &MC6809::aslb, &MC6809::rolb, &MC6809::decb, &MC6809::dccb,
183 &MC6809::incb, &MC6809::tstb, &MC6809::clcb, &MC6809::clrb,
185 &MC6809::neg_ix, &MC6809::neg_ix, &MC6809::ngc_ix, &MC6809::com_ix,
186 &MC6809::lsr_ix, &MC6809::lsr_ix, &MC6809::ror_ix, &MC6809::asr_ix,
187 &MC6809::asl_ix, &MC6809::rol_ix, &MC6809::dec_ix, &MC6809::dcc_ix,
188 &MC6809::inc_ix, &MC6809::tst_ix, &MC6809::jmp_ix, &MC6809::clr_ix,
190 &MC6809::neg_ex, &MC6809::neg_ex, &MC6809::ngc_ex, &MC6809::com_ex,
191 &MC6809::lsr_ex, &MC6809::lsr_ex, &MC6809::ror_ex, &MC6809::asr_ex,
192 &MC6809::asl_ex, &MC6809::rol_ex, &MC6809::dec_ex, &MC6809::dcc_ex,
193 &MC6809::inc_ex, &MC6809::tst_ex, &MC6809::jmp_ex, &MC6809::clr_ex,
195 &MC6809::suba_im, &MC6809::cmpa_im, &MC6809::sbca_im, &MC6809::subd_im,
196 &MC6809::anda_im, &MC6809::bita_im, &MC6809::lda_im, &MC6809::flag8_im,
197 &MC6809::eora_im, &MC6809::adca_im, &MC6809::ora_im, &MC6809::adda_im,
198 &MC6809::cmpx_im, &MC6809::bsr, &MC6809::ldx_im, &MC6809::flag16_im,
200 &MC6809::suba_di, &MC6809::cmpa_di, &MC6809::sbca_di, &MC6809::subd_di,
201 &MC6809::anda_di, &MC6809::bita_di, &MC6809::lda_di, &MC6809::sta_di,
202 &MC6809::eora_di, &MC6809::adca_di, &MC6809::ora_di, &MC6809::adda_di,
203 &MC6809::cmpx_di, &MC6809::jsr_di, &MC6809::ldx_di, &MC6809::stx_di,
205 &MC6809::suba_ix, &MC6809::cmpa_ix, &MC6809::sbca_ix, &MC6809::subd_ix,
206 &MC6809::anda_ix, &MC6809::bita_ix, &MC6809::lda_ix, &MC6809::sta_ix,
207 &MC6809::eora_ix, &MC6809::adca_ix, &MC6809::ora_ix, &MC6809::adda_ix,
208 &MC6809::cmpx_ix, &MC6809::jsr_ix, &MC6809::ldx_ix, &MC6809::stx_ix,
210 &MC6809::suba_ex, &MC6809::cmpa_ex, &MC6809::sbca_ex, &MC6809::subd_ex,
211 &MC6809::anda_ex, &MC6809::bita_ex, &MC6809::lda_ex, &MC6809::sta_ex,
212 &MC6809::eora_ex, &MC6809::adca_ex, &MC6809::ora_ex, &MC6809::adda_ex,
213 &MC6809::cmpx_ex, &MC6809::jsr_ex, &MC6809::ldx_ex, &MC6809::stx_ex,
215 &MC6809::subb_im, &MC6809::cmpb_im, &MC6809::sbcb_im, &MC6809::addd_im,
216 &MC6809::andb_im, &MC6809::bitb_im, &MC6809::ldb_im, &MC6809::flag8_im,
217 &MC6809::eorb_im, &MC6809::adcb_im, &MC6809::orb_im, &MC6809::addb_im,
218 &MC6809::ldd_im, &MC6809::trap, &MC6809::ldu_im, &MC6809::flag16_im,
220 &MC6809::subb_di, &MC6809::cmpb_di, &MC6809::sbcb_di, &MC6809::addd_di,
221 &MC6809::andb_di, &MC6809::bitb_di, &MC6809::ldb_di, &MC6809::stb_di,
222 &MC6809::eorb_di, &MC6809::adcb_di, &MC6809::orb_di, &MC6809::addb_di,
223 &MC6809::ldd_di, &MC6809::std_di, &MC6809::ldu_di, &MC6809::stu_di,
225 &MC6809::subb_ix, &MC6809::cmpb_ix, &MC6809::sbcb_ix, &MC6809::addd_ix,
226 &MC6809::andb_ix, &MC6809::bitb_ix, &MC6809::ldb_ix, &MC6809::stb_ix,
227 &MC6809::eorb_ix, &MC6809::adcb_ix, &MC6809::orb_ix, &MC6809::addb_ix,
228 &MC6809::ldd_ix, &MC6809::std_ix, &MC6809::ldu_ix, &MC6809::stu_ix,
230 &MC6809::subb_ex, &MC6809::cmpb_ex, &MC6809::sbcb_ex, &MC6809::addd_ex,
231 &MC6809::andb_ex, &MC6809::bitb_ex, &MC6809::ldb_ex, &MC6809::stb_ex,
232 &MC6809::eorb_ex, &MC6809::adcb_ex, &MC6809::orb_ex, &MC6809::addb_ex,
233 &MC6809::ldd_ex, &MC6809::std_ex, &MC6809::ldu_ex, &MC6809::stu_ex
239 int_state &= MC6809_HALT_BIT;
243 DPD = 0; /* Reset direct page register */
251 #if defined(_FM7) || defined(_FM8) || defined(_FM77_VARIANTS) || defined(_FM77AV_VARIANTS)
253 write_signals(&outputs_bus_clr, 0x00000000);
255 write_signals(&outputs_bus_halt, ((int_state & MC6809_HALT_BIT) != 0) ? 0xffffffff : 0x00000000);
257 CC |= CC_II; /* IRQ disabled */
258 CC |= CC_IF; /* FIRQ disabled */
260 pPC = RM16_PAIR(0xfffe);
264 void MC6809::initialize()
269 d_mem_stored = d_mem;
270 d_debugger->set_context_mem(d_mem);
274 void MC6809::write_signal(int id, uint32_t data, uint32_t mask)
276 if(id == SIG_CPU_IRQ) {
278 int_state |= MC6809_IRQ_BIT;
280 int_state &= ~MC6809_IRQ_BIT;
282 } else if(id == SIG_CPU_FIRQ) {
284 int_state |= MC6809_FIRQ_BIT;
286 int_state &= ~MC6809_FIRQ_BIT;
288 } else if(id == SIG_CPU_NMI) {
290 int_state |= MC6809_NMI_BIT;
292 int_state &= ~MC6809_NMI_BIT;
294 } else if(id == SIG_CPU_BUSREQ) {
296 int_state |= MC6809_HALT_BIT;
298 int_state &= ~MC6809_HALT_BIT;
303 void MC6809::cpu_nmi(void)
306 if ((int_state & MC6809_CWAI_IN) == 0) {
317 CC = CC | CC_II | CC_IF; // 0x50
318 pPC = RM16_PAIR(0xfffc);
319 // printf("NMI occured PC=0x%04x VECTOR=%04x SP=%04x \n",rpc.w.l,pPC.w.l,S);
320 int_state |= MC6809_CWAI_OUT;
321 int_state &= ~(MC6809_NMI_BIT | MC6809_SYNC_IN | MC6809_SYNC_OUT | MC6809_CWAI_IN); // $FF1E
325 // Refine from cpu_x86.asm of V3.52a.
326 void MC6809::cpu_firq(void)
329 if ((int_state & MC6809_CWAI_IN) == 0) {
335 CC = CC | CC_IF | CC_II;
336 pPC = RM16_PAIR(0xfff6);
337 int_state |= MC6809_CWAI_OUT;
338 int_state &= ~(MC6809_SYNC_IN | MC6809_SYNC_OUT | MC6809_CWAI_IN);
339 // printf("Firq occured PC=0x%04x VECTOR=%04x SP=%04x \n",rpc.w.l,pPC.w.l,S);
342 // Refine from cpu_x86.asm of V3.52a.
343 void MC6809::cpu_irq(void)
346 if ((int_state & MC6809_CWAI_IN) == 0) {
358 pPC = RM16_PAIR(0xfff8);
359 int_state |= MC6809_CWAI_OUT;
360 int_state &= ~(MC6809_SYNC_IN | MC6809_SYNC_OUT | MC6809_CWAI_IN);
362 // printf("IRQ occured PC=0x%04x VECTOR=%04x SP=%04x \n",rpc.w.l,pPC.w.l,S);
365 int MC6809::run(int clock)
372 first_icount = icount;
374 if ((int_state & MC6809_HALT_BIT) != 0) { // 0x80
376 icount -= extra_icount;
378 if(!busreq) write_signals(&outputs_bus_halt, 0xffffffff);
380 return first_icount - icount;
382 if(busreq) write_signals(&outputs_bus_halt, 0x00000000);
384 if((int_state & MC6809_INSN_HALT) != 0) { // 0x80
385 uint8_t dmy = RM(PCD);
387 icount -= extra_icount;
390 return first_icount - icount;
396 if ((int_state & (MC6809_NMI_BIT | MC6809_FIRQ_BIT | MC6809_IRQ_BIT)) != 0) { // 0x0007
397 if ((int_state & MC6809_NMI_BIT) == 0)
399 //if ((int_state & MC6809_LDS) == 0)
403 int_state &= ~MC6809_SYNC_IN;
411 if ((int_state & MC6809_FIRQ_BIT) != 0) {
412 if ((CC & CC_IF) != 0)
416 int_state &= ~MC6809_SYNC_IN;
422 if ((int_state & MC6809_IRQ_BIT) != 0) {
423 if ((CC & CC_II) != 0)
427 int_state &= ~MC6809_SYNC_IN;
439 if((int_state & MC6809_CWAI_IN) == 0) {
442 int_state &= ~MC6809_CWAI_IN;
444 return first_icount - icount;
448 if((int_state & MC6809_SYNC_IN) != 0) {
454 return first_icount - icount;
456 if((int_state & MC6809_CWAI_IN) == 0) {
458 // run only one opcode
462 // run cpu while given clocks
466 return first_icount - icount;
475 return first_icount - icount;
480 void MC6809::run_one_opecode()
483 bool now_debugging = d_debugger->now_debugging;
485 d_debugger->check_break_points(PC);
486 if(d_debugger->now_suspended) {
488 while(d_debugger->now_debugging && d_debugger->now_suspended) {
492 if(d_debugger->now_debugging) {
495 now_debugging = false;
499 uint8_t ireg = ROP(PCD);
501 icount -= cycles1[ireg];
502 icount -= extra_icount;
507 if(!d_debugger->now_going) {
508 d_debugger->now_suspended = true;
510 d_mem = d_mem_stored;
514 uint8_t ireg = ROP(PCD);
516 icount -= cycles1[ireg];
517 icount -= extra_icount;
523 uint8_t ireg = ROP(PCD);
525 icount -= cycles1[ireg];
526 icount -= extra_icount;
532 void MC6809::op(uint8_t ireg)
534 #if defined(_FM7) || defined(_FM8) || defined(_FM77_VARIANTS) || defined(_FM77AV_VARIANTS)
535 if(ireg == 0x0f) { // clr_di()
536 write_signals(&outputs_bus_clr, 0x00000001);
538 } else if((ireg == 0x6f) || (ireg == 0x7f)){ //clr_ex() clr_ix()
539 write_signals(&outputs_bus_clr, 0x00000002);
542 if(clr_used) write_signals(&outputs_bus_clr, 0x00000000);
547 //printf("CPU(%08x) PC=%04x OP=%02x %02x %02x %02x %02x\n", (void *)this, PC, ireg, RM(PC), RM(PC + 1), RM(PC + 2), RM(PC + 3));
549 (this->*m6809_main[ireg])();
553 void MC6809::write_debug_data8(uint32_t addr, uint32_t data)
555 d_mem_stored->write_data8(addr, data);
558 uint32_t MC6809::read_debug_data8(uint32_t addr)
560 return d_mem_stored->read_data8(addr);
563 void MC6809::write_debug_io8(uint32_t addr, uint32_t data)
565 d_mem_stored->write_io8(addr, data);
568 uint32_t MC6809::read_debug_io8(uint32_t addr)
570 uint8_t val = d_mem_stored->read_io8(addr);
574 bool MC6809::write_debug_reg(const _TCHAR *reg, uint32_t data)
576 if(_tcsicmp(reg, _T("PC")) == 0) {
578 } else if(_tcsicmp(reg, _T("DP")) == 0) {
580 } else if(_tcsicmp(reg, _T("A")) == 0) {
582 } else if(_tcsicmp(reg, _T("B")) == 0) {
584 } else if(_tcsicmp(reg, _T("D")) == 0) {
586 } else if(_tcsicmp(reg, _T("U")) == 0) {
588 } else if(_tcsicmp(reg, _T("X")) == 0) {
590 } else if(_tcsicmp(reg, _T("Y")) == 0) {
592 } else if(_tcsicmp(reg, _T("S")) == 0) {
594 } else if(_tcsicmp(reg, _T("CC")) == 0) {
602 void MC6809::get_debug_regs_info(_TCHAR *buffer, size_t buffer_len)
604 my_stprintf_s(buffer, buffer_len,
605 _T("PC = %04x PPC = %04x INTR=[%s %s %s %s][%s %s %s %s %s] CC = [%c%c%c%c%c%c%c%c]\nA = %02x B = %02x DP = %02x X = %04x Y = %04x U = %04x S = %04x EA = %04x"),
608 ((int_state & MC6809_IRQ_BIT) == 0) ? _T("----") : _T(" IRQ"),
609 ((int_state & MC6809_FIRQ_BIT) == 0) ? _T("----") : _T("FIRQ"),
610 ((int_state & MC6809_NMI_BIT) == 0) ? _T("----") : _T(" NMI"),
611 ((int_state & MC6809_HALT_BIT) == 0) ? _T("----") : _T("HALT"),
612 ((int_state & MC6809_CWAI_IN) == 0) ? _T("--") : _T("CI"),
613 ((int_state & MC6809_CWAI_OUT) == 0) ? _T("--") : _T("CO"),
614 ((int_state & MC6809_SYNC_IN) == 0) ? _T("--") : _T("SI"),
615 ((int_state & MC6809_SYNC_OUT) == 0) ? _T("--") : _T("SO"),
616 ((int_state & MC6809_INSN_HALT) == 0) ? _T("----") : _T("TRAP"),
617 ((CC & CC_E) == 0) ? _T('-') : _T('E'),
618 ((CC & CC_IF) == 0) ? _T('-') : _T('F'),
619 ((CC & CC_H) == 0) ? _T('-') : _T('H'),
620 ((CC & CC_II) == 0) ? _T('-') : _T('I'),
621 ((CC & CC_N) == 0) ? _T('-') : _T('N'),
622 ((CC & CC_Z) == 0) ? _T('-') : _T('Z'),
623 ((CC & CC_V) == 0) ? _T('-') : _T('V'),
624 ((CC & CC_C) == 0) ? _T('-') : _T('C'),
633 /*****************************************************************************
635 6809dasm.c - a 6809 opcode disassembler
637 Copyright Sean Riddle
639 Thanks to Franklin Bowen for bug fixes, ideas
641 Freely distributable on any medium given all copyrights are retained
642 by the author and no charge greater than $7.00 is made for obtaining
645 Please send all bug reports, update ideas and data files to:
648 *****************************************************************************/
653 uint8_t opcode; // 8-bit opcode value
654 uint8_t length; // Opcode length in bytes
655 _TCHAR name[6]; // Opcode name
656 uint8_t mode; // Addressing mode
657 // unsigned flags; // Disassembly flags
660 enum m6809_addressing_modes
665 REL, // Relative (8 bit)
666 LREL, // Long relative (16 bit)
669 IMM_RR, // Register-to-register
670 PG1, // Switch to page 1 opcodes
671 PG2 // Switch to page 2 opcodes
674 // Page 0 opcodes (single byte)
675 static const opcodeinfo m6809_pg0opcodes[] =
677 { 0x00, 2, _T("NEG"), DIR },
678 { 0x01, 2, _T("NEG"), DIR },
679 { 0x02, 2, _T("NGC"), DIR },
680 { 0x03, 2, _T("COM"), DIR },
681 { 0x04, 2, _T("LSR"), DIR },
682 { 0x05, 2, _T("LSR"), DIR },
683 { 0x06, 2, _T("ROR"), DIR },
684 { 0x07, 2, _T("ASR"), DIR },
685 { 0x08, 2, _T("ASL"), DIR },
686 { 0x09, 2, _T("ROL"), DIR },
687 { 0x0A, 2, _T("DEC"), DIR },
688 { 0x0B, 2, _T("DCC"), DIR },
689 { 0x0C, 2, _T("INC"), DIR },
690 { 0x0D, 2, _T("TST"), DIR },
691 { 0x0E, 2, _T("JMP"), DIR },
692 { 0x0F, 2, _T("CLR"), DIR },
694 { 0x10, 1, _T("page1"), PG1 },
695 { 0x11, 1, _T("page2"), PG2 },
696 { 0x12, 1, _T("NOP"), INH },
697 { 0x13, 1, _T("SYNC"), INH },
698 { 0x14, 1, _T("HALT"), INH },
699 { 0x15, 1, _T("HALT"), INH },
700 { 0x16, 3, _T("LBRA"), LREL },
701 { 0x17, 3, _T("LBSR"), LREL },
702 { 0x18, 1, _T("ASLCC"), INH },
703 { 0x19, 1, _T("DAA"), INH },
704 { 0x1A, 2, _T("ORCC"), IMM },
705 { 0x1B, 1, _T("NOP"), INH },
706 { 0x1C, 2, _T("ANDCC"), IMM },
707 { 0x1D, 1, _T("SEX"), INH },
708 { 0x1E, 2, _T("EXG"), IMM_RR },
709 { 0x1F, 2, _T("TFR"), IMM_RR },
711 { 0x20, 2, _T("BRA"), REL },
712 { 0x21, 2, _T("BRN"), REL },
713 { 0x22, 2, _T("BHI"), REL },
714 { 0x23, 2, _T("BLS"), REL },
715 { 0x24, 2, _T("BCC"), REL },
716 { 0x25, 2, _T("BCS"), REL },
717 { 0x26, 2, _T("BNE"), REL },
718 { 0x27, 2, _T("BEQ"), REL },
719 { 0x28, 2, _T("BVC"), REL },
720 { 0x29, 2, _T("BVS"), REL },
721 { 0x2A, 2, _T("BPL"), REL },
722 { 0x2B, 2, _T("BMI"), REL },
723 { 0x2C, 2, _T("BGE"), REL },
724 { 0x2D, 2, _T("BLT"), REL },
725 { 0x2E, 2, _T("BGT"), REL },
726 { 0x2F, 2, _T("BLE"), REL },
728 { 0x30, 2, _T("LEAX"), IND },
729 { 0x31, 2, _T("LEAY"), IND },
730 { 0x32, 2, _T("LEAS"), IND },
731 { 0x33, 2, _T("LEAU"), IND },
732 { 0x34, 2, _T("PSHS"), INH },
733 { 0x35, 2, _T("PULS"), INH },
734 { 0x36, 2, _T("PSHU"), INH },
735 { 0x37, 2, _T("PULU"), INH },
736 { 0x38, 2, _T("ANDCC"), IMM },
737 { 0x39, 1, _T("RTS"), INH },
738 { 0x3A, 1, _T("ABX"), INH },
739 { 0x3B, 1, _T("RTI"), INH },
740 { 0x3C, 2, _T("CWAI"), IMM },
741 { 0x3D, 1, _T("MUL"), INH },
742 { 0x3F, 1, _T("SWI"), INH },
744 { 0x40, 1, _T("NEGA"), INH },
745 { 0x41, 1, _T("NEGA"), INH },
746 { 0x42, 1, _T("NGGA"), INH },
747 { 0x43, 1, _T("COMA"), INH },
748 { 0x44, 1, _T("LSRA"), INH },
749 { 0x45, 1, _T("LSRA"), INH },
750 { 0x46, 1, _T("RORA"), INH },
751 { 0x47, 1, _T("ASRA"), INH },
752 { 0x48, 1, _T("ASLA"), INH },
753 { 0x49, 1, _T("ROLA"), INH },
754 { 0x4A, 1, _T("DECA"), INH },
755 { 0x4B, 1, _T("DCCA"), INH },
756 { 0x4C, 1, _T("INCA"), INH },
757 { 0x4D, 1, _T("TSTA"), INH },
758 { 0x4E, 1, _T("CLCA"), INH },
759 { 0x4F, 1, _T("CLRA"), INH },
761 { 0x50, 1, _T("NEGB"), INH },
762 { 0x51, 1, _T("NEGB"), INH },
763 { 0x52, 1, _T("NGGB"), INH },
764 { 0x53, 1, _T("COMB"), INH },
765 { 0x54, 1, _T("LSRB"), INH },
766 { 0x55, 1, _T("LSRB"), INH },
767 { 0x56, 1, _T("RORB"), INH },
768 { 0x57, 1, _T("ASRB"), INH },
769 { 0x58, 1, _T("ASLB"), INH },
770 { 0x59, 1, _T("ROLB"), INH },
771 { 0x5A, 1, _T("DECB"), INH },
772 { 0x5B, 1, _T("DCCB"), INH },
773 { 0x5C, 1, _T("INCB"), INH },
774 { 0x5D, 1, _T("TSTB"), INH },
775 { 0x5E, 1, _T("CLCB"), INH },
776 { 0x5F, 1, _T("CLRB"), INH },
778 { 0x60, 2, _T("NEG"), IND },
779 { 0x61, 2, _T("NEG"), IND },
780 { 0x62, 2, _T("NGC"), IND },
781 { 0x63, 2, _T("COM"), IND },
782 { 0x64, 2, _T("LSR"), IND },
783 { 0x65, 2, _T("LSR"), IND },
784 { 0x66, 2, _T("ROR"), IND },
785 { 0x67, 2, _T("ASR"), IND },
786 { 0x68, 2, _T("ASL"), IND },
787 { 0x69, 2, _T("ROL"), IND },
788 { 0x6A, 2, _T("DEC"), IND },
789 { 0x6B, 2, _T("DCC"), IND },
790 { 0x6C, 2, _T("INC"), IND },
791 { 0x6D, 2, _T("TST"), IND },
792 { 0x6E, 2, _T("JMP"), IND },
793 { 0x6F, 2, _T("CLR"), IND },
795 { 0x70, 3, _T("NEG"), EXT },
796 { 0x71, 3, _T("NEG"), EXT },
797 { 0x72, 3, _T("NGC"), EXT },
798 { 0x73, 3, _T("COM"), EXT },
799 { 0x74, 3, _T("LSR"), EXT },
800 { 0x75, 3, _T("LSR"), EXT },
801 { 0x76, 3, _T("ROR"), EXT },
802 { 0x77, 3, _T("ASR"), EXT },
803 { 0x78, 3, _T("ASL"), EXT },
804 { 0x79, 3, _T("ROL"), EXT },
805 { 0x7A, 3, _T("DEC"), EXT },
806 { 0x7B, 3, _T("DCC"), EXT },
807 { 0x7C, 3, _T("INC"), EXT },
808 { 0x7D, 3, _T("TST"), EXT },
809 { 0x7E, 3, _T("JMP"), EXT },
810 { 0x7F, 3, _T("CLR"), EXT },
812 { 0x80, 2, _T("SUBA"), IMM },
813 { 0x81, 2, _T("CMPA"), IMM },
814 { 0x82, 2, _T("SBCA"), IMM },
815 { 0x83, 3, _T("SUBD"), IMM },
816 { 0x84, 2, _T("ANDA"), IMM },
817 { 0x85, 2, _T("BITA"), IMM },
818 { 0x86, 2, _T("LDA"), IMM },
819 { 0x87, 2, _T("FLAG"), IMM },
820 { 0x88, 2, _T("EORA"), IMM },
821 { 0x89, 2, _T("ADCA"), IMM },
822 { 0x8A, 2, _T("ORA"), IMM },
823 { 0x8B, 2, _T("ADDA"), IMM },
824 { 0x8C, 3, _T("CMPX"), IMM },
825 { 0x8D, 2, _T("BSR"), REL },
826 { 0x8E, 3, _T("LDX"), IMM },
827 { 0x8F, 3, _T("FLAG"), IMM },
829 { 0x90, 2, _T("SUBA"), DIR },
830 { 0x91, 2, _T("CMPA"), DIR },
831 { 0x92, 2, _T("SBCA"), DIR },
832 { 0x93, 2, _T("SUBD"), DIR },
833 { 0x94, 2, _T("ANDA"), DIR },
834 { 0x95, 2, _T("BITA"), DIR },
835 { 0x96, 2, _T("LDA"), DIR },
836 { 0x97, 2, _T("STA"), DIR },
837 { 0x98, 2, _T("EORA"), DIR },
838 { 0x99, 2, _T("ADCA"), DIR },
839 { 0x9A, 2, _T("ORA"), DIR },
840 { 0x9B, 2, _T("ADDA"), DIR },
841 { 0x9C, 2, _T("CMPX"), DIR },
842 { 0x9D, 2, _T("JSR"), DIR },
843 { 0x9E, 2, _T("LDX"), DIR },
844 { 0x9F, 2, _T("STX"), DIR },
846 { 0xA0, 2, _T("SUBA"), IND },
847 { 0xA1, 2, _T("CMPA"), IND },
848 { 0xA2, 2, _T("SBCA"), IND },
849 { 0xA3, 2, _T("SUBD"), IND },
850 { 0xA4, 2, _T("ANDA"), IND },
851 { 0xA5, 2, _T("BITA"), IND },
852 { 0xA6, 2, _T("LDA"), IND },
853 { 0xA7, 2, _T("STA"), IND },
854 { 0xA8, 2, _T("EORA"), IND },
855 { 0xA9, 2, _T("ADCA"), IND },
856 { 0xAA, 2, _T("ORA"), IND },
857 { 0xAB, 2, _T("ADDA"), IND },
858 { 0xAC, 2, _T("CMPX"), IND },
859 { 0xAD, 2, _T("JSR"), IND },
860 { 0xAE, 2, _T("LDX"), IND },
861 { 0xAF, 2, _T("STX"), IND },
863 { 0xB0, 3, _T("SUBA"), EXT },
864 { 0xB1, 3, _T("CMPA"), EXT },
865 { 0xB2, 3, _T("SBCA"), EXT },
866 { 0xB3, 3, _T("SUBD"), EXT },
867 { 0xB4, 3, _T("ANDA"), EXT },
868 { 0xB5, 3, _T("BITA"), EXT },
869 { 0xB6, 3, _T("LDA"), EXT },
870 { 0xB7, 3, _T("STA"), EXT },
871 { 0xB8, 3, _T("EORA"), EXT },
872 { 0xB9, 3, _T("ADCA"), EXT },
873 { 0xBA, 3, _T("ORA"), EXT },
874 { 0xBB, 3, _T("ADDA"), EXT },
875 { 0xBC, 3, _T("CMPX"), EXT },
876 { 0xBD, 3, _T("JSR"), EXT },
877 { 0xBE, 3, _T("LDX"), EXT },
878 { 0xBF, 3, _T("STX"), EXT },
880 { 0xC0, 2, _T("SUBB"), IMM },
881 { 0xC1, 2, _T("CMPB"), IMM },
882 { 0xC2, 2, _T("SBCB"), IMM },
883 { 0xC3, 3, _T("ADDD"), IMM },
884 { 0xC4, 2, _T("ANDB"), IMM },
885 { 0xC5, 2, _T("BITB"), IMM },
886 { 0xC6, 2, _T("LDB"), IMM },
887 { 0xC7, 2, _T("FLAG"), IMM },
888 { 0xC8, 2, _T("EORB"), IMM },
889 { 0xC9, 2, _T("ADCB"), IMM },
890 { 0xCA, 2, _T("ORB"), IMM },
891 { 0xCB, 2, _T("ADDB"), IMM },
892 { 0xCC, 3, _T("LDD"), IMM },
893 { 0xCD, 1, _T("HALT"), INH },
894 { 0xCE, 3, _T("LDU"), IMM },
895 { 0xCF, 3, _T("FLAG"), IMM },
897 { 0xD0, 2, _T("SUBB"), DIR },
898 { 0xD1, 2, _T("CMPB"), DIR },
899 { 0xD2, 2, _T("SBCB"), DIR },
900 { 0xD3, 2, _T("ADDD"), DIR },
901 { 0xD4, 2, _T("ANDB"), DIR },
902 { 0xD5, 2, _T("BITB"), DIR },
903 { 0xD6, 2, _T("LDB"), DIR },
904 { 0xD7, 2, _T("STB"), DIR },
905 { 0xD8, 2, _T("EORB"), DIR },
906 { 0xD9, 2, _T("ADCB"), DIR },
907 { 0xDA, 2, _T("ORB"), DIR },
908 { 0xDB, 2, _T("ADDB"), DIR },
909 { 0xDC, 2, _T("LDD"), DIR },
910 { 0xDD, 2, _T("STD"), DIR },
911 { 0xDE, 2, _T("LDU"), DIR },
912 { 0xDF, 2, _T("STU"), DIR },
914 { 0xE0, 2, _T("SUBB"), IND },
915 { 0xE1, 2, _T("CMPB"), IND },
916 { 0xE2, 2, _T("SBCB"), IND },
917 { 0xE3, 2, _T("ADDD"), IND },
918 { 0xE4, 2, _T("ANDB"), IND },
919 { 0xE5, 2, _T("BITB"), IND },
920 { 0xE6, 2, _T("LDB"), IND },
921 { 0xE7, 2, _T("STB"), IND },
922 { 0xE8, 2, _T("EORB"), IND },
923 { 0xE9, 2, _T("ADCB"), IND },
924 { 0xEA, 2, _T("ORB"), IND },
925 { 0xEB, 2, _T("ADDB"), IND },
926 { 0xEC, 2, _T("LDD"), IND },
927 { 0xED, 2, _T("STD"), IND },
928 { 0xEE, 2, _T("LDU"), IND },
929 { 0xEF, 2, _T("STU"), IND },
931 { 0xF0, 3, _T("SUBB"), EXT },
932 { 0xF1, 3, _T("CMPB"), EXT },
933 { 0xF2, 3, _T("SBCB"), EXT },
934 { 0xF3, 3, _T("ADDD"), EXT },
935 { 0xF4, 3, _T("ANDB"), EXT },
936 { 0xF5, 3, _T("BITB"), EXT },
937 { 0xF6, 3, _T("LDB"), EXT },
938 { 0xF7, 3, _T("STB"), EXT },
939 { 0xF8, 3, _T("EORB"), EXT },
940 { 0xF9, 3, _T("ADCB"), EXT },
941 { 0xFA, 3, _T("ORB"), EXT },
942 { 0xFB, 3, _T("ADDB"), EXT },
943 { 0xFC, 3, _T("LDD"), EXT },
944 { 0xFD, 3, _T("STD"), EXT },
945 { 0xFE, 3, _T("LDU"), EXT },
946 { 0xFF, 3, _T("STU"), EXT }
949 // Page 1 opcodes (0x10 0x..)
950 static const opcodeinfo m6809_pg1opcodes[] =
952 { 0x20, 4, _T("LBRA"), LREL },
953 { 0x21, 4, _T("LBRN"), LREL },
954 { 0x22, 4, _T("LBHI"), LREL },
955 { 0x23, 4, _T("LBLS"), LREL },
956 { 0x24, 4, _T("LBCC"), LREL },
957 { 0x25, 4, _T("LBCS"), LREL },
958 { 0x26, 4, _T("LBNE"), LREL },
959 { 0x27, 4, _T("LBEQ"), LREL },
960 { 0x28, 4, _T("LBVC"), LREL },
961 { 0x29, 4, _T("LBVS"), LREL },
962 { 0x2A, 4, _T("LBPL"), LREL },
963 { 0x2B, 4, _T("LBMI"), LREL },
964 { 0x2C, 4, _T("LBGE"), LREL },
965 { 0x2D, 4, _T("LBLT"), LREL },
966 { 0x2E, 4, _T("LBGT"), LREL },
967 { 0x2F, 4, _T("LBLE"), LREL },
968 { 0x3F, 2, _T("SWI2"), INH },
969 { 0x83, 4, _T("CMPD"), IMM },
970 { 0x8C, 4, _T("CMPY"), IMM },
971 { 0x8D, 4, _T("LBSR"), LREL },
972 { 0x8E, 4, _T("LDY"), IMM },
973 { 0x93, 3, _T("CMPD"), DIR },
974 { 0x9C, 3, _T("CMPY"), DIR },
975 { 0x9E, 3, _T("LDY"), DIR },
976 { 0x9F, 3, _T("STY"), DIR },
977 { 0xA3, 3, _T("CMPD"), IND },
978 { 0xAC, 3, _T("CMPY"), IND },
979 { 0xAE, 3, _T("LDY"), IND },
980 { 0xAF, 3, _T("STY"), IND },
981 { 0xB3, 4, _T("CMPD"), EXT },
982 { 0xBC, 4, _T("CMPY"), EXT },
983 { 0xBE, 4, _T("LDY"), EXT },
984 { 0xBF, 4, _T("STY"), EXT },
985 { 0xCE, 4, _T("LDS"), IMM },
986 { 0xDE, 3, _T("LDS"), DIR },
987 { 0xDF, 3, _T("STS"), DIR },
988 { 0xEE, 3, _T("LDS"), IND },
989 { 0xEF, 3, _T("STS"), IND },
990 { 0xFE, 4, _T("LDS"), EXT },
991 { 0xFF, 4, _T("STS"), EXT }
994 // Page 2 opcodes (0x11 0x..)
995 static const opcodeinfo m6809_pg2opcodes[] =
997 { 0x3F, 2, _T("SWI3"), INH },
998 { 0x83, 4, _T("CMPU"), IMM },
999 { 0x8C, 4, _T("CMPS"), IMM },
1000 { 0x93, 3, _T("CMPU"), DIR },
1001 { 0x9C, 3, _T("CMPS"), DIR },
1002 { 0xA3, 3, _T("CMPU"), IND },
1003 { 0xAC, 3, _T("CMPS"), IND },
1004 { 0xB3, 4, _T("CMPU"), EXT },
1005 { 0xBC, 4, _T("CMPS"), EXT }
1008 static const opcodeinfo *const m6809_pgpointers[3] =
1010 m6809_pg0opcodes, m6809_pg1opcodes, m6809_pg2opcodes
1013 static const int m6809_numops[3] =
1015 array_length(m6809_pg0opcodes),
1016 array_length(m6809_pg1opcodes),
1017 array_length(m6809_pg2opcodes)
1020 static const _TCHAR *const m6809_regs[5] = { _T("X"), _T("Y"), _T("U"), _T("S"), _T("PC") };
1022 static const _TCHAR *const m6809_regs_te[16] =
1024 _T("D"), _T("X"), _T("Y"), _T("U"), _T("S"), _T("PC"), _T("inv"), _T("inv"),
1025 _T("A"), _T("B"), _T("CC"), _T("DP"), _T("inv"), _T("inv"), _T("inv"), _T("inv")
1028 uint32_t MC6809::cpu_disassemble_m6809(_TCHAR *buffer, uint32_t pc, const uint8_t *oprom, const uint8_t *opram)
1030 uint8_t opcode, mode, pb, pbm, reg;
1031 const uint8_t *operandarray;
1032 unsigned int ea;//, flags;
1033 int numoperands, offset;
1034 int i, p = 0, page = 0;
1035 bool opcode_found = false;
1039 opcode = oprom[p++];
1041 for (i = 0; i < m6809_numops[page]; i++)
1042 if (m6809_pgpointers[page][i].opcode == opcode)
1045 if (i < m6809_numops[page])
1046 opcode_found = true;
1049 _stprintf(buffer, _T("Illegal Opcode %02X"), opcode);
1053 if (m6809_pgpointers[page][i].mode >= PG1)
1055 page = m6809_pgpointers[page][i].mode - PG1 + 1;
1056 opcode_found = false;
1058 } while (!opcode_found);
1061 numoperands = m6809_pgpointers[page][i].length - 1;
1063 numoperands = m6809_pgpointers[page][i].length - 2;
1065 operandarray = &opram[p];
1068 mode = m6809_pgpointers[page][i].mode;
1069 // flags = m6809_pgpointers[page][i].flags;
1071 buffer += _stprintf(buffer, _T("%-6s"), m6809_pgpointers[page][i].name);
1080 pb = operandarray[0];
1082 buffer += _stprintf(buffer, _T("PC"));
1084 buffer += _stprintf(buffer, _T("%s%s"), (pb&0x80)?_T(","):_T(""), (opcode==0x34)?"U":"S");
1086 buffer += _stprintf(buffer, _T("%sY"), (pb&0xc0)?_T(","):_T(""));
1088 buffer += _stprintf(buffer, _T("%sX"), (pb&0xe0)?_T(","):_T(""));
1090 buffer += _stprintf(buffer, _T("%sDP"), (pb&0xf0)?_T(","):_T(""));
1092 buffer += _stprintf(buffer, _T("%sB"), (pb&0xf8)?_T(","):_T(""));
1094 buffer += _stprintf(buffer, _T("%sA"), (pb&0xfc)?_T(","):_T(""));
1096 buffer += _stprintf(buffer, _T("%sCC"), (pb&0xfe)?_T(","):_T(""));
1100 pb = operandarray[0];
1102 buffer += _stprintf(buffer, _T("CC"));
1104 buffer += _stprintf(buffer, _T("%sA"), (pb&0x01)?_T(","):_T(""));
1106 buffer += _stprintf(buffer, _T("%sB"), (pb&0x03)?_T(","):_T(""));
1108 buffer += _stprintf(buffer, _T("%sDP"), (pb&0x07)?_T(","):_T(""));
1110 buffer += _stprintf(buffer, _T("%sX"), (pb&0x0f)?_T(","):_T(""));
1112 buffer += _stprintf(buffer, _T("%sY"), (pb&0x1f)?_T(","):_T(""));
1114 buffer += _stprintf(buffer, _T("%s%s"), (pb&0x3f)?_T(","):_T(""), (opcode==0x35)?_T("U"):_T("S"));
1116 buffer += _stprintf(buffer, _T("%sPC ; (PUL? PC=RTS)"), (pb&0x7f)?_T(","):_T(""));
1125 ea = operandarray[0];
1126 buffer += _stprintf(buffer, _T("$%02X"), ea);
1130 offset = (int8_t)operandarray[0];
1131 buffer += _stprintf(buffer, _T("$%04X"), (pc + offset) & 0xffff);
1135 offset = (int16_t)((operandarray[0] << 8) + operandarray[1]);
1136 buffer += _stprintf(buffer, _T("$%04X"), (pc + offset) & 0xffff);
1140 ea = (operandarray[0] << 8) + operandarray[1];
1141 buffer += _stprintf(buffer, _T("$%04X"), ea);
1145 pb = operandarray[0];
1146 reg = (pb >> 5) & 3;
1148 indirect = ((pb & 0x90) == 0x90 )? true : false;
1150 // open brackets if indirect
1151 if (indirect && pbm != 0x80 && pbm != 0x82)
1152 buffer += _stprintf(buffer, _T("["));
1158 _tcscpy(buffer, _T("Illegal Postbyte"));
1160 buffer += _stprintf(buffer, _T(",%s+"), m6809_regs[reg]);
1164 buffer += _stprintf(buffer, _T(",%s++"), m6809_regs[reg]);
1169 // _tcscpy(buffer, _T("Illegal Postbyte"));
1171 buffer += _stprintf(buffer, _T(",-%s"), m6809_regs[reg]);
1175 buffer += _stprintf(buffer, _T(",--%s"), m6809_regs[reg]);
1179 buffer += _stprintf(buffer, _T(",%s"), m6809_regs[reg]);
1182 case 0x85: // (+/- B),R
1183 buffer += _stprintf(buffer, _T("B,%s"), m6809_regs[reg]);
1186 case 0x86: // (+/- A),R
1187 buffer += _stprintf(buffer, _T("A,%s"), m6809_regs[reg]);
1190 case 0x87: // (+/- A),R // Also 0x*6.
1191 buffer += _stprintf(buffer, _T("A,%s"), m6809_regs[reg]);
1194 //_tcscpy(buffer, _T("Illegal Postbyte"));
1197 case 0x88: // (+/- 7 bit offset),R
1198 offset = (int8_t)opram[p++];
1199 buffer += _stprintf(buffer, _T("%s"), (offset < 0) ? "-" : "");
1200 buffer += _stprintf(buffer, _T("$%02X,"), (offset < 0) ? -offset : offset);
1201 buffer += _stprintf(buffer, _T("%s"), m6809_regs[reg]);
1204 case 0x89: // (+/- 15 bit offset),R
1205 offset = (int16_t)((opram[p+0] << 8) + opram[p+1]);
1207 buffer += _stprintf(buffer, _T("%s"), (offset < 0) ? "-" : "");
1208 buffer += _stprintf(buffer, _T("$%04X,"), (offset < 0) ? -offset : offset);
1209 buffer += _stprintf(buffer, _T("%s"), m6809_regs[reg]);
1213 _tcscpy(buffer, _T("Illegal Postbyte"));
1216 case 0x8b: // (+/- D),R
1217 buffer += _stprintf(buffer, _T("D,%s"), m6809_regs[reg]);
1220 case 0x8c: // (+/- 7 bit offset),PC
1221 offset = (int8_t)opram[p++];
1222 buffer += _stprintf(buffer, _T("%s"), (offset < 0) ? "-" : "");
1223 buffer += _stprintf(buffer, _T("$%02X,PC"), (offset < 0) ? -offset : offset);
1226 case 0x8d: // (+/- 15 bit offset),PC
1227 offset = (int16_t)((opram[p+0] << 8) + opram[p+1]);
1229 buffer += _stprintf(buffer, _T("%s"), (offset < 0) ? "-" : "");
1230 buffer += _stprintf(buffer, _T("$%04X,PC"), (offset < 0) ? -offset : offset);
1233 case 0x8e: // $FFFFF
1234 //_tcscpy(buffer, _T("Illegal Postbyte"));
1235 offset = (int16_t)0xffff;
1237 buffer += _stprintf(buffer, _T("$%04X"), offset);
1240 case 0x8f: // address
1241 ea = (uint16_t)((opram[p+0] << 8) + opram[p+1]);
1243 buffer += _stprintf(buffer, _T("$%04X"), ea);
1246 default: // (+/- 4 bit offset),R
1249 offset = offset - 32;
1250 buffer += _stprintf(buffer, _T("%s"), (offset < 0) ? "-" : "");
1251 buffer += _stprintf(buffer, _T("$%X,"), (offset < 0) ? -offset : offset);
1252 buffer += _stprintf(buffer, _T("%s"), m6809_regs[reg]);
1256 // close brackets if indirect
1257 if (indirect && pbm != 0x80 && pbm != 0x82)
1258 buffer += _stprintf(buffer, _T("]"));
1262 if (numoperands == 2)
1264 ea = (operandarray[0] << 8) + operandarray[1];
1265 buffer += _stprintf(buffer, _T("#$%04X"), ea);
1268 if (numoperands == 1)
1270 ea = operandarray[0];
1271 buffer += _stprintf(buffer, _T("#$%02X"), ea);
1276 pb = operandarray[0];
1277 buffer += _stprintf(buffer, _T("%s,%s"), m6809_regs_te[(pb >> 4) & 0xf], m6809_regs_te[pb & 0xf]);
1284 int MC6809::debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len)
1286 _TCHAR buffer_tmp[1024]; // enough ???
1288 for(int i = 0; i < 4; i++) {
1289 ops[i] = d_mem_stored->read_data8(pc + i);
1291 int length = cpu_disassemble_m6809(buffer_tmp, pc, ops, ops);
1292 my_tcscpy_s(buffer, buffer_len, buffer_tmp);
1300 inline void MC6809::fetch_effective_address()
1303 uint8_t upper, lower;
1307 upper = (postbyte >> 4) & 0x0f;
1308 lower = postbyte & 0x0f;
1314 EA = X - 16 + lower;
1320 EA = Y - 16 + lower;
1326 EA = U - 16 + lower;
1332 EA = S - 16 + lower;
1335 fetch_effective_address_IDX(upper, lower);
1339 icount -= index_cycle_em[postbyte];
1342 inline void MC6809::fetch_effective_address_IDX(uint8_t upper, uint8_t lower)
1344 bool indirect = false;
1349 indirect = ((upper & 0x01) != 0) ? true : false;
1351 switch ((upper >> 1) & 0x03) { // $8-$f >> 1 = $4 - $7 : delete bit2
1370 *reg = *reg & 0xffff;
1375 *reg = *reg & 0xffff;
1379 *reg = *reg & 0xffff;
1384 *reg = *reg & 0xffff;
1391 EA = *reg + SIGNED(B);
1395 EA = *reg + SIGNED(A);
1399 EA = *reg + SIGNED(bx_p);
1405 case 0x0a: // Undocumented
1415 EA = PC + SIGNED(bx_p);
1417 case 0x0d: // xxxx,pc
1421 case 0x0e: // Undocumented
1429 // $9x,$bx,$dx,$fx = INDIRECT
1432 EAP = RM16_PAIR(pp.d);
1436 #define IIError() illegal()
1440 //logerror("M6809: illegal opcode at %04x\n",PC);
1441 //printf("M6809: illegal opcode at %04x %02x %02x %02x %02x %02x \n",
1442 // PC - 2, RM(PC - 2), RM(PC - 1), RM(PC), RM(PC + 1), RM(PC + 2));
1446 inline uint8_t MC6809::GET_INDEXED_DATA(void)
1449 fetch_effective_address();
1454 inline pair_t MC6809::GET_INDEXED_DATA16(void)
1457 fetch_effective_address();
1463 inline void MC6809::NEG_MEM(uint8_t a_neg)
1466 r_neg = 0 - (uint16_t)a_neg;
1468 SET_FLAGS8(0, a_neg, r_neg);
1472 inline uint8_t MC6809::NEG_REG(uint8_t a_neg)
1475 r_neg = 0 - (uint16_t)a_neg;
1477 SET_FLAGS8(0, a_neg, r_neg);
1478 return (uint8_t)r_neg;
1483 inline void MC6809::COM_MEM(uint8_t a_com)
1493 inline uint8_t MC6809::COM_REG(uint8_t r_com)
1502 inline void MC6809::LSR_MEM(uint8_t t)
1505 CC = CC | (t & CC_C);
1511 inline uint8_t MC6809::LSR_REG(uint8_t r)
1520 inline void MC6809::ROR_MEM(uint8_t t)
1523 r = (CC & CC_C) << 7;
1532 inline uint8_t MC6809::ROR_REG(uint8_t t)
1535 r = (CC & CC_C) << 7;
1545 inline void MC6809::ASR_MEM(uint8_t t)
1549 CC = CC | (t & CC_C);
1550 r = (t & 0x80) | (t >> 1);
1557 inline uint8_t MC6809::ASR_REG(uint8_t t)
1561 CC = CC | (t & CC_C);
1562 r = (t & 0x80) | (t >> 1);
1569 inline void MC6809::ASL_MEM(uint8_t t)
1572 tt = (uint16_t)t & 0x00ff;
1575 SET_FLAGS8(tt, tt, r);
1577 WM(EAD, (uint8_t)r);
1580 inline uint8_t MC6809::ASL_REG(uint8_t t)
1583 tt = (uint16_t)t & 0x00ff;
1586 SET_FLAGS8(tt, tt, r);
1591 inline void MC6809::ROL_MEM(uint8_t t)
1594 tt = (uint16_t)t & 0x00ff;
1595 r = (CC & CC_C) | (tt << 1);
1600 // if((r & 0x80) == 0)SEV;
1602 // if((r & 0x80) != 0) SEV;
1604 SET_FLAGS8(tt, tt, r);
1605 WM(EAD, (uint8_t)r);
1608 inline uint8_t MC6809::ROL_REG(uint8_t t)
1611 tt = (uint16_t)t & 0x00ff;
1612 r = (CC & CC_C) | (tt << 1);
1617 // if((r & 0x80) == 0) SEV;
1619 // if((r & 0x80) != 0) SEV;
1621 SET_FLAGS8(tt, tt, r);
1625 inline void MC6809::DEC_MEM(uint8_t t)
1634 inline uint8_t MC6809::DEC_REG(uint8_t t)
1643 inline void MC6809::DCC_MEM(uint8_t t)
1657 inline uint8_t MC6809::DCC_REG(uint8_t t)
1671 inline void MC6809::INC_MEM(uint8_t t)
1673 uint16_t tt = t + 1;
1679 inline uint8_t MC6809::INC_REG(uint8_t t)
1681 uint16_t tt = t + 1;
1687 inline void MC6809::TST_MEM(uint8_t t)
1693 inline uint8_t MC6809::TST_REG(uint8_t t)
1700 inline uint8_t MC6809::CLC_REG(uint8_t t)
1710 inline void MC6809::CLR_MEM(uint8_t t)
1717 inline uint8_t MC6809::CLR_REG(uint8_t t)
1724 inline uint8_t MC6809::SUB8_REG(uint8_t reg, uint8_t data)
1727 r = (uint16_t)reg - (uint16_t)data;
1730 SET_FLAGS8(reg, data, r);
1734 inline uint8_t MC6809::CMP8_REG(uint8_t reg, uint8_t data)
1737 r = (uint16_t)reg - (uint16_t)data;
1740 SET_FLAGS8(reg, data, r);
1744 inline uint8_t MC6809::SBC8_REG(uint8_t reg, uint8_t data)
1747 uint8_t cc_c = CC & CC_C;
1748 r = (uint16_t)reg - (uint16_t)data - (uint16_t)cc_c;
1750 SET_FLAGS8(reg, data + cc_c , r);
1754 inline uint8_t MC6809::AND8_REG(uint8_t reg, uint8_t data)
1763 inline uint8_t MC6809::BIT8_REG(uint8_t reg, uint8_t data)
1769 SET_V8(reg, data, r);
1773 inline uint8_t MC6809::EOR8_REG(uint8_t reg, uint8_t data)
1782 inline uint8_t MC6809::OR8_REG(uint8_t reg, uint8_t data)
1791 inline uint8_t MC6809::ADD8_REG(uint8_t reg, uint8_t data)
1794 t = (uint16_t) data;
1798 SET_HNZVC8(reg, t, r);
1802 inline uint8_t MC6809::ADC8_REG(uint8_t reg, uint8_t data)
1805 uint8_t c_cc = CC & CC_C;
1806 t = (uint16_t) data;
1810 SET_HNZVC8(reg, t + c_cc, r);
1814 inline uint8_t MC6809::LOAD8_REG(uint8_t reg)
1821 inline void MC6809::STORE8_REG(uint8_t reg)
1828 inline uint16_t MC6809::LOAD16_REG(uint16_t reg)
1836 inline uint16_t MC6809::SUB16_REG(uint16_t reg, uint16_t data)
1842 SET_FLAGS16(d, data, r);
1846 inline uint16_t MC6809::ADD16_REG(uint16_t reg, uint16_t data)
1850 r = d + (uint32_t)data;
1852 SET_HNZVC16(d, data, r);
1856 inline uint16_t MC6809::CMP16_REG(uint16_t reg, uint16_t data)
1862 SET_FLAGS16(d, data, r);
1866 inline void MC6809::STORE16_REG(pair_t *p)
1874 /* $00 NEG direct ?**** */
1875 OP_HANDLER(neg_di) {
1881 /* $01 Undefined Neg */
1882 /* $03 COM direct -**01 */
1883 OP_HANDLER(com_di) {
1889 /* $02 NGC Direct (Undefined) */
1890 OP_HANDLER(ngc_di) {
1891 if ((CC & CC_C) == 0) {
1900 /* $04 LSR direct -0*-* */
1901 OP_HANDLER(lsr_di) {
1909 /* $06 ROR direct -**-* */
1910 OP_HANDLER(ror_di) {
1916 /* $07 ASR direct ?**-* */
1917 OP_HANDLER(asr_di) {
1923 /* $08 ASL direct ?**** */
1924 OP_HANDLER(asl_di) {
1930 /* $09 ROL direct -**** */
1931 OP_HANDLER(rol_di) {
1937 /* $0A DEC direct -***- */
1938 OP_HANDLER(dec_di) {
1944 /* $0B DCC direct */
1945 OP_HANDLER(dcc_di) {
1952 /* $OC INC direct -***- */
1953 OP_HANDLER(inc_di) {
1959 /* $OD TST direct -**0- */
1960 OP_HANDLER(tst_di) {
1967 /* $0E JMP direct ----- */
1968 OP_HANDLER(jmp_di) {
1973 /* $0F CLR direct -0100 */
1974 OP_HANDLER(clr_di) {
1977 dummy = RM(EAD); // Dummy Read(Alpha etc...)
1985 /* $12 NOP inherent ----- */
1990 /* $13 SYNC inherent ----- */
1991 OP_HANDLER(sync_09) // Rename 20101110
1993 int_state |= MC6809_SYNC_IN;
1998 /* $14 trap(HALT) */
2000 int_state |= MC6809_INSN_HALT; // HALTフラグ
2002 emu->out_debug_log(_T("MC6809 : TRAP(HALT) @%04x %02x %02x\n"), PC - 1, RM(PC - 1), RM(PC));
2007 /* $16 LBRA relative ----- */
2012 /* $17 LBSR relative ----- */
2021 OP_HANDLER(aslcc_in) {
2023 if ((cc_r & CC_Z) != 0x00) { //20100824 Fix
2031 /* $19 DAA inherent (A) -**0* */
2037 if (lsn > 0x09 || CC & CC_H)
2039 if (msn > 0x80 && lsn > 0x09)
2041 if (msn > 0x90 || CC & CC_C)
2044 CLR_NZV; /* keep carry from previous operation */
2045 SET_NZ8((uint8_t) t);
2051 /* $1A ORCC immediate ##### */
2061 /* $1C ANDCC immediate ##### */
2066 // check_irq_lines(); /* HJB 990116 */
2069 /* $1D SEX inherent -**-- */
2073 D = t; // Endian OK?
2074 // CLR_NZV; Tim Lindner 20020905: verified that V flag is not affected
2079 /* $1E EXG inherent ----- */// 20100825
2087 * 20111011: 16bit vs 16Bitの演算にする(XM7/ cpu_x86.asmより
2090 switch ((tb >> 4) & 15) {
2169 switch ((tb >> 4) & 15) {
2184 int_state |= MC6809_LDS;
2217 int_state |= MC6809_LDS;
2237 /* $1F TFR inherent ----- */
2244 * 20111011: 16bit vs 16Bitの演算にする(XM7/ cpu_x86.asmより)
2247 switch ((tb >> 4) & 15) {
2302 int_state |= MC6809_LDS;
2322 /* $20 BRA relative ----- */
2327 /* $21 BRN relative ----- */
2332 /* $1021 LBRN relative ----- */
2337 /* $22 BHI relative ----- */
2339 BRANCH(((CC & (CC_Z | CC_C)) == 0));
2342 /* $1022 LBHI relative ----- */
2344 LBRANCH(((CC & (CC_Z | CC_C)) == 0));
2347 /* $23 BLS relative ----- */
2349 BRANCH(((CC & (CC_Z | CC_C)) != 0));
2352 /* $1023 LBLS relative ----- */
2354 LBRANCH(((CC & (CC_Z | CC_C)) != 0));
2355 //LBRANCH((CC & (CC_Z | CC_C)));
2358 /* $24 BCC relative ----- */
2360 BRANCH((CC & CC_C) == 0);
2363 /* $1024 LBCC relative ----- */
2365 LBRANCH((CC & CC_C) == 0);
2368 /* $25 BCS relative ----- */
2370 BRANCH((CC & CC_C) != 0);
2373 /* $1025 LBCS relative ----- */
2375 LBRANCH((CC & CC_C) != 0);
2378 /* $26 BNE relative ----- */
2380 BRANCH((CC & CC_Z) == 0);
2383 /* $1026 LBNE relative ----- */
2385 LBRANCH((CC & CC_Z) == 0);
2388 /* $27 BEQ relative ----- */
2390 BRANCH((CC & CC_Z) != 0);
2393 /* $1027 LBEQ relative ----- */
2395 LBRANCH((CC & CC_Z) != 0);
2398 /* $28 BVC relative ----- */
2400 BRANCH((CC & CC_V) == 0);
2403 /* $1028 LBVC relative ----- */
2405 LBRANCH((CC & CC_V) == 0);
2408 /* $29 BVS relative ----- */
2410 BRANCH((CC & CC_V) != 0);
2413 /* $1029 LBVS relative ----- */
2415 LBRANCH((CC & CC_V) != 0);
2418 /* $2A BPL relative ----- */
2420 BRANCH((CC & CC_N) == 0);
2423 /* $102A LBPL relative ----- */
2425 LBRANCH((CC & CC_N) == 0);
2428 /* $2B BMI relative ----- */
2430 BRANCH((CC & CC_N) != 0);
2433 /* $102B LBMI relative ----- */
2435 LBRANCH((CC & CC_N) != 0);
2438 /* $2C BGE relative ----- */
2443 /* $102C LBGE relative ----- */
2448 /* $2D BLT relative ----- */
2453 /* $102D LBLT relative ----- */
2458 /* $2E BGT relative ----- */
2460 BRANCH(!(NXORV || (CC & CC_Z)));
2463 /* $102E LBGT relative ----- */
2465 LBRANCH(!(NXORV || (CC & CC_Z)));
2468 /* $2F BLE relative ----- */
2470 BRANCH((NXORV || (CC & CC_Z)));
2473 /* $102F LBLE relative ----- */
2475 LBRANCH((NXORV || (CC & CC_Z)));
2478 /* $30 LEAX indexed --*-- */
2480 fetch_effective_address();
2486 /* $31 LEAY indexed --*-- */
2488 fetch_effective_address();
2494 /* $32 LEAS indexed ----- */
2496 fetch_effective_address();
2498 int_state |= MC6809_LDS;
2501 /* $33 LEAU indexed ----- */
2503 fetch_effective_address();
2507 /* $34 PSHS inherent ----- */
2511 dmy = RM(S); // Add 20100825
2546 /* 35 PULS inherent ----- */
2582 dmy = RM(S); // Add 20100825
2584 /* HJB 990225: moved check after all PULLs */
2585 // if( t&0x01 ) { check_irq_lines(); }
2588 /* $36 PSHU inherent ----- */
2592 dmy = RM(U); // Add 20100825
2627 /* 37 PULU inherent ----- */
2663 dmy = RM(U); // Add 20100825
2665 /* HJB 990225: moved check after all PULLs */
2666 //if( t&0x01 ) { check_irq_lines(); }
2671 /* $39 RTS inherent ----- */
2673 //printf("RTS: Before PC=%04x", pPC.w.l);
2675 //printf(" After PC=%04x\n", pPC.w.l);
2678 /* $3A ABX inherent ----- */
2686 /* $3B RTI inherent ##### */
2689 // t = CC & CC_E; /* HJB 990225: entire state saved? */
2690 if ((CC & CC_E) != 0) { // NMIIRQ
2700 // check_irq_lines(); /* HJB 990116 */
2703 /* $3C CWAI inherent ----1 */
2708 CC |= CC_E; /* HJB 990225: save entire state */
2718 int_state = int_state | MC6809_CWAI_IN;
2719 int_state &= ~MC6809_CWAI_OUT; // 0xfeff
2723 /* $3D MUL inherent --*-@ */
2733 if (t.b.l & 0x80) SEC;
2744 /* $3F SWI (SWI2 SWI3) absolute indirect ----- */
2746 CC |= CC_E; /* HJB 980225: save entire state */
2755 CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
2756 pPC = RM16_PAIR(0xfffa);
2759 /* $103F SWI2 absolute indirect ----- */
2761 CC |= CC_E; /* HJB 980225: save entire state */
2770 pPC = RM16_PAIR(0xfff4);
2773 /* $113F SWI3 absolute indirect ----- */
2775 CC |= CC_E; /* HJB 980225: save entire state */
2784 pPC = RM16_PAIR(0xfff2);
2787 /* $40 NEGA inherent ?**** */
2795 /* $43 COMA inherent -**01 */
2802 if ((CC & CC_C) == 0) {
2809 /* $44 LSRA inherent -0*-* */
2816 /* $46 RORA inherent -**-* */
2821 /* $47 ASRA inherent ?**-* */
2826 /* $48 ASLA inherent ?**** */
2831 /* $49 ROLA inherent -**** */
2836 /* $4A DECA inherent -***- */
2847 /* $4C INCA inherent -***- */
2852 /* $4D TSTA inherent -**0- */
2862 /* $4F CLRA inherent -0100 */
2867 /* $50 NEGB inherent ?**** */
2876 /* $53 COMB inherent -**01 */
2883 if ((CC & CC_C) == 0) {
2890 /* $54 LSRB inherent -0*-* */
2897 /* $56 RORB inherent -**-* */
2902 /* $57 ASRB inherent ?**-* */
2907 /* $58 ASLB inherent ?**** */
2912 /* $59 ROLB inherent -**** */
2917 /* $5A DECB inherent -***- */
2927 /* $5C INCB inherent -***- */
2932 /* $5D TSTB inherent -**0- */
2942 /* $5F CLRB inherent -0100 */
2947 /* $60 NEG indexed ?**** */
2948 OP_HANDLER(neg_ix) {
2950 t = GET_INDEXED_DATA();
2957 /* $63 COM indexed -**01 */
2958 OP_HANDLER(com_ix) {
2960 t = GET_INDEXED_DATA();
2965 OP_HANDLER(ngc_ix) {
2966 if ((CC & CC_C) == 0) {
2973 /* $64 LSR indexed -0*-* */
2974 OP_HANDLER(lsr_ix) {
2976 t = GET_INDEXED_DATA();
2982 /* $66 ROR indexed -**-* */
2983 OP_HANDLER(ror_ix) {
2985 t = GET_INDEXED_DATA();
2989 /* $67 ASR indexed ?**-* */
2990 OP_HANDLER(asr_ix) {
2992 t = GET_INDEXED_DATA();
2996 /* $68 ASL indexed ?**** */
2997 OP_HANDLER(asl_ix) {
2999 t = GET_INDEXED_DATA();
3003 /* $69 ROL indexed -**** */
3004 OP_HANDLER(rol_ix) {
3006 t = GET_INDEXED_DATA();
3010 /* $6A DEC indexed -***- */
3011 OP_HANDLER(dec_ix) {
3013 t = GET_INDEXED_DATA();
3018 OP_HANDLER(dcc_ix) {
3020 t = GET_INDEXED_DATA();
3024 /* $6C INC indexed -***- */
3025 OP_HANDLER(inc_ix) {
3027 t = GET_INDEXED_DATA();
3031 /* $6D TST indexed -**0- */
3032 OP_HANDLER(tst_ix) {
3034 t = GET_INDEXED_DATA();
3038 /* $6E JMP indexed ----- */
3039 OP_HANDLER(jmp_ix) {
3040 fetch_effective_address();
3044 /* $6F CLR indexed -0100 */
3045 OP_HANDLER(clr_ix) {
3047 t = GET_INDEXED_DATA();
3048 dummy = RM(EAD); // Dummy Read(Alpha etc...)
3052 /* $70 NEG extended ?**** */
3053 OP_HANDLER(neg_ex) {
3060 /* $73 COM extended -**01 */
3061 OP_HANDLER(com_ex) {
3067 /* $72 NGC extended */
3068 OP_HANDLER(ngc_ex) {
3069 if ((CC & CC_C) == 0) {
3076 /* $74 LSR extended -0*-* */
3077 OP_HANDLER(lsr_ex) {
3085 /* $76 ROR extended -**-* */
3086 OP_HANDLER(ror_ex) {
3092 /* $77 ASR extended ?**-* */
3093 OP_HANDLER(asr_ex) {
3099 /* $78 ASL extended ?**** */
3100 OP_HANDLER(asl_ex) {
3106 /* $79 ROL extended -**** */
3107 OP_HANDLER(rol_ex) {
3113 /* $7A DEC extended -***- */
3114 OP_HANDLER(dec_ex) {
3122 OP_HANDLER(dcc_ex) {
3128 /* $7C INC extended -***- */
3129 OP_HANDLER(inc_ex) {
3135 /* $7D TST extended -**0- */
3136 OP_HANDLER(tst_ex) {
3142 /* $7E JMP extended ----- */
3143 OP_HANDLER(jmp_ex) {
3148 /* $7F CLR extended -0100 */
3149 OP_HANDLER(clr_ex) {
3156 /* $80 SUBA immediate ?**** */
3157 OP_HANDLER(suba_im) {
3163 /* $81 CMPA immediate ?**** */
3164 OP_HANDLER(cmpa_im) {
3170 /* $82 SBCA immediate ?**** */
3171 OP_HANDLER(sbca_im) {
3177 /* $83 SUBD (CMPD CMPU) immediate -**** */
3178 OP_HANDLER(subd_im) {
3181 D = SUB16_REG(D, b.w.l);
3184 /* $1083 CMPD immediate -**** */
3185 OP_HANDLER(cmpd_im) {
3188 D = CMP16_REG(D, b.w.l);
3191 /* $1183 CMPU immediate -**** */
3192 OP_HANDLER(cmpu_im) {
3195 U = CMP16_REG(U, b.w.l);
3198 /* $84 ANDA immediate -**0- */
3199 OP_HANDLER(anda_im) {
3205 /* $85 BITA immediate -**0- */
3206 OP_HANDLER(bita_im) {
3212 /* $86 LDA immediate -**0- */
3213 OP_HANDLER(lda_im) {
3218 /* is this a legal instruction? */
3219 /* $87 STA immediate -**0- */
3220 OP_HANDLER(sta_im) {
3230 OP_HANDLER(flag8_im) {
3239 /* $88 EORA immediate -**0- */
3240 OP_HANDLER(eora_im) {
3246 /* $89 ADCA immediate ***** */
3247 OP_HANDLER(adca_im) {
3253 /* $8A ORA immediate -**0- */
3254 OP_HANDLER(ora_im) {
3260 /* $8B ADDA immediate ***** */
3261 OP_HANDLER(adda_im) {
3267 /* $8C CMPX (CMPY CMPS) immediate -**** */
3268 OP_HANDLER(cmpx_im) {
3271 X = CMP16_REG(X, b.w.l);
3274 /* $108C CMPY immediate -**** */
3275 OP_HANDLER(cmpy_im) {
3278 Y = CMP16_REG(Y, b.w.l);
3281 /* $118C CMPS immediate -**** */
3282 OP_HANDLER(cmps_im) {
3285 S = CMP16_REG(S, b.w.l);
3296 /* $8E LDX (LDY) immediate -**0- */
3297 OP_HANDLER(ldx_im) {
3302 /* $108E LDY immediate -**0- */
3303 OP_HANDLER(ldy_im) {
3308 /* is this a legal instruction? */
3309 /* $8F STX (STY) immediate -**0- */
3310 OP_HANDLER(stx_im) {
3320 OP_HANDLER(flag16_im) {
3328 /* is this a legal instruction? */
3329 /* $108F STY immediate -**0- */
3330 OP_HANDLER(sty_im) {
3337 /* $90 SUBA direct ?**** */
3338 OP_HANDLER(suba_di) {
3344 /* $91 CMPA direct ?**** */
3345 OP_HANDLER(cmpa_di) {
3351 /* $92 SBCA direct ?**** */
3352 OP_HANDLER(sbca_di) {
3358 /* $93 SUBD (CMPD CMPU) direct -**** */
3359 OP_HANDLER(subd_di) {
3362 D = SUB16_REG(D, b.w.l);
3365 /* $1093 CMPD direct -**** */
3366 OP_HANDLER(cmpd_di) {
3369 D = CMP16_REG(D, b.w.l);
3372 /* $1193 CMPU direct -**** */
3373 OP_HANDLER(cmpu_di) {
3376 U = CMP16_REG(U, b.w.l);
3379 /* $94 ANDA direct -**0- */
3380 OP_HANDLER(anda_di) {
3386 /* $95 BITA direct -**0- */
3387 OP_HANDLER(bita_di) {
3393 /* $96 LDA direct -**0- */
3394 OP_HANDLER(lda_di) {
3399 /* $97 STA direct -**0- */
3400 OP_HANDLER(sta_di) {
3405 /* $98 EORA direct -**0- */
3406 OP_HANDLER(eora_di) {
3412 /* $99 ADCA direct ***** */
3413 OP_HANDLER(adca_di) {
3419 /* $9A ORA direct -**0- */
3420 OP_HANDLER(ora_di) {
3426 /* $9B ADDA direct ***** */
3427 OP_HANDLER(adda_di) {
3433 /* $9C CMPX (CMPY CMPS) direct -**** */
3434 OP_HANDLER(cmpx_di) {
3437 X = CMP16_REG(X, b.w.l);
3440 /* $109C CMPY direct -**** */
3441 OP_HANDLER(cmpy_di) {
3444 Y = CMP16_REG(Y, b.w.l);
3447 /* $119C CMPS direct -**** */
3448 OP_HANDLER(cmps_di) {
3451 S = CMP16_REG(S, b.w.l);
3454 /* $9D JSR direct ----- */
3455 OP_HANDLER(jsr_di) {
3461 /* $9E LDX (LDY) direct -**0- */
3462 OP_HANDLER(ldx_di) {
3467 /* $109E LDY direct -**0- */
3468 OP_HANDLER(ldy_di) {
3473 /* $9F STX (STY) direct -**0- */
3474 OP_HANDLER(stx_di) {
3479 /* $109F STY direct -**0- */
3480 OP_HANDLER(sty_di) {
3485 /* $a0 SUBA indexed ?**** */
3486 OP_HANDLER(suba_ix) {
3488 t = GET_INDEXED_DATA();
3492 /* $a1 CMPA indexed ?**** */
3493 OP_HANDLER(cmpa_ix) {
3495 t = GET_INDEXED_DATA();
3499 /* $a2 SBCA indexed ?**** */
3500 OP_HANDLER(sbca_ix) {
3502 t = GET_INDEXED_DATA();
3506 /* $a3 SUBD (CMPD CMPU) indexed -**** */
3507 OP_HANDLER(subd_ix) {
3509 b = GET_INDEXED_DATA16();
3510 D = SUB16_REG(D, b.w.l);
3513 /* $10a3 CMPD indexed -**** */
3514 OP_HANDLER(cmpd_ix) {
3516 b = GET_INDEXED_DATA16();
3517 D = CMP16_REG(D, b.w.l);
3520 /* $11a3 CMPU indexed -**** */
3521 OP_HANDLER(cmpu_ix) {
3523 b = GET_INDEXED_DATA16();
3524 U = CMP16_REG(U, b.w.l);
3527 /* $a4 ANDA indexed -**0- */
3528 OP_HANDLER(anda_ix) {
3530 t = GET_INDEXED_DATA();
3534 /* $a5 BITA indexed -**0- */
3535 OP_HANDLER(bita_ix) {
3537 t = GET_INDEXED_DATA();
3541 /* $a6 LDA indexed -**0- */
3542 OP_HANDLER(lda_ix) {
3543 A = GET_INDEXED_DATA();
3547 /* $a7 STA indexed -**0- */
3548 OP_HANDLER(sta_ix) {
3549 fetch_effective_address();
3553 /* $a8 EORA indexed -**0- */
3554 OP_HANDLER(eora_ix) {
3556 t = GET_INDEXED_DATA();
3560 /* $a9 ADCA indexed ***** */
3561 OP_HANDLER(adca_ix) {
3563 t = GET_INDEXED_DATA();
3567 /* $aA ORA indexed -**0- */
3568 OP_HANDLER(ora_ix) {
3570 t = GET_INDEXED_DATA();
3574 /* $aB ADDA indexed ***** */
3575 OP_HANDLER(adda_ix) {
3577 t = GET_INDEXED_DATA();
3581 /* $aC CMPX (CMPY CMPS) indexed -**** */
3582 OP_HANDLER(cmpx_ix) {
3584 b = GET_INDEXED_DATA16();
3585 X = CMP16_REG(X, b.w.l);
3588 /* $10aC CMPY indexed -**** */
3589 OP_HANDLER(cmpy_ix) {
3591 b = GET_INDEXED_DATA16();
3592 Y = CMP16_REG(Y, b.w.l);
3595 /* $11aC CMPS indexed -**** */
3596 OP_HANDLER(cmps_ix) {
3598 b = GET_INDEXED_DATA16();
3599 S = CMP16_REG(S, b.w.l);
3602 /* $aD JSR indexed ----- */
3603 OP_HANDLER(jsr_ix) {
3604 fetch_effective_address();
3609 /* $aE LDX (LDY) indexed -**0- */
3610 OP_HANDLER(ldx_ix) {
3612 t = GET_INDEXED_DATA16();
3617 /* $10aE LDY indexed -**0- */
3618 OP_HANDLER(ldy_ix) {
3620 t = GET_INDEXED_DATA16();
3625 /* $aF STX (STY) indexed -**0- */
3626 OP_HANDLER(stx_ix) {
3627 fetch_effective_address();
3631 /* $10aF STY indexed -**0- */
3632 OP_HANDLER(sty_ix) {
3633 fetch_effective_address();
3637 /* $b0 SUBA extended ?**** */
3638 OP_HANDLER(suba_ex) {
3644 /* $b1 CMPA extended ?**** */
3645 OP_HANDLER(cmpa_ex) {
3651 /* $b2 SBCA extended ?**** */
3652 OP_HANDLER(sbca_ex) {
3658 /* $b3 SUBD (CMPD CMPU) extended -**** */
3659 OP_HANDLER(subd_ex) {
3662 D = SUB16_REG(D, b.w.l);
3665 /* $10b3 CMPD extended -**** */
3666 OP_HANDLER(cmpd_ex) {
3669 D = CMP16_REG(D, b.w.l);
3672 /* $11b3 CMPU extended -**** */
3673 OP_HANDLER(cmpu_ex) {
3676 U = CMP16_REG(U, b.w.l);
3679 /* $b4 ANDA extended -**0- */
3680 OP_HANDLER(anda_ex) {
3686 /* $b5 BITA extended -**0- */
3687 OP_HANDLER(bita_ex) {
3693 /* $b6 LDA extended -**0- */
3694 OP_HANDLER(lda_ex) {
3699 /* $b7 STA extended -**0- */
3700 OP_HANDLER(sta_ex) {
3705 /* $b8 EORA extended -**0- */
3706 OP_HANDLER(eora_ex) {
3712 /* $b9 ADCA extended ***** */
3713 OP_HANDLER(adca_ex) {
3719 /* $bA ORA extended -**0- */
3720 OP_HANDLER(ora_ex) {
3726 /* $bB ADDA extended ***** */
3727 OP_HANDLER(adda_ex) {
3733 /* $bC CMPX (CMPY CMPS) extended -**** */
3734 OP_HANDLER(cmpx_ex) {
3737 X = CMP16_REG(X, b.w.l);
3740 /* $10bC CMPY extended -**** */
3741 OP_HANDLER(cmpy_ex) {
3744 Y = CMP16_REG(Y, b.w.l);
3747 /* $11bC CMPS extended -**** */
3748 OP_HANDLER(cmps_ex) {
3751 S = CMP16_REG(S, b.w.l);
3754 /* $bD JSR extended ----- */
3755 OP_HANDLER(jsr_ex) {
3761 /* $bE LDX (LDY) extended -**0- */
3762 OP_HANDLER(ldx_ex) {
3767 /* $10bE LDY extended -**0- */
3768 OP_HANDLER(ldy_ex) {
3773 /* $bF STX (STY) extended -**0- */
3774 OP_HANDLER(stx_ex) {
3779 /* $10bF STY extended -**0- */
3780 OP_HANDLER(sty_ex) {
3785 /* $c0 SUBB immediate ?**** */
3786 OP_HANDLER(subb_im) {
3792 /* $c1 CMPB immediate ?**** */
3793 OP_HANDLER(cmpb_im) {
3799 /* $c2 SBCB immediate ?**** */
3800 OP_HANDLER(sbcb_im) {
3806 /* $c3 ADDD immediate -**** */
3807 OP_HANDLER(addd_im) {
3810 D = ADD16_REG(D, b.w.l);
3813 /* $c4 ANDB immediate -**0- */
3814 OP_HANDLER(andb_im) {
3820 /* $c5 BITB immediate -**0- */
3821 OP_HANDLER(bitb_im) {
3827 /* $c6 LDB immediate -**0- */
3828 OP_HANDLER(ldb_im) {
3833 /* is this a legal instruction? */
3834 /* $c7 STB immediate -**0- */
3835 OP_HANDLER(stb_im) {
3842 /* $c8 EORB immediate -**0- */
3843 OP_HANDLER(eorb_im) {
3849 /* $c9 ADCB immediate ***** */
3850 OP_HANDLER(adcb_im) {
3856 /* $cA ORB immediate -**0- */
3857 OP_HANDLER(orb_im) {
3863 /* $cB ADDB immediate ***** */
3864 OP_HANDLER(addb_im) {
3870 /* $cC LDD immediate -**0- */
3871 OP_HANDLER(ldd_im) {
3876 /* is this a legal instruction? */
3877 /* $cD STD immediate -**0- */
3878 OP_HANDLER(std_im) {
3885 /* $cE LDU (LDS) immediate -**0- */
3886 OP_HANDLER(ldu_im) {
3891 /* $10cE LDS immediate -**0- */
3892 OP_HANDLER(lds_im) {
3895 int_state |= MC6809_LDS;
3898 /* is this a legal instruction? */
3899 /* $cF STU (STS) immediate -**0- */
3900 OP_HANDLER(stu_im) {
3907 /* is this a legal instruction? */
3908 /* $10cF STS immediate -**0- */
3909 OP_HANDLER(sts_im) {
3916 /* $d0 SUBB direct ?**** */
3917 OP_HANDLER(subb_di) {
3922 /* $d1 CMPB direct ?**** */
3923 OP_HANDLER(cmpb_di) {
3929 /* $d2 SBCB direct ?**** */
3930 OP_HANDLER(sbcb_di) {
3936 /* $d3 ADDD direct -**** */
3937 OP_HANDLER(addd_di) {
3940 D = ADD16_REG(D, b.w.l);
3943 /* $d4 ANDB direct -**0- */
3944 OP_HANDLER(andb_di) {
3950 /* $d5 BITB direct -**0- */
3951 OP_HANDLER(bitb_di) {
3957 /* $d6 LDB direct -**0- */
3958 OP_HANDLER(ldb_di) {
3963 /* $d7 STB direct -**0- */
3964 OP_HANDLER(stb_di) {
3969 /* $d8 EORB direct -**0- */
3970 OP_HANDLER(eorb_di) {
3976 /* $d9 ADCB direct ***** */
3977 OP_HANDLER(adcb_di) {
3983 /* $dA ORB direct -**0- */
3984 OP_HANDLER(orb_di) {
3990 /* $dB ADDB direct ***** */
3991 OP_HANDLER(addb_di) {
3997 /* $dC LDD direct -**0- */
3998 OP_HANDLER(ldd_di) {
4003 /* $dD STD direct -**0- */
4004 OP_HANDLER(std_di) {
4009 /* $dE LDU (LDS) direct -**0- */
4010 OP_HANDLER(ldu_di) {
4015 /* $10dE LDS direct -**0- */
4016 OP_HANDLER(lds_di) {
4019 int_state |= MC6809_LDS;
4022 /* $dF STU (STS) direct -**0- */
4023 OP_HANDLER(stu_di) {
4028 /* $10dF STS direct -**0- */
4029 OP_HANDLER(sts_di) {
4034 /* $e0 SUBB indexed ?**** */
4035 OP_HANDLER(subb_ix) {
4037 t = GET_INDEXED_DATA();
4041 /* $e1 CMPB indexed ?**** */
4042 OP_HANDLER(cmpb_ix) {
4044 t = GET_INDEXED_DATA();
4048 /* $e2 SBCB indexed ?**** */
4049 OP_HANDLER(sbcb_ix) {
4051 t = GET_INDEXED_DATA();
4055 /* $e3 ADDD indexed -**** */
4056 OP_HANDLER(addd_ix) {
4058 b = GET_INDEXED_DATA16();
4059 D = ADD16_REG(D, b.w.l);
4062 /* $e4 ANDB indexed -**0- */
4063 OP_HANDLER(andb_ix) {
4065 t = GET_INDEXED_DATA();
4069 /* $e5 BITB indexed -**0- */
4070 OP_HANDLER(bitb_ix) {
4072 t = GET_INDEXED_DATA();
4076 /* $e6 LDB indexed -**0- */
4077 OP_HANDLER(ldb_ix) {
4078 B = GET_INDEXED_DATA();
4082 /* $e7 STB indexed -**0- */
4083 OP_HANDLER(stb_ix) {
4084 fetch_effective_address();
4088 /* $e8 EORB indexed -**0- */
4089 OP_HANDLER(eorb_ix) {
4091 t = GET_INDEXED_DATA();
4095 /* $e9 ADCB indexed ***** */
4096 OP_HANDLER(adcb_ix) {
4098 t = GET_INDEXED_DATA();
4102 /* $eA ORB indexed -**0- */
4103 OP_HANDLER(orb_ix) {
4105 t = GET_INDEXED_DATA();
4109 /* $eB ADDB indexed ***** */
4110 OP_HANDLER(addb_ix) {
4112 t = GET_INDEXED_DATA();
4116 /* $eC LDD indexed -**0- */
4117 OP_HANDLER(ldd_ix) {
4119 t = GET_INDEXED_DATA16();
4124 /* $eD STD indexed -**0- */
4125 OP_HANDLER(std_ix) {
4126 fetch_effective_address();
4130 /* $eE LDU (LDS) indexed -**0- */
4131 OP_HANDLER(ldu_ix) {
4133 t = GET_INDEXED_DATA16();
4138 /* $10eE LDS indexed -**0- */
4139 OP_HANDLER(lds_ix) {
4141 t = GET_INDEXED_DATA16();
4144 int_state |= MC6809_LDS;
4147 /* $eF STU (STS) indexed -**0- */
4148 OP_HANDLER(stu_ix) {
4149 fetch_effective_address();
4153 /* $10eF STS indexed -**0- */
4154 OP_HANDLER(sts_ix) {
4155 fetch_effective_address();
4159 /* $f0 SUBB extended ?**** */
4160 OP_HANDLER(subb_ex) {
4166 /* $f1 CMPB extended ?**** */
4167 OP_HANDLER(cmpb_ex) {
4173 /* $f2 SBCB extended ?**** */
4174 OP_HANDLER(sbcb_ex) {
4180 /* $f3 ADDD extended -**** */
4181 OP_HANDLER(addd_ex) {
4184 D = ADD16_REG(D, b.w.l);
4187 /* $f4 ANDB extended -**0- */
4188 OP_HANDLER(andb_ex) {
4194 /* $f5 BITB extended -**0- */
4195 OP_HANDLER(bitb_ex) {
4201 /* $f6 LDB extended -**0- */
4202 OP_HANDLER(ldb_ex) {
4207 /* $f7 STB extended -**0- */
4208 OP_HANDLER(stb_ex) {
4213 /* $f8 EORB extended -**0- */
4214 OP_HANDLER(eorb_ex) {
4220 /* $f9 ADCB extended ***** */
4221 OP_HANDLER(adcb_ex) {
4227 /* $fA ORB extended -**0- */
4228 OP_HANDLER(orb_ex) {
4234 /* $fB ADDB extended ***** */
4235 OP_HANDLER(addb_ex) {
4241 /* $fC LDD extended -**0- */
4242 OP_HANDLER(ldd_ex) {
4247 /* $fD STD extended -**0- */
4248 OP_HANDLER(std_ex) {
4253 /* $fE LDU (LDS) extended -**0- */
4254 OP_HANDLER(ldu_ex) {
4259 /* $10fE LDS extended -**0- */
4260 OP_HANDLER(lds_ex) {
4263 int_state |= MC6809_LDS;
4266 /* $fF STU (STS) extended -**0- */
4267 OP_HANDLER(stu_ex) {
4272 /* $10fF STS extended -**0- */
4273 OP_HANDLER(sts_ex) {
4280 OP_HANDLER(pref10) {
4281 uint8_t ireg2 = ROP_ARG(PCD);
4368 // case 0x8f: flag16_im();->cycle=4; break; // 20130417
4421 // case 0xcf: flag16_im();->cycle=4; break;
4454 OP_HANDLER(pref11) {
4455 uint8_t ireg2 = ROP_ARG(PCD);
4506 #define STATE_VERSION 1
4508 void MC6809::save_state(FILEIO* state_fio)
4510 state_fio->FputUint32(STATE_VERSION);
4511 state_fio->FputInt32(this_device_id);
4513 state_fio->FputInt32(icount);
4514 state_fio->FputInt32(extra_icount);
4515 state_fio->FputUint32(int_state);
4517 state_fio->FputUint32(pc.d);
4518 state_fio->FputUint32(ppc.d);
4519 state_fio->FputUint32(acc.d);
4520 state_fio->FputUint32(dp.d);
4521 state_fio->FputUint32(u.d);
4522 state_fio->FputUint32(s.d);
4523 state_fio->FputUint32(x.d);
4524 state_fio->FputUint32(y.d);
4525 state_fio->FputUint8(cc);
4526 state_fio->FputUint32(ea.d);
4529 bool MC6809::load_state(FILEIO* state_fio)
4531 if(state_fio->FgetUint32() != STATE_VERSION) {
4534 if(state_fio->FgetInt32() != this_device_id) {
4538 icount = state_fio->FgetInt32();
4539 extra_icount = state_fio->FgetInt32();
4540 int_state = state_fio->FgetUint32();
4541 pc.d = state_fio->FgetUint32();
4542 ppc.d = state_fio->FgetUint32();
4543 acc.d = state_fio->FgetUint32();
4544 dp.d = state_fio->FgetUint32();
4545 u.d = state_fio->FgetUint32();
4546 s.d = state_fio->FgetUint32();
4547 x.d = state_fio->FgetUint32();
4548 y.d = state_fio->FgetUint32();
4549 cc = state_fio->FgetUint8();
4550 ea.d = state_fio->FgetUint32();