2 Skelton for retropc emulator
5 Author : Takeda.Toshiya
9 Notes from K.Ohta <whatisthis.sowhat _at_ gmail.com> at Jan 16, 2015:
10 All of undocumented instructions (i.e. ngc, flag16) of MC6809(not HD6309) are written by me.
11 These behaviors of undocumented insns are refered from "vm/cpu_x86.asm" (ia32 assembly codefor nasm) within XM7
12 written by Ryu Takegami , and older article wrote in magazine, "I/O" at 1985.
13 But, these C implements are written from scratch by me , and I tested many years at XM7/SDL.
14 Perhaps, these insns. are not implement MAME/MESS yet.
17 // Fixed IRQ/FIRQ by Mr.Sasaji at 2011.06.17
20 #include "mc6809_consts.h"
52 /****************************************************************************/
54 /****************************************************************************/
57 #define RM(Addr) d_mem->read_data8(Addr)
58 #define WM(Addr,Value) d_mem->write_data8(Addr, Value)
60 #define ROP(Addr) d_mem->read_data8(Addr)
61 #define ROP_ARG(Addr) d_mem->read_data8(Addr)
63 /* macros to access memory */
64 #define IMMBYTE(b) b = ROP_ARG(PCD); PC++
65 #define IMMWORD(w) w.d = (ROP_ARG(PCD) << 8) | ROP_ARG((PCD + 1) & 0xffff); PC += 2
67 #define PUSHBYTE(b) --S; WM(SD,b)
68 #define PUSHWORD(w) --S; WM(SD, w.b.l); --S; WM(SD, w.b.h)
69 #define PULLBYTE(b) b = RM(SD); S++
70 #define PULLWORD(w) w = RM(SD) << 8; S++; w |= RM(SD); S++
72 #define PSHUBYTE(b) --U; WM(UD, b);
73 #define PSHUWORD(w) --U; WM(UD, w.b.l); --U; WM(UD, w.b.h)
74 #define PULUBYTE(b) b = RM(UD); U++
75 #define PULUWORD(w) w = RM(UD) << 8; U++; w |= RM(UD); U++
77 #define CLR_HNZVC CC &= ~(CC_H | CC_N | CC_Z | CC_V | CC_C)
78 #define CLR_NZV CC &= ~(CC_N | CC_Z | CC_V)
79 #define CLR_NZ CC &= ~(CC_N | CC_Z)
80 #define CLR_HNZC CC &= ~(CC_H | CC_N | CC_Z | CC_C)
81 #define CLR_NZVC CC &= ~(CC_N | CC_Z | CC_V | CC_C)
82 #define CLR_Z CC &= ~(CC_Z)
83 #define CLR_NZC CC &= ~(CC_N | CC_Z | CC_C)
84 #define CLR_ZC CC &= ~(CC_Z | CC_C)
86 /* macros for CC -- CC bits affected should be reset before calling */
87 #define SET_Z(a) if(a == 0) SEZ
88 #define SET_Z8(a) SET_Z((uint8)a)
89 #define SET_Z16(a) SET_Z((uint16)a)
90 //#define SET_N8(a) CC |= ((a & 0x80) >> 4)
91 //#define SET_N16(a) CC |= ((a & 0x8000) >> 12)
92 //#define SET_H(a,b,r) CC |= (((a ^ b ^ r) & 0x10) << 1)
93 #define SET_N8(a) if(a & 0x80)CC|=CC_N
94 #define SET_N16(a) if(a & 0x8000)CC|=CC_N
95 #define SET_H(a,b,r) if((a^b^r)&0x10)CC|=CC_H
97 #define SET_C8(a) if(a&0x0100)CC|=CC_C
98 #define SET_C16(a) if(a&0x010000)CC|=CC_C
99 #define SET_V8(a,b,r) if((a^b^r^(r>>1))&0x80)CC|=CC_V
100 #define SET_V16(a,b,r) if((a^b^r^(r>>1))&0x8000)CC|=CC_V
102 #define SET_FLAGS8I(a) {CC |= flags8i[a & 0xff];}
103 #define SET_FLAGS8D(a) {CC |= flags8d[a & 0xff];}
106 #define SET_NZ8(a) {SET_N8(a); SET_Z(a);}
107 #define SET_NZ16(a) {SET_N16(a); SET_Z(a);}
108 #define SET_FLAGS8(a,b,r) {SET_N8(r); SET_Z8(r); SET_V8(a, b, r); SET_C8(r);}
109 #define SET_FLAGS16(a,b,r) {SET_N16(r); SET_Z16(r); SET_V16(a, b, r); SET_C16(r);}
110 #define SET_HNZVC8(a,b,r) {SET_H(a,b,r);SET_N8(r);SET_Z8(r);SET_V8(a,b,r);SET_C8(r);}
111 #define SET_HNZVC16(a,b,r) {SET_H(a,b,r);SET_N16(r);SET_Z16(r);SET_V16(a,b,r);SET_C16(r);}
113 //#define NXORV ((CC & CC_N) ^ ((CC & CC_V) << 2))
114 #define NXORV (((CC&CC_N)^((CC&CC_V)<<2)) !=0)
116 /* for treating an unsigned byte as a signed word */
117 #define SIGNED(b) ((uint16)((b & 0x80) ? (b | 0xff00) : b))
119 /* macros for addressing modes (postbytes have their own code) */
120 //#define DIRECT EAD = DPD; IMMBYTE(ea.b.l)
121 #define DIRECT {uint8 tmpt; EAD = DP << 8; IMMBYTE(tmpt); EAD = EAD + tmpt; }
122 #define IMM8 EAD = PCD; PC++
123 #define IMM16 EAD = PCD; PC += 2
124 #define EXTENDED IMMWORD(EAP)
126 /* macros to set status flags */
127 #define SEC CC |= CC_C
128 #define CLC CC &= ~CC_C
129 #define SEZ CC |= CC_Z
130 #define CLZ CC &= ~CC_Z
131 #define SEN CC |= CC_N
132 #define CLN CC &= ~CC_N
133 #define SEV CC |= CC_V
134 #define CLV CC &= ~CC_V
135 #define SEH CC |= CC_H
136 #define CLH CC &= ~CC_H
138 /* macros for convenience */
139 #define DIRBYTE(b) {DIRECT; b = RM(EAD); }
140 #define DIRWORD(w) {DIRECT; w.d = RM16(EAD);}
141 #define EXTBYTE(b) {EXTENDED; b = RM(EAD); }
142 #define EXTWORD(w) {EXTENDED; w.d = RM16(EAD);}
144 #define OP_HANDLER(_name) inline void MC6809::_name (void)
147 /* macros for branch instructions */
148 #define BRANCH(f) { \
153 PC = PC - (0x0100 - t); \
160 #define LBRANCH(f) { \
170 /* macros for setting/getting registers in TFR/EXG instructions */
172 inline uint32 MC6809::RM16(uint32 Addr)
174 uint32 result = RM(Addr) << 8;
175 return result | RM((Addr + 1) & 0xffff);
178 inline void MC6809::WM16(uint32 Addr, pair *p)
181 WM((Addr + 1) & 0xffff, p->b.l);
185 static const uint8 flags8i[256] = {
186 CC_Z,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
187 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
188 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
189 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
190 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
191 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
192 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
193 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
194 CC_N|CC_V,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
195 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
196 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
197 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
198 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
199 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
200 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
201 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N
205 static const uint8 flags8d[256] = {
206 CC_Z,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
207 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
208 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
209 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
210 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
211 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
212 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
213 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,CC_V,
214 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
215 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
216 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
217 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
218 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
219 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
220 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,
221 CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N,CC_N
224 /* FIXME: Cycles differ slighly from hd6309 emulation */
225 static const int index_cycle_em[256] = { /* Index Loopup cycle counts */
226 /* 0xX0, 0xX1, 0xX2, 0xX3, 0xX4, 0xX5, 0xX6, 0xX7, 0xX8, 0xX9, 0xXA, 0xXB, 0xXC, 0xXD, 0xXE, 0xXF */
228 /* 0x0X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
229 /* 0x1X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
230 /* 0x2X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
231 /* 0x3X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
232 /* 0x4X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
233 /* 0x5X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
234 /* 0x6X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
235 /* 0x7X */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
236 /* 0x8X */ 2, 3, 2, 3, 0, 1, 1, 1, 1, 4, 0, 4, 1, 5, 0, 5,
237 /* 0x9X */ 5, 6, 5, 6, 3, 4, 4, 4, 4, 7, 3, 7, 4, 8, 3, 8,
238 /* 0xAX */ 2, 3, 2, 3, 0, 1, 1, 1, 1, 4, 0, 4, 1, 5, 0, 5,
239 /* 0xBX */ 5, 6, 5, 6, 3, 4, 4, 4, 4, 7, 3, 7, 4, 8, 3, 8,
240 /* 0xCX */ 2, 3, 2, 3, 0, 1, 1, 1, 1, 4, 0, 4, 1, 5, 0, 3,
241 /* 0xDX */ 5, 6, 5, 6, 3, 4, 4, 4, 4, 7, 3, 7, 4, 8, 3, 8,
242 /* 0xEX */ 2, 3, 2, 3, 0, 1, 1, 1, 1, 4, 0, 4, 1, 5, 0, 5,
243 /* 0xFX */ 4, 6, 5, 6, 3, 4, 4, 4, 4, 7, 3, 7, 4, 8, 3, 8
246 /* timings for 1-byte opcodes */
247 /* 20100731 Fix to XM7 */
248 static const int cycles1[] = {
249 /* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
250 /*0 */ 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 3, 6,
251 /*1 */ 0, 0, 2, 2, 0, 0, 5, 9, 3, 2, 3, 2, 3, 2, 8, 6,
252 /*2 */ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
253 /*3 */ 4, 4, 4, 4, 5, 5, 5, 5, 4, 5, 3, 6, 20, 11, 1, 19,
254 /*4 */ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
255 /*5 */ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
256 /*6 */ 6, 6, 6, 6, 6, 2, 6, 6, 6, 6, 6, 6, 6, 6, 3, 6,
257 /*7 */ 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 4, 7,
258 /*8 */ 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 2, 4, 7, 3, 3,
259 /*9 */ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 6, 7, 5, 5,
260 /*A*/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 6, 7, 5, 5,
261 /*B*/ 5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 5, 7, 8, 6, 6,
262 /*C*/ 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 2, 3, 0, 3, 3,
263 /*D*/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
264 /*E*/ 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5,
265 /*F*/ 5, 5, 5, 7, 5, 5, 5, 5, 5, 5, 5, 5, 6, 6, 6, 6
269 static void (MC6809::*m6809_main[0x100]) (void) = {
270 /* 0xX0, 0xX1, 0xX2, 0xX3, 0xX4, 0xX5, 0xX6, 0xX7,
271 0xX8, 0xX9, 0xXA, 0xXB, 0xXC, 0xXD, 0xXE, 0xXF */
274 &MC6809::neg_di, &MC6809::neg_di, &MC6809::ngc_di, &MC6809::com_di,
275 &MC6809::lsr_di, &MC6809::lsr_di, &MC6809::ror_di, &MC6809::asr_di,
276 &MC6809::asl_di, &MC6809::rol_di, &MC6809::dec_di, &MC6809::dcc_di,
277 &MC6809::inc_di, &MC6809::tst_di, &MC6809::jmp_di, &MC6809::clr_di,
279 &MC6809::pref10, &MC6809::pref11, &MC6809::nop, &MC6809::sync_09,
280 &MC6809::trap, &MC6809::trap, &MC6809::lbra, &MC6809::lbsr,
281 &MC6809::aslcc_in, &MC6809::daa, &MC6809::orcc, &MC6809::nop,
282 &MC6809::andcc, &MC6809::sex, &MC6809::exg, &MC6809::tfr,
284 &MC6809::bra, &MC6809::brn, &MC6809::bhi, &MC6809::bls,
285 &MC6809::bcc, &MC6809::bcs, &MC6809::bne, &MC6809::beq,
286 &MC6809::bvc, &MC6809::bvs, &MC6809::bpl, &MC6809::bmi,
287 &MC6809::bge, &MC6809::blt, &MC6809::bgt, &MC6809::ble,
289 &MC6809::leax, &MC6809::leay, &MC6809::leas, &MC6809::leau,
290 &MC6809::pshs, &MC6809::puls, &MC6809::pshu, &MC6809::pulu,
291 &MC6809::andcc, &MC6809::rts, &MC6809::abx, &MC6809::rti,
292 &MC6809::cwai, &MC6809::mul, &MC6809::rst, &MC6809::swi,
294 &MC6809::nega, &MC6809::nega, &MC6809::ngca, &MC6809::coma,
295 &MC6809::lsra, &MC6809::lsra, &MC6809::rora, &MC6809::asra,
296 &MC6809::asla, &MC6809::rola, &MC6809::deca, &MC6809::dcca,
297 &MC6809::inca, &MC6809::tsta, &MC6809::clca, &MC6809::clra,
299 &MC6809::negb, &MC6809::negb, &MC6809::ngcb, &MC6809::comb,
300 &MC6809::lsrb, &MC6809::lsrb, &MC6809::rorb, &MC6809::asrb,
301 &MC6809::aslb, &MC6809::rolb, &MC6809::decb, &MC6809::dccb,
302 &MC6809::incb, &MC6809::tstb, &MC6809::clcb, &MC6809::clrb,
304 &MC6809::neg_ix, &MC6809::neg_ix, &MC6809::ngc_ix, &MC6809::com_ix,
305 &MC6809::lsr_ix, &MC6809::lsr_ix, &MC6809::ror_ix, &MC6809::asr_ix,
306 &MC6809::asl_ix, &MC6809::rol_ix, &MC6809::dec_ix, &MC6809::dcc_ix,
307 &MC6809::inc_ix, &MC6809::tst_ix, &MC6809::jmp_ix, &MC6809::clr_ix,
309 &MC6809::neg_ex, &MC6809::neg_ex, &MC6809::ngc_ex, &MC6809::com_ex,
310 &MC6809::lsr_ex, &MC6809::lsr_ex, &MC6809::ror_ex, &MC6809::asr_ex,
311 &MC6809::asl_ex, &MC6809::rol_ex, &MC6809::dec_ex, &MC6809::dcc_ex,
312 &MC6809::inc_ex, &MC6809::tst_ex, &MC6809::jmp_ex, &MC6809::clr_ex,
314 &MC6809::suba_im, &MC6809::cmpa_im, &MC6809::sbca_im, &MC6809::subd_im,
315 &MC6809::anda_im, &MC6809::bita_im, &MC6809::lda_im, &MC6809::flag8_im,
316 &MC6809::eora_im, &MC6809::adca_im, &MC6809::ora_im, &MC6809::adda_im,
317 &MC6809::cmpx_im, &MC6809::bsr, &MC6809::ldx_im, &MC6809::flag16_im,
319 &MC6809::suba_di, &MC6809::cmpa_di, &MC6809::sbca_di, &MC6809::subd_di,
320 &MC6809::anda_di, &MC6809::bita_di, &MC6809::lda_di, &MC6809::sta_di,
321 &MC6809::eora_di, &MC6809::adca_di, &MC6809::ora_di, &MC6809::adda_di,
322 &MC6809::cmpx_di, &MC6809::jsr_di, &MC6809::ldx_di, &MC6809::stx_di,
324 &MC6809::suba_ix, &MC6809::cmpa_ix, &MC6809::sbca_ix, &MC6809::subd_ix,
325 &MC6809::anda_ix, &MC6809::bita_ix, &MC6809::lda_ix, &MC6809::sta_ix,
326 &MC6809::eora_ix, &MC6809::adca_ix, &MC6809::ora_ix, &MC6809::adda_ix,
327 &MC6809::cmpx_ix, &MC6809::jsr_ix, &MC6809::ldx_ix, &MC6809::stx_ix,
329 &MC6809::suba_ex, &MC6809::cmpa_ex, &MC6809::sbca_ex, &MC6809::subd_ex,
330 &MC6809::anda_ex, &MC6809::bita_ex, &MC6809::lda_ex, &MC6809::sta_ex,
331 &MC6809::eora_ex, &MC6809::adca_ex, &MC6809::ora_ex, &MC6809::adda_ex,
332 &MC6809::cmpx_ex, &MC6809::jsr_ex, &MC6809::ldx_ex, &MC6809::stx_ex,
334 &MC6809::subb_im, &MC6809::cmpb_im, &MC6809::sbcb_im, &MC6809::addd_im,
335 &MC6809::andb_im, &MC6809::bitb_im, &MC6809::ldb_im, &MC6809::flag8_im,
336 &MC6809::eorb_im, &MC6809::adcb_im, &MC6809::orb_im, &MC6809::addb_im,
337 &MC6809::ldd_im, &MC6809::trap, &MC6809::ldu_im, &MC6809::flag16_im,
339 &MC6809::subb_di, &MC6809::cmpb_di, &MC6809::sbcb_di, &MC6809::addd_di,
340 &MC6809::andb_di, &MC6809::bitb_di, &MC6809::ldb_di, &MC6809::stb_di,
341 &MC6809::eorb_di, &MC6809::adcb_di, &MC6809::orb_di, &MC6809::addb_di,
342 &MC6809::ldd_di, &MC6809::std_di, &MC6809::ldu_di, &MC6809::stu_di,
344 &MC6809::subb_ix, &MC6809::cmpb_ix, &MC6809::sbcb_ix, &MC6809::addd_ix,
345 &MC6809::andb_ix, &MC6809::bitb_ix, &MC6809::ldb_ix, &MC6809::stb_ix,
346 &MC6809::eorb_ix, &MC6809::adcb_ix, &MC6809::orb_ix, &MC6809::addb_ix,
347 &MC6809::ldd_ix, &MC6809::std_ix, &MC6809::ldu_ix, &MC6809::stu_ix,
349 &MC6809::subb_ex, &MC6809::cmpb_ex, &MC6809::sbcb_ex, &MC6809::addd_ex,
350 &MC6809::andb_ex, &MC6809::bitb_ex, &MC6809::ldb_ex, &MC6809::stb_ex,
351 &MC6809::eorb_ex, &MC6809::adcb_ex, &MC6809::orb_ex, &MC6809::addb_ex,
352 &MC6809::ldd_ex, &MC6809::std_ex, &MC6809::ldu_ex, &MC6809::stu_ex
362 DPD = 0; /* Reset direct page register */
370 #if defined(_FM7) || defined(_FM8) || defined(_FM77) || defined(_FM77L2) || defined(_FM77L4) || defined(_FM77_VARIANTS)
372 write_signals(&outputs_bus_clr, 0x00000000);
374 write_signals(&outputs_bus_halt, 0x00000000);
376 CC |= CC_II; /* IRQ disabled */
377 CC |= CC_IF; /* FIRQ disabled */
382 void MC6809::write_signal(int id, uint32 data, uint32 mask)
384 if(id == SIG_CPU_IRQ) {
386 int_state |= MC6809_IRQ_BIT;
388 int_state &= ~MC6809_IRQ_BIT;
390 } else if(id == SIG_CPU_FIRQ) {
392 int_state |= MC6809_FIRQ_BIT;
394 int_state &= ~MC6809_FIRQ_BIT;
396 } else if(id == SIG_CPU_NMI) {
398 int_state |= MC6809_NMI_BIT;
400 int_state &= ~MC6809_NMI_BIT;
402 } else if(id == SIG_CPU_BUSREQ) {
404 int_state |= MC6809_HALT_BIT;
406 int_state &= ~MC6809_HALT_BIT;
411 void MC6809::cpu_nmi(void)
414 if ((int_state & MC6809_CWAI_IN) == 0) {
425 CC = CC | CC_II | CC_IF; // 0x50
427 // printf("NMI occured PC=0x%04x VECTOR=%04x SP=%04x \n",rpc.w.l,pPC.w.l,S);
428 int_state &= ~(MC6809_SYNC_IN | MC6809_SYNC_OUT | MC6809_CWAI_IN | MC6809_CWAI_OUT | MC6809_NMI_BIT); // $FE1E
432 // Refine from cpu_x86.asm of V3.52a.
433 void MC6809::cpu_firq(void)
436 if ((int_state & MC6809_CWAI_IN) == 0) {
442 CC = CC | CC_II | CC_IF;
444 // printf("Firq occured PC=0x%04x VECTOR=%04x SP=%04x \n",rpc.w.l,pPC.w.l,S);
445 int_state &= ~(MC6809_SYNC_IN | MC6809_SYNC_OUT | MC6809_CWAI_IN | MC6809_CWAI_OUT); // $FE1F
448 // Refine from cpu_x86.asm of V3.52a.
449 void MC6809::cpu_irq(void)
452 if ((int_state & MC6809_CWAI_IN) == 0) {
466 // printf("IRQ occured PC=0x%04x VECTOR=%04x SP=%04x \n",rpc.w.l,pPC.w.l,S);
467 int_state &= ~(MC6809_SYNC_IN | MC6809_SYNC_OUT | MC6809_CWAI_IN | MC6809_CWAI_OUT); // $FE1F
470 int MC6809::run(int clock)
473 if ((int_state & MC6809_HALT_BIT) != 0) { // 0x80
474 if(icount > 0) icount = 0; // OK?
475 if(!busreq) write_signals(&outputs_bus_halt, 0xffffffff);
479 if(busreq) write_signals(&outputs_bus_halt, 0x00000000);
481 if((int_state & MC6809_INSN_HALT) != 0) { // 0x80
484 icount -= extra_icount;
493 if ((int_state & (MC6809_NMI_BIT | MC6809_FIRQ_BIT | MC6809_IRQ_BIT)) != 0) { // 0x0007
494 if ((int_state & MC6809_NMI_BIT) == 0)
496 int_state |= MC6809_SYNC_OUT;
497 //if ((int_state & MC6809_LDS) == 0)
499 if ((int_state & MC6809_SYNC_IN) != 0) {
500 if ((int_state & MC6809_NMI_LC) != 0)
514 if ((int_state & MC6809_FIRQ_BIT) != 0) {
515 int_state |= MC6809_SYNC_OUT;
516 if ((cc & CC_IF) != 0)
518 if ((int_state & MC6809_SYNC_IN) != 0) {
519 if ((int_state & MC6809_FIRQ_LC) != 0)
530 if ((int_state & MC6809_IRQ_BIT) != 0) {
531 int_state |= MC6809_SYNC_OUT;
532 if ((cc & CC_II) != 0)
534 if ((int_state & MC6809_SYNC_IN) != 0) {
535 if ((int_state & MC6809_IRQ_LC) != 0)
553 if ((int_state & MC6809_CWAI_IN) == 0) {
561 // run only one opcode
566 // run cpu while given clocks
568 int first_icount = icount;
573 return first_icount - icount;
578 void MC6809::run_one_opecode()
583 uint8 ireg = ROP(PCD);
585 icount -= cycles1[ireg];
586 icount -= extra_icount;
591 void MC6809::op(uint8 ireg)
593 #if defined(_FM7) || defined(_FM8) || defined(_FM77) || defined(_FM77L2) || defined(_FM77L4) || defined(_FM77_VARIANTS)
594 if(ireg == 0x0f) { // clr_di()
595 write_signals(&outputs_bus_clr, 0x00000001);
597 } else if((ireg == 0x6f) || (ireg == 0x7f)){ //clr_ex() clr_ix()
598 write_signals(&outputs_bus_clr, 0x00000002);
601 if(clr_used) write_signals(&outputs_bus_clr, 0x00000000);
606 (this->*m6809_main[ireg])();
609 inline void MC6809::fetch_effective_address()
616 upper = (postbyte >> 4) & 0x0f;
617 lower = postbyte & 0x0f;
645 fetch_effective_address_IDX(upper, lower);
649 icount -= index_cycle_em[postbyte];
652 inline void MC6809::fetch_effective_address_IDX(uint8 upper, uint8 lower)
654 bool indirect = false;
657 if ((upper & 0x08) != 0)
658 indirect = ((upper & 0x01) != 0);
660 switch ((upper >> 1) & 0x03) { // $8-$f >> 1 = $4 - $7 : delete bit2
679 *reg = *reg & 0xffff;
684 *reg = *reg & 0xffff;
688 *reg = *reg & 0xffff;
693 *reg = *reg & 0xffff;
700 EA = *reg + SIGNED(B);
704 EA = *reg + SIGNED(A);
708 EA = *reg + SIGNED(bx);
714 case 0x0a: // Undocumented
724 EA = PC + SIGNED(bx);
726 case 0x0d: // xxxx,pc
730 case 0x0e: // Undocumented
740 // $9x,$bx,$dx,$fx = INDIRECT
746 #define IIError() illegal()
750 //logerror("M6809: illegal opcode at %04x\n",PC);
751 printf("M6809: illegal opcode at %04x %02x %02x %02x %02x %02x \n",
752 PC - 2, RM(PC - 2), RM(PC - 1), RM(PC), RM(PC + 1), RM(PC + 2));
755 /* $00 NEG direct ?**** */
765 /* $01 Undefined Neg */
766 /* $03 COM direct -**01 */
777 /* $02 NGC Direct (Undefined) */
779 if ((CC & CC_C) == 0) {
788 /* $04 LSR direct -0*-* */
801 /* $06 ROR direct -**-* */
805 r = (CC & CC_C) << 7;
815 /* $07 ASR direct ?**-* */
821 t = (t & 0x80) | (t >> 1);
826 /* $08 ASL direct ?**** */
836 /* $09 ROL direct -**** */
840 r = (CC & CC_C) | (t << 1);
846 /* $0A DEC direct -***- */
872 /* $OC INC direct -***- */
882 /* $OD TST direct -**0- */
890 /* $0E JMP direct ----- */
896 /* $0F CLR direct -0100 */
900 dummy = RM(EAD); // Dummy Read(Alpha etc...)
910 /* $12 NOP inherent ----- */
915 /* $13 SYNC inherent ----- */
916 OP_HANDLER(sync_09) // Rename 20101110
919 if ((int_state & MC6809_SYNC_IN) == 0) {
921 int_state |= MC6809_SYNC_IN;
922 // int_state &= 0xffbf;
923 int_state &= ~MC6809_SYNC_OUT;
924 PC -= 1; // 次のサイクルも同じ命令
928 if ((int_state & MC6809_SYNC_OUT) != 0) {
930 int_state &= ~(MC6809_SYNC_OUT | MC6809_SYNC_IN);
933 PC -= 1; // 割込こないと次のサイクルも同じ命令
941 int_state |= MC6809_INSN_HALT; // HALTフラグ
943 printf("INSN: TRAP @%04x %02x %02x\n", PC - 1, RM(PC - 1), RM(PC));
948 /* $16 LBRA relative ----- */
953 /* $17 LBSR relative ----- */
962 OP_HANDLER(aslcc_in) {
964 if ((cc & CC_Z) != 0x00) //20100824 Fix
973 /* $19 DAA inherent (A) -**0* */
979 if (lsn > 0x09 || CC & CC_H)
981 if (msn > 0x80 && lsn > 0x09)
983 if (msn > 0x90 || CC & CC_C)
986 CLR_NZV; /* keep carry from previous operation */
993 /* $1A ORCC immediate ##### */
1003 /* $1C ANDCC immediate ##### */
1008 // check_irq_lines(); /* HJB 990116 */
1011 /* $1D SEX inherent -**-- */
1016 // CLR_NZV; Tim Lindner 20020905: verified that V flag is not affected
1021 /* $1E EXG inherent ----- */// 20100825
1027 * 20111011: 16bit vs 16Bitの演算にする(XM7/ cpu_x86.asmより
1030 switch ((tb >> 4) & 15) {
1101 switch ((tb >> 4) & 15) {
1116 int_state |= MC6809_LDS;
1149 int_state |= MC6809_LDS;
1169 /* $1F TFR inherent ----- */
1175 * 20111011: 16bit vs 16Bitの演算にする(XM7/ cpu_x86.asmより)
1178 switch ((tb >> 4) & 15) {
1229 int_state |= MC6809_LDS;
1249 /* $20 BRA relative ----- */
1254 /* $21 BRN relative ----- */
1259 /* $1021 LBRN relative ----- */
1264 /* $22 BHI relative ----- */
1266 BRANCH(!(CC & (CC_Z | CC_C)));
1269 /* $1022 LBHI relative ----- */
1271 LBRANCH(!(CC & (CC_Z | CC_C)));
1274 /* $23 BLS relative ----- */
1276 BRANCH((CC & (CC_Z | CC_C)));
1279 /* $1023 LBLS relative ----- */
1281 LBRANCH((CC & (CC_Z | CC_C)));
1284 /* $24 BCC relative ----- */
1286 BRANCH(!(CC & CC_C));
1289 /* $1024 LBCC relative ----- */
1291 LBRANCH(!(CC & CC_C));
1294 /* $25 BCS relative ----- */
1296 BRANCH((CC & CC_C));
1299 /* $1025 LBCS relative ----- */
1301 LBRANCH((CC & CC_C));
1304 /* $26 BNE relative ----- */
1306 BRANCH(!(CC & CC_Z));
1309 /* $1026 LBNE relative ----- */
1311 LBRANCH(!(CC & CC_Z));
1314 /* $27 BEQ relative ----- */
1316 BRANCH((CC & CC_Z));
1319 /* $1027 LBEQ relative ----- */
1321 LBRANCH((CC & CC_Z));
1324 /* $28 BVC relative ----- */
1326 BRANCH(!(CC & CC_V));
1329 /* $1028 LBVC relative ----- */
1331 LBRANCH(!(CC & CC_V));
1334 /* $29 BVS relative ----- */
1336 BRANCH((CC & CC_V));
1339 /* $1029 LBVS relative ----- */
1341 LBRANCH((CC & CC_V));
1344 /* $2A BPL relative ----- */
1346 BRANCH(!(CC & CC_N));
1349 /* $102A LBPL relative ----- */
1351 LBRANCH(!(CC & CC_N));
1354 /* $2B BMI relative ----- */
1356 BRANCH((CC & CC_N));
1359 /* $102B LBMI relative ----- */
1361 LBRANCH((CC & CC_N));
1364 /* $2C BGE relative ----- */
1369 /* $102C LBGE relative ----- */
1374 /* $2D BLT relative ----- */
1379 /* $102D LBLT relative ----- */
1384 /* $2E BGT relative ----- */
1386 BRANCH(!(NXORV || (CC & CC_Z)));
1389 /* $102E LBGT relative ----- */
1391 LBRANCH(!(NXORV || (CC & CC_Z)));
1394 /* $2F BLE relative ----- */
1396 BRANCH((NXORV || (CC & CC_Z)));
1399 /* $102F LBLE relative ----- */
1401 LBRANCH((NXORV || (CC & CC_Z)));
1404 /* $30 LEAX indexed --*-- */
1406 fetch_effective_address();
1412 /* $31 LEAY indexed --*-- */
1414 fetch_effective_address();
1421 /* $32 LEAS indexed ----- */
1423 fetch_effective_address();
1425 // int_state |= MC6809_LDS; // 20130513 removed.
1428 /* $33 LEAU indexed ----- */
1430 fetch_effective_address();
1434 /* $34 PSHS inherent ----- */
1438 dmy = RM(S); // Add 20100825
1473 /* 35 PULS inherent ----- */
1509 dmy = RM(S); // Add 20100825
1511 /* HJB 990225: moved check after all PULLs */
1512 // if( t&0x01 ) { check_irq_lines(); }
1515 /* $36 PSHU inherent ----- */
1519 dmy = RM(U); // Add 20100825
1554 /* 37 PULU inherent ----- */
1590 dmy = RM(U); // Add 20100825
1592 /* HJB 990225: moved check after all PULLs */
1593 //if( t&0x01 ) { check_irq_lines(); }
1598 /* $39 RTS inherent ----- */
1603 /* $3A ABX inherent ----- */
1605 uint16 b = B & 0x00ff;
1609 /* $3B RTI inherent ##### */
1613 // t = CC & CC_E; /* HJB 990225: entire state saved? */
1614 if ((CC & CC_E) != 0) { // NMIIRQ
1624 // check_irq_lines(); /* HJB 990116 */
1627 /* $3C CWAI inherent ----1 */
1631 if ((int_state & MC6809_CWAI_IN) != 0) { // FIX 20130417
1633 PC -= 1; // 次回もCWAI命令実行
1640 CC |= CC_E; /* HJB 990225: save entire state */
1650 int_state = int_state | MC6809_CWAI_IN;
1651 int_state &= ~MC6809_CWAI_OUT; // 0xfeff
1652 PC -= 2; // レジスタ退避して再度実行
1656 /* $3D MUL inherent --*-@ */
1665 A = (t & 0xff00) >> 8;
1675 /* $3F SWI (SWI2 SWI3) absolute indirect ----- */
1677 CC |= CC_E; /* HJB 980225: save entire state */
1686 CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
1690 /* $103F SWI2 absolute indirect ----- */
1692 CC |= CC_E; /* HJB 980225: save entire state */
1704 /* $113F SWI3 absolute indirect ----- */
1706 CC |= CC_E; /* HJB 980225: save entire state */
1718 /* $40 NEGA inherent ?**** */
1723 SET_FLAGS8(0, A, r);
1730 /* $43 COMA inherent -**01 */
1740 if ((CC & CC_C) == 0) {
1748 /* $44 LSRA inherent -0*-* */
1758 /* $46 RORA inherent -**-* */
1763 r = (CC & CC_C) << 7;
1772 /* $47 ASRA inherent ?**-* */
1776 A = (A & 0x80) | (A >> 1);
1780 /* $48 ASLA inherent ?**** */
1785 SET_FLAGS8(A, A, r);
1789 /* $49 ROLA inherent -**** */
1793 r = (CC & CC_C) | (t << 1);
1795 SET_FLAGS8(t, t, r);
1796 A = (BYTE) (r & 0x00ff);
1799 /* $4A DECA inherent -***- */
1821 /* $4C INCA inherent -***- */
1828 /* $4D TSTA inherent -**0- */
1842 /* $4F CLRA inherent -0100 */
1849 /* $50 NEGB inherent ?**** */
1854 SET_FLAGS8(0, B, r);
1862 /* $53 COMB inherent -**01 */
1872 if ((CC & CC_C) == 0) {
1880 /* $54 LSRB inherent -0*-* */
1890 /* $56 RORB inherent -**-* */
1895 r = (CC & CC_C) << 7;
1904 /* $57 ASRB inherent ?**-* */
1908 B = (B & 0x80) | (B >> 1);
1912 /* $58 ASLB inherent ?**** */
1917 SET_FLAGS8(B, B, r);
1921 /* $59 ROLB inherent -**** */
1928 SET_FLAGS8(t, t, r);
1932 /* $5A DECB inherent -***- */
1955 /* $5C INCB inherent -***- */
1962 /* $5D TSTB inherent -**0- */
1976 /* $5F CLRB inherent -0100 */
1983 /* $60 NEG indexed ?**** */
1984 OP_HANDLER(neg_ix) {
1986 fetch_effective_address();
1990 SET_FLAGS8(0, t, r);
1997 /* $63 COM indexed -**01 */
1998 OP_HANDLER(com_ix) {
2000 fetch_effective_address();
2008 OP_HANDLER(ngc_ix) {
2009 if ((CC & CC_C) == 0) {
2017 /* $64 LSR indexed -0*-* */
2018 OP_HANDLER(lsr_ix) {
2020 fetch_effective_address();
2031 /* $66 ROR indexed -**-* */
2032 OP_HANDLER(ror_ix) {
2034 fetch_effective_address();
2036 r = (CC & CC_C) << 7;
2044 /* $67 ASR indexed ?**-* */
2045 OP_HANDLER(asr_ix) {
2047 fetch_effective_address();
2051 t = (t & 0x80) | (t >> 1);
2056 /* $68 ASL indexed ?**** */
2057 OP_HANDLER(asl_ix) {
2059 fetch_effective_address();
2063 SET_FLAGS8(t, t, r);
2067 /* $69 ROL indexed -**** */
2068 OP_HANDLER(rol_ix) {
2070 fetch_effective_address();
2075 SET_FLAGS8(t, t, r);
2079 /* $6A DEC indexed -***- */
2080 OP_HANDLER(dec_ix) {
2082 fetch_effective_address();
2090 OP_HANDLER(dcc_ix) {
2092 fetch_effective_address();
2104 /* $6C INC indexed -***- */
2105 OP_HANDLER(inc_ix) {
2107 fetch_effective_address();
2114 /* $6D TST indexed -**0- */
2115 OP_HANDLER(tst_ix) {
2117 fetch_effective_address();
2123 /* $6E JMP indexed ----- */
2124 OP_HANDLER(jmp_ix) {
2125 fetch_effective_address();
2129 /* $6F CLR indexed -0100 */
2130 OP_HANDLER(clr_ix) {
2132 fetch_effective_address();
2139 /* $70 NEG extended ?**** */
2140 OP_HANDLER(neg_ex) {
2146 SET_FLAGS8(0, t, r);
2151 /* $73 COM extended -**01 */
2152 OP_HANDLER(com_ex) {
2162 /* $72 NGC extended */
2163 OP_HANDLER(ngc_ex) {
2164 if ((CC & CC_C) == 0) {
2172 /* $74 LSR extended -0*-* */
2173 OP_HANDLER(lsr_ex) {
2185 /* $76 ROR extended -**-* */
2186 OP_HANDLER(ror_ex) {
2189 r = (CC & CC_C) << 7;
2197 /* $77 ASR extended ?**-* */
2198 OP_HANDLER(asr_ex) {
2203 t = (t & 0x80) | (t >> 1);
2208 /* $78 ASL extended ?**** */
2209 OP_HANDLER(asl_ex) {
2214 SET_FLAGS8(t, t, r);
2218 /* $79 ROL extended -**** */
2219 OP_HANDLER(rol_ex) {
2222 r = (CC & CC_C) | (t << 1);
2224 SET_FLAGS8(t, t, r);
2228 /* $7A DEC extended -***- */
2229 OP_HANDLER(dec_ex) {
2240 OP_HANDLER(dcc_ex) {
2254 /* $7C INC extended -***- */
2255 OP_HANDLER(inc_ex) {
2264 /* $7D TST extended -**0- */
2265 OP_HANDLER(tst_ex) {
2272 /* $7E JMP extended ----- */
2273 OP_HANDLER(jmp_ex) {
2278 /* $7F CLR extended -0100 */
2279 OP_HANDLER(clr_ex) {
2287 /* $80 SUBA immediate ?**** */
2288 OP_HANDLER(suba_im) {
2294 SET_FLAGS8(A, t, r);
2298 /* $81 CMPA immediate ?**** */
2299 OP_HANDLER(cmpa_im) {
2305 SET_FLAGS8(A, t, r);
2308 /* $82 SBCA immediate ?**** */
2309 OP_HANDLER(sbca_im) {
2313 r = A - t - (CC & CC_C);
2315 SET_FLAGS8(A, t, r);
2319 /* $83 SUBD (CMPD CMPU) immediate -**** */
2320 OP_HANDLER(subd_im) {
2327 SET_FLAGS16(d, b.d, r);
2331 /* $1083 CMPD immediate -**** */
2332 OP_HANDLER(cmpd_im) {
2339 SET_FLAGS16(d, b.d, r);
2342 /* $1183 CMPU immediate -**** */
2343 OP_HANDLER(cmpu_im) {
2350 SET_FLAGS16(d, b.d, r);
2353 /* $84 ANDA immediate -**0- */
2354 OP_HANDLER(anda_im) {
2362 /* $85 BITA immediate -**0- */
2363 OP_HANDLER(bita_im) {
2371 /* $86 LDA immediate -**0- */
2372 OP_HANDLER(lda_im) {
2378 /* is this a legal instruction? */
2379 /* $87 STA immediate -**0- */
2380 OP_HANDLER(sta_im) {
2390 OP_HANDLER(flag8_im) {
2399 /* $88 EORA immediate -**0- */
2400 OP_HANDLER(eora_im) {
2408 /* $89 ADCA immediate ***** */
2409 OP_HANDLER(adca_im) {
2412 r = A + t + (CC & CC_C);
2414 SET_HNZVC8(A, t, r);
2418 /* $8A ORA immediate -**0- */
2419 OP_HANDLER(ora_im) {
2427 /* $8B ADDA immediate ***** */
2428 OP_HANDLER(adda_im) {
2433 SET_HNZVC8(A, t, r);
2437 /* $8C CMPX (CMPY CMPS) immediate -**** */
2438 OP_HANDLER(cmpx_im) {
2445 SET_FLAGS16(d, b.d, r);
2448 /* $108C CMPY immediate -**** */
2449 OP_HANDLER(cmpy_im) {
2456 SET_FLAGS16(d, b.d, r);
2459 /* $118C CMPS immediate -**** */
2460 OP_HANDLER(cmps_im) {
2467 SET_FLAGS16(d, b.d, r);
2478 /* $8E LDX (LDY) immediate -**0- */
2479 OP_HANDLER(ldx_im) {
2485 /* $108E LDY immediate -**0- */
2486 OP_HANDLER(ldy_im) {
2492 /* is this a legal instruction? */
2493 /* $8F STX (STY) immediate -**0- */
2494 OP_HANDLER(stx_im) {
2504 OP_HANDLER(flag16_im) {
2519 /* is this a legal instruction? */
2520 /* $108F STY immediate -**0- */
2521 OP_HANDLER(sty_im) {
2528 /* $90 SUBA direct ?**** */
2529 OP_HANDLER(suba_di) {
2534 SET_FLAGS8(A, t, r);
2538 /* $91 CMPA direct ?**** */
2539 OP_HANDLER(cmpa_di) {
2544 SET_FLAGS8(A, t, r);
2547 /* $92 SBCA direct ?**** */
2548 OP_HANDLER(sbca_di) {
2551 r = A - t - (CC & CC_C);
2553 SET_FLAGS8(A, t, r);
2557 /* $93 SUBD (CMPD CMPU) direct -**** */
2558 OP_HANDLER(subd_di) {
2565 SET_FLAGS16(d, b.d, r);
2569 /* $1093 CMPD direct -**** */
2570 OP_HANDLER(cmpd_di) {
2577 SET_FLAGS16(d, b.d, r);
2580 /* $1193 CMPU direct -**** */
2581 OP_HANDLER(cmpu_di) {
2588 SET_FLAGS16(U, b.d, r);
2591 /* $94 ANDA direct -**0- */
2592 OP_HANDLER(anda_di) {
2600 /* $95 BITA direct -**0- */
2601 OP_HANDLER(bita_di) {
2609 /* $96 LDA direct -**0- */
2610 OP_HANDLER(lda_di) {
2616 /* $97 STA direct -**0- */
2617 OP_HANDLER(sta_di) {
2624 /* $98 EORA direct -**0- */
2625 OP_HANDLER(eora_di) {
2633 /* $99 ADCA direct ***** */
2634 OP_HANDLER(adca_di) {
2637 r = A + t + (CC & CC_C);
2639 SET_HNZVC8(A, t, r);
2643 /* $9A ORA direct -**0- */
2644 OP_HANDLER(ora_di) {
2652 /* $9B ADDA direct ***** */
2653 OP_HANDLER(adda_di) {
2658 SET_HNZVC8(A, t, r);
2662 /* $9C CMPX (CMPY CMPS) direct -**** */
2663 OP_HANDLER(cmpx_di) {
2670 SET_FLAGS16(d, b.d, r);
2673 /* $109C CMPY direct -**** */
2674 OP_HANDLER(cmpy_di) {
2681 SET_FLAGS16(d, b.d, r);
2684 /* $119C CMPS direct -**** */
2685 OP_HANDLER(cmps_di) {
2692 SET_FLAGS16(d, b.d, r);
2695 /* $9D JSR direct ----- */
2696 OP_HANDLER(jsr_di) {
2702 /* $9E LDX (LDY) direct -**0- */
2703 OP_HANDLER(ldx_di) {
2709 /* $109E LDY direct -**0- */
2710 OP_HANDLER(ldy_di) {
2716 /* $9F STX (STY) direct -**0- */
2717 OP_HANDLER(stx_di) {
2724 /* $109F STY direct -**0- */
2725 OP_HANDLER(sty_di) {
2732 /* $a0 SUBA indexed ?**** */
2733 OP_HANDLER(suba_ix) {
2735 fetch_effective_address();
2739 SET_FLAGS8(A, t, r);
2743 /* $a1 CMPA indexed ?**** */
2744 OP_HANDLER(cmpa_ix) {
2746 fetch_effective_address();
2750 SET_FLAGS8(A, t, r);
2753 /* $a2 SBCA indexed ?**** */
2754 OP_HANDLER(sbca_ix) {
2756 fetch_effective_address();
2758 r = A - t - (CC & CC_C);
2760 SET_FLAGS8(A, t, r);
2764 /* $a3 SUBD (CMPD CMPU) indexed -**** */
2765 OP_HANDLER(subd_ix) {
2768 fetch_effective_address();
2773 SET_FLAGS16(d, b, r);
2777 /* $10a3 CMPD indexed -**** */
2778 OP_HANDLER(cmpd_ix) {
2781 fetch_effective_address();
2786 SET_FLAGS16(d, b, r);
2789 /* $11a3 CMPU indexed -**** */
2790 OP_HANDLER(cmpu_ix) {
2793 fetch_effective_address();
2797 SET_FLAGS16(U, b, r);
2800 /* $a4 ANDA indexed -**0- */
2801 OP_HANDLER(anda_ix) {
2802 fetch_effective_address();
2808 /* $a5 BITA indexed -**0- */
2809 OP_HANDLER(bita_ix) {
2811 fetch_effective_address();
2817 /* $a6 LDA indexed -**0- */
2818 OP_HANDLER(lda_ix) {
2819 fetch_effective_address();
2825 /* $a7 STA indexed -**0- */
2826 OP_HANDLER(sta_ix) {
2827 fetch_effective_address();
2833 /* $a8 EORA indexed -**0- */
2834 OP_HANDLER(eora_ix) {
2835 fetch_effective_address();
2841 /* $a9 ADCA indexed ***** */
2842 OP_HANDLER(adca_ix) {
2844 fetch_effective_address();
2846 r = A + t + (CC & CC_C);
2848 SET_FLAGS8(A, t, r);
2853 /* $aA ORA indexed -**0- */
2854 OP_HANDLER(ora_ix) {
2855 fetch_effective_address();
2861 /* $aB ADDA indexed ***** */
2862 OP_HANDLER(adda_ix) {
2864 fetch_effective_address();
2868 SET_FLAGS8(A, t, r);
2873 /* $aC CMPX (CMPY CMPS) indexed -**** */
2874 OP_HANDLER(cmpx_ix) {
2877 fetch_effective_address();
2882 SET_FLAGS16(d, b, r);
2885 /* $10aC CMPY indexed -**** */
2886 OP_HANDLER(cmpy_ix) {
2889 fetch_effective_address();
2894 SET_FLAGS16(d, b, r);
2897 /* $11aC CMPS indexed -**** */
2898 OP_HANDLER(cmps_ix) {
2901 fetch_effective_address();
2906 SET_FLAGS16(d, b, r);
2909 /* $aD JSR indexed ----- */
2910 OP_HANDLER(jsr_ix) {
2911 fetch_effective_address();
2916 /* $aE LDX (LDY) indexed -**0- */
2917 OP_HANDLER(ldx_ix) {
2918 fetch_effective_address();
2924 /* $10aE LDY indexed -**0- */
2925 OP_HANDLER(ldy_ix) {
2926 fetch_effective_address();
2932 /* $aF STX (STY) indexed -**0- */
2933 OP_HANDLER(stx_ix) {
2934 fetch_effective_address();
2940 /* $10aF STY indexed -**0- */
2941 OP_HANDLER(sty_ix) {
2942 fetch_effective_address();
2948 /* $b0 SUBA extended ?**** */
2949 OP_HANDLER(suba_ex) {
2954 SET_FLAGS8(A, t, r);
2958 /* $b1 CMPA extended ?**** */
2959 OP_HANDLER(cmpa_ex) {
2964 SET_FLAGS8(A, t, r);
2967 /* $b2 SBCA extended ?**** */
2968 OP_HANDLER(sbca_ex) {
2971 r = A - t - (CC & CC_C);
2973 SET_FLAGS8(A, t, r);
2977 /* $b3 SUBD (CMPD CMPU) extended -**** */
2978 OP_HANDLER(subd_ex) {
2985 SET_FLAGS16(d, b.d, r);
2989 /* $10b3 CMPD extended -**** */
2990 OP_HANDLER(cmpd_ex) {
2997 SET_FLAGS16(d, b.d, r);
3000 /* $11b3 CMPU extended -**** */
3001 OP_HANDLER(cmpu_ex) {
3008 SET_FLAGS16(d, b.d, r);
3011 /* $b4 ANDA extended -**0- */
3012 OP_HANDLER(anda_ex) {
3020 /* $b5 BITA extended -**0- */
3021 OP_HANDLER(bita_ex) {
3029 /* $b6 LDA extended -**0- */
3030 OP_HANDLER(lda_ex) {
3036 /* $b7 STA extended -**0- */
3037 OP_HANDLER(sta_ex) {
3044 /* $b8 EORA extended -**0- */
3045 OP_HANDLER(eora_ex) {
3053 /* $b9 ADCA extended ***** */
3054 OP_HANDLER(adca_ex) {
3057 r = A + t + (CC & CC_C);
3059 SET_HNZVC8(A, t, r);
3063 /* $bA ORA extended -**0- */
3064 OP_HANDLER(ora_ex) {
3072 /* $bB ADDA extended ***** */
3073 OP_HANDLER(adda_ex) {
3078 SET_HNZVC8(A, t, r);
3082 /* $bC CMPX (CMPY CMPS) extended -**** */
3083 OP_HANDLER(cmpx_ex) {
3090 SET_FLAGS16(d, b.d, r);
3093 /* $10bC CMPY extended -**** */
3094 OP_HANDLER(cmpy_ex) {
3101 SET_FLAGS16(d, b.d, r);
3104 /* $11bC CMPS extended -**** */
3105 OP_HANDLER(cmps_ex) {
3112 SET_FLAGS16(d, b.d, r);
3115 /* $bD JSR extended ----- */
3116 OP_HANDLER(jsr_ex) {
3122 /* $bE LDX (LDY) extended -**0- */
3123 OP_HANDLER(ldx_ex) {
3129 /* $10bE LDY extended -**0- */
3130 OP_HANDLER(ldy_ex) {
3136 /* $bF STX (STY) extended -**0- */
3137 OP_HANDLER(stx_ex) {
3144 /* $10bF STY extended -**0- */
3145 OP_HANDLER(sty_ex) {
3152 /* $c0 SUBB immediate ?**** */
3153 OP_HANDLER(subb_im) {
3158 SET_FLAGS8(B, t, r);
3162 /* $c1 CMPB immediate ?**** */
3163 OP_HANDLER(cmpb_im) {
3168 SET_FLAGS8(B, t, r);
3171 /* $c2 SBCB immediate ?**** */
3172 OP_HANDLER(sbcb_im) {
3175 r = B - t - (CC & CC_C);
3177 SET_FLAGS8(B, t, r);
3181 /* $c3 ADDD immediate -**** */
3182 OP_HANDLER(addd_im) {
3189 SET_FLAGS16(d, b.d, r);
3193 /* $c4 ANDB immediate -**0- */
3194 OP_HANDLER(andb_im) {
3202 /* $c5 BITB immediate -**0- */
3203 OP_HANDLER(bitb_im) {
3211 /* $c6 LDB immediate -**0- */
3212 OP_HANDLER(ldb_im) {
3218 /* is this a legal instruction? */
3219 /* $c7 STB immediate -**0- */
3220 OP_HANDLER(stb_im) {
3227 /* $c8 EORB immediate -**0- */
3228 OP_HANDLER(eorb_im) {
3236 /* $c9 ADCB immediate ***** */
3237 OP_HANDLER(adcb_im) {
3240 r = B + t + (CC & CC_C);
3242 SET_HNZVC8(B, t, r);
3246 /* $cA ORB immediate -**0- */
3247 OP_HANDLER(orb_im) {
3255 /* $cB ADDB immediate ***** */
3256 OP_HANDLER(addb_im) {
3261 SET_HNZVC8(B, t, r);
3265 /* $cC LDD immediate -**0- */
3266 OP_HANDLER(ldd_im) {
3272 /* is this a legal instruction? */
3273 /* $cD STD immediate -**0- */
3274 OP_HANDLER(std_im) {
3281 /* $cE LDU (LDS) immediate -**0- */
3282 OP_HANDLER(ldu_im) {
3288 /* $10cE LDS immediate -**0- */
3289 OP_HANDLER(lds_im) {
3293 int_state |= MC6809_LDS;
3296 /* is this a legal instruction? */
3297 /* $cF STU (STS) immediate -**0- */
3298 OP_HANDLER(stu_im) {
3305 /* is this a legal instruction? */
3306 /* $10cF STS immediate -**0- */
3307 OP_HANDLER(sts_im) {
3314 /* $d0 SUBB direct ?**** */
3315 OP_HANDLER(subb_di) {
3320 SET_FLAGS8(B, t, r);
3324 /* $d1 CMPB direct ?**** */
3325 OP_HANDLER(cmpb_di) {
3330 SET_FLAGS8(B, t, r);
3333 /* $d2 SBCB direct ?**** */
3334 OP_HANDLER(sbcb_di) {
3337 r = B - t - (CC & CC_C);
3339 SET_FLAGS8(B, t, r);
3343 /* $d3 ADDD direct -**** */
3344 OP_HANDLER(addd_di) {
3351 SET_FLAGS16(d, b.d, r);
3355 /* $d4 ANDB direct -**0- */
3356 OP_HANDLER(andb_di) {
3364 /* $d5 BITB direct -**0- */
3365 OP_HANDLER(bitb_di) {
3373 /* $d6 LDB direct -**0- */
3374 OP_HANDLER(ldb_di) {
3380 /* $d7 STB direct -**0- */
3381 OP_HANDLER(stb_di) {
3388 /* $d8 EORB direct -**0- */
3389 OP_HANDLER(eorb_di) {
3397 /* $d9 ADCB direct ***** */
3398 OP_HANDLER(adcb_di) {
3401 r = B + t + (CC & CC_C);
3403 SET_HNZVC8(B, t, r);
3407 /* $dA ORB direct -**0- */
3408 OP_HANDLER(orb_di) {
3416 /* $dB ADDB direct ***** */
3417 OP_HANDLER(addb_di) {
3422 SET_HNZVC8(B, t, r);
3426 /* $dC LDD direct -**0- */
3427 OP_HANDLER(ldd_di) {
3433 /* $dD STD direct -**0- */
3434 OP_HANDLER(std_di) {
3441 /* $dE LDU (LDS) direct -**0- */
3442 OP_HANDLER(ldu_di) {
3448 /* $10dE LDS direct -**0- */
3449 OP_HANDLER(lds_di) {
3453 int_state |= MC6809_LDS;
3454 // ->int_state |= M6809_LDS;
3457 /* $dF STU (STS) direct -**0- */
3458 OP_HANDLER(stu_di) {
3465 /* $10dF STS direct -**0- */
3466 OP_HANDLER(sts_di) {
3473 /* $e0 SUBB indexed ?**** */
3474 OP_HANDLER(subb_ix) {
3476 fetch_effective_address();
3480 SET_FLAGS8(B, t, r);
3484 /* $e1 CMPB indexed ?**** */
3485 OP_HANDLER(cmpb_ix) {
3487 fetch_effective_address();
3491 SET_FLAGS8(B, t, r);
3494 /* $e2 SBCB indexed ?**** */
3495 OP_HANDLER(sbcb_ix) {
3497 fetch_effective_address();
3499 r = B - t - (CC & CC_C);
3501 SET_FLAGS8(B, t, r);
3505 /* $e3 ADDD indexed -**** */
3506 OP_HANDLER(addd_ix) {
3509 fetch_effective_address();
3514 SET_FLAGS16(d, b, r);
3518 /* $e4 ANDB indexed -**0- */
3519 OP_HANDLER(andb_ix) {
3520 fetch_effective_address();
3526 /* $e5 BITB indexed -**0- */
3527 OP_HANDLER(bitb_ix) {
3529 fetch_effective_address();
3535 /* $e6 LDB indexed -**0- */
3536 OP_HANDLER(ldb_ix) {
3537 fetch_effective_address();
3543 /* $e7 STB indexed -**0- */
3544 OP_HANDLER(stb_ix) {
3545 fetch_effective_address();
3551 /* $e8 EORB indexed -**0- */
3552 OP_HANDLER(eorb_ix) {
3553 fetch_effective_address();
3559 /* $e9 ADCB indexed ***** */
3560 OP_HANDLER(adcb_ix) {
3562 fetch_effective_address();
3564 r = B + t + (CC & CC_C);
3566 SET_HNZVC8(B, t, r);
3570 /* $eA ORB indexed -**0- */
3571 OP_HANDLER(orb_ix) {
3572 fetch_effective_address();
3578 /* $eB ADDB indexed ***** */
3579 OP_HANDLER(addb_ix) {
3581 fetch_effective_address();
3585 SET_HNZVC8(B, t, r);
3589 /* $eC LDD indexed -**0- */
3590 OP_HANDLER(ldd_ix) {
3591 fetch_effective_address();
3597 /* $eD STD indexed -**0- */
3598 OP_HANDLER(std_ix) {
3599 fetch_effective_address();
3605 /* $eE LDU (LDS) indexed -**0- */
3606 OP_HANDLER(ldu_ix) {
3607 fetch_effective_address();
3613 /* $10eE LDS indexed -**0- */
3614 OP_HANDLER(lds_ix) {
3615 fetch_effective_address();
3619 int_state |= MC6809_LDS;
3620 // ->int_state |= M6809_LDS;
3623 /* $eF STU (STS) indexed -**0- */
3624 OP_HANDLER(stu_ix) {
3625 fetch_effective_address();
3631 /* $10eF STS indexed -**0- */
3632 OP_HANDLER(sts_ix) {
3633 fetch_effective_address();
3639 /* $f0 SUBB extended ?**** */
3640 OP_HANDLER(subb_ex) {
3645 SET_FLAGS8(B, t, r);
3649 /* $f1 CMPB extended ?**** */
3650 OP_HANDLER(cmpb_ex) {
3655 SET_FLAGS8(B, t, r);
3658 /* $f2 SBCB extended ?**** */
3659 OP_HANDLER(sbcb_ex) {
3662 r = B - t - (CC & CC_C);
3664 SET_FLAGS8(B, t, r);
3668 /* $f3 ADDD extended -**** */
3669 OP_HANDLER(addd_ex) {
3676 SET_FLAGS16(d, b.d, r);
3680 /* $f4 ANDB extended -**0- */
3681 OP_HANDLER(andb_ex) {
3689 /* $f5 BITB extended -**0- */
3690 OP_HANDLER(bitb_ex) {
3698 /* $f6 LDB extended -**0- */
3699 OP_HANDLER(ldb_ex) {
3705 /* $f7 STB extended -**0- */
3706 OP_HANDLER(stb_ex) {
3713 /* $f8 EORB extended -**0- */
3714 OP_HANDLER(eorb_ex) {
3722 /* $f9 ADCB extended ***** */
3723 OP_HANDLER(adcb_ex) {
3726 r = B + t + (CC & CC_C);
3728 SET_HNZVC8(B, t, r);
3732 /* $fA ORB extended -**0- */
3733 OP_HANDLER(orb_ex) {
3741 /* $fB ADDB extended ***** */
3742 OP_HANDLER(addb_ex) {
3747 SET_HNZVC8(B, t, r);
3751 /* $fC LDD extended -**0- */
3752 OP_HANDLER(ldd_ex) {
3758 /* $fD STD extended -**0- */
3759 OP_HANDLER(std_ex) {
3766 /* $fE LDU (LDS) extended -**0- */
3767 OP_HANDLER(ldu_ex) {
3773 /* $10fE LDS extended -**0- */
3774 OP_HANDLER(lds_ex) {
3778 int_state |= MC6809_LDS;
3779 // ->int_state |= M6809_LDS;
3782 /* $fF STU (STS) extended -**0- */
3783 OP_HANDLER(stu_ex) {
3790 /* $10fF STS extended -**0- */
3791 OP_HANDLER(sts_ex) {
3800 OP_HANDLER(pref10) {
3801 uint8 ireg2 = ROP_ARG(PCD);
3888 // case 0x8f: flag16_im();->cycle=4; break; // 20130417
3941 // case 0xcf: flag16_im();->cycle=4; break;
3969 // default: PC--; cpu_execline(); icount -= 2; break; /* 121228 Change Handring Exception by K.Ohta */
3974 OP_HANDLER(pref11) {
3975 uint8 ireg2 = ROP_ARG(PCD);
4022 // default: PC--; cpu_execline(); icount -= 2 ; break; /* 121228 Change Handring Exception by K.Ohta */
4026 #define STATE_VERSION 1
4028 void MC6809::save_state(FILEIO* state_fio)
4030 state_fio->FputUint32(STATE_VERSION);
4031 state_fio->FputInt32(this_device_id);
4033 state_fio->FputInt32(icount);
4034 state_fio->FputInt32(extra_icount);
4035 state_fio->FputUint32(int_state);
4037 state_fio->FputUint32(pc.d);
4038 state_fio->FputUint32(ppc.d);
4039 state_fio->FputUint32(acc.d);
4040 state_fio->FputUint32(dp.d);
4041 state_fio->FputUint32(u.d);
4042 state_fio->FputUint32(s.d);
4043 state_fio->FputUint32(x.d);
4044 state_fio->FputUint32(y.d);
4045 state_fio->FputUint8(cc);
4046 state_fio->FputUint32(ea.d);
4050 bool MC6809::load_state(FILEIO* state_fio)
4052 if(state_fio->FgetUint32() != STATE_VERSION) {
4055 if(state_fio->FgetInt32() != this_device_id) {
4059 icount = state_fio->FgetInt32();
4060 extra_icount = state_fio->FgetInt32();
4061 int_state = state_fio->FgetUint32();
4063 pc.d = state_fio->FgetUint32();
4064 ppc.d = state_fio->FgetUint32();
4065 acc.d = state_fio->FgetUint32();
4066 dp.d = state_fio->FgetUint32();
4067 u.d = state_fio->FgetUint32();
4068 s.d = state_fio->FgetUint32();
4069 x.d = state_fio->FgetUint32();
4070 y.d = state_fio->FgetUint32();
4071 cc = state_fio->FgetUint8();
4072 ea.d = state_fio->FgetUint32();