2 Skelton for retropc emulator
5 Author : Takeda.Toshiya
9 Notes from K.Ohta <whatisthis.sowhat _at_ gmail.com> at Jan 16, 2015:
10 All of undocumented instructions (i.e. ngc, flag16) of MC6809(not HD6309) are written by me.
11 These behaviors of undocumented insns are refered from "vm/cpu_x86.asm" (ia32 assembly codefor nasm) within XM7
12 written by Ryu Takegami , and older article wrote in magazine, "I/O" at 1985.
13 But, these C implements are written from scratch by me , and I tested many years at XM7/SDL.
14 Perhaps, these insns. are not implement MAME/MESS yet.
17 // Fixed IRQ/FIRQ by Mr.Sasaji at 2011.06.17
22 #include "./mc6809_consts.h"
28 #define OP_HANDLER(_name) void MC6809::_name (void)
30 void (__FASTCALL MC6809::*MC6809::m6809_optable[0x100]) (void) =
32 /* 0xX0, 0xX1, 0xX2, 0xX3, 0xX4, 0xX5, 0xX6, 0xX7,
33 0xX8, 0xX9, 0xXA, 0xXB, 0xXC, 0xXD, 0xXE, 0xXF */
36 &MC6809::neg_di, &MC6809::neg_di, &MC6809::ngc_di, &MC6809::com_di,
37 &MC6809::lsr_di, &MC6809::lsr_di, &MC6809::ror_di, &MC6809::asr_di,
38 &MC6809::asl_di, &MC6809::rol_di, &MC6809::dec_di, &MC6809::dcc_di,
39 &MC6809::inc_di, &MC6809::tst_di, &MC6809::jmp_di, &MC6809::clr_di,
41 &MC6809::pref10, &MC6809::pref11, &MC6809::nop, &MC6809::sync_09,
42 &MC6809::trap, &MC6809::trap, &MC6809::lbra, &MC6809::lbsr,
43 &MC6809::aslcc_in, &MC6809::daa, &MC6809::orcc, &MC6809::nop,
44 &MC6809::andcc, &MC6809::sex, &MC6809::exg, &MC6809::tfr,
46 &MC6809::bra, &MC6809::brn, &MC6809::bhi, &MC6809::bls,
47 &MC6809::bcc, &MC6809::bcs, &MC6809::bne, &MC6809::beq,
48 &MC6809::bvc, &MC6809::bvs, &MC6809::bpl, &MC6809::bmi,
49 &MC6809::bge, &MC6809::blt, &MC6809::bgt, &MC6809::ble,
51 &MC6809::leax, &MC6809::leay, &MC6809::leas, &MC6809::leau,
52 &MC6809::pshs, &MC6809::puls, &MC6809::pshu, &MC6809::pulu,
53 &MC6809::andcc, &MC6809::rts, &MC6809::abx, &MC6809::rti,
54 &MC6809::cwai, &MC6809::mul, &MC6809::rst, &MC6809::swi,
56 &MC6809::nega, &MC6809::nega, &MC6809::ngca, &MC6809::coma,
57 &MC6809::lsra, &MC6809::lsra, &MC6809::rora, &MC6809::asra,
58 &MC6809::asla, &MC6809::rola, &MC6809::deca, &MC6809::dcca,
59 &MC6809::inca, &MC6809::tsta, &MC6809::clca, &MC6809::clra,
61 &MC6809::negb, &MC6809::negb, &MC6809::ngcb, &MC6809::comb,
62 &MC6809::lsrb, &MC6809::lsrb, &MC6809::rorb, &MC6809::asrb,
63 &MC6809::aslb, &MC6809::rolb, &MC6809::decb, &MC6809::dccb,
64 &MC6809::incb, &MC6809::tstb, &MC6809::clcb, &MC6809::clrb,
66 &MC6809::neg_ix, &MC6809::neg_ix, &MC6809::ngc_ix, &MC6809::com_ix,
67 &MC6809::lsr_ix, &MC6809::lsr_ix, &MC6809::ror_ix, &MC6809::asr_ix,
68 &MC6809::asl_ix, &MC6809::rol_ix, &MC6809::dec_ix, &MC6809::dcc_ix,
69 &MC6809::inc_ix, &MC6809::tst_ix, &MC6809::jmp_ix, &MC6809::clr_ix,
71 &MC6809::neg_ex, &MC6809::neg_ex, &MC6809::ngc_ex, &MC6809::com_ex,
72 &MC6809::lsr_ex, &MC6809::lsr_ex, &MC6809::ror_ex, &MC6809::asr_ex,
73 &MC6809::asl_ex, &MC6809::rol_ex, &MC6809::dec_ex, &MC6809::dcc_ex,
74 &MC6809::inc_ex, &MC6809::tst_ex, &MC6809::jmp_ex, &MC6809::clr_ex,
76 &MC6809::suba_im, &MC6809::cmpa_im, &MC6809::sbca_im, &MC6809::subd_im,
77 &MC6809::anda_im, &MC6809::bita_im, &MC6809::lda_im, &MC6809::flag8_im,
78 &MC6809::eora_im, &MC6809::adca_im, &MC6809::ora_im, &MC6809::adda_im,
79 &MC6809::cmpx_im, &MC6809::bsr, &MC6809::ldx_im, &MC6809::flag16_im,
81 &MC6809::suba_di, &MC6809::cmpa_di, &MC6809::sbca_di, &MC6809::subd_di,
82 &MC6809::anda_di, &MC6809::bita_di, &MC6809::lda_di, &MC6809::sta_di,
83 &MC6809::eora_di, &MC6809::adca_di, &MC6809::ora_di, &MC6809::adda_di,
84 &MC6809::cmpx_di, &MC6809::jsr_di, &MC6809::ldx_di, &MC6809::stx_di,
86 &MC6809::suba_ix, &MC6809::cmpa_ix, &MC6809::sbca_ix, &MC6809::subd_ix,
87 &MC6809::anda_ix, &MC6809::bita_ix, &MC6809::lda_ix, &MC6809::sta_ix,
88 &MC6809::eora_ix, &MC6809::adca_ix, &MC6809::ora_ix, &MC6809::adda_ix,
89 &MC6809::cmpx_ix, &MC6809::jsr_ix, &MC6809::ldx_ix, &MC6809::stx_ix,
91 &MC6809::suba_ex, &MC6809::cmpa_ex, &MC6809::sbca_ex, &MC6809::subd_ex,
92 &MC6809::anda_ex, &MC6809::bita_ex, &MC6809::lda_ex, &MC6809::sta_ex,
93 &MC6809::eora_ex, &MC6809::adca_ex, &MC6809::ora_ex, &MC6809::adda_ex,
94 &MC6809::cmpx_ex, &MC6809::jsr_ex, &MC6809::ldx_ex, &MC6809::stx_ex,
96 &MC6809::subb_im, &MC6809::cmpb_im, &MC6809::sbcb_im, &MC6809::addd_im,
97 &MC6809::andb_im, &MC6809::bitb_im, &MC6809::ldb_im, &MC6809::flag8_im,
98 &MC6809::eorb_im, &MC6809::adcb_im, &MC6809::orb_im, &MC6809::addb_im,
99 &MC6809::ldd_im, &MC6809::trap, &MC6809::ldu_im, &MC6809::flag16_im,
101 &MC6809::subb_di, &MC6809::cmpb_di, &MC6809::sbcb_di, &MC6809::addd_di,
102 &MC6809::andb_di, &MC6809::bitb_di, &MC6809::ldb_di, &MC6809::stb_di,
103 &MC6809::eorb_di, &MC6809::adcb_di, &MC6809::orb_di, &MC6809::addb_di,
104 &MC6809::ldd_di, &MC6809::std_di, &MC6809::ldu_di, &MC6809::stu_di,
106 &MC6809::subb_ix, &MC6809::cmpb_ix, &MC6809::sbcb_ix, &MC6809::addd_ix,
107 &MC6809::andb_ix, &MC6809::bitb_ix, &MC6809::ldb_ix, &MC6809::stb_ix,
108 &MC6809::eorb_ix, &MC6809::adcb_ix, &MC6809::orb_ix, &MC6809::addb_ix,
109 &MC6809::ldd_ix, &MC6809::std_ix, &MC6809::ldu_ix, &MC6809::stu_ix,
111 &MC6809::subb_ex, &MC6809::cmpb_ex, &MC6809::sbcb_ex, &MC6809::addd_ex,
112 &MC6809::andb_ex, &MC6809::bitb_ex, &MC6809::ldb_ex, &MC6809::stb_ex,
113 &MC6809::eorb_ex, &MC6809::adcb_ex, &MC6809::orb_ex, &MC6809::addb_ex,
114 &MC6809::ldd_ex, &MC6809::std_ex, &MC6809::ldu_ex, &MC6809::stu_ex
117 /* macros for branch instructions */
118 inline void MC6809::BRANCH(bool cond)
127 inline void MC6809::LBRANCH(bool cond)
137 /* macros for setting/getting registers in TFR/EXG instructions */
139 inline pair32_t MC6809::RM16_PAIR(uint32_t addr)
144 b.b.l = RM((addr + 1));
148 inline void MC6809::WM16(uint32_t Addr, pair32_t *p)
151 WM((Addr + 1), p->b.l);
156 //extar_tmp_count += extra_icount;
160 int_state &= MC6809_HALT_BIT;
164 DPD = 0; /* Reset direct page register */
172 //#if defined(_FM7) || defined(_FM8) || defined(_FM77_VARIANTS) || defined(_FM77AV_VARIANTS)
174 if((req_halt_on) && !(req_halt_off)) {
175 int_state |= MC6809_HALT_BIT;
177 req_halt_on = req_halt_off = false;
179 if((int_state & MC6809_HALT_BIT) != 0) {
180 write_signals(&outputs_bus_ba, 0xffffffff);
181 write_signals(&outputs_bus_bs, 0xffffffff);
183 write_signals(&outputs_bus_ba, 0x00000000);
184 write_signals(&outputs_bus_bs, 0x00000000);
188 CC |= CC_II; /* IRQ disabled */
189 CC |= CC_IF; /* FIRQ disabled */
191 pPC = RM16_PAIR(0xfffe);
196 void MC6809::initialize()
198 DEVICE::initialize();
203 req_halt_on = req_halt_off = false;
204 cycles_tmp_count = 0;
209 cycles_tmp_count = 0;
213 // if(config.print_statistics) {
214 register_frame_event(this);
219 void (__FASTCALL MC6809::*_op)(void);
220 for(int i = 0; i < 0x100; i++) {
221 _op = (void (__FASTCALL MC6809::*)(void))m6809_optable[i];
225 d_mem_stored = d_mem;
226 d_debugger->set_context_mem(d_mem);
231 void MC6809::event_frame()
233 if(frames_count < 0) {
234 cycles_tmp_count = total_icount;
241 } else if(frames_count >= 16) {
242 uint64_t _icount = total_icount - cycles_tmp_count;
243 if(config.print_statistics) {
244 out_debug_log(_T("INFO: 16 frames done.\nINFO: CLOCKS = %ld INSNS = %d EXTRA_ICOUNT = %d \nINFO: NMI# = %d FIRQ# = %d IRQ# = %d"), _icount, insns_count, extra_tmp_count, nmi_count, firq_count, irq_count);
246 cycles_tmp_count = total_icount;
258 void MC6809::write_signal(int id, uint32_t data, uint32_t mask)
260 if(id == SIG_CPU_IRQ) {
262 int_state |= MC6809_IRQ_BIT;
265 int_state &= ~MC6809_IRQ_BIT;
267 } else if(id == SIG_CPU_FIRQ) {
269 int_state |= MC6809_FIRQ_BIT;
272 int_state &= ~MC6809_FIRQ_BIT;
274 } else if(id == SIG_CPU_NMI) {
276 int_state |= MC6809_NMI_BIT;
279 int_state &= ~MC6809_NMI_BIT;
281 } else if(id == SIG_CPU_BUSREQ) {
284 req_halt_off = false;
285 int_state |= MC6809_HALT_BIT;
289 req_halt_off = false;
290 int_state &= ~MC6809_HALT_BIT;
292 } else if(id == SIG_CPU_HALTREQ) {
295 //int_state |= MC6809_HALT_BIT;
300 //int_state &= ~MC6809_HALT_BIT;
302 } else if(id == SIG_CPU_WAIT_FACTOR) {
303 waitfactor = data; // 65536.
307 void MC6809::cpu_nmi_push(void)
309 if ((int_state & MC6809_CWAI_IN) == 0) {
323 void MC6809::cpu_nmi_fetch_vector_address(void)
325 pPC = RM16_PAIR(0xfffc);
326 // printf("NMI occured PC=0x%04x VECTOR=%04x SP=%04x \n",rpc.w.l,pPC.w.l,S);
327 int_state |= MC6809_CWAI_OUT;
328 //int_state &= ~(MC6809_NMI_BIT | MC6809_SYNC_IN | MC6809_SYNC_OUT | MC6809_CWAI_IN); // $FF1E
334 void MC6809::cpu_firq_fetch_vector_address(void)
336 pPC = RM16_PAIR(0xfff6);
337 int_state |= MC6809_CWAI_OUT;
338 int_state &= ~(MC6809_SYNC_IN | MC6809_SYNC_OUT );
342 void MC6809::cpu_firq_push(void)
344 //pair32_t rpc = pPC;
345 if ((int_state & MC6809_CWAI_IN) == 0) {
351 // printf("Firq occured PC=0x%04x VECTOR=%04x SP=%04x \n",rpc.w.l,pPC.w.l,S);
353 void MC6809::cpu_irq_push(void)
355 if ((int_state & MC6809_CWAI_IN) == 0) {
367 void MC6809::cpu_irq_fetch_vector_address(void)
369 //pair32_t rpc = pPC;
370 pPC = RM16_PAIR(0xfff8);
371 int_state |= MC6809_CWAI_OUT;
372 int_state &= ~(MC6809_SYNC_IN | MC6809_SYNC_OUT);
375 void MC6809::cpu_wait(int clocks)
378 if(clocks < 0) return;
379 if(waitfactor == 0) return;
380 waitcount += (waitfactor * (uint32_t)clocks);
381 if(waitcount >= 65536) {
382 ncount = waitcount >> 16;
383 waitcount = waitcount - (ncount << 16);
385 if(ncount > 0) extra_icount += ncount;
388 int MC6809::run(int clock)
391 int first_icount = 0;
392 int passed_icount = 0;
393 first_icount = icount;
394 if(extra_icount > 0) {
395 extra_tmp_count += extra_icount;
398 if((req_halt_on) && !(req_halt_off)) {
399 int_state |= MC6809_HALT_BIT;
400 } else if(req_halt_on && req_halt_off) { // HALT OFF
401 int_state &= ~MC6809_HALT_BIT;
402 req_halt_on = req_halt_off = false;
405 if ((int_state & MC6809_HALT_BIT) != 0) { // 0x80
411 first_icount = icount;
413 write_signals(&outputs_bus_ba, 0);
414 write_signals(&outputs_bus_bs, 0);
417 icount -= extra_icount;
419 passed_icount = first_icount - icount;
420 total_icount += passed_icount;
422 write_signals(&outputs_bus_ba, 0xffffffff);
423 write_signals(&outputs_bus_bs, 0xffffffff);
425 cpu_wait(passed_icount);
426 return passed_icount;
429 icount -= extra_icount;
431 passed_icount = first_icount - icount;
432 total_icount += passed_icount;
434 cpu_wait(passed_icount);
435 return passed_icount;
438 if(busreq) { // Exit from BUSREQ state.
439 if((int_state & MC6809_SYNC_IN) != 0) {
440 write_signals(&outputs_bus_ba, 0xffffffff);
442 write_signals(&outputs_bus_ba, 0x00000000);
444 write_signals(&outputs_bus_bs, 0x00000000);
447 if((int_state & MC6809_INSN_HALT) != 0) { // 0x80
448 if(clock <= 1) clock = 1;
450 first_icount = icount;
452 RM(PCD); //Will save.Need to keep.
455 icount -= extra_icount;
456 passed_icount = first_icount - icount;
460 total_icount += passed_icount;
461 cpu_wait(passed_icount);
462 return passed_icount;
468 if ((int_state & (MC6809_NMI_BIT | MC6809_FIRQ_BIT | MC6809_IRQ_BIT)) != 0) { // 0x0007
469 if ((int_state & MC6809_NMI_BIT) == 0)
471 int_state &= ~MC6809_SYNC_IN; // Thanks to Ryu Takegami.
472 write_signals(&outputs_bus_ba, 0x00000000);
473 write_signals(&outputs_bus_bs, 0x00000000);
474 if((int_state & MC6809_CWAI_IN) == 0) {
479 write_signals(&outputs_bus_bs, 0xffffffff);
480 CC = CC | CC_II | CC_IF; // 0x50
482 cpu_nmi_fetch_vector_address();
484 write_signals(&outputs_bus_bs, 0x00000000);
485 int_state &= ~(MC6809_NMI_BIT | MC6809_SYNC_IN | MC6809_SYNC_OUT); // $FF1E
488 // OK, none interrupts.
492 if ((int_state & MC6809_FIRQ_BIT) != 0) {
493 int_state &= ~MC6809_SYNC_IN; // Moved to before checking MASK.Thanks to Ryu Takegami.
494 if ((CC & CC_IF) != 0)
496 write_signals(&outputs_bus_bs, 0x00000000);
497 write_signals(&outputs_bus_ba, 0x00000000);
498 if((int_state & MC6809_CWAI_IN) == 0) {
499 CC = CC & (uint8_t)(~CC_E);
503 write_signals(&outputs_bus_bs, 0xffffffff);
504 CC = CC | CC_II | CC_IF; // 0x50
506 cpu_firq_fetch_vector_address();
508 write_signals(&outputs_bus_bs, 0x00000000);
509 int_state &= ~(MC6809_SYNC_IN | MC6809_SYNC_OUT); // $FF1E
514 if ((int_state & MC6809_IRQ_BIT) != 0) {
515 int_state &= ~MC6809_SYNC_IN; // Moved to before checking MASK.Thanks to Ryu Takegami.
516 if ((CC & CC_II) != 0)
518 write_signals(&outputs_bus_bs, 0x00000000);
519 write_signals(&outputs_bus_ba, 0x00000000);
520 if((int_state & MC6809_CWAI_IN) == 0) {
525 write_signals(&outputs_bus_bs, 0xffffffff);
527 CC = CC | CC_II; // 0x50
528 cpu_irq_fetch_vector_address();
530 write_signals(&outputs_bus_bs, 0x00000000);
531 int_state &= ~(MC6809_SYNC_IN | MC6809_SYNC_OUT); // $FF1E
542 if((int_state & MC6809_CWAI_IN) != 0) {
543 int_state &= ~MC6809_CWAI_IN;
545 if(clock >= 0) icount += clock;
546 first_icount = icount;
549 icount -= extra_icount;
550 passed_icount = first_icount - icount;
552 total_icount += (uint64_t)passed_icount;
553 cpu_wait(passed_icount);
555 if((icount <= 0) || (clock <= passed_icount)) return passed_icount;
556 clock -= passed_icount;
558 return passed_icount;
563 if((int_state & MC6809_SYNC_IN) != 0) {
564 int tmp_passed_icount = 0;
565 first_icount = icount;
566 if(clock < 1) clock = 1;
567 icount -= extra_icount;
571 tmp_passed_icount = first_icount - icount;
572 total_icount += (uint64_t)passed_icount;
573 cpu_wait(tmp_passed_icount);
574 return passed_icount + tmp_passed_icount;
576 if((int_state & MC6809_CWAI_IN) == 0) {
578 // run only one opcode
579 int tmp_passed_icount = 0;
580 first_icount = icount;
583 tmp_passed_icount = first_icount - icount;
584 cpu_wait(tmp_passed_icount);
585 return passed_icount + tmp_passed_icount;;
587 // run cpu while given clocks
588 int tmp_passed_icount = 0;
590 first_icount = icount;
591 while((icount > 0) && (!(req_halt_on) && !(req_halt_off)) && (!busreq)) {
595 tmp_passed_icount = first_icount - icount;
596 cpu_wait(tmp_passed_icount);
597 return tmp_passed_icount + passed_icount;
600 int tmp_passed_icount = 0;
601 first_icount = icount;
602 if(clock < 1) clock = 1;
603 icount -= extra_icount;
607 tmp_passed_icount = first_icount - icount;
608 total_icount += tmp_passed_icount;
609 cpu_wait(tmp_passed_icount);
610 return passed_icount + tmp_passed_icount;
615 void MC6809::run_one_opecode()
618 bool now_debugging = d_debugger->now_debugging;
620 d_debugger->check_break_points(PC);
621 if(d_debugger->now_suspended) {
622 d_debugger->now_waiting = true;
623 emu->start_waiting_in_debugger();
624 while(d_debugger->now_debugging && d_debugger->now_suspended) {
625 emu->process_waiting_in_debugger();
627 emu->finish_waiting_in_debugger();
628 d_debugger->now_waiting = false;
630 if(d_debugger->now_debugging) {
633 now_debugging = false;
636 d_debugger->add_cpu_trace(PC & 0xffff);
637 int first_icount = icount;
639 uint8_t ireg = ROP(PCD);
641 icount -= cycles1[ireg];
642 icount -= extra_icount;
645 total_icount += first_icount - icount;
648 if(!d_debugger->now_going) {
649 d_debugger->now_suspended = true;
651 d_mem = d_mem_stored;
654 d_debugger->add_cpu_trace(PC & 0xffff);
655 int first_icount = icount;
657 uint8_t ireg = ROP(PCD);
659 icount -= cycles1[ireg];
660 icount -= extra_icount;
663 total_icount += first_icount - icount;
667 d_debugger->add_cpu_trace(PC & 0xffff);
668 uint8_t ireg = ROP(PCD);
670 icount -= cycles1[ireg];
671 icount -= extra_icount;
677 void MC6809::debugger_hook()
680 bool now_debugging = d_debugger->now_debugging;
682 d_debugger->check_break_points(PC);
683 if(d_debugger->now_suspended) {
684 d_debugger->now_waiting = true;
685 emu->start_waiting_in_debugger();
686 while(d_debugger->now_debugging && d_debugger->now_suspended) {
687 emu->process_waiting_in_debugger();
689 emu->finish_waiting_in_debugger();
690 d_debugger->now_waiting = false;
692 if(d_debugger->now_debugging) {
695 now_debugging = false;
698 //d_debugger->add_cpu_trace(PC);
699 int first_icount = icount;
702 if(!d_debugger->now_going) {
703 d_debugger->now_suspended = true;
705 d_mem = d_mem_stored;
711 void MC6809::op(uint8_t ireg)
713 //printf("CPU(%08x) PC=%04x OP=%02x %02x %02x %02x %02x\n", (void *)this, PC, ireg, RM(PC), RM(PC + 1), RM(PC + 2), RM(PC + 3));
715 (this->*m6809_main[ireg])();
719 void MC6809::write_debug_data8(uint32_t addr, uint32_t data)
721 if(__USE_DEBUGGER) d_mem_stored->write_data8(addr, data);
724 uint32_t MC6809::read_debug_data8(uint32_t addr)
727 return d_mem_stored->read_data8(addr);
732 void MC6809::write_debug_io8(uint32_t addr, uint32_t data)
734 if(__USE_DEBUGGER) d_mem_stored->write_io8(addr, data);
737 uint32_t MC6809::read_debug_io8(uint32_t addr)
740 uint8_t val = d_mem_stored->read_io8(addr);
746 inline void MC6809::fetch_effective_address()
749 uint8_t upper, lower;
753 upper = (postbyte >> 4) & 0x0f;
754 lower = postbyte & 0x0f;
781 fetch_effective_address_IDX(upper, lower);
785 icount -= index_cycle_em[postbyte];
788 inline void MC6809::fetch_effective_address_IDX(uint8_t upper, uint8_t lower)
790 bool indirect = false;
795 indirect = ((upper & 0x01) != 0) ? true : false;
797 switch ((upper >> 1) & 0x03) { // $8-$f >> 1 = $4 - $7 : delete bit2
816 *reg = *reg & 0xffff;
821 *reg = *reg & 0xffff;
825 *reg = *reg & 0xffff;
830 *reg = *reg & 0xffff;
837 EA = *reg + SIGNED(B);
841 EA = *reg + SIGNED(A);
845 EA = *reg + SIGNED(bx_p);
851 case 0x0a: // Undocumented
861 EA = PC + SIGNED(bx_p);
863 case 0x0d: // xxxx,pc
867 case 0x0e: // Undocumented
875 // $9x,$bx,$dx,$fx = INDIRECT
878 EAP = RM16_PAIR(pp.d);
882 #define IIError() illegal()
886 //logerror("M6809: illegal opcode at %04x\n",PC);
887 //printf("M6809: illegal opcode at %04x %02x %02x %02x %02x %02x \n",
888 // PC - 2, RM(PC - 2), RM(PC - 1), RM(PC), RM(PC + 1), RM(PC + 2));
892 inline uint8_t MC6809::GET_INDEXED_DATA(void)
895 fetch_effective_address();
900 inline pair32_t MC6809::GET_INDEXED_DATA16(void)
903 fetch_effective_address();
909 inline void MC6809::NEG_MEM(uint8_t a_neg)
912 r_neg = 0 - (uint16_t)a_neg;
914 SET_FLAGS8(0, a_neg, r_neg);
918 inline uint8_t MC6809::NEG_REG(uint8_t a_neg)
921 r_neg = 0 - (uint16_t)a_neg;
923 SET_FLAGS8(0, a_neg, r_neg);
924 return (uint8_t)r_neg;
929 inline void MC6809::COM_MEM(uint8_t a_com)
939 inline uint8_t MC6809::COM_REG(uint8_t r_com)
948 inline void MC6809::LSR_MEM(uint8_t t)
951 CC = CC | (t & CC_C);
957 inline uint8_t MC6809::LSR_REG(uint8_t r)
966 inline void MC6809::ROR_MEM(uint8_t t)
969 r = (CC & CC_C) << 7;
978 inline uint8_t MC6809::ROR_REG(uint8_t t)
981 r = (CC & CC_C) << 7;
991 inline void MC6809::ASR_MEM(uint8_t t)
995 CC = CC | (t & CC_C);
996 r = (t & 0x80) | (t >> 1);
1003 inline uint8_t MC6809::ASR_REG(uint8_t t)
1007 CC = CC | (t & CC_C);
1008 r = (t & 0x80) | (t >> 1);
1015 inline void MC6809::ASL_MEM(uint8_t t)
1018 tt = (uint16_t)t & 0x00ff;
1021 SET_FLAGS8(tt, tt, r);
1023 WM(EAD, (uint8_t)r);
1026 inline uint8_t MC6809::ASL_REG(uint8_t t)
1029 tt = (uint16_t)t & 0x00ff;
1032 SET_FLAGS8(tt, tt, r);
1037 inline void MC6809::ROL_MEM(uint8_t t)
1040 tt = (uint16_t)t & 0x00ff;
1041 r = (CC & CC_C) | (tt << 1);
1046 // if((r & 0x80) == 0)SEV;
1048 // if((r & 0x80) != 0) SEV;
1050 SET_FLAGS8(tt, tt, r);
1051 WM(EAD, (uint8_t)r);
1054 inline uint8_t MC6809::ROL_REG(uint8_t t)
1057 tt = (uint16_t)t & 0x00ff;
1058 r = (CC & CC_C) | (tt << 1);
1063 // if((r & 0x80) == 0) SEV;
1065 // if((r & 0x80) != 0) SEV;
1067 SET_FLAGS8(tt, tt, r);
1071 inline void MC6809::DEC_MEM(uint8_t t)
1080 inline uint8_t MC6809::DEC_REG(uint8_t t)
1089 inline void MC6809::DCC_MEM(uint8_t t)
1103 inline uint8_t MC6809::DCC_REG(uint8_t t)
1117 inline void MC6809::INC_MEM(uint8_t t)
1119 uint16_t tt = t + 1;
1125 inline uint8_t MC6809::INC_REG(uint8_t t)
1127 uint16_t tt = t + 1;
1133 inline void MC6809::TST_MEM(uint8_t t)
1139 inline uint8_t MC6809::TST_REG(uint8_t t)
1146 inline uint8_t MC6809::CLC_REG(uint8_t t)
1156 inline void MC6809::CLR_MEM(uint8_t t)
1163 inline uint8_t MC6809::CLR_REG(uint8_t t)
1170 inline uint8_t MC6809::SUB8_REG(uint8_t reg, uint8_t data)
1173 r = (uint16_t)reg - (uint16_t)data;
1176 SET_FLAGS8(reg, data, r);
1180 inline uint8_t MC6809::CMP8_REG(uint8_t reg, uint8_t data)
1183 r = (uint16_t)reg - (uint16_t)data;
1186 SET_FLAGS8(reg, data, r);
1190 inline uint8_t MC6809::SBC8_REG(uint8_t reg, uint8_t data)
1193 uint8_t cc_c = CC & CC_C;
1194 r = (uint16_t)reg - (uint16_t)data - (uint16_t)cc_c;
1196 SET_FLAGS8(reg, (data + cc_c) , r);
1200 inline uint8_t MC6809::AND8_REG(uint8_t reg, uint8_t data)
1209 inline uint8_t MC6809::BIT8_REG(uint8_t reg, uint8_t data)
1215 SET_V8(reg, data, r);
1219 inline uint8_t MC6809::EOR8_REG(uint8_t reg, uint8_t data)
1228 inline uint8_t MC6809::OR8_REG(uint8_t reg, uint8_t data)
1237 inline uint8_t MC6809::ADD8_REG(uint8_t reg, uint8_t data)
1240 t = (uint16_t) data;
1244 SET_HNZVC8(reg, t, r);
1248 inline uint8_t MC6809::ADC8_REG(uint8_t reg, uint8_t data)
1251 uint8_t c_cc = CC & CC_C;
1252 t = (uint16_t) data;
1256 SET_HNZVC8(reg, (t + c_cc), r);
1260 inline uint8_t MC6809::LOAD8_REG(uint8_t reg)
1267 inline void MC6809::STORE8_REG(uint8_t reg)
1274 inline uint16_t MC6809::LOAD16_REG(uint16_t reg)
1282 inline uint16_t MC6809::SUB16_REG(uint16_t reg, uint16_t data)
1288 SET_FLAGS16(d, data, r);
1292 inline uint16_t MC6809::ADD16_REG(uint16_t reg, uint16_t data)
1296 r = d + (uint32_t)data;
1298 SET_HNZVC16(d, data, r);
1302 inline uint16_t MC6809::CMP16_REG(uint16_t reg, uint16_t data)
1308 SET_FLAGS16(d, data, r);
1312 inline void MC6809::STORE16_REG(pair32_t *p)
1320 /* $00 NEG direct ?**** */
1321 OP_HANDLER(neg_di) {
1327 /* $01 Undefined Neg */
1328 /* $03 COM direct -**01 */
1329 OP_HANDLER(com_di) {
1335 /* $02 NGC Direct (Undefined) */
1336 OP_HANDLER(ngc_di) {
1337 if ((CC & CC_C) == 0) {
1346 /* $04 LSR direct -0*-* */
1347 OP_HANDLER(lsr_di) {
1355 /* $06 ROR direct -**-* */
1356 OP_HANDLER(ror_di) {
1362 /* $07 ASR direct ?**-* */
1363 OP_HANDLER(asr_di) {
1369 /* $08 ASL direct ?**** */
1370 OP_HANDLER(asl_di) {
1376 /* $09 ROL direct -**** */
1377 OP_HANDLER(rol_di) {
1383 /* $0A DEC direct -***- */
1384 OP_HANDLER(dec_di) {
1390 /* $0B DCC direct */
1391 OP_HANDLER(dcc_di) {
1398 /* $OC INC direct -***- */
1399 OP_HANDLER(inc_di) {
1405 /* $OD TST direct -**0- */
1406 OP_HANDLER(tst_di) {
1413 /* $0E JMP direct ----- */
1414 OP_HANDLER(jmp_di) {
1419 /* $0F CLR direct -0100 */
1420 OP_HANDLER(clr_di) {
1423 dummy = RM(EAD); // Dummy Read(Alpha etc...)
1431 /* $12 NOP inherent ----- */
1436 /* $13 SYNC inherent ----- */
1437 OP_HANDLER(sync_09) // Rename 20101110
1439 int_state |= MC6809_SYNC_IN;
1440 write_signals(&outputs_bus_ba, 0xffffffff);
1441 write_signals(&outputs_bus_bs, 0x00000000);
1446 /* $14 trap(HALT) */
1448 int_state |= MC6809_INSN_HALT; // HALT繝輔Λ繧ー
1450 this->out_debug_log(_T("TRAP(HALT) @%04x %02x %02x\n"), PC - 1, RM((PC - 1)), RM(PC));
1455 /* $16 LBRA relative ----- */
1460 /* $17 LBSR relative ----- */
1469 OP_HANDLER(aslcc_in) {
1471 if ((cc_r & CC_Z) != 0x00) { //20100824 Fix
1479 /* $19 DAA inherent (A) -**0* */
1485 if (lsn > 0x09 || CC & CC_H)
1487 if (msn > 0x80 && lsn > 0x09)
1489 if (msn > 0x90 || CC & CC_C)
1492 CLR_NZV; /* keep carry from previous operation */
1493 SET_NZ8((uint8_t) t);
1499 /* $1A ORCC immediate ##### */
1509 /* $1C ANDCC immediate ##### */
1514 // check_irq_lines(); /* HJB 990116 */
1517 /* $1D SEX inherent -**-- */
1521 D = t; // Endian OK?
1522 // CLR_NZV; Tim Lindner 20020905: verified that V flag is not affected
1527 /* $1E EXG inherent ----- */// 20100825
1535 * 20111011: 16bit vs 16Bit縺ョ貍皮ョ励↓縺吶k(XM7/ cpu_x86.asm繧医j
1538 switch ((tb >> 4) & 15) {
1617 switch ((tb >> 4) & 15) {
1632 int_state |= MC6809_LDS;
1665 int_state |= MC6809_LDS;
1685 /* $1F TFR inherent ----- */
1692 * 20111011: 16bit vs 16Bit縺ョ貍皮ョ励↓縺吶k(XM7/ cpu_x86.asm繧医j)
1695 switch ((tb >> 4) & 15) {
1750 int_state |= MC6809_LDS;
1770 /* $20 BRA relative ----- */
1775 /* $21 BRN relative ----- */
1780 /* $1021 LBRN relative ----- */
1785 /* $22 BHI relative ----- */
1787 BRANCH(((CC & (CC_Z | CC_C)) == 0));
1790 /* $1022 LBHI relative ----- */
1792 LBRANCH(((CC & (CC_Z | CC_C)) == 0));
1795 /* $23 BLS relative ----- */
1797 BRANCH(((CC & (CC_Z | CC_C)) != 0));
1800 /* $1023 LBLS relative ----- */
1802 LBRANCH(((CC & (CC_Z | CC_C)) != 0));
1803 //LBRANCH((CC & (CC_Z | CC_C)));
1806 /* $24 BCC relative ----- */
1808 BRANCH((CC & CC_C) == 0);
1811 /* $1024 LBCC relative ----- */
1813 LBRANCH((CC & CC_C) == 0);
1816 /* $25 BCS relative ----- */
1818 BRANCH((CC & CC_C) != 0);
1821 /* $1025 LBCS relative ----- */
1823 LBRANCH((CC & CC_C) != 0);
1826 /* $26 BNE relative ----- */
1828 BRANCH((CC & CC_Z) == 0);
1831 /* $1026 LBNE relative ----- */
1833 LBRANCH((CC & CC_Z) == 0);
1836 /* $27 BEQ relative ----- */
1838 BRANCH((CC & CC_Z) != 0);
1841 /* $1027 LBEQ relative ----- */
1843 LBRANCH((CC & CC_Z) != 0);
1846 /* $28 BVC relative ----- */
1848 BRANCH((CC & CC_V) == 0);
1851 /* $1028 LBVC relative ----- */
1853 LBRANCH((CC & CC_V) == 0);
1856 /* $29 BVS relative ----- */
1858 BRANCH((CC & CC_V) != 0);
1861 /* $1029 LBVS relative ----- */
1863 LBRANCH((CC & CC_V) != 0);
1866 /* $2A BPL relative ----- */
1868 BRANCH((CC & CC_N) == 0);
1871 /* $102A LBPL relative ----- */
1873 LBRANCH((CC & CC_N) == 0);
1876 /* $2B BMI relative ----- */
1878 BRANCH((CC & CC_N) != 0);
1881 /* $102B LBMI relative ----- */
1883 LBRANCH((CC & CC_N) != 0);
1886 /* $2C BGE relative ----- */
1891 /* $102C LBGE relative ----- */
1896 /* $2D BLT relative ----- */
1901 /* $102D LBLT relative ----- */
1906 /* $2E BGT relative ----- */
1908 BRANCH(!(NXORV || (CC & CC_Z)));
1911 /* $102E LBGT relative ----- */
1913 LBRANCH(!(NXORV || (CC & CC_Z)));
1916 /* $2F BLE relative ----- */
1918 BRANCH((NXORV || (CC & CC_Z)));
1921 /* $102F LBLE relative ----- */
1923 LBRANCH((NXORV || (CC & CC_Z)));
1926 /* $30 LEAX indexed --*-- */
1928 fetch_effective_address();
1934 /* $31 LEAY indexed --*-- */
1936 fetch_effective_address();
1942 /* $32 LEAS indexed ----- */
1944 fetch_effective_address();
1946 int_state |= MC6809_LDS;
1949 /* $33 LEAU indexed ----- */
1951 fetch_effective_address();
1955 /* $34 PSHS inherent ----- */
1959 //dmy = RM(S); // Add 20100825
1960 RM(S); // Add 20100825
1995 /* 35 PULS inherent ----- */
2031 //dmy = RM(S); // Add 20100825
2032 RM(S); // Add 20100825
2033 /* HJB 990225: moved check after all PULLs */
2034 // if( t&0x01 ) { check_irq_lines(); }
2037 /* $36 PSHU inherent ----- */
2041 //dmy = RM(U); // Add 20100825
2042 RM(U); // Add 20100825
2077 /* 37 PULU inherent ----- */
2113 //dmy = RM(U); // Add 20100825
2114 RM(U); // Add 20100825
2115 /* HJB 990225: moved check after all PULLs */
2116 //if( t&0x01 ) { check_irq_lines(); }
2121 /* $39 RTS inherent ----- */
2123 //printf("RTS: Before PC=%04x", pPC.w.l);
2125 //printf(" After PC=%04x\n", pPC.w.l);
2128 /* $3A ABX inherent ----- */
2136 /* $3B RTI inherent ##### */
2139 // t = CC & CC_E; /* HJB 990225: entire state saved? */
2140 if ((CC & CC_E) != 0) { // NMIIRQ
2150 // check_irq_lines(); /* HJB 990116 */
2153 /* $3C CWAI inherent ----1 */
2158 CC |= CC_E; /* HJB 990225: save entire state */
2168 int_state = int_state | MC6809_CWAI_IN;
2169 int_state &= ~MC6809_CWAI_OUT; // 0xfeff
2173 /* $3D MUL inherent --*-@ */
2183 if (t.b.l & 0x80) SEC;
2194 /* $3F SWI (SWI2 SWI3) absolute indirect ----- */
2196 CC |= CC_E; /* HJB 980225: save entire state */
2205 CC |= CC_IF | CC_II; /* inhibit FIRQ and IRQ */
2206 pPC = RM16_PAIR(0xfffa);
2209 /* $103F SWI2 absolute indirect ----- */
2211 CC |= CC_E; /* HJB 980225: save entire state */
2220 pPC = RM16_PAIR(0xfff4);
2223 /* $113F SWI3 absolute indirect ----- */
2225 CC |= CC_E; /* HJB 980225: save entire state */
2234 pPC = RM16_PAIR(0xfff2);
2237 /* $40 NEGA inherent ?**** */
2245 /* $43 COMA inherent -**01 */
2252 if ((CC & CC_C) == 0) {
2259 /* $44 LSRA inherent -0*-* */
2266 /* $46 RORA inherent -**-* */
2271 /* $47 ASRA inherent ?**-* */
2276 /* $48 ASLA inherent ?**** */
2281 /* $49 ROLA inherent -**** */
2286 /* $4A DECA inherent -***- */
2297 /* $4C INCA inherent -***- */
2302 /* $4D TSTA inherent -**0- */
2312 /* $4F CLRA inherent -0100 */
2317 /* $50 NEGB inherent ?**** */
2326 /* $53 COMB inherent -**01 */
2333 if ((CC & CC_C) == 0) {
2340 /* $54 LSRB inherent -0*-* */
2347 /* $56 RORB inherent -**-* */
2352 /* $57 ASRB inherent ?**-* */
2357 /* $58 ASLB inherent ?**** */
2362 /* $59 ROLB inherent -**** */
2367 /* $5A DECB inherent -***- */
2377 /* $5C INCB inherent -***- */
2382 /* $5D TSTB inherent -**0- */
2392 /* $5F CLRB inherent -0100 */
2397 /* $60 NEG indexed ?**** */
2398 OP_HANDLER(neg_ix) {
2400 t = GET_INDEXED_DATA();
2407 /* $63 COM indexed -**01 */
2408 OP_HANDLER(com_ix) {
2410 t = GET_INDEXED_DATA();
2415 OP_HANDLER(ngc_ix) {
2416 if ((CC & CC_C) == 0) {
2423 /* $64 LSR indexed -0*-* */
2424 OP_HANDLER(lsr_ix) {
2426 t = GET_INDEXED_DATA();
2432 /* $66 ROR indexed -**-* */
2433 OP_HANDLER(ror_ix) {
2435 t = GET_INDEXED_DATA();
2439 /* $67 ASR indexed ?**-* */
2440 OP_HANDLER(asr_ix) {
2442 t = GET_INDEXED_DATA();
2446 /* $68 ASL indexed ?**** */
2447 OP_HANDLER(asl_ix) {
2449 t = GET_INDEXED_DATA();
2453 /* $69 ROL indexed -**** */
2454 OP_HANDLER(rol_ix) {
2456 t = GET_INDEXED_DATA();
2460 /* $6A DEC indexed -***- */
2461 OP_HANDLER(dec_ix) {
2463 t = GET_INDEXED_DATA();
2468 OP_HANDLER(dcc_ix) {
2470 t = GET_INDEXED_DATA();
2474 /* $6C INC indexed -***- */
2475 OP_HANDLER(inc_ix) {
2477 t = GET_INDEXED_DATA();
2481 /* $6D TST indexed -**0- */
2482 OP_HANDLER(tst_ix) {
2484 t = GET_INDEXED_DATA();
2488 /* $6E JMP indexed ----- */
2489 OP_HANDLER(jmp_ix) {
2490 fetch_effective_address();
2494 /* $6F CLR indexed -0100 */
2495 OP_HANDLER(clr_ix) {
2497 t = GET_INDEXED_DATA();
2498 //dummy = RM(EAD); // Dummy Read(Alpha etc...)
2499 RM(EAD); // Dummy Read(Alpha etc...)
2503 /* $70 NEG extended ?**** */
2504 OP_HANDLER(neg_ex) {
2511 /* $73 COM extended -**01 */
2512 OP_HANDLER(com_ex) {
2518 /* $72 NGC extended */
2519 OP_HANDLER(ngc_ex) {
2520 if ((CC & CC_C) == 0) {
2527 /* $74 LSR extended -0*-* */
2528 OP_HANDLER(lsr_ex) {
2536 /* $76 ROR extended -**-* */
2537 OP_HANDLER(ror_ex) {
2543 /* $77 ASR extended ?**-* */
2544 OP_HANDLER(asr_ex) {
2550 /* $78 ASL extended ?**** */
2551 OP_HANDLER(asl_ex) {
2557 /* $79 ROL extended -**** */
2558 OP_HANDLER(rol_ex) {
2564 /* $7A DEC extended -***- */
2565 OP_HANDLER(dec_ex) {
2573 OP_HANDLER(dcc_ex) {
2579 /* $7C INC extended -***- */
2580 OP_HANDLER(inc_ex) {
2586 /* $7D TST extended -**0- */
2587 OP_HANDLER(tst_ex) {
2593 /* $7E JMP extended ----- */
2594 OP_HANDLER(jmp_ex) {
2599 /* $7F CLR extended -0100 */
2600 OP_HANDLER(clr_ex) {
2607 /* $80 SUBA immediate ?**** */
2608 OP_HANDLER(suba_im) {
2614 /* $81 CMPA immediate ?**** */
2615 OP_HANDLER(cmpa_im) {
2621 /* $82 SBCA immediate ?**** */
2622 OP_HANDLER(sbca_im) {
2628 /* $83 SUBD (CMPD CMPU) immediate -**** */
2629 OP_HANDLER(subd_im) {
2632 D = SUB16_REG(D, b.w.l);
2635 /* $1083 CMPD immediate -**** */
2636 OP_HANDLER(cmpd_im) {
2639 D = CMP16_REG(D, b.w.l);
2642 /* $1183 CMPU immediate -**** */
2643 OP_HANDLER(cmpu_im) {
2646 U = CMP16_REG(U, b.w.l);
2649 /* $84 ANDA immediate -**0- */
2650 OP_HANDLER(anda_im) {
2656 /* $85 BITA immediate -**0- */
2657 OP_HANDLER(bita_im) {
2663 /* $86 LDA immediate -**0- */
2664 OP_HANDLER(lda_im) {
2669 /* is this a legal instruction? */
2670 /* $87 STA immediate -**0- */
2671 OP_HANDLER(sta_im) {
2681 OP_HANDLER(flag8_im) {
2692 /* $88 EORA immediate -**0- */
2693 OP_HANDLER(eora_im) {
2699 /* $89 ADCA immediate ***** */
2700 OP_HANDLER(adca_im) {
2706 /* $8A ORA immediate -**0- */
2707 OP_HANDLER(ora_im) {
2713 /* $8B ADDA immediate ***** */
2714 OP_HANDLER(adda_im) {
2720 /* $8C CMPX (CMPY CMPS) immediate -**** */
2721 OP_HANDLER(cmpx_im) {
2724 X = CMP16_REG(X, b.w.l);
2727 /* $108C CMPY immediate -**** */
2728 OP_HANDLER(cmpy_im) {
2731 Y = CMP16_REG(Y, b.w.l);
2734 /* $118C CMPS immediate -**** */
2735 OP_HANDLER(cmps_im) {
2738 S = CMP16_REG(S, b.w.l);
2749 /* $8E LDX (LDY) immediate -**0- */
2750 OP_HANDLER(ldx_im) {
2755 /* $108E LDY immediate -**0- */
2756 OP_HANDLER(ldy_im) {
2761 /* is this a legal instruction? */
2762 /* $8F STX (STY) immediate -**0- */
2763 OP_HANDLER(stx_im) {
2773 OP_HANDLER(flag16_im) {
2781 /* is this a legal instruction? */
2782 /* $108F STY immediate -**0- */
2783 OP_HANDLER(sty_im) {
2790 /* $90 SUBA direct ?**** */
2791 OP_HANDLER(suba_di) {
2797 /* $91 CMPA direct ?**** */
2798 OP_HANDLER(cmpa_di) {
2804 /* $92 SBCA direct ?**** */
2805 OP_HANDLER(sbca_di) {
2811 /* $93 SUBD (CMPD CMPU) direct -**** */
2812 OP_HANDLER(subd_di) {
2815 D = SUB16_REG(D, b.w.l);
2818 /* $1093 CMPD direct -**** */
2819 OP_HANDLER(cmpd_di) {
2822 D = CMP16_REG(D, b.w.l);
2825 /* $1193 CMPU direct -**** */
2826 OP_HANDLER(cmpu_di) {
2829 U = CMP16_REG(U, b.w.l);
2832 /* $94 ANDA direct -**0- */
2833 OP_HANDLER(anda_di) {
2839 /* $95 BITA direct -**0- */
2840 OP_HANDLER(bita_di) {
2846 /* $96 LDA direct -**0- */
2847 OP_HANDLER(lda_di) {
2852 /* $97 STA direct -**0- */
2853 OP_HANDLER(sta_di) {
2858 /* $98 EORA direct -**0- */
2859 OP_HANDLER(eora_di) {
2865 /* $99 ADCA direct ***** */
2866 OP_HANDLER(adca_di) {
2872 /* $9A ORA direct -**0- */
2873 OP_HANDLER(ora_di) {
2879 /* $9B ADDA direct ***** */
2880 OP_HANDLER(adda_di) {
2886 /* $9C CMPX (CMPY CMPS) direct -**** */
2887 OP_HANDLER(cmpx_di) {
2890 X = CMP16_REG(X, b.w.l);
2893 /* $109C CMPY direct -**** */
2894 OP_HANDLER(cmpy_di) {
2897 Y = CMP16_REG(Y, b.w.l);
2900 /* $119C CMPS direct -**** */
2901 OP_HANDLER(cmps_di) {
2904 S = CMP16_REG(S, b.w.l);
2907 /* $9D JSR direct ----- */
2908 OP_HANDLER(jsr_di) {
2914 /* $9E LDX (LDY) direct -**0- */
2915 OP_HANDLER(ldx_di) {
2920 /* $109E LDY direct -**0- */
2921 OP_HANDLER(ldy_di) {
2926 /* $9F STX (STY) direct -**0- */
2927 OP_HANDLER(stx_di) {
2932 /* $109F STY direct -**0- */
2933 OP_HANDLER(sty_di) {
2938 /* $a0 SUBA indexed ?**** */
2939 OP_HANDLER(suba_ix) {
2941 t = GET_INDEXED_DATA();
2945 /* $a1 CMPA indexed ?**** */
2946 OP_HANDLER(cmpa_ix) {
2948 t = GET_INDEXED_DATA();
2952 /* $a2 SBCA indexed ?**** */
2953 OP_HANDLER(sbca_ix) {
2955 t = GET_INDEXED_DATA();
2959 /* $a3 SUBD (CMPD CMPU) indexed -**** */
2960 OP_HANDLER(subd_ix) {
2962 b = GET_INDEXED_DATA16();
2963 D = SUB16_REG(D, b.w.l);
2966 /* $10a3 CMPD indexed -**** */
2967 OP_HANDLER(cmpd_ix) {
2969 b = GET_INDEXED_DATA16();
2970 D = CMP16_REG(D, b.w.l);
2973 /* $11a3 CMPU indexed -**** */
2974 OP_HANDLER(cmpu_ix) {
2976 b = GET_INDEXED_DATA16();
2977 U = CMP16_REG(U, b.w.l);
2980 /* $a4 ANDA indexed -**0- */
2981 OP_HANDLER(anda_ix) {
2983 t = GET_INDEXED_DATA();
2987 /* $a5 BITA indexed -**0- */
2988 OP_HANDLER(bita_ix) {
2990 t = GET_INDEXED_DATA();
2994 /* $a6 LDA indexed -**0- */
2995 OP_HANDLER(lda_ix) {
2996 A = GET_INDEXED_DATA();
3000 /* $a7 STA indexed -**0- */
3001 OP_HANDLER(sta_ix) {
3002 fetch_effective_address();
3006 /* $a8 EORA indexed -**0- */
3007 OP_HANDLER(eora_ix) {
3009 t = GET_INDEXED_DATA();
3013 /* $a9 ADCA indexed ***** */
3014 OP_HANDLER(adca_ix) {
3016 t = GET_INDEXED_DATA();
3020 /* $aA ORA indexed -**0- */
3021 OP_HANDLER(ora_ix) {
3023 t = GET_INDEXED_DATA();
3027 /* $aB ADDA indexed ***** */
3028 OP_HANDLER(adda_ix) {
3030 t = GET_INDEXED_DATA();
3034 /* $aC CMPX (CMPY CMPS) indexed -**** */
3035 OP_HANDLER(cmpx_ix) {
3037 b = GET_INDEXED_DATA16();
3038 X = CMP16_REG(X, b.w.l);
3041 /* $10aC CMPY indexed -**** */
3042 OP_HANDLER(cmpy_ix) {
3044 b = GET_INDEXED_DATA16();
3045 Y = CMP16_REG(Y, b.w.l);
3048 /* $11aC CMPS indexed -**** */
3049 OP_HANDLER(cmps_ix) {
3051 b = GET_INDEXED_DATA16();
3052 S = CMP16_REG(S, b.w.l);
3055 /* $aD JSR indexed ----- */
3056 OP_HANDLER(jsr_ix) {
3057 fetch_effective_address();
3062 /* $aE LDX (LDY) indexed -**0- */
3063 OP_HANDLER(ldx_ix) {
3065 t = GET_INDEXED_DATA16();
3070 /* $10aE LDY indexed -**0- */
3071 OP_HANDLER(ldy_ix) {
3073 t = GET_INDEXED_DATA16();
3078 /* $aF STX (STY) indexed -**0- */
3079 OP_HANDLER(stx_ix) {
3080 fetch_effective_address();
3084 /* $10aF STY indexed -**0- */
3085 OP_HANDLER(sty_ix) {
3086 fetch_effective_address();
3090 /* $b0 SUBA extended ?**** */
3091 OP_HANDLER(suba_ex) {
3097 /* $b1 CMPA extended ?**** */
3098 OP_HANDLER(cmpa_ex) {
3104 /* $b2 SBCA extended ?**** */
3105 OP_HANDLER(sbca_ex) {
3111 /* $b3 SUBD (CMPD CMPU) extended -**** */
3112 OP_HANDLER(subd_ex) {
3115 D = SUB16_REG(D, b.w.l);
3118 /* $10b3 CMPD extended -**** */
3119 OP_HANDLER(cmpd_ex) {
3122 D = CMP16_REG(D, b.w.l);
3125 /* $11b3 CMPU extended -**** */
3126 OP_HANDLER(cmpu_ex) {
3129 U = CMP16_REG(U, b.w.l);
3132 /* $b4 ANDA extended -**0- */
3133 OP_HANDLER(anda_ex) {
3139 /* $b5 BITA extended -**0- */
3140 OP_HANDLER(bita_ex) {
3146 /* $b6 LDA extended -**0- */
3147 OP_HANDLER(lda_ex) {
3152 /* $b7 STA extended -**0- */
3153 OP_HANDLER(sta_ex) {
3158 /* $b8 EORA extended -**0- */
3159 OP_HANDLER(eora_ex) {
3165 /* $b9 ADCA extended ***** */
3166 OP_HANDLER(adca_ex) {
3172 /* $bA ORA extended -**0- */
3173 OP_HANDLER(ora_ex) {
3179 /* $bB ADDA extended ***** */
3180 OP_HANDLER(adda_ex) {
3186 /* $bC CMPX (CMPY CMPS) extended -**** */
3187 OP_HANDLER(cmpx_ex) {
3190 X = CMP16_REG(X, b.w.l);
3193 /* $10bC CMPY extended -**** */
3194 OP_HANDLER(cmpy_ex) {
3197 Y = CMP16_REG(Y, b.w.l);
3200 /* $11bC CMPS extended -**** */
3201 OP_HANDLER(cmps_ex) {
3204 S = CMP16_REG(S, b.w.l);
3207 /* $bD JSR extended ----- */
3208 OP_HANDLER(jsr_ex) {
3214 /* $bE LDX (LDY) extended -**0- */
3215 OP_HANDLER(ldx_ex) {
3220 /* $10bE LDY extended -**0- */
3221 OP_HANDLER(ldy_ex) {
3226 /* $bF STX (STY) extended -**0- */
3227 OP_HANDLER(stx_ex) {
3232 /* $10bF STY extended -**0- */
3233 OP_HANDLER(sty_ex) {
3238 /* $c0 SUBB immediate ?**** */
3239 OP_HANDLER(subb_im) {
3245 /* $c1 CMPB immediate ?**** */
3246 OP_HANDLER(cmpb_im) {
3252 /* $c2 SBCB immediate ?**** */
3253 OP_HANDLER(sbcb_im) {
3259 /* $c3 ADDD immediate -**** */
3260 OP_HANDLER(addd_im) {
3263 D = ADD16_REG(D, b.w.l);
3266 /* $c4 ANDB immediate -**0- */
3267 OP_HANDLER(andb_im) {
3273 /* $c5 BITB immediate -**0- */
3274 OP_HANDLER(bitb_im) {
3280 /* $c6 LDB immediate -**0- */
3281 OP_HANDLER(ldb_im) {
3286 /* is this a legal instruction? */
3287 /* $c7 STB immediate -**0- */
3288 OP_HANDLER(stb_im) {
3295 /* $c8 EORB immediate -**0- */
3296 OP_HANDLER(eorb_im) {
3302 /* $c9 ADCB immediate ***** */
3303 OP_HANDLER(adcb_im) {
3309 /* $cA ORB immediate -**0- */
3310 OP_HANDLER(orb_im) {
3316 /* $cB ADDB immediate ***** */
3317 OP_HANDLER(addb_im) {
3323 /* $cC LDD immediate -**0- */
3324 OP_HANDLER(ldd_im) {
3329 /* is this a legal instruction? */
3330 /* $cD STD immediate -**0- */
3331 OP_HANDLER(std_im) {
3338 /* $cE LDU (LDS) immediate -**0- */
3339 OP_HANDLER(ldu_im) {
3344 /* $10cE LDS immediate -**0- */
3345 OP_HANDLER(lds_im) {
3348 int_state |= MC6809_LDS;
3351 /* is this a legal instruction? */
3352 /* $cF STU (STS) immediate -**0- */
3353 OP_HANDLER(stu_im) {
3360 /* is this a legal instruction? */
3361 /* $10cF STS immediate -**0- */
3362 OP_HANDLER(sts_im) {
3369 /* $d0 SUBB direct ?**** */
3370 OP_HANDLER(subb_di) {
3375 /* $d1 CMPB direct ?**** */
3376 OP_HANDLER(cmpb_di) {
3382 /* $d2 SBCB direct ?**** */
3383 OP_HANDLER(sbcb_di) {
3389 /* $d3 ADDD direct -**** */
3390 OP_HANDLER(addd_di) {
3393 D = ADD16_REG(D, b.w.l);
3396 /* $d4 ANDB direct -**0- */
3397 OP_HANDLER(andb_di) {
3403 /* $d5 BITB direct -**0- */
3404 OP_HANDLER(bitb_di) {
3410 /* $d6 LDB direct -**0- */
3411 OP_HANDLER(ldb_di) {
3416 /* $d7 STB direct -**0- */
3417 OP_HANDLER(stb_di) {
3422 /* $d8 EORB direct -**0- */
3423 OP_HANDLER(eorb_di) {
3429 /* $d9 ADCB direct ***** */
3430 OP_HANDLER(adcb_di) {
3436 /* $dA ORB direct -**0- */
3437 OP_HANDLER(orb_di) {
3443 /* $dB ADDB direct ***** */
3444 OP_HANDLER(addb_di) {
3450 /* $dC LDD direct -**0- */
3451 OP_HANDLER(ldd_di) {
3456 /* $dD STD direct -**0- */
3457 OP_HANDLER(std_di) {
3462 /* $dE LDU (LDS) direct -**0- */
3463 OP_HANDLER(ldu_di) {
3468 /* $10dE LDS direct -**0- */
3469 OP_HANDLER(lds_di) {
3472 int_state |= MC6809_LDS;
3475 /* $dF STU (STS) direct -**0- */
3476 OP_HANDLER(stu_di) {
3481 /* $10dF STS direct -**0- */
3482 OP_HANDLER(sts_di) {
3487 /* $e0 SUBB indexed ?**** */
3488 OP_HANDLER(subb_ix) {
3490 t = GET_INDEXED_DATA();
3494 /* $e1 CMPB indexed ?**** */
3495 OP_HANDLER(cmpb_ix) {
3497 t = GET_INDEXED_DATA();
3501 /* $e2 SBCB indexed ?**** */
3502 OP_HANDLER(sbcb_ix) {
3504 t = GET_INDEXED_DATA();
3508 /* $e3 ADDD indexed -**** */
3509 OP_HANDLER(addd_ix) {
3511 b = GET_INDEXED_DATA16();
3512 D = ADD16_REG(D, b.w.l);
3515 /* $e4 ANDB indexed -**0- */
3516 OP_HANDLER(andb_ix) {
3518 t = GET_INDEXED_DATA();
3522 /* $e5 BITB indexed -**0- */
3523 OP_HANDLER(bitb_ix) {
3525 t = GET_INDEXED_DATA();
3529 /* $e6 LDB indexed -**0- */
3530 OP_HANDLER(ldb_ix) {
3531 B = GET_INDEXED_DATA();
3535 /* $e7 STB indexed -**0- */
3536 OP_HANDLER(stb_ix) {
3537 fetch_effective_address();
3541 /* $e8 EORB indexed -**0- */
3542 OP_HANDLER(eorb_ix) {
3544 t = GET_INDEXED_DATA();
3548 /* $e9 ADCB indexed ***** */
3549 OP_HANDLER(adcb_ix) {
3551 t = GET_INDEXED_DATA();
3555 /* $eA ORB indexed -**0- */
3556 OP_HANDLER(orb_ix) {
3558 t = GET_INDEXED_DATA();
3562 /* $eB ADDB indexed ***** */
3563 OP_HANDLER(addb_ix) {
3565 t = GET_INDEXED_DATA();
3569 /* $eC LDD indexed -**0- */
3570 OP_HANDLER(ldd_ix) {
3572 t = GET_INDEXED_DATA16();
3577 /* $eD STD indexed -**0- */
3578 OP_HANDLER(std_ix) {
3579 fetch_effective_address();
3583 /* $eE LDU (LDS) indexed -**0- */
3584 OP_HANDLER(ldu_ix) {
3586 t = GET_INDEXED_DATA16();
3591 /* $10eE LDS indexed -**0- */
3592 OP_HANDLER(lds_ix) {
3594 t = GET_INDEXED_DATA16();
3597 int_state |= MC6809_LDS;
3600 /* $eF STU (STS) indexed -**0- */
3601 OP_HANDLER(stu_ix) {
3602 fetch_effective_address();
3606 /* $10eF STS indexed -**0- */
3607 OP_HANDLER(sts_ix) {
3608 fetch_effective_address();
3612 /* $f0 SUBB extended ?**** */
3613 OP_HANDLER(subb_ex) {
3619 /* $f1 CMPB extended ?**** */
3620 OP_HANDLER(cmpb_ex) {
3626 /* $f2 SBCB extended ?**** */
3627 OP_HANDLER(sbcb_ex) {
3633 /* $f3 ADDD extended -**** */
3634 OP_HANDLER(addd_ex) {
3637 D = ADD16_REG(D, b.w.l);
3640 /* $f4 ANDB extended -**0- */
3641 OP_HANDLER(andb_ex) {
3647 /* $f5 BITB extended -**0- */
3648 OP_HANDLER(bitb_ex) {
3654 /* $f6 LDB extended -**0- */
3655 OP_HANDLER(ldb_ex) {
3660 /* $f7 STB extended -**0- */
3661 OP_HANDLER(stb_ex) {
3666 /* $f8 EORB extended -**0- */
3667 OP_HANDLER(eorb_ex) {
3673 /* $f9 ADCB extended ***** */
3674 OP_HANDLER(adcb_ex) {
3680 /* $fA ORB extended -**0- */
3681 OP_HANDLER(orb_ex) {
3687 /* $fB ADDB extended ***** */
3688 OP_HANDLER(addb_ex) {
3694 /* $fC LDD extended -**0- */
3695 OP_HANDLER(ldd_ex) {
3700 /* $fD STD extended -**0- */
3701 OP_HANDLER(std_ex) {
3706 /* $fE LDU (LDS) extended -**0- */
3707 OP_HANDLER(ldu_ex) {
3712 /* $10fE LDS extended -**0- */
3713 OP_HANDLER(lds_ex) {
3716 int_state |= MC6809_LDS;
3719 /* $fF STU (STS) extended -**0- */
3720 OP_HANDLER(stu_ex) {
3725 /* $10fF STS extended -**0- */
3726 OP_HANDLER(sts_ex) {
3733 OP_HANDLER(pref10) {
3734 uint8_t ireg2 = ROP_ARG(PCD);
3821 // case 0x8f: flag16_im();->cycle=4; break; // 20130417
3874 // case 0xcf: flag16_im();->cycle=4; break;
3907 OP_HANDLER(pref11) {
3908 uint8_t ireg2 = ROP_ARG(PCD);
3961 //#ifdef USE_DEBUGGER
3963 /*****************************************************************************
3965 6809dasm.c - a 6809 opcode disassembler
3966 Version 1.4 1-MAR-95
3967 Copyright Sean Riddle
3969 Thanks to Franklin Bowen for bug fixes, ideas
3971 Freely distributable on any medium given all copyrights are retained
3972 by the author and no charge greater than $7.00 is made for obtaining
3975 Please send all bug reports, update ideas and data files to:
3978 *****************************************************************************/
3982 uint8_t opcode; // 8-bit opcode value
3983 uint8_t length; // Opcode length in bytes
3984 _TCHAR name[6]; // Opcode name
3985 uint8_t mode; // Addressing mode
3986 // unsigned flags; // Disassembly flags
3989 enum m6809_addressing_modes
3994 REL, // Relative (8 bit)
3995 LREL, // Long relative (16 bit)
3998 IMM_RR, // Register-to-register
3999 PG1, // Switch to page 1 opcodes
4000 PG2 // Switch to page 2 opcodes
4003 // Page 0 opcodes (single byte)
4004 static const opcodeinfo m6809_pg0opcodes[] =
4006 { 0x00, 2, _T("NEG"), DIR },
4007 { 0x01, 2, _T("NEG"), DIR },
4008 { 0x02, 2, _T("NGC"), DIR },
4009 { 0x03, 2, _T("COM"), DIR },
4010 { 0x04, 2, _T("LSR"), DIR },
4011 { 0x05, 2, _T("LSR"), DIR },
4012 { 0x06, 2, _T("ROR"), DIR },
4013 { 0x07, 2, _T("ASR"), DIR },
4014 { 0x08, 2, _T("ASL"), DIR },
4015 { 0x09, 2, _T("ROL"), DIR },
4016 { 0x0A, 2, _T("DEC"), DIR },
4017 { 0x0B, 2, _T("DCC"), DIR },
4018 { 0x0C, 2, _T("INC"), DIR },
4019 { 0x0D, 2, _T("TST"), DIR },
4020 { 0x0E, 2, _T("JMP"), DIR },
4021 { 0x0F, 2, _T("CLR"), DIR },
4023 { 0x10, 1, _T("page1"), PG1 },
4024 { 0x11, 1, _T("page2"), PG2 },
4025 { 0x12, 1, _T("NOP"), INH },
4026 { 0x13, 1, _T("SYNC"), INH },
4027 { 0x14, 1, _T("HALT"), INH },
4028 { 0x15, 1, _T("HALT"), INH },
4029 { 0x16, 3, _T("LBRA"), LREL },
4030 { 0x17, 3, _T("LBSR"), LREL },
4031 { 0x18, 1, _T("ASLCC"), INH },
4032 { 0x19, 1, _T("DAA"), INH },
4033 { 0x1A, 2, _T("ORCC"), IMM },
4034 { 0x1B, 1, _T("NOP"), INH },
4035 { 0x1C, 2, _T("ANDCC"), IMM },
4036 { 0x1D, 1, _T("SEX"), INH },
4037 { 0x1E, 2, _T("EXG"), IMM_RR },
4038 { 0x1F, 2, _T("TFR"), IMM_RR },
4040 { 0x20, 2, _T("BRA"), REL },
4041 { 0x21, 2, _T("BRN"), REL },
4042 { 0x22, 2, _T("BHI"), REL },
4043 { 0x23, 2, _T("BLS"), REL },
4044 { 0x24, 2, _T("BCC"), REL },
4045 { 0x25, 2, _T("BCS"), REL },
4046 { 0x26, 2, _T("BNE"), REL },
4047 { 0x27, 2, _T("BEQ"), REL },
4048 { 0x28, 2, _T("BVC"), REL },
4049 { 0x29, 2, _T("BVS"), REL },
4050 { 0x2A, 2, _T("BPL"), REL },
4051 { 0x2B, 2, _T("BMI"), REL },
4052 { 0x2C, 2, _T("BGE"), REL },
4053 { 0x2D, 2, _T("BLT"), REL },
4054 { 0x2E, 2, _T("BGT"), REL },
4055 { 0x2F, 2, _T("BLE"), REL },
4057 { 0x30, 2, _T("LEAX"), IND },
4058 { 0x31, 2, _T("LEAY"), IND },
4059 { 0x32, 2, _T("LEAS"), IND },
4060 { 0x33, 2, _T("LEAU"), IND },
4061 { 0x34, 2, _T("PSHS"), INH },
4062 { 0x35, 2, _T("PULS"), INH },
4063 { 0x36, 2, _T("PSHU"), INH },
4064 { 0x37, 2, _T("PULU"), INH },
4065 { 0x38, 2, _T("ANDCC"), IMM },
4066 { 0x39, 1, _T("RTS"), INH },
4067 { 0x3A, 1, _T("ABX"), INH },
4068 { 0x3B, 1, _T("RTI"), INH },
4069 { 0x3C, 2, _T("CWAI"), IMM },
4070 { 0x3D, 1, _T("MUL"), INH },
4071 { 0x3F, 1, _T("SWI"), INH },
4073 { 0x40, 1, _T("NEGA"), INH },
4074 { 0x41, 1, _T("NEGA"), INH },
4075 { 0x42, 1, _T("NGGA"), INH },
4076 { 0x43, 1, _T("COMA"), INH },
4077 { 0x44, 1, _T("LSRA"), INH },
4078 { 0x45, 1, _T("LSRA"), INH },
4079 { 0x46, 1, _T("RORA"), INH },
4080 { 0x47, 1, _T("ASRA"), INH },
4081 { 0x48, 1, _T("ASLA"), INH },
4082 { 0x49, 1, _T("ROLA"), INH },
4083 { 0x4A, 1, _T("DECA"), INH },
4084 { 0x4B, 1, _T("DCCA"), INH },
4085 { 0x4C, 1, _T("INCA"), INH },
4086 { 0x4D, 1, _T("TSTA"), INH },
4087 { 0x4E, 1, _T("CLCA"), INH },
4088 { 0x4F, 1, _T("CLRA"), INH },
4090 { 0x50, 1, _T("NEGB"), INH },
4091 { 0x51, 1, _T("NEGB"), INH },
4092 { 0x52, 1, _T("NGGB"), INH },
4093 { 0x53, 1, _T("COMB"), INH },
4094 { 0x54, 1, _T("LSRB"), INH },
4095 { 0x55, 1, _T("LSRB"), INH },
4096 { 0x56, 1, _T("RORB"), INH },
4097 { 0x57, 1, _T("ASRB"), INH },
4098 { 0x58, 1, _T("ASLB"), INH },
4099 { 0x59, 1, _T("ROLB"), INH },
4100 { 0x5A, 1, _T("DECB"), INH },
4101 { 0x5B, 1, _T("DCCB"), INH },
4102 { 0x5C, 1, _T("INCB"), INH },
4103 { 0x5D, 1, _T("TSTB"), INH },
4104 { 0x5E, 1, _T("CLCB"), INH },
4105 { 0x5F, 1, _T("CLRB"), INH },
4107 { 0x60, 2, _T("NEG"), IND },
4108 { 0x61, 2, _T("NEG"), IND },
4109 { 0x62, 2, _T("NGC"), IND },
4110 { 0x63, 2, _T("COM"), IND },
4111 { 0x64, 2, _T("LSR"), IND },
4112 { 0x65, 2, _T("LSR"), IND },
4113 { 0x66, 2, _T("ROR"), IND },
4114 { 0x67, 2, _T("ASR"), IND },
4115 { 0x68, 2, _T("ASL"), IND },
4116 { 0x69, 2, _T("ROL"), IND },
4117 { 0x6A, 2, _T("DEC"), IND },
4118 { 0x6B, 2, _T("DCC"), IND },
4119 { 0x6C, 2, _T("INC"), IND },
4120 { 0x6D, 2, _T("TST"), IND },
4121 { 0x6E, 2, _T("JMP"), IND },
4122 { 0x6F, 2, _T("CLR"), IND },
4124 { 0x70, 3, _T("NEG"), EXT },
4125 { 0x71, 3, _T("NEG"), EXT },
4126 { 0x72, 3, _T("NGC"), EXT },
4127 { 0x73, 3, _T("COM"), EXT },
4128 { 0x74, 3, _T("LSR"), EXT },
4129 { 0x75, 3, _T("LSR"), EXT },
4130 { 0x76, 3, _T("ROR"), EXT },
4131 { 0x77, 3, _T("ASR"), EXT },
4132 { 0x78, 3, _T("ASL"), EXT },
4133 { 0x79, 3, _T("ROL"), EXT },
4134 { 0x7A, 3, _T("DEC"), EXT },
4135 { 0x7B, 3, _T("DCC"), EXT },
4136 { 0x7C, 3, _T("INC"), EXT },
4137 { 0x7D, 3, _T("TST"), EXT },
4138 { 0x7E, 3, _T("JMP"), EXT },
4139 { 0x7F, 3, _T("CLR"), EXT },
4141 { 0x80, 2, _T("SUBA"), IMM },
4142 { 0x81, 2, _T("CMPA"), IMM },
4143 { 0x82, 2, _T("SBCA"), IMM },
4144 { 0x83, 3, _T("SUBD"), IMM },
4145 { 0x84, 2, _T("ANDA"), IMM },
4146 { 0x85, 2, _T("BITA"), IMM },
4147 { 0x86, 2, _T("LDA"), IMM },
4148 { 0x87, 2, _T("FLAG"), IMM },
4149 { 0x88, 2, _T("EORA"), IMM },
4150 { 0x89, 2, _T("ADCA"), IMM },
4151 { 0x8A, 2, _T("ORA"), IMM },
4152 { 0x8B, 2, _T("ADDA"), IMM },
4153 { 0x8C, 3, _T("CMPX"), IMM },
4154 { 0x8D, 2, _T("BSR"), REL },
4155 { 0x8E, 3, _T("LDX"), IMM },
4156 { 0x8F, 3, _T("FLAG"), IMM },
4158 { 0x90, 2, _T("SUBA"), DIR },
4159 { 0x91, 2, _T("CMPA"), DIR },
4160 { 0x92, 2, _T("SBCA"), DIR },
4161 { 0x93, 2, _T("SUBD"), DIR },
4162 { 0x94, 2, _T("ANDA"), DIR },
4163 { 0x95, 2, _T("BITA"), DIR },
4164 { 0x96, 2, _T("LDA"), DIR },
4165 { 0x97, 2, _T("STA"), DIR },
4166 { 0x98, 2, _T("EORA"), DIR },
4167 { 0x99, 2, _T("ADCA"), DIR },
4168 { 0x9A, 2, _T("ORA"), DIR },
4169 { 0x9B, 2, _T("ADDA"), DIR },
4170 { 0x9C, 2, _T("CMPX"), DIR },
4171 { 0x9D, 2, _T("JSR"), DIR },
4172 { 0x9E, 2, _T("LDX"), DIR },
4173 { 0x9F, 2, _T("STX"), DIR },
4175 { 0xA0, 2, _T("SUBA"), IND },
4176 { 0xA1, 2, _T("CMPA"), IND },
4177 { 0xA2, 2, _T("SBCA"), IND },
4178 { 0xA3, 2, _T("SUBD"), IND },
4179 { 0xA4, 2, _T("ANDA"), IND },
4180 { 0xA5, 2, _T("BITA"), IND },
4181 { 0xA6, 2, _T("LDA"), IND },
4182 { 0xA7, 2, _T("STA"), IND },
4183 { 0xA8, 2, _T("EORA"), IND },
4184 { 0xA9, 2, _T("ADCA"), IND },
4185 { 0xAA, 2, _T("ORA"), IND },
4186 { 0xAB, 2, _T("ADDA"), IND },
4187 { 0xAC, 2, _T("CMPX"), IND },
4188 { 0xAD, 2, _T("JSR"), IND },
4189 { 0xAE, 2, _T("LDX"), IND },
4190 { 0xAF, 2, _T("STX"), IND },
4192 { 0xB0, 3, _T("SUBA"), EXT },
4193 { 0xB1, 3, _T("CMPA"), EXT },
4194 { 0xB2, 3, _T("SBCA"), EXT },
4195 { 0xB3, 3, _T("SUBD"), EXT },
4196 { 0xB4, 3, _T("ANDA"), EXT },
4197 { 0xB5, 3, _T("BITA"), EXT },
4198 { 0xB6, 3, _T("LDA"), EXT },
4199 { 0xB7, 3, _T("STA"), EXT },
4200 { 0xB8, 3, _T("EORA"), EXT },
4201 { 0xB9, 3, _T("ADCA"), EXT },
4202 { 0xBA, 3, _T("ORA"), EXT },
4203 { 0xBB, 3, _T("ADDA"), EXT },
4204 { 0xBC, 3, _T("CMPX"), EXT },
4205 { 0xBD, 3, _T("JSR"), EXT },
4206 { 0xBE, 3, _T("LDX"), EXT },
4207 { 0xBF, 3, _T("STX"), EXT },
4209 { 0xC0, 2, _T("SUBB"), IMM },
4210 { 0xC1, 2, _T("CMPB"), IMM },
4211 { 0xC2, 2, _T("SBCB"), IMM },
4212 { 0xC3, 3, _T("ADDD"), IMM },
4213 { 0xC4, 2, _T("ANDB"), IMM },
4214 { 0xC5, 2, _T("BITB"), IMM },
4215 { 0xC6, 2, _T("LDB"), IMM },
4216 { 0xC7, 2, _T("FLAG"), IMM },
4217 { 0xC8, 2, _T("EORB"), IMM },
4218 { 0xC9, 2, _T("ADCB"), IMM },
4219 { 0xCA, 2, _T("ORB"), IMM },
4220 { 0xCB, 2, _T("ADDB"), IMM },
4221 { 0xCC, 3, _T("LDD"), IMM },
4222 { 0xCD, 1, _T("HALT"), INH },
4223 { 0xCE, 3, _T("LDU"), IMM },
4224 { 0xCF, 3, _T("FLAG"), IMM },
4226 { 0xD0, 2, _T("SUBB"), DIR },
4227 { 0xD1, 2, _T("CMPB"), DIR },
4228 { 0xD2, 2, _T("SBCB"), DIR },
4229 { 0xD3, 2, _T("ADDD"), DIR },
4230 { 0xD4, 2, _T("ANDB"), DIR },
4231 { 0xD5, 2, _T("BITB"), DIR },
4232 { 0xD6, 2, _T("LDB"), DIR },
4233 { 0xD7, 2, _T("STB"), DIR },
4234 { 0xD8, 2, _T("EORB"), DIR },
4235 { 0xD9, 2, _T("ADCB"), DIR },
4236 { 0xDA, 2, _T("ORB"), DIR },
4237 { 0xDB, 2, _T("ADDB"), DIR },
4238 { 0xDC, 2, _T("LDD"), DIR },
4239 { 0xDD, 2, _T("STD"), DIR },
4240 { 0xDE, 2, _T("LDU"), DIR },
4241 { 0xDF, 2, _T("STU"), DIR },
4243 { 0xE0, 2, _T("SUBB"), IND },
4244 { 0xE1, 2, _T("CMPB"), IND },
4245 { 0xE2, 2, _T("SBCB"), IND },
4246 { 0xE3, 2, _T("ADDD"), IND },
4247 { 0xE4, 2, _T("ANDB"), IND },
4248 { 0xE5, 2, _T("BITB"), IND },
4249 { 0xE6, 2, _T("LDB"), IND },
4250 { 0xE7, 2, _T("STB"), IND },
4251 { 0xE8, 2, _T("EORB"), IND },
4252 { 0xE9, 2, _T("ADCB"), IND },
4253 { 0xEA, 2, _T("ORB"), IND },
4254 { 0xEB, 2, _T("ADDB"), IND },
4255 { 0xEC, 2, _T("LDD"), IND },
4256 { 0xED, 2, _T("STD"), IND },
4257 { 0xEE, 2, _T("LDU"), IND },
4258 { 0xEF, 2, _T("STU"), IND },
4260 { 0xF0, 3, _T("SUBB"), EXT },
4261 { 0xF1, 3, _T("CMPB"), EXT },
4262 { 0xF2, 3, _T("SBCB"), EXT },
4263 { 0xF3, 3, _T("ADDD"), EXT },
4264 { 0xF4, 3, _T("ANDB"), EXT },
4265 { 0xF5, 3, _T("BITB"), EXT },
4266 { 0xF6, 3, _T("LDB"), EXT },
4267 { 0xF7, 3, _T("STB"), EXT },
4268 { 0xF8, 3, _T("EORB"), EXT },
4269 { 0xF9, 3, _T("ADCB"), EXT },
4270 { 0xFA, 3, _T("ORB"), EXT },
4271 { 0xFB, 3, _T("ADDB"), EXT },
4272 { 0xFC, 3, _T("LDD"), EXT },
4273 { 0xFD, 3, _T("STD"), EXT },
4274 { 0xFE, 3, _T("LDU"), EXT },
4275 { 0xFF, 3, _T("STU"), EXT }
4278 // Page 1 opcodes (0x10 0x..)
4279 static const opcodeinfo m6809_pg1opcodes[] =
4281 { 0x20, 4, _T("LBRA"), LREL },
4282 { 0x21, 4, _T("LBRN"), LREL },
4283 { 0x22, 4, _T("LBHI"), LREL },
4284 { 0x23, 4, _T("LBLS"), LREL },
4285 { 0x24, 4, _T("LBCC"), LREL },
4286 { 0x25, 4, _T("LBCS"), LREL },
4287 { 0x26, 4, _T("LBNE"), LREL },
4288 { 0x27, 4, _T("LBEQ"), LREL },
4289 { 0x28, 4, _T("LBVC"), LREL },
4290 { 0x29, 4, _T("LBVS"), LREL },
4291 { 0x2A, 4, _T("LBPL"), LREL },
4292 { 0x2B, 4, _T("LBMI"), LREL },
4293 { 0x2C, 4, _T("LBGE"), LREL },
4294 { 0x2D, 4, _T("LBLT"), LREL },
4295 { 0x2E, 4, _T("LBGT"), LREL },
4296 { 0x2F, 4, _T("LBLE"), LREL },
4297 { 0x3F, 2, _T("SWI2"), INH },
4298 { 0x83, 4, _T("CMPD"), IMM },
4299 { 0x8C, 4, _T("CMPY"), IMM },
4300 { 0x8D, 4, _T("LBSR"), LREL },
4301 { 0x8E, 4, _T("LDY"), IMM },
4302 { 0x93, 3, _T("CMPD"), DIR },
4303 { 0x9C, 3, _T("CMPY"), DIR },
4304 { 0x9E, 3, _T("LDY"), DIR },
4305 { 0x9F, 3, _T("STY"), DIR },
4306 { 0xA3, 3, _T("CMPD"), IND },
4307 { 0xAC, 3, _T("CMPY"), IND },
4308 { 0xAE, 3, _T("LDY"), IND },
4309 { 0xAF, 3, _T("STY"), IND },
4310 { 0xB3, 4, _T("CMPD"), EXT },
4311 { 0xBC, 4, _T("CMPY"), EXT },
4312 { 0xBE, 4, _T("LDY"), EXT },
4313 { 0xBF, 4, _T("STY"), EXT },
4314 { 0xCE, 4, _T("LDS"), IMM },
4315 { 0xDE, 3, _T("LDS"), DIR },
4316 { 0xDF, 3, _T("STS"), DIR },
4317 { 0xEE, 3, _T("LDS"), IND },
4318 { 0xEF, 3, _T("STS"), IND },
4319 { 0xFE, 4, _T("LDS"), EXT },
4320 { 0xFF, 4, _T("STS"), EXT }
4323 // Page 2 opcodes (0x11 0x..)
4324 static const opcodeinfo m6809_pg2opcodes[] =
4326 { 0x3F, 2, _T("SWI3"), INH },
4327 { 0x83, 4, _T("CMPU"), IMM },
4328 { 0x8C, 4, _T("CMPS"), IMM },
4329 { 0x93, 3, _T("CMPU"), DIR },
4330 { 0x9C, 3, _T("CMPS"), DIR },
4331 { 0xA3, 3, _T("CMPU"), IND },
4332 { 0xAC, 3, _T("CMPS"), IND },
4333 { 0xB3, 4, _T("CMPU"), EXT },
4334 { 0xBC, 4, _T("CMPS"), EXT }
4337 static const opcodeinfo *const m6809_pgpointers[3] =
4339 m6809_pg0opcodes, m6809_pg1opcodes, m6809_pg2opcodes
4342 static const int m6809_numops[3] =
4344 array_length(m6809_pg0opcodes),
4345 array_length(m6809_pg1opcodes),
4346 array_length(m6809_pg2opcodes)
4349 static const _TCHAR *const m6809_regs[5] = { _T("X"), _T("Y"), _T("U"), _T("S"), _T("PC") };
4351 static const _TCHAR *const m6809_regs_te[16] =
4353 _T("D"), _T("X"), _T("Y"), _T("U"), _T("S"), _T("PC"), _T("inv"), _T("inv"),
4354 _T("A"), _T("B"), _T("CC"), _T("DP"), _T("inv"), _T("inv"), _T("inv"), _T("inv")
4356 //#endif /* USE_DEBUGGER */
4358 uint32_t MC6809::cpu_disassemble_m6809(_TCHAR *buffer, uint32_t pc, const uint8_t *oprom, const uint8_t *opram)
4360 if(__USE_DEBUGGER) {
4361 uint8_t opcode, mode, pb, pbm, reg;
4362 const uint8_t *operandarray;
4363 unsigned int ea;//, flags;
4364 int numoperands, offset;
4365 int i, p = 0, page = 0;
4366 bool opcode_found = false;
4368 const _TCHAR *name = NULL;
4371 opcode = oprom[p++];
4373 for (i = 0; i < m6809_numops[page]; i++)
4374 if (m6809_pgpointers[page][i].opcode == opcode)
4377 if (i < m6809_numops[page])
4378 opcode_found = true;
4381 _stprintf(buffer, _T("Illegal Opcode %02X"), opcode);
4385 if (m6809_pgpointers[page][i].mode >= PG1)
4387 page = m6809_pgpointers[page][i].mode - PG1 + 1;
4388 opcode_found = false;
4390 } while (!opcode_found);
4393 numoperands = m6809_pgpointers[page][i].length - 1;
4395 numoperands = m6809_pgpointers[page][i].length - 2;
4397 operandarray = &opram[p];
4400 mode = m6809_pgpointers[page][i].mode;
4401 // flags = m6809_pgpointers[page][i].flags;
4403 buffer += _stprintf(buffer, _T("%-6s"), m6809_pgpointers[page][i].name);
4412 pb = operandarray[0];
4414 buffer += _stprintf(buffer, _T("PC"));
4416 buffer += _stprintf(buffer, _T("%s%s"), (pb&0x80)?_T(","):_T(""), (opcode==0x34)?"U":"S");
4418 buffer += _stprintf(buffer, _T("%sY"), (pb&0xc0)?_T(","):_T(""));
4420 buffer += _stprintf(buffer, _T("%sX"), (pb&0xe0)?_T(","):_T(""));
4422 buffer += _stprintf(buffer, _T("%sDP"), (pb&0xf0)?_T(","):_T(""));
4424 buffer += _stprintf(buffer, _T("%sB"), (pb&0xf8)?_T(","):_T(""));
4426 buffer += _stprintf(buffer, _T("%sA"), (pb&0xfc)?_T(","):_T(""));
4428 buffer += _stprintf(buffer, _T("%sCC"), (pb&0xfe)?_T(","):_T(""));
4432 pb = operandarray[0];
4434 buffer += _stprintf(buffer, _T("CC"));
4436 buffer += _stprintf(buffer, _T("%sA"), (pb&0x01)?_T(","):_T(""));
4438 buffer += _stprintf(buffer, _T("%sB"), (pb&0x03)?_T(","):_T(""));
4440 buffer += _stprintf(buffer, _T("%sDP"), (pb&0x07)?_T(","):_T(""));
4442 buffer += _stprintf(buffer, _T("%sX"), (pb&0x0f)?_T(","):_T(""));
4444 buffer += _stprintf(buffer, _T("%sY"), (pb&0x1f)?_T(","):_T(""));
4446 buffer += _stprintf(buffer, _T("%s%s"), (pb&0x3f)?_T(","):_T(""), (opcode==0x35)?_T("U"):_T("S"));
4448 buffer += _stprintf(buffer, _T("%sPC ; (PUL? PC=RTS)"), (pb&0x7f)?_T(","):_T(""));
4457 ea = operandarray[0];
4458 buffer += _stprintf(buffer, _T("<$%02X"), ea);
4462 offset = (int8_t)operandarray[0];
4463 buffer += _stprintf(buffer, _T("%s"), get_value_or_symbol(d_debugger->first_symbol, _T("$%04X"), (pc + offset) & 0xffff));
4467 offset = (int16_t)((operandarray[0] << 8) + operandarray[1]);
4468 buffer += _stprintf(buffer, _T("%s"), get_value_or_symbol(d_debugger->first_symbol, _T("$%04X"), (pc + offset) & 0xffff));
4472 ea = (operandarray[0] << 8) + operandarray[1];
4473 buffer += _stprintf(buffer, _T("%s"), get_value_or_symbol(d_debugger->first_symbol, _T("$%04X"), ea));
4477 pb = operandarray[0];
4478 reg = (pb >> 5) & 3;
4480 indirect = ((pb & 0x90) == 0x90 )? true : false;
4482 // open brackets if indirect
4483 if (indirect /*&& pbm != 0x80 && pbm != 0x82*/)
4484 buffer += _stprintf(buffer, _T("["));
4490 // _tcscpy(buffer, _T("Illegal Postbyte"));
4492 buffer += _stprintf(buffer, _T(",%s+"), m6809_regs[reg]); // Legal even INDIRECT
4496 buffer += _stprintf(buffer, _T(",%s++"), m6809_regs[reg]);
4501 // _tcscpy(buffer, _T("Illegal Postbyte"));
4503 buffer += _stprintf(buffer, _T(",-%s"), m6809_regs[reg]); // Legal even INDIRECT
4507 buffer += _stprintf(buffer, _T(",--%s"), m6809_regs[reg]);
4511 buffer += _stprintf(buffer, _T(",%s"), m6809_regs[reg]);
4514 case 0x85: // (+/- B),R
4515 buffer += _stprintf(buffer, _T("B,%s"), m6809_regs[reg]);
4518 case 0x86: // (+/- A),R
4519 buffer += _stprintf(buffer, _T("A,%s"), m6809_regs[reg]);
4522 case 0x87: // (+/- A),R // Also 0x*6.
4523 buffer += _stprintf(buffer, _T("A,%s"), m6809_regs[reg]);
4526 //_tcscpy(buffer, _T("Illegal Postbyte"));
4529 case 0x88: // (+/- 7 bit offset),R
4530 offset = (int8_t)opram[p++];
4531 buffer += _stprintf(buffer, _T("%s"), (offset < 0) ? "-" : "");
4532 buffer += _stprintf(buffer, _T("$%02X,"), (offset < 0) ? -offset : offset);
4533 buffer += _stprintf(buffer, _T("%s"), m6809_regs[reg]);
4536 case 0x89: // (+/- 15 bit offset),R
4537 offset = (int16_t)((opram[p+0] << 8) + opram[p+1]);
4539 buffer += _stprintf(buffer, _T("%s"), (offset < 0) ? "-" : "");
4540 buffer += _stprintf(buffer, _T("$%04X,"), (offset < 0) ? -offset : offset);
4541 buffer += _stprintf(buffer, _T("%s"), m6809_regs[reg]);
4545 //_tcscpy(buffer, _T("Illegal Postbyte"));
4548 __ea.w = pc & 0xffff;
4551 buffer += _stprintf(buffer, _T("%s"), get_value_or_symbol(d_debugger->first_symbol, _T("$%04X"), __ea.w));
4556 case 0x8b: // (+/- D),R
4557 buffer += _stprintf(buffer, _T("D,%s"), m6809_regs[reg]);
4560 case 0x8c: // (+/- 7 bit offset),PC
4561 offset = (int8_t)opram[p++];
4562 if((name = get_symbol(d_debugger->first_symbol, (pc + 1 + offset) & 0xffff)) != NULL) {
4563 buffer += _stprintf(buffer, _T("%s,PCR"), name);
4565 //buffer += _stprintf(buffer, _T("%s"), (offset < 0) ? "-" : "");
4566 //buffer += _stprintf(buffer, _T("$%02X,PC"), (offset < 0) ? -offset : offset);
4567 buffer += _stprintf(buffer, _T("$%04X,PCR"), get_relative_address_8bit(pc + 1, 0xffff, (int8_t)offset));
4571 case 0x8d: // (+/- 15 bit offset),PC
4572 offset = (int16_t)((opram[p+0] << 8) + opram[p+1]);
4574 if((name = get_symbol(d_debugger->first_symbol, (pc + 2 + offset) & 0xffff)) != NULL) {
4575 buffer += _stprintf(buffer, _T("%s,PCR"), name);
4577 //buffer += _stprintf(buffer, _T("%s"), (offset < 0) ? "-" : "");
4578 buffer += _stprintf(buffer, _T("$%04X,PCR"), get_relative_address_16bit(pc + 2, 0xffff, (int16_t)offset));
4583 //_tcscpy(buffer, _T("Illegal Postbyte"));
4584 offset = (int16_t)0xffff;
4586 buffer += _stprintf(buffer, _T("$%04X"), offset);
4589 case 0x8f: // address
4590 ea = (uint16_t)((opram[p+0] << 8) + opram[p+1]);
4592 buffer += _stprintf(buffer, _T("%s"), get_value_or_symbol(d_debugger->first_symbol, _T("$%04X"), ea));
4595 default: // (+/- 4 bit offset),R
4598 offset = offset - 32;
4599 buffer += _stprintf(buffer, _T("%s"), (offset < 0) ? "-" : "");
4600 buffer += _stprintf(buffer, _T("$%X,"), (offset < 0) ? -offset : offset);
4601 buffer += _stprintf(buffer, _T("%s"), m6809_regs[reg]);
4605 // close brackets if indirect
4606 if (indirect && pbm != 0x80 && pbm != 0x82)
4607 buffer += _stprintf(buffer, _T("]"));
4611 if (numoperands == 2)
4613 ea = (operandarray[0] << 8) + operandarray[1];
4614 buffer += _stprintf(buffer, _T("#%s"), get_value_or_symbol(d_debugger->first_symbol, _T("$%04X"), ea));
4617 if (numoperands == 1)
4619 ea = operandarray[0];
4620 buffer += _stprintf(buffer, _T("#$%02X"), ea);
4625 pb = operandarray[0];
4626 buffer += _stprintf(buffer, _T("%s,%s"), m6809_regs_te[(pb >> 4) & 0xf], m6809_regs_te[pb & 0xf]);
4636 int MC6809::debug_dasm_with_userdata(uint32_t pc, _TCHAR *buffer, size_t buffer_len, uint32_t userdata)
4638 if(__USE_DEBUGGER) {
4639 _TCHAR buffer_tmp[1024]; // enough ???
4641 for(int i = 0; i < 4; i++) {
4642 ops[i] = d_mem_stored->read_data8(pc + i);
4644 int length = cpu_disassemble_m6809(buffer_tmp, pc, ops, ops);
4645 my_tcscpy_s(buffer, buffer_len, buffer_tmp);
4653 bool MC6809::write_debug_reg(const _TCHAR *reg, uint32_t data)
4655 //#ifdef USE_DEBUGGER
4656 if(_tcsicmp(reg, _T("PC")) == 0) {
4658 } else if(_tcsicmp(reg, _T("DP")) == 0) {
4660 } else if(_tcsicmp(reg, _T("A")) == 0) {
4662 } else if(_tcsicmp(reg, _T("B")) == 0) {
4664 } else if(_tcsicmp(reg, _T("D")) == 0) {
4666 } else if(_tcsicmp(reg, _T("U")) == 0) {
4668 } else if(_tcsicmp(reg, _T("X")) == 0) {
4670 } else if(_tcsicmp(reg, _T("Y")) == 0) {
4672 } else if(_tcsicmp(reg, _T("S")) == 0) {
4674 } else if(_tcsicmp(reg, _T("CC")) == 0) {
4683 bool MC6809::get_debug_regs_description(_TCHAR *buffer, size_t buffer_len)
4685 my_stprintf_s(buffer, buffer_len,
4686 _T("PC : PROGRAM COUNTER (16bit)\n")
4687 _T("CC : CONDITION FLAGS (16bit)\n")
4688 _T("DP : DIRECT POINTER (8bit)\n")
4689 _T("S : SYSTEM STACK POINTER (16bit)\n")
4690 _T("U : USER STACK POINTER (16bit)\n")
4691 _T("X : INDEX REGISTER (16bit)\n")
4692 _T("Y : INDEX REGISTER (16bit)\n")
4693 _T("A : ACCUMLATOR (8bit)\n")
4694 _T("B : ACCUMLATOR (8bit)\n")
4695 _T("D : ACCUMLATOR (16bit)\n")
4696 _T("NOTE: D is chain of A and B.D = (A << 8) | B.\n")
4697 _T("NOTE: ENDIANNESS is BIG.\n")
4699 _T("foo #bar (16/8bit) : immediate value of bar\n")
4700 _T("foo <bar (8bit) : direct addressing of bar; address = (DP << 8) | bar.\n")
4701 _T("foo bar (16bit or index) : extended address.address = bar\n")
4702 _T("foo [bar] (16bit or index) : indirect addressing.address = VALUE16(bar)\n")
4704 _T("E: ENTIRE / F: FAST INTERRUPT(FIRQ) / H: HALF CARRY / I: (STANDARD) INTERRUPT(IRQ/SWI)\n")
4705 _T("N: NEGATIVE / Z: ZERO / V: OVERFLOW / C: CARRY")
4711 PC = 0000 PPC = 0000
4712 INTR=[ IRQ FIRQ NMI HALT][CI CO SI SO TRAP] CC =[EFHINZVC]
4713 A = 00 B = 00 DP = 00 X = 0000 Y = 0000 U = 0000 S = 0000 EA = 0000
4714 Clocks = 0 (0) Since Scanline = 0/0 (0/0)
4716 bool MC6809::get_debug_regs_info(_TCHAR *buffer, size_t buffer_len)
4718 //#ifdef USE_DEBUGGER
4719 my_stprintf_s(buffer, buffer_len,
4720 _T("PC = %04x PPC = %04x\n")
4721 _T("INTR = [%s %s %s %s][%s %s %s %s %s] CC = [%c%c%c%c%c%c%c%c]\n")
4722 _T("A = %02x B = %02x DP = %02x X = %04x Y = %04x U = %04x S = %04x EA = %04x\n")
4723 _T("Clocks = %llu (%llu) Since Scanline = %d/%d (%d/%d)"),
4726 ((int_state & MC6809_IRQ_BIT) == 0) ? _T("----") : _T(" IRQ"),
4727 ((int_state & MC6809_FIRQ_BIT) == 0) ? _T("----") : _T("FIRQ"),
4728 ((int_state & MC6809_NMI_BIT) == 0) ? _T("----") : _T(" NMI"),
4729 ((int_state & MC6809_HALT_BIT) == 0) ? _T("----") : _T("HALT"),
4730 ((int_state & MC6809_CWAI_IN) == 0) ? _T("--") : _T("CI"),
4731 ((int_state & MC6809_CWAI_OUT) == 0) ? _T("--") : _T("CO"),
4732 ((int_state & MC6809_SYNC_IN) == 0) ? _T("--") : _T("SI"),
4733 ((int_state & MC6809_SYNC_OUT) == 0) ? _T("--") : _T("SO"),
4734 ((int_state & MC6809_INSN_HALT) == 0) ? _T("----") : _T("TRAP"),
4735 ((CC & CC_E) == 0) ? _T('-') : _T('E'),
4736 ((CC & CC_IF) == 0) ? _T('-') : _T('F'),
4737 ((CC & CC_H) == 0) ? _T('-') : _T('H'),
4738 ((CC & CC_II) == 0) ? _T('-') : _T('I'),
4739 ((CC & CC_N) == 0) ? _T('-') : _T('N'),
4740 ((CC & CC_Z) == 0) ? _T('-') : _T('Z'),
4741 ((CC & CC_V) == 0) ? _T('-') : _T('V'),
4742 ((CC & CC_C) == 0) ? _T('-') : _T('C'),
4746 total_icount, total_icount - prev_total_icount,
4747 get_passed_clock_since_vline(), get_cur_vline_clocks(), get_cur_vline(), get_lines_per_frame()
4749 prev_total_icount = total_icount;
4754 #define STATE_VERSION 5
4756 bool MC6809::process_state(FILEIO* state_fio, bool loading)
4758 if(!state_fio->StateCheckUint32(STATE_VERSION)) {
4761 if(!state_fio->StateCheckInt32(this_device_id)) {
4764 state_fio->StateValue(icount);
4765 state_fio->StateValue(extra_icount);
4766 state_fio->StateValue(int_state);
4768 state_fio->StateValue(pc.d);
4769 state_fio->StateValue(ppc.d);
4770 state_fio->StateValue(acc.d);
4771 state_fio->StateValue(dp.d);
4772 state_fio->StateValue(u.d);
4773 state_fio->StateValue(s.d);
4774 state_fio->StateValue(x.d);
4775 state_fio->StateValue(y.d);
4776 state_fio->StateValue(cc);
4777 state_fio->StateValue(ea.d);
4780 state_fio->StateValue(req_halt_on);
4781 state_fio->StateValue(req_halt_off);
4782 state_fio->StateValue(busreq);
4784 state_fio->StateValue(total_icount);
4785 state_fio->StateValue(waitfactor);
4786 state_fio->StateValue(waitcount);
4790 prev_total_icount = total_icount;
4791 // Post process for collecting statistics.
4792 cycles_tmp_count = total_icount;
4793 extra_tmp_count = 0;