source/src/vm/mc6809_base.cpp

   1 /*
   2         Skelton for retropc emulator
   3
   4         Origin : MAME 0.142
   5         Author : Takeda.Toshiya
   6         Date   : 2011.05.06-
   7
   8         [ MC6809 ]
   9         Notes from K.Ohta <whatisthis.sowhat _at_ gmail.com> at Jan 16, 2015:
  10               All of undocumented instructions (i.e. ngc, flag16) of MC6809(not HD6309) are written by me.
  11               These behaviors of undocumented insns are refered from "vm/cpu_x86.asm" (ia32 assembly codefor nasm) within XM7
  12               written by Ryu Takegami , and older article wrote in magazine, "I/O" at 1985.
  13               But, these C implements are written from scratch by me , and I tested many years at XM7/SDL.
  14               Perhaps, these insns. are not implement MAME/MESS yet.
  15 */
  16
  17 // Fixed IRQ/FIRQ by Mr.Sasaji at 2011.06.17
  18 #include "./mc6809.h"
  19 #include "./mc6809_consts.h"
  20 #include "common.h"
  21 #include "../config.h"
  22
  23 #define OP_HANDLER(_name) void MC6809_BASE::_name (void)
  24
  25 static void (MC6809_BASE::*m6809_main[0x100]) (void) = {
  26 /*          0xX0,   0xX1,     0xX2,    0xX3,    0xX4,    0xX5,    0xX6,    0xX7,
  27             0xX8,   0xX9,     0xXA,    0xXB,    0xXC,    0xXD,    0xXE,    0xXF   */
  28
  29 /* 0x0X */
  30         &MC6809_BASE::neg_di, &MC6809_BASE::neg_di, &MC6809_BASE::ngc_di, &MC6809_BASE::com_di,
  31         &MC6809_BASE::lsr_di, &MC6809_BASE::lsr_di, &MC6809_BASE::ror_di, &MC6809_BASE::asr_di,
  32         &MC6809_BASE::asl_di, &MC6809_BASE::rol_di, &MC6809_BASE::dec_di, &MC6809_BASE::dcc_di,
  33         &MC6809_BASE::inc_di, &MC6809_BASE::tst_di, &MC6809_BASE::jmp_di, &MC6809_BASE::clr_di,
  34 /* 0x1X */
  35         &MC6809_BASE::pref10, &MC6809_BASE::pref11, &MC6809_BASE::nop, &MC6809_BASE::sync_09,
  36         &MC6809_BASE::trap, &MC6809_BASE::trap, &MC6809_BASE::lbra, &MC6809_BASE::lbsr,
  37         &MC6809_BASE::aslcc_in, &MC6809_BASE::daa, &MC6809_BASE::orcc, &MC6809_BASE::nop,
  38         &MC6809_BASE::andcc, &MC6809_BASE::sex, &MC6809_BASE::exg, &MC6809_BASE::tfr,
  39 /* 0x2X */
  40         &MC6809_BASE::bra, &MC6809_BASE::brn, &MC6809_BASE::bhi, &MC6809_BASE::bls,
  41         &MC6809_BASE::bcc, &MC6809_BASE::bcs, &MC6809_BASE::bne, &MC6809_BASE::beq,
  42         &MC6809_BASE::bvc, &MC6809_BASE::bvs, &MC6809_BASE::bpl, &MC6809_BASE::bmi,
  43         &MC6809_BASE::bge, &MC6809_BASE::blt, &MC6809_BASE::bgt, &MC6809_BASE::ble,
  44 /* 0x3X */
  45         &MC6809_BASE::leax, &MC6809_BASE::leay, &MC6809_BASE::leas, &MC6809_BASE::leau,
  46         &MC6809_BASE::pshs, &MC6809_BASE::puls, &MC6809_BASE::pshu, &MC6809_BASE::pulu,
  47         &MC6809_BASE::andcc, &MC6809_BASE::rts, &MC6809_BASE::abx, &MC6809_BASE::rti,
  48         &MC6809_BASE::cwai, &MC6809_BASE::mul, &MC6809_BASE::rst, &MC6809_BASE::swi,
  49 /* 0x4X */
  50         &MC6809_BASE::nega, &MC6809_BASE::nega, &MC6809_BASE::ngca, &MC6809_BASE::coma,
  51         &MC6809_BASE::lsra, &MC6809_BASE::lsra, &MC6809_BASE::rora, &MC6809_BASE::asra,
  52         &MC6809_BASE::asla, &MC6809_BASE::rola, &MC6809_BASE::deca, &MC6809_BASE::dcca,
  53         &MC6809_BASE::inca, &MC6809_BASE::tsta, &MC6809_BASE::clca, &MC6809_BASE::clra,
  54 /* 0x5X */
  55         &MC6809_BASE::negb, &MC6809_BASE::negb, &MC6809_BASE::ngcb, &MC6809_BASE::comb,
  56         &MC6809_BASE::lsrb, &MC6809_BASE::lsrb, &MC6809_BASE::rorb, &MC6809_BASE::asrb,
  57         &MC6809_BASE::aslb, &MC6809_BASE::rolb, &MC6809_BASE::decb, &MC6809_BASE::dccb,
  58         &MC6809_BASE::incb, &MC6809_BASE::tstb, &MC6809_BASE::clcb, &MC6809_BASE::clrb,
  59 /* 0x6X */
  60         &MC6809_BASE::neg_ix, &MC6809_BASE::neg_ix, &MC6809_BASE::ngc_ix, &MC6809_BASE::com_ix,
  61         &MC6809_BASE::lsr_ix, &MC6809_BASE::lsr_ix, &MC6809_BASE::ror_ix, &MC6809_BASE::asr_ix,
  62         &MC6809_BASE::asl_ix, &MC6809_BASE::rol_ix, &MC6809_BASE::dec_ix, &MC6809_BASE::dcc_ix,
  63         &MC6809_BASE::inc_ix, &MC6809_BASE::tst_ix, &MC6809_BASE::jmp_ix, &MC6809_BASE::clr_ix,
  64 /* 0x7X */
  65         &MC6809_BASE::neg_ex, &MC6809_BASE::neg_ex, &MC6809_BASE::ngc_ex, &MC6809_BASE::com_ex,
  66         &MC6809_BASE::lsr_ex, &MC6809_BASE::lsr_ex, &MC6809_BASE::ror_ex, &MC6809_BASE::asr_ex,
  67         &MC6809_BASE::asl_ex, &MC6809_BASE::rol_ex, &MC6809_BASE::dec_ex, &MC6809_BASE::dcc_ex,
  68         &MC6809_BASE::inc_ex, &MC6809_BASE::tst_ex, &MC6809_BASE::jmp_ex, &MC6809_BASE::clr_ex,
  69 /* 0x8X */
  70         &MC6809_BASE::suba_im, &MC6809_BASE::cmpa_im, &MC6809_BASE::sbca_im, &MC6809_BASE::subd_im,
  71         &MC6809_BASE::anda_im, &MC6809_BASE::bita_im, &MC6809_BASE::lda_im, &MC6809_BASE::flag8_im,
  72         &MC6809_BASE::eora_im, &MC6809_BASE::adca_im, &MC6809_BASE::ora_im, &MC6809_BASE::adda_im,
  73         &MC6809_BASE::cmpx_im, &MC6809_BASE::bsr, &MC6809_BASE::ldx_im, &MC6809_BASE::flag16_im,
  74 /* 0x9X */
  75         &MC6809_BASE::suba_di, &MC6809_BASE::cmpa_di, &MC6809_BASE::sbca_di, &MC6809_BASE::subd_di,
  76         &MC6809_BASE::anda_di, &MC6809_BASE::bita_di, &MC6809_BASE::lda_di, &MC6809_BASE::sta_di,
  77         &MC6809_BASE::eora_di, &MC6809_BASE::adca_di, &MC6809_BASE::ora_di, &MC6809_BASE::adda_di,
  78         &MC6809_BASE::cmpx_di, &MC6809_BASE::jsr_di, &MC6809_BASE::ldx_di, &MC6809_BASE::stx_di,
  79 /* 0xAX */
  80         &MC6809_BASE::suba_ix, &MC6809_BASE::cmpa_ix, &MC6809_BASE::sbca_ix, &MC6809_BASE::subd_ix,
  81         &MC6809_BASE::anda_ix, &MC6809_BASE::bita_ix, &MC6809_BASE::lda_ix, &MC6809_BASE::sta_ix,
  82         &MC6809_BASE::eora_ix, &MC6809_BASE::adca_ix, &MC6809_BASE::ora_ix, &MC6809_BASE::adda_ix,
  83         &MC6809_BASE::cmpx_ix, &MC6809_BASE::jsr_ix, &MC6809_BASE::ldx_ix, &MC6809_BASE::stx_ix,
  84 /* 0xBX */
  85         &MC6809_BASE::suba_ex, &MC6809_BASE::cmpa_ex, &MC6809_BASE::sbca_ex, &MC6809_BASE::subd_ex,
  86         &MC6809_BASE::anda_ex, &MC6809_BASE::bita_ex, &MC6809_BASE::lda_ex, &MC6809_BASE::sta_ex,
  87         &MC6809_BASE::eora_ex, &MC6809_BASE::adca_ex, &MC6809_BASE::ora_ex, &MC6809_BASE::adda_ex,
  88         &MC6809_BASE::cmpx_ex, &MC6809_BASE::jsr_ex, &MC6809_BASE::ldx_ex, &MC6809_BASE::stx_ex,
  89 /* 0xCX */
  90         &MC6809_BASE::subb_im, &MC6809_BASE::cmpb_im, &MC6809_BASE::sbcb_im, &MC6809_BASE::addd_im,
  91         &MC6809_BASE::andb_im, &MC6809_BASE::bitb_im, &MC6809_BASE::ldb_im, &MC6809_BASE::flag8_im,
  92         &MC6809_BASE::eorb_im, &MC6809_BASE::adcb_im, &MC6809_BASE::orb_im, &MC6809_BASE::addb_im,
  93         &MC6809_BASE::ldd_im, &MC6809_BASE::trap, &MC6809_BASE::ldu_im, &MC6809_BASE::flag16_im,
  94 /* 0xDX */
  95         &MC6809_BASE::subb_di, &MC6809_BASE::cmpb_di, &MC6809_BASE::sbcb_di, &MC6809_BASE::addd_di,
  96         &MC6809_BASE::andb_di, &MC6809_BASE::bitb_di, &MC6809_BASE::ldb_di, &MC6809_BASE::stb_di,
  97         &MC6809_BASE::eorb_di, &MC6809_BASE::adcb_di, &MC6809_BASE::orb_di, &MC6809_BASE::addb_di,
  98         &MC6809_BASE::ldd_di, &MC6809_BASE::std_di, &MC6809_BASE::ldu_di, &MC6809_BASE::stu_di,
  99 /* 0xEX */
 100         &MC6809_BASE::subb_ix, &MC6809_BASE::cmpb_ix, &MC6809_BASE::sbcb_ix, &MC6809_BASE::addd_ix,
 101         &MC6809_BASE::andb_ix, &MC6809_BASE::bitb_ix, &MC6809_BASE::ldb_ix, &MC6809_BASE::stb_ix,
 102         &MC6809_BASE::eorb_ix, &MC6809_BASE::adcb_ix, &MC6809_BASE::orb_ix, &MC6809_BASE::addb_ix,
 103         &MC6809_BASE::ldd_ix, &MC6809_BASE::std_ix, &MC6809_BASE::ldu_ix, &MC6809_BASE::stu_ix,
 104 /* 0xFX */
 105         &MC6809_BASE::subb_ex, &MC6809_BASE::cmpb_ex, &MC6809_BASE::sbcb_ex, &MC6809_BASE::addd_ex,
 106         &MC6809_BASE::andb_ex, &MC6809_BASE::bitb_ex, &MC6809_BASE::ldb_ex, &MC6809_BASE::stb_ex,
 107         &MC6809_BASE::eorb_ex, &MC6809_BASE::adcb_ex, &MC6809_BASE::orb_ex, &MC6809_BASE::addb_ex,
 108         &MC6809_BASE::ldd_ex, &MC6809_BASE::std_ex, &MC6809_BASE::ldu_ex, &MC6809_BASE::stu_ex
 109         };
 110 /* macros for branch instructions */
 111 inline void MC6809_BASE::BRANCH(bool cond)
 112 {
 113         uint8_t t;
 114         IMMBYTE(t);
 115         if(!cond) return;
 116         PC = PC + SIGNED(t);
 117         PC = PC & 0xffff;
 118 }
 119
 120 inline void MC6809_BASE::LBRANCH(bool cond)
 121 {
 122         pair32_t t;
 123         IMMWORD(t);
 124         if(!cond) return;
 125         icount -= 1;
 126         PC += t.w.l;
 127         PC = PC & 0xffff;
 128 }
 129
 130 /* macros for setting/getting registers in TFR/EXG instructions */
 131
 132 inline pair32_t MC6809_BASE::RM16_PAIR(uint32_t addr)
 133 {
 134         pair32_t b;
 135         b.d = 0;
 136         b.b.h = RM(addr);
 137         b.b.l = RM((addr + 1));
 138         return b;
 139 }
 140
 141 inline void MC6809_BASE::WM16(uint32_t Addr, pair32_t *p)
 142 {
 143         WM(Addr , p->b.h);
 144         WM((Addr + 1), p->b.l);
 145 }
 146
 147 void MC6809_BASE::reset()
 148 {
 149         //extar_tmp_count += extra_icount;
 150
 151         icount = 0;
 152         waitcount = 0;
 153         int_state &= MC6809_HALT_BIT;
 154         extra_icount = 0;
 155         //busreq = false;
 156
 157         DPD = 0;        /* Reset direct page register */
 158         CC = 0;
 159         D = 0;
 160         X = 0;
 161         Y = 0;
 162         U = 0;
 163         S = 0;
 164         EA = 0;
 165 //#if defined(_FM7) || defined(_FM8) || defined(_FM77_VARIANTS) || defined(_FM77AV_VARIANTS)
 166
 167         if((req_halt_on) && !(req_halt_off)) {
 168                 int_state |= MC6809_HALT_BIT;
 169         } else {
 170                 req_halt_on = req_halt_off = false;
 171         }
 172         if((int_state & MC6809_HALT_BIT) != 0) {
 173                 write_signals(&outputs_bus_ba, 0xffffffff);
 174                 write_signals(&outputs_bus_bs, 0xffffffff);
 175         } else {
 176                 write_signals(&outputs_bus_ba, 0x00000000);
 177                 write_signals(&outputs_bus_bs, 0x00000000);
 178         }
 179
 180 //#endif
 181         CC |= CC_II;    /* IRQ disabled */
 182         CC |= CC_IF;    /* FIRQ disabled */
 183
 184         pPC = RM16_PAIR(0xfffe);
 185 }
 186
 187
 188 void MC6809_BASE::initialize()
 189 {
 190         DEVICE::initialize();
 191         int_state = 0;
 192         busreq = false;
 193         icount = 0;
 194         extra_icount = 0;
 195         req_halt_on = req_halt_off = false;
 196         cycles_tmp_count = 0;
 197         insns_count = 0;
 198
 199         __USE_DEBUGGER = osd->check_feature(_T("USE_DEBUGGER"));
 200         insns_count = 0;
 201         frames_count = 0;
 202         cycles_tmp_count = 0;
 203         nmi_count = 0;
 204         firq_count = 0;
 205         irq_count = 0;
 206 //      if(config.print_statistics) {
 207                 register_frame_event(this);
 208 //      }
 209         waitfactor = 0;
 210         waitcount = 0;
 211 }
 212
 213 void MC6809_BASE::event_frame()
 214 {
 215         if(frames_count < 0) {
 216                 cycles_tmp_count = total_icount;
 217                 extra_tmp_count = 0;
 218                 insns_count = 0;
 219                 frames_count = 0;
 220                 nmi_count = 0;
 221                 firq_count = 0;
 222                 irq_count = 0;
 223         } else if(frames_count >= 16) {
 224                 uint64_t _icount = total_icount - cycles_tmp_count;
 225                 if(config.print_statistics) {
 226                         out_debug_log(_T("INFO: 16 frames done.\nINFO: CLOCKS = %ld INSNS = %d EXTRA_ICOUNT = %d \nINFO: NMI# = %d FIRQ# = %d IRQ# = %d"), _icount, insns_count, extra_tmp_count, nmi_count, firq_count, irq_count);
 227                 }
 228                 cycles_tmp_count = total_icount;
 229                 insns_count = 0;
 230                 extra_tmp_count = 0;
 231                 frames_count = 0;
 232                 nmi_count = 0;
 233                 firq_count = 0;
 234                 irq_count = 0;
 235         } else {
 236                 frames_count++;
 237         }
 238 }
 239
 240 void MC6809_BASE::write_signal(int id, uint32_t data, uint32_t mask)
 241 {
 242         if(id == SIG_CPU_IRQ) {
 243                 if(data & mask) {
 244                         int_state |= MC6809_IRQ_BIT;
 245                         irq_count++;
 246                 } else {
 247                         int_state &= ~MC6809_IRQ_BIT;
 248                 }
 249         } else if(id == SIG_CPU_FIRQ) {
 250                 if(data & mask) {
 251                         int_state |= MC6809_FIRQ_BIT;
 252                         firq_count++;
 253                 } else {
 254                         int_state &= ~MC6809_FIRQ_BIT;
 255                 }
 256         } else if(id == SIG_CPU_NMI) {
 257                 if(data & mask) {
 258                         int_state |= MC6809_NMI_BIT;
 259                         nmi_count++;
 260                 } else {
 261                         int_state &= ~MC6809_NMI_BIT;
 262                 }
 263         } else if(id == SIG_CPU_BUSREQ) {
 264                 if(data & mask) {
 265                         req_halt_on = false;
 266                         req_halt_off = false;
 267                         int_state |= MC6809_HALT_BIT;
 268                         busreq = false;
 269                 } else {
 270                         req_halt_on = false;
 271                         req_halt_off = false;
 272                         int_state &= ~MC6809_HALT_BIT;
 273                 }
 274         } else if(id == SIG_CPU_HALTREQ) {
 275                 if(data & mask) {
 276                         req_halt_on = true;
 277                         //int_state |= MC6809_HALT_BIT;
 278                 } else {
 279                         if(req_halt_on) {
 280                                 req_halt_off = true;
 281                         }
 282                         //int_state &= ~MC6809_HALT_BIT;
 283                 }
 284         } else if(id == SIG_CPU_WAIT_FACTOR) {
 285                 waitfactor = data; // 65536.
 286         }
 287 }
 288
 289 void MC6809_BASE::cpu_nmi_push(void)
 290 {
 291         if ((int_state & MC6809_CWAI_IN) == 0) {
 292                 CC |= CC_E;
 293                 PUSHWORD(pPC);
 294                 PUSHWORD(pU);
 295                 PUSHWORD(pY);
 296                 PUSHWORD(pX);
 297                 PUSHBYTE(DP);
 298                 PUSHBYTE(B);
 299                 PUSHBYTE(A);
 300                 PUSHBYTE(CC);
 301         }
 302         return;
 303 }
 304
 305 void MC6809_BASE::cpu_nmi_fetch_vector_address(void)
 306 {
 307         pPC = RM16_PAIR(0xfffc);
 308 //      printf("NMI occured PC=0x%04x VECTOR=%04x SP=%04x \n",rpc.w.l,pPC.w.l,S);
 309         int_state |= MC6809_CWAI_OUT;
 310         //int_state &= ~(MC6809_NMI_BIT | MC6809_SYNC_IN | MC6809_SYNC_OUT | MC6809_CWAI_IN);   // $FF1E
 311         return;
 312 }
 313
 314
 315
 316 void MC6809_BASE::cpu_firq_fetch_vector_address(void)
 317 {
 318         pPC = RM16_PAIR(0xfff6);
 319         int_state |= MC6809_CWAI_OUT;
 320         int_state &= ~(MC6809_SYNC_IN | MC6809_SYNC_OUT );
 321         return;
 322 }
 323
 324 void MC6809_BASE::cpu_firq_push(void)
 325 {
 326         //pair32_t rpc = pPC;
 327         if ((int_state & MC6809_CWAI_IN) == 0) {
 328                 /* NORMAL */
 329                 CC &= ~CC_E;
 330                 PUSHWORD(pPC);
 331                 PUSHBYTE(CC);
 332         }
 333 //      printf("Firq occured PC=0x%04x VECTOR=%04x SP=%04x \n",rpc.w.l,pPC.w.l,S);
 334 }
 335 void MC6809_BASE::cpu_irq_push(void)
 336 {
 337         if ((int_state & MC6809_CWAI_IN) == 0) {
 338                 CC |= CC_E;
 339                 PUSHWORD(pPC);
 340                 PUSHWORD(pU);
 341                 PUSHWORD(pY);
 342                 PUSHWORD(pX);
 343                 PUSHBYTE(DP);
 344                 PUSHBYTE(B);
 345                 PUSHBYTE(A);
 346                 PUSHBYTE(CC);
 347         }
 348 }
 349 void MC6809_BASE::cpu_irq_fetch_vector_address(void)
 350 {
 351         //pair32_t rpc = pPC;
 352         pPC = RM16_PAIR(0xfff8);
 353         int_state |= MC6809_CWAI_OUT;
 354         int_state &= ~(MC6809_SYNC_IN | MC6809_SYNC_OUT);
 355 }
 356
 357 void MC6809_BASE::cpu_wait(int clocks)
 358 {
 359         uint32_t ncount = 0;
 360         if(clocks < 0) return;
 361         if(waitfactor == 0) return;
 362         waitcount += (waitfactor * (uint32_t)clocks);
 363         if(waitcount >= 65536) {
 364                 ncount = waitcount >> 16;
 365                 waitcount = waitcount - (ncount << 16);
 366         }
 367         if(ncount > 0) extra_icount += ncount;
 368 }
 369
 370
 371 int MC6809_BASE::run(int clock)
 372 {
 373         int cycle = 0;
 374         int first_icount = 0;
 375         int passed_icount = 0;
 376         first_icount = icount;
 377         if(extra_icount > 0) {
 378                 extra_tmp_count += extra_icount;
 379         }
 380
 381         if((req_halt_on) && !(req_halt_off)) {
 382                 int_state |= MC6809_HALT_BIT;
 383         } else  if(req_halt_on && req_halt_off) { // HALT OFF
 384                 int_state &= ~MC6809_HALT_BIT;
 385                 req_halt_on = req_halt_off = false;
 386         }
 387
 388         if ((int_state & MC6809_HALT_BIT) != 0) {       // 0x80
 389                 if(clock <= 0) {
 390                         clock = 1;
 391                 } else {
 392                         icount += clock;
 393                 }
 394                 first_icount = icount;
 395                 if(!busreq) {
 396                         write_signals(&outputs_bus_ba, 0);
 397                         write_signals(&outputs_bus_bs, 0);
 398                         busreq = true;
 399                         icount -= clock;
 400                         icount -= extra_icount;
 401                         extra_icount = 0;
 402                         passed_icount = first_icount - icount;
 403                         total_icount += passed_icount;
 404
 405                         write_signals(&outputs_bus_ba, 0xffffffff);
 406                         write_signals(&outputs_bus_bs, 0xffffffff);
 407                         debugger_hook();
 408                         cpu_wait(passed_icount);
 409                         return passed_icount;
 410                 } else {
 411                         icount -= clock;
 412                         icount -= extra_icount;
 413                         extra_icount = 0;
 414                         passed_icount = first_icount - icount;
 415                         total_icount += passed_icount;
 416                         debugger_hook();
 417                         cpu_wait(passed_icount);
 418                         return passed_icount;
 419                 }
 420         }
 421         if(busreq) { // Exit from BUSREQ state.
 422                 if((int_state & MC6809_SYNC_IN) != 0) {
 423                         write_signals(&outputs_bus_ba, 0xffffffff);
 424                 } else {
 425                         write_signals(&outputs_bus_ba, 0x00000000);
 426                 }
 427                 write_signals(&outputs_bus_bs, 0x00000000);
 428                 busreq = false;
 429         }
 430         if((int_state & MC6809_INSN_HALT) != 0) {       // 0x80
 431                 if(clock <= 1) clock = 1;
 432                 icount += clock;
 433                 first_icount = icount;
 434                 while(icount > 0) {
 435                         RM(PCD); //Will save.Need to keep.
 436                         icount -= 1;
 437                 }
 438                 icount -= extra_icount;
 439                 passed_icount = first_icount - icount;
 440                 extra_icount = 0;
 441                 PC++;
 442                 debugger_hook();
 443                 total_icount += passed_icount;
 444                 cpu_wait(passed_icount);
 445                 return passed_icount;
 446         }
 447         /*
 448          * Check Interrupt
 449          */
 450 check_nmi:
 451         if ((int_state & (MC6809_NMI_BIT | MC6809_FIRQ_BIT | MC6809_IRQ_BIT)) != 0) {   // 0x0007
 452                 if ((int_state & MC6809_NMI_BIT) == 0)
 453                         goto check_firq;
 454                 int_state &= ~MC6809_SYNC_IN; // Thanks to Ryu Takegami.
 455                 write_signals(&outputs_bus_ba, 0x00000000);
 456                 write_signals(&outputs_bus_bs, 0x00000000);
 457                 if((int_state & MC6809_CWAI_IN) == 0) {
 458                         CC = CC | CC_E;
 459                         cycle += 14;
 460                         cpu_nmi_push();
 461                 }
 462                 write_signals(&outputs_bus_bs, 0xffffffff);
 463                 CC = CC | CC_II | CC_IF;        // 0x50
 464                 cycle += 2;
 465                 cpu_nmi_fetch_vector_address();
 466                 cycle += 3;
 467                 write_signals(&outputs_bus_bs, 0x00000000);
 468                 int_state &= ~(MC6809_NMI_BIT | MC6809_SYNC_IN | MC6809_SYNC_OUT);      // $FF1E
 469                 goto int_cycle;
 470         } else {
 471                 // OK, none interrupts.
 472                 goto check_ok;
 473         }
 474 check_firq:
 475         if ((int_state & MC6809_FIRQ_BIT) != 0) {
 476                 int_state &= ~MC6809_SYNC_IN; // Moved to before checking MASK.Thanks to Ryu Takegami.
 477                 if ((CC & CC_IF) != 0)
 478                         goto check_irq;
 479                 write_signals(&outputs_bus_bs, 0x00000000);
 480                 write_signals(&outputs_bus_ba, 0x00000000);
 481                 if((int_state & MC6809_CWAI_IN) == 0) {
 482                         CC = CC & (uint8_t)(~CC_E);
 483                         cycle += 5;
 484                         cpu_firq_push();
 485                 }
 486                 write_signals(&outputs_bus_bs, 0xffffffff);
 487                 CC = CC | CC_II | CC_IF;        // 0x50
 488                 cycle += 2;
 489                 cpu_firq_fetch_vector_address();
 490                 cycle += 3;
 491                 write_signals(&outputs_bus_bs, 0x00000000);
 492                 int_state &= ~(MC6809_SYNC_IN | MC6809_SYNC_OUT);       // $FF1E
 493                 goto int_cycle;
 494
 495         }
 496 check_irq:
 497         if ((int_state & MC6809_IRQ_BIT) != 0) {
 498                 int_state &= ~MC6809_SYNC_IN; // Moved to before checking MASK.Thanks to Ryu Takegami.
 499                 if ((CC & CC_II) != 0)
 500                         goto check_ok;
 501                 write_signals(&outputs_bus_bs, 0x00000000);
 502                 write_signals(&outputs_bus_ba, 0x00000000);
 503                 if((int_state & MC6809_CWAI_IN) == 0) {
 504                         CC = CC | CC_E;
 505                         cycle += 14;
 506                         cpu_irq_push();
 507                 }
 508                 write_signals(&outputs_bus_bs, 0xffffffff);
 509                 cycle += 2;
 510                 CC = CC | CC_II;        // 0x50
 511                 cpu_irq_fetch_vector_address();
 512                 cycle += 3;
 513                 write_signals(&outputs_bus_bs, 0x00000000);
 514                 int_state &= ~(MC6809_SYNC_IN | MC6809_SYNC_OUT);       // $FF1E
 515                 goto int_cycle;
 516         }
 517         /*
 518          * NO INTERRUPT
 519          */
 520         goto check_ok;
 521         /*
 522          * INTERRUPT
 523          */
 524 int_cycle:
 525         if((int_state & MC6809_CWAI_IN) != 0) {
 526                 int_state &= ~MC6809_CWAI_IN;
 527         }
 528         if(clock >= 0) icount += clock;
 529         first_icount = icount;
 530         icount -= cycle;
 531         debugger_hook();
 532         icount -= extra_icount;
 533         passed_icount = first_icount - icount;
 534         extra_icount = 0;
 535         total_icount += (uint64_t)passed_icount;
 536         cpu_wait(passed_icount);
 537 #if 1
 538         if((icount <= 0) || (clock <= passed_icount)) return passed_icount;
 539         clock -= passed_icount;
 540 #else
 541         return passed_icount;
 542 #endif
 543         // goto check_ok;
 544         // run cpu
 545 check_ok:
 546         if((int_state & MC6809_SYNC_IN) != 0) {
 547                 int tmp_passed_icount = 0;
 548                 first_icount = icount;
 549                 if(clock < 1) clock = 1;
 550                 icount -= extra_icount;
 551                 icount -= clock;
 552                 extra_icount = 0;
 553                 debugger_hook();
 554                 tmp_passed_icount = first_icount - icount;
 555                 total_icount += (uint64_t)passed_icount;
 556                 cpu_wait(tmp_passed_icount);
 557                 return passed_icount + tmp_passed_icount;
 558         }
 559         if((int_state & MC6809_CWAI_IN) == 0) {
 560                 if(clock <= -1) {
 561                         // run only one opcode
 562                         int tmp_passed_icount = 0;
 563                         first_icount = icount;
 564                         insns_count++;
 565                         run_one_opecode();
 566                         tmp_passed_icount = first_icount - icount;
 567                         cpu_wait(tmp_passed_icount);
 568                         return passed_icount + tmp_passed_icount;;
 569                 } else {
 570                         // run cpu while given clocks
 571                         int tmp_passed_icount = 0;
 572                         icount += clock;
 573                         first_icount = icount;
 574                         while((icount > 0) && (!(req_halt_on) && !(req_halt_off)) && (!busreq)) {
 575                                 insns_count++;
 576                                 run_one_opecode();
 577                         }
 578                         tmp_passed_icount = first_icount - icount;
 579                         cpu_wait(tmp_passed_icount);
 580                         return tmp_passed_icount + passed_icount;
 581                 }
 582         } else { // CWAI_IN
 583                 int tmp_passed_icount = 0;
 584                 first_icount = icount;
 585                 if(clock < 1) clock = 1;
 586                 icount -= extra_icount;
 587                 icount -= clock;
 588                 extra_icount = 0;
 589                 debugger_hook();
 590                 tmp_passed_icount = first_icount - icount;
 591                 total_icount += tmp_passed_icount;
 592                 cpu_wait(tmp_passed_icount);
 593                 return passed_icount + tmp_passed_icount;
 594         }
 595
 596 }
 597
 598 void MC6809_BASE::debugger_hook()
 599 {
 600
 601 }
 602
 603 void MC6809_BASE::run_one_opecode()
 604 {
 605         pPPC = pPC;
 606         uint8_t ireg = ROP(PCD);
 607         PC++;
 608         icount -= cycles1[ireg];
 609         icount -= extra_icount;
 610         extra_icount = 0;
 611         op(ireg);
 612 }
 613
 614 void MC6809_BASE::op(uint8_t ireg)
 615 {
 616         //printf("CPU(%08x) PC=%04x OP=%02x %02x %02x %02x %02x\n", (void *)this, PC, ireg, RM(PC), RM(PC + 1), RM(PC + 2), RM(PC + 3));
 617
 618         (this->*m6809_main[ireg])();
 619 }
 620
 621
 622 void MC6809_BASE::write_debug_data8(uint32_t addr, uint32_t data)
 623 {
 624         if(__USE_DEBUGGER) d_mem_stored->write_data8(addr, data);
 625 }
 626
 627 uint32_t MC6809_BASE::read_debug_data8(uint32_t addr)
 628 {
 629         if(__USE_DEBUGGER) {
 630                 return d_mem_stored->read_data8(addr);
 631         }
 632         return 0xff;
 633 }
 634
 635 void MC6809_BASE::write_debug_io8(uint32_t addr, uint32_t data)
 636 {
 637         if(__USE_DEBUGGER) d_mem_stored->write_io8(addr, data);
 638 }
 639
 640 uint32_t MC6809_BASE::read_debug_io8(uint32_t addr)
 641 {
 642         if(__USE_DEBUGGER) {
 643                 uint8_t val = d_mem_stored->read_io8(addr);
 644                 return val;
 645         }
 646         return 0xff;
 647 }
 648
 649
 650 bool MC6809_BASE::write_debug_reg(const _TCHAR *reg, uint32_t data)
 651 {
 652 //#ifdef USE_DEBUGGER
 653         if(_tcsicmp(reg, _T("PC")) == 0) {
 654                 PC = data;
 655         } else if(_tcsicmp(reg, _T("DP")) == 0) {
 656                 DP = data;
 657         } else if(_tcsicmp(reg, _T("A")) == 0) {
 658                 A = data;
 659         } else if(_tcsicmp(reg, _T("B")) == 0) {
 660                 B = data;
 661         } else if(_tcsicmp(reg, _T("D")) == 0) {
 662                 D = data;
 663         } else if(_tcsicmp(reg, _T("U")) == 0) {
 664                 U = data;
 665         } else if(_tcsicmp(reg, _T("X")) == 0) {
 666                 X = data;
 667         } else if(_tcsicmp(reg, _T("Y")) == 0) {
 668                 Y = data;
 669         } else if(_tcsicmp(reg, _T("S")) == 0) {
 670                 S = data;
 671         } else if(_tcsicmp(reg, _T("CC")) == 0) {
 672                 CC = data;
 673         } else {
 674                 return false;
 675         }
 676 //#endif
 677         return true;
 678 }
 679
 680 /*
 681 PC = 0000 PPC = 0000
 682 INTR=[ IRQ FIRQ  NMI HALT][CI CO SI SO TRAP] CC =[EFHINZVC]
 683 A = 00 B = 00 DP = 00 X = 0000 Y = 0000 U = 0000 S = 0000 EA = 0000
 684 Clocks = 0 (0)  Since Scanline = 0/0 (0/0)
 685 */
 686 void MC6809_BASE::get_debug_regs_info(_TCHAR *buffer, size_t buffer_len)
 687 {
 688 //#ifdef USE_DEBUGGER
 689         my_stprintf_s(buffer, buffer_len,
 690                  _T("PC = %04x PPC = %04x\nINTR = [%s %s %s %s][%s %s %s %s %s] CC = [%c%c%c%c%c%c%c%c]\nA = %02x B = %02x DP = %02x X = %04x Y = %04x U = %04x S = %04x EA = %04x\nClocks = %llu (%llu) Since Scanline = %d/%d (%d/%d)"),
 691                  PC,
 692                  PPC,
 693                  ((int_state & MC6809_IRQ_BIT) == 0)   ? _T("----") : _T(" IRQ"),
 694                  ((int_state & MC6809_FIRQ_BIT) == 0)  ? _T("----") : _T("FIRQ"),
 695                  ((int_state & MC6809_NMI_BIT) == 0)   ? _T("----") : _T(" NMI"),
 696                  ((int_state & MC6809_HALT_BIT) == 0)  ? _T("----") : _T("HALT"),
 697                  ((int_state & MC6809_CWAI_IN) == 0)   ? _T("--") : _T("CI"),
 698                  ((int_state & MC6809_CWAI_OUT) == 0)  ? _T("--") : _T("CO"),
 699                  ((int_state & MC6809_SYNC_IN) == 0)   ? _T("--") : _T("SI"),
 700                  ((int_state & MC6809_SYNC_OUT) == 0)  ? _T("--") : _T("SO"),
 701                  ((int_state & MC6809_INSN_HALT) == 0) ? _T("----") : _T("TRAP"),
 702                  ((CC & CC_E) == 0)  ? _T('-') : _T('E'),
 703                  ((CC & CC_IF) == 0) ? _T('-') : _T('F'),
 704                  ((CC & CC_H) == 0)  ? _T('-') : _T('H'),
 705                  ((CC & CC_II) == 0) ? _T('-') : _T('I'),
 706                  ((CC & CC_N) == 0)  ? _T('-') : _T('N'),
 707                  ((CC & CC_Z) == 0)  ? _T('-') : _T('Z'),
 708                  ((CC & CC_V) == 0)  ? _T('-') : _T('V'),
 709                  ((CC & CC_C) == 0)  ? _T('-') : _T('C'),
 710                  A, B, DP,
 711                  X, Y, U, S,
 712                  EAD,
 713                   total_icount, total_icount - prev_total_icount,
 714                  get_passed_clock_since_vline(), get_cur_vline_clocks(), get_cur_vline(), get_lines_per_frame()
 715                 );
 716         prev_total_icount = total_icount;
 717 //#endif
 718 }
 719
 720 uint32_t MC6809_BASE::cpu_disassemble_m6809(_TCHAR *buffer, uint32_t pc, const uint8_t *oprom, const uint8_t *opram)
 721 {
 722         return 0;
 723 }
 724
 725 int MC6809_BASE::debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len)
 726 {
 727         return 0;
 728 }
 729
 730
 731
 732 inline void MC6809_BASE::fetch_effective_address()
 733 {
 734         uint8_t postbyte;
 735         uint8_t upper, lower;
 736
 737         IMMBYTE(postbyte);
 738
 739         upper = (postbyte >> 4) & 0x0f;
 740         lower = postbyte & 0x0f;
 741         switch (upper) {
 742                 case 0x00:
 743                         EA = X + lower;
 744                         break;
 745                 case 0x01:
 746                         EA = X - 16 + lower;
 747                         break;
 748                 case 0x02:
 749                         EA = Y + lower;
 750                         break;
 751                 case 0x03:
 752                         EA = Y - 16 + lower;
 753                         break;
 754                 case 0x04:
 755                         EA = U + lower;
 756                         break;
 757                 case 0x05:
 758                         EA = U - 16 + lower;
 759                         break;
 760                 case 0x06:
 761                         EA = S + lower;
 762                         break;
 763                 case 0x07:
 764                         EA = S - 16 + lower;
 765                         break;
 766                 default:
 767                         fetch_effective_address_IDX(upper, lower);
 768                         break;
 769         }
 770         EAD &= 0xffff;
 771         icount -= index_cycle_em[postbyte];
 772 }
 773
 774 inline void MC6809_BASE::fetch_effective_address_IDX(uint8_t upper, uint8_t lower)
 775 {
 776         bool indirect = false;
 777         uint16_t *reg;
 778         uint8_t bx_p;
 779         pair32_t pp;
 780
 781         indirect = ((upper & 0x01) != 0) ? true : false;
 782
 783         switch ((upper >> 1) & 0x03) {  // $8-$f >> 1 = $4 - $7 : delete bit2
 784                 case 0: // $8x,$9x
 785                         reg = &X;
 786                         break;
 787                 case 1: // $ax,$bx
 788                         reg = &Y;
 789                         break;
 790                 case 2: // $cx,$dx
 791                         reg = &U;
 792                         break;
 793                 case 3: // $ex,$fx
 794                         reg = &S;
 795                         break;
 796         }
 797
 798         switch (lower) {
 799                 case 0: // ,r+
 800                         EA = *reg;
 801                         *reg = *reg + 1;
 802                         *reg = *reg & 0xffff;
 803                         break;
 804                 case 1: // ,r++
 805                         EA = *reg;
 806                         *reg = *reg + 2;
 807                         *reg = *reg & 0xffff;
 808                         break;
 809                 case 2: // ,-r
 810                         *reg = *reg - 1;
 811                         *reg = *reg & 0xffff;
 812                         EA = *reg;
 813                         break;
 814                 case 3: // ,--r
 815                         *reg = *reg - 2;
 816                         *reg = *reg & 0xffff;
 817                         EA = *reg;
 818                         break;
 819                 case 4: // ,r
 820                         EA = *reg;
 821                         break;
 822                 case 5: // b,r
 823                         EA = *reg + SIGNED(B);
 824                         break;
 825                 case 6: // a,r
 826                 case 7:
 827                         EA = *reg + SIGNED(A);
 828                         break;
 829                 case 8: // $xx,r
 830                         IMMBYTE(bx_p);
 831                         EA = *reg + SIGNED(bx_p);
 832                         break;
 833                 case 9: // $xxxx, r
 834                         IMMWORD(EAP);
 835                         EA = EA + *reg;
 836                         break;
 837                 case 0x0a:      // Undocumented
 838                         EA = PC;
 839                         EA++;
 840                         EAP.w.l |= 0x00ff;
 841                         break;
 842                 case 0x0b:      // D,r
 843                         EA = *reg + D;
 844                         break;
 845                 case 0x0c:      // xx,pc
 846                         IMMBYTE(bx_p);
 847                         EA = PC + SIGNED(bx_p);
 848                         break;
 849                 case 0x0d:      // xxxx,pc
 850                         IMMWORD(EAP);
 851                         EA = EA + PC;
 852                         break;
 853                 case 0x0e:      // Undocumented
 854                         EA = 0xffff;
 855                         break;
 856                 case 0x0f:
 857                         IMMWORD(EAP);
 858                         break;
 859         }
 860         EAP.w.h = 0x0000;
 861         // $9x,$bx,$dx,$fx = INDIRECT
 862         if (indirect) {
 863                 pp = EAP;
 864                 EAP = RM16_PAIR(pp.d);
 865         }
 866 }
 867
 868 #define IIError() illegal()
 869
 870 OP_HANDLER(illegal)
 871 {
 872         //logerror("M6809: illegal opcode at %04x\n",PC);
 873         //printf("M6809: illegal opcode at %04x %02x %02x %02x %02x %02x \n",
 874         //       PC - 2, RM(PC - 2), RM(PC - 1), RM(PC), RM(PC + 1), RM(PC + 2));
 875 //        PC-=1;
 876 }
 877
 878 inline uint8_t MC6809_BASE::GET_INDEXED_DATA(void)
 879 {
 880         uint8_t t;
 881         fetch_effective_address();
 882         t = RM(EAD);
 883         return t;
 884 }
 885
 886 inline pair32_t MC6809_BASE::GET_INDEXED_DATA16(void)
 887 {
 888         pair32_t t;
 889         fetch_effective_address();
 890         t = RM16_PAIR(EAD);
 891         return t;
 892 }
 893
 894 // $x0, $x1
 895 inline void MC6809_BASE::NEG_MEM(uint8_t a_neg)
 896 {
 897         uint16_t r_neg;
 898         r_neg = 0 - (uint16_t)a_neg;
 899         CLR_NZVC;
 900         SET_FLAGS8(0, a_neg, r_neg);
 901         WM(EAD, r_neg);
 902 }
 903
 904 inline uint8_t MC6809_BASE::NEG_REG(uint8_t a_neg)
 905 {
 906         uint16_t r_neg;
 907         r_neg = 0 - (uint16_t)a_neg;
 908         CLR_NZVC;
 909         SET_FLAGS8(0, a_neg, r_neg);
 910         return (uint8_t)r_neg;
 911 }
 912
 913
 914 // $x2
 915 inline void MC6809_BASE::COM_MEM(uint8_t a_com)
 916 {
 917         uint8_t t_com;
 918         t_com = ~a_com;
 919         CLR_NZVC;
 920         SET_NZ8(t_com);
 921         SEC;
 922         WM(EAD, t_com);
 923 }
 924
 925 inline uint8_t MC6809_BASE::COM_REG(uint8_t r_com)
 926 {
 927         r_com = ~r_com;
 928         CLR_NZVC;
 929         SET_NZ8(r_com);
 930         SEC;
 931         return r_com;
 932 }
 933
 934 inline void MC6809_BASE::LSR_MEM(uint8_t t)
 935 {
 936         CLR_NZC;
 937         CC = CC | (t & CC_C);
 938         t >>= 1;
 939         SET_NZ8(t);
 940         WM(EAD, t);
 941 }
 942
 943 inline uint8_t MC6809_BASE::LSR_REG(uint8_t r)
 944 {
 945         CLR_NZC;
 946         CC |= (r & CC_C);
 947         r >>= 1;
 948         SET_NZ8(r);
 949         return r;
 950 }
 951
 952 inline void MC6809_BASE::ROR_MEM(uint8_t t)
 953 {
 954         uint8_t r;
 955         r = (CC & CC_C) << 7;
 956         CLR_NZC;
 957         CC |= (t & CC_C);
 958         t >>= 1;
 959         r |= t;
 960         SET_NZ8(r); //NZ8?
 961         WM(EAD, r);
 962 }
 963
 964 inline uint8_t MC6809_BASE::ROR_REG(uint8_t t)
 965 {
 966         uint8_t r;
 967         r = (CC & CC_C) << 7;
 968         CLR_NZC;
 969         CC |= (t & CC_C);
 970         t >>= 1;
 971         r |= t;
 972         SET_NZ8(r); //NZ8?
 973         return r;
 974 }
 975
 976
 977 inline void MC6809_BASE::ASR_MEM(uint8_t t)
 978 {
 979         uint8_t r;
 980         CLR_NZC;
 981         CC = CC | (t & CC_C);
 982         r = (t & 0x80) | (t >> 1);
 983         // H is undefined
 984         SET_NZ8(r);
 985         //SET_H(t, t, r);
 986         WM(EAD, r);
 987 }
 988
 989 inline uint8_t MC6809_BASE::ASR_REG(uint8_t t)
 990 {
 991         uint8_t r;
 992         CLR_NZC;
 993         CC = CC | (t & CC_C);
 994         r = (t & 0x80) | (t >> 1);
 995         // H is undefined
 996         SET_NZ8(r);
 997         //SET_H(t, t, r);
 998         return r;
 999 }
1000
1001 inline void MC6809_BASE::ASL_MEM(uint8_t t)
1002 {
1003         uint16_t r, tt;
1004         tt = (uint16_t)t & 0x00ff;
1005         r = tt << 1;
1006         CLR_NZVC;
1007         SET_FLAGS8(tt, tt, r);
1008         //SET_H(tt, tt, r);
1009         WM(EAD, (uint8_t)r);
1010 }
1011
1012 inline uint8_t MC6809_BASE::ASL_REG(uint8_t t)
1013 {
1014         uint16_t r, tt;
1015         tt = (uint16_t)t & 0x00ff;
1016         r = tt << 1;
1017         CLR_NZVC;
1018         SET_FLAGS8(tt, tt, r);
1019         //SET_H(tt, tt, r);
1020         return (uint8_t)r;
1021 }
1022
1023 inline void MC6809_BASE::ROL_MEM(uint8_t t)
1024 {
1025         uint16_t r, tt;
1026         tt = (uint16_t)t & 0x00ff;
1027         r = (CC & CC_C) | (tt << 1);
1028         CLR_NZVC;
1029         //SET_NZ8(r);
1030         //if(t & 0x80) {
1031         //      SEC;
1032         //      if((r & 0x80) == 0)SEV;
1033         //} else {
1034         //      if((r & 0x80) != 0) SEV;
1035         //}
1036         SET_FLAGS8(tt, tt, r);
1037         WM(EAD, (uint8_t)r);
1038 }
1039
1040 inline uint8_t MC6809_BASE::ROL_REG(uint8_t t)
1041 {
1042         uint16_t r, tt;
1043         tt = (uint16_t)t & 0x00ff;
1044         r = (CC & CC_C) | (tt << 1);
1045         CLR_NZVC;
1046         //SET_NZ8(r);
1047         //if(t & 0x80) {
1048         //      SEC;
1049         //      if((r & 0x80) == 0) SEV;
1050         //} else {
1051         //      if((r & 0x80) != 0) SEV;
1052         //}
1053         SET_FLAGS8(tt, tt, r);
1054         return (uint8_t)r;
1055 }
1056
1057 inline void MC6809_BASE::DEC_MEM(uint8_t t)
1058 {
1059         uint16_t tt;
1060         tt = t - 1;
1061         CLR_NZV;
1062         SET_FLAGS8D(tt);
1063         WM(EAD, tt);
1064 }
1065
1066 inline uint8_t MC6809_BASE::DEC_REG(uint8_t t)
1067 {
1068         uint8_t tt;
1069         tt = t - 1;
1070         CLR_NZV;
1071         SET_FLAGS8D(tt);
1072         return tt;
1073 }
1074
1075 inline void MC6809_BASE::DCC_MEM(uint8_t t)
1076 {
1077         uint16_t tt, ss;
1078         tt = t - 1;
1079         CLR_NZVC;
1080         SET_FLAGS8D(tt);
1081         ss = CC;
1082         ss >>= 2;
1083         ss = ~ss;
1084         ss = ss & CC_C;
1085         CC = ss | CC;
1086         WM(EAD, tt);
1087 }
1088
1089 inline uint8_t MC6809_BASE::DCC_REG(uint8_t t)
1090 {
1091         uint16_t tt, ss;
1092         tt = t - 1;
1093         CLR_NZVC;
1094         SET_FLAGS8D(tt);
1095         ss = CC;
1096         ss >>= 2;
1097         ss = ~ss;
1098         ss = ss & CC_C;
1099         CC = ss | CC;
1100         return (uint8_t)tt;
1101 }
1102
1103 inline void MC6809_BASE::INC_MEM(uint8_t t)
1104 {
1105         uint16_t tt = t + 1;
1106         CLR_NZV;
1107         SET_FLAGS8I(tt);
1108         WM(EAD, tt);
1109 }
1110
1111 inline uint8_t MC6809_BASE::INC_REG(uint8_t t)
1112 {
1113         uint16_t tt = t + 1;
1114         CLR_NZV;
1115         SET_FLAGS8I(tt);
1116         return (uint8_t)tt;
1117 }
1118
1119 inline void MC6809_BASE::TST_MEM(uint8_t t)
1120 {
1121         CLR_NZV;
1122         SET_NZ8(t);
1123 }
1124
1125 inline uint8_t MC6809_BASE::TST_REG(uint8_t t)
1126 {
1127         CLR_NZV;
1128         SET_NZ8(t);
1129         return t;
1130 }
1131
1132 inline uint8_t MC6809_BASE::CLC_REG(uint8_t t)
1133 {
1134         uint8_t r;
1135         r = 0;
1136         CLR_NZV;
1137         SEZ;
1138         return r;
1139 }
1140
1141
1142 inline void MC6809_BASE::CLR_MEM(uint8_t t)
1143 {
1144         WM(EAD, 0);
1145         CLR_NZVC;
1146         SEZ;
1147 }
1148
1149 inline uint8_t MC6809_BASE::CLR_REG(uint8_t t)
1150 {
1151         CLR_NZVC;
1152         SEZ;
1153         return 0;
1154 }
1155
1156 inline uint8_t MC6809_BASE::SUB8_REG(uint8_t reg, uint8_t data)
1157 {
1158         uint16_t r;
1159         r = (uint16_t)reg - (uint16_t)data;
1160         CLR_HNZVC;
1161         // H is undefined
1162         SET_FLAGS8(reg, data, r);
1163         return (uint8_t)r;
1164 }
1165
1166 inline uint8_t MC6809_BASE::CMP8_REG(uint8_t reg, uint8_t data)
1167 {
1168         uint16_t r;
1169         r = (uint16_t)reg - (uint16_t)data;
1170         CLR_NZVC;
1171         // H is undefined
1172         SET_FLAGS8(reg, data, r);
1173         return reg;
1174 }
1175
1176 inline uint8_t MC6809_BASE::SBC8_REG(uint8_t reg, uint8_t data)
1177 {
1178         uint16_t r;
1179         uint8_t cc_c = CC & CC_C;
1180         r = (uint16_t)reg - (uint16_t)data - (uint16_t)cc_c;
1181         CLR_HNZVC;
1182         SET_FLAGS8(reg, (data + cc_c) , r);
1183         return (uint8_t)r;
1184 }
1185
1186 inline uint8_t MC6809_BASE::AND8_REG(uint8_t reg, uint8_t data)
1187 {
1188         uint8_t r = reg;
1189         r &= data;
1190         CLR_NZV;
1191         SET_NZ8(r);
1192         return r;
1193 }
1194
1195 inline uint8_t MC6809_BASE::BIT8_REG(uint8_t reg, uint8_t data)
1196 {
1197         uint16_t r;
1198         r = reg & data;
1199         CLR_NZV;
1200         SET_NZ8(r);
1201         SET_V8(reg, data, r);
1202         return reg;
1203 }
1204
1205 inline uint8_t MC6809_BASE::EOR8_REG(uint8_t reg, uint8_t data)
1206 {
1207         uint8_t r = reg;
1208         r ^= data;
1209         CLR_NZV;
1210         SET_NZ8(r);
1211         return r;
1212 }
1213
1214 inline uint8_t MC6809_BASE::OR8_REG(uint8_t reg, uint8_t data)
1215 {
1216         uint8_t r = reg;
1217         r |= data;
1218         CLR_NZV;
1219         SET_NZ8(r);
1220         return r;
1221 }
1222
1223 inline uint8_t MC6809_BASE::ADD8_REG(uint8_t reg, uint8_t data)
1224 {
1225         uint16_t t, r;
1226         t = (uint16_t) data;
1227         t &= 0x00ff;
1228         r = reg + t;
1229         CLR_HNZVC;
1230         SET_HNZVC8(reg, t, r);
1231         return (uint8_t)r;
1232 }
1233
1234 inline uint8_t MC6809_BASE::ADC8_REG(uint8_t reg, uint8_t data)
1235 {
1236         uint16_t t, r;
1237         uint8_t c_cc = CC & CC_C;
1238         t = (uint16_t) data;
1239         t &= 0x00ff;
1240         r = reg + t + c_cc;
1241         CLR_HNZVC;
1242         SET_HNZVC8(reg, (t + c_cc), r);
1243         return (uint8_t)r;
1244 }
1245
1246 inline uint8_t MC6809_BASE::LOAD8_REG(uint8_t reg)
1247 {
1248         CLR_NZV;
1249         SET_NZ8(reg);
1250         return reg;
1251 }
1252
1253 inline void MC6809_BASE::STORE8_REG(uint8_t reg)
1254 {
1255         CLR_NZV;
1256         SET_NZ8(reg);
1257         WM(EAD, reg);
1258 }
1259
1260 inline uint16_t MC6809_BASE::LOAD16_REG(uint16_t reg)
1261 {
1262         CLR_NZV;
1263         SET_NZ16(reg);
1264         return reg;
1265 }
1266
1267
1268 inline uint16_t MC6809_BASE::SUB16_REG(uint16_t reg, uint16_t data)
1269 {
1270         uint32_t r, d;
1271         d = reg;
1272         r = d - data;
1273         CLR_NZVC;
1274         SET_FLAGS16(d, data, r);
1275         return (uint16_t)r;
1276 }
1277
1278 inline uint16_t MC6809_BASE::ADD16_REG(uint16_t reg, uint16_t data)
1279 {
1280         uint32_t r, d;
1281         d = reg;
1282         r = d + (uint32_t)data;
1283         CLR_HNZVC;
1284         SET_HNZVC16(d, data, r);
1285         return (uint16_t)r;
1286 }
1287
1288 inline uint16_t MC6809_BASE::CMP16_REG(uint16_t reg, uint16_t data)
1289 {
1290         uint32_t r, d;
1291         d = reg;
1292         r = d - data;
1293         CLR_NZVC;
1294         SET_FLAGS16(d, data, r);
1295         return reg;
1296 }
1297
1298 inline void MC6809_BASE::STORE16_REG(pair32_t *p)
1299 {
1300         CLR_NZV;
1301         SET_NZ16(p->w.l);
1302         WM16(EAD, p);
1303 }
1304
1305
1306 /* $00 NEG direct ?**** */
1307 OP_HANDLER(neg_di) {
1308         uint8_t t;
1309         DIRBYTE(t);
1310         NEG_MEM(t);
1311 }
1312
1313 /* $01 Undefined Neg */
1314 /* $03 COM direct -**01 */
1315 OP_HANDLER(com_di) {
1316         uint8_t t;
1317         DIRBYTE(t);
1318         COM_MEM(t);
1319 }
1320
1321 /* $02 NGC Direct (Undefined) */
1322 OP_HANDLER(ngc_di) {
1323         if ((CC & CC_C) == 0) {
1324                 neg_di();
1325         }
1326         else {
1327                 com_di();
1328         }
1329 }
1330
1331
1332 /* $04 LSR direct -0*-* */
1333 OP_HANDLER(lsr_di) {
1334         uint8_t t;
1335         DIRBYTE(t);
1336         LSR_MEM(t);
1337 }
1338
1339 /* $05 ILLEGAL */
1340
1341 /* $06 ROR direct -**-* */
1342 OP_HANDLER(ror_di) {
1343         uint8_t t;
1344         DIRBYTE(t);
1345         ROR_MEM(t);
1346 }
1347
1348 /* $07 ASR direct ?**-* */
1349 OP_HANDLER(asr_di) {
1350         uint8_t t;
1351         DIRBYTE(t);
1352         ASR_MEM(t);
1353 }
1354
1355 /* $08 ASL direct ?**** */
1356 OP_HANDLER(asl_di) {
1357         uint8_t t;
1358         DIRBYTE(t);
1359         ASL_MEM(t);
1360 }
1361
1362 /* $09 ROL direct -**** */
1363 OP_HANDLER(rol_di) {
1364         uint8_t t;
1365         DIRBYTE(t);
1366         ROL_MEM(t);
1367 }
1368
1369 /* $0A DEC direct -***- */
1370 OP_HANDLER(dec_di) {
1371         uint8_t t;
1372         DIRBYTE(t);
1373         DEC_MEM(t);
1374 }
1375
1376 /* $0B DCC direct */
1377 OP_HANDLER(dcc_di) {
1378         uint8_t t;
1379         DIRBYTE(t);
1380         DCC_MEM(t);
1381 }
1382
1383
1384 /* $OC INC direct -***- */
1385 OP_HANDLER(inc_di) {
1386         uint8_t t;
1387         DIRBYTE(t);
1388         INC_MEM(t);
1389 }
1390
1391 /* $OD TST direct -**0- */
1392 OP_HANDLER(tst_di) {
1393         uint8_t t;
1394         DIRBYTE(t);
1395         t = RM(EAD);
1396         TST_MEM(t);
1397 }
1398
1399 /* $0E JMP direct ----- */
1400 OP_HANDLER(jmp_di) {
1401         DIRECT;
1402         PC = EA;
1403 }
1404
1405 /* $0F CLR direct -0100 */
1406 OP_HANDLER(clr_di) {
1407         uint8_t dummy;
1408         DIRECT;
1409         dummy = RM(EAD);        // Dummy Read(Alpha etc...)
1410         CLR_MEM(dummy);
1411 }
1412
1413 /* $10 FLAG */
1414
1415 /* $11 FLAG */
1416
1417 /* $12 NOP inherent ----- */
1418 OP_HANDLER(nop) {
1419         ;
1420 }
1421
1422 /* $13 SYNC inherent ----- */
1423 OP_HANDLER(sync_09)     // Rename 20101110
1424 {
1425         int_state |= MC6809_SYNC_IN;
1426         write_signals(&outputs_bus_ba, 0xffffffff);
1427         write_signals(&outputs_bus_bs, 0x00000000);
1428 }
1429
1430
1431
1432 /* $14 trap(HALT) */
1433 OP_HANDLER(trap) {
1434         int_state |= MC6809_INSN_HALT;  // HALTフラグ
1435         // Debug: ã\83\88ã\83©ã\83\81E\81Eè¦\81å\9b
1436         this->out_debug_log(_T("TRAP(HALT) @%04x %02x %02x\n"), PC - 1, RM((PC - 1)), RM(PC));
1437 }
1438
1439 /* $15 trap */
1440
1441 /* $16 LBRA relative ----- */
1442 OP_HANDLER(lbra) {
1443         LBRANCH(true);
1444 }
1445
1446 /* $17 LBSR relative ----- */
1447 OP_HANDLER(lbsr) {
1448         IMMWORD(EAP);
1449         PUSHWORD(pPC);
1450         PC += EAD;
1451 }
1452
1453 /* $18 ASLCC */
1454
1455 OP_HANDLER(aslcc_in) {
1456         uint8_t cc_r = CC;
1457         if ((cc_r & CC_Z) != 0x00) { //20100824 Fix
1458                 cc_r |= CC_C;
1459         }
1460         cc_r <<= 1;
1461         cc_r &= 0x3e;
1462         CC = cc_r;
1463 }
1464
1465 /* $19 DAA inherent (A) -**0* */
1466 OP_HANDLER(daa) {
1467         uint8_t msn, lsn;
1468         uint16_t t, cf = 0;
1469         msn = A & 0xf0;
1470         lsn = A & 0x0f;
1471         if (lsn > 0x09 || CC & CC_H)
1472                 cf |= 0x06;
1473         if (msn > 0x80 && lsn > 0x09)
1474                 cf |= 0x60;
1475         if (msn > 0x90 || CC & CC_C)
1476                 cf |= 0x60;
1477         t = cf + A;
1478         CLR_NZV;        /* keep carry from previous operation */
1479         SET_NZ8((uint8_t) t);
1480         SET_C8(t);
1481         A = (uint8_t)t;
1482 }
1483
1484
1485 /* $1A ORCC immediate ##### */
1486 OP_HANDLER(orcc) {
1487         uint8_t t;
1488         IMMBYTE(t);
1489         CC |= t;
1490 }
1491
1492 /* $1B ILLEGAL */
1493
1494
1495 /* $1C ANDCC immediate ##### */
1496 OP_HANDLER(andcc) {
1497         uint8_t t;
1498         IMMBYTE(t);
1499         CC &= t;
1500 //  check_irq_lines(); /* HJB 990116 */
1501 }
1502
1503 /* $1D SEX inherent -**-- */
1504 OP_HANDLER(sex) {
1505         uint16_t t;
1506         t = SIGNED(B);
1507         D = t; // Endian OK?
1508         //  CLR_NZV;    Tim Lindner 20020905: verified that V flag is not affected
1509         CLR_NZ;
1510         SET_NZ16(t);
1511 }
1512
1513         /* $1E EXG inherent ----- */// 20100825
1514 OP_HANDLER(exg) {
1515         pair32_t t1, t2;
1516         uint8_t tb;
1517         IMMBYTE(tb);
1518         t1.d = 0;
1519         t2.d = 0;
1520         /*
1521          * 20111011: 16bit vs 16Bitの演算にする(XM7/ cpu_x86.asmより
1522          */
1523         {
1524                 switch ((tb >> 4) & 15) {
1525                         case 0:
1526                                 t1.w.l = D;
1527                                 break;
1528                         case 1:
1529                                 t1.w.l = X;
1530                                 break;
1531                         case 2:
1532                                 t1.w.l = Y;
1533                                 break;
1534                         case 3:
1535                                 t1.w.l = U;
1536                                 break;
1537                         case 4:
1538                                 t1.w.l = S;
1539                                 break;
1540                         case 5:
1541                                 t1.w.l = PC;
1542                                 break;
1543                         case 8:
1544                                 t1.b.l = A;
1545                                 t1.b.h = 0xff;
1546                                 break;
1547                         case 9:
1548                                 t1.b.l = B;
1549                                 t1.b.h = 0xff;
1550                                 break;
1551                         case 10:
1552                                 t1.b.l = CC;
1553                                 t1.b.h = 0xff;
1554                                 break;
1555                         case 11:
1556                                 t1.b.l = DP;
1557                                 t1.b.h = 0xff;
1558                                 break;
1559                         default:
1560                                 t1.w.l = 0xffff;
1561                                 break;
1562                 }
1563                 switch (tb & 15) {
1564                         case 0:
1565                                 t2.w.l = D;
1566                                 break;
1567                         case 1:
1568                                 t2.w.l = X;
1569                                 break;
1570                         case 2:
1571                                 t2.w.l = Y;
1572                                 break;
1573                         case 3:
1574                                 t2.w.l = U;
1575                                 break;
1576                         case 4:
1577                                 t2.w.l = S;
1578                                 break;
1579                         case 5:
1580                                 t2.w.l = PC;
1581                                 break;
1582                         case 8:
1583                                 t2.b.l = A;
1584                                 t2.b.h = 0xff;
1585                                 break;
1586                         case 9:
1587                                 t2.b.l = B;
1588                                 t2.b.h = 0xff;
1589                                 break;
1590                         case 10:
1591                                 t2.b.l = CC;
1592                                 t2.b.h = 0xff;
1593                                 break;
1594                         case 11:
1595                                 t2.b.l = DP;
1596                                 t2.b.h = 0xff;
1597                                 break;
1598                         default:
1599                                 t2.w.l = 0xffff;
1600                                 break;
1601                 }
1602         }
1603         switch ((tb >> 4) & 15) {
1604                 case 0:
1605                         D = t2.w.l;
1606                         break;
1607                 case 1:
1608                         X = t2.w.l;
1609                         break;
1610                 case 2:
1611                         Y = t2.w.l;
1612                         break;
1613                 case 3:
1614                         U = t2.w.l;
1615                         break;
1616                 case 4:
1617                         S = t2.w.l;
1618                         int_state |= MC6809_LDS;
1619                         break;
1620                 case 5:
1621                         PC = t2.w.l;
1622                         break;
1623                 case 8:
1624                         A = t2.b.l;
1625                         break;
1626                 case 9:
1627                         B = t2.b.l;
1628                         break;
1629                 case 10:
1630                         CC = t2.b.l;
1631                         break;
1632                 case 11:
1633                         DP = t2.b.l;
1634                         break;
1635         }
1636         switch (tb & 15) {
1637                 case 0:
1638                         D = t1.w.l;
1639                         break;
1640                 case 1:
1641                         X = t1.w.l;
1642                         break;
1643                 case 2:
1644                         Y = t1.w.l;
1645                         break;
1646                 case 3:
1647                         U = t1.w.l;
1648                         break;
1649                 case 4:
1650                         S = t1.w.l;
1651                         int_state |= MC6809_LDS;
1652                         break;
1653                 case 5:
1654                         PC = t1.w.l;
1655                         break;
1656                 case 8:
1657                         A = t1.b.l;
1658                         break;
1659                 case 9:
1660                         B = t1.b.l;
1661                         break;
1662                 case 10:
1663                         CC = t1.b.l;
1664                         break;
1665                 case 11:
1666                         DP = t1.b.l;
1667                         break;
1668         }
1669 }
1670
1671 /* $1F TFR inherent ----- */
1672 OP_HANDLER(tfr) {
1673         uint8_t tb;
1674         pair32_t t;
1675         IMMBYTE(tb);
1676         t.d = 0;
1677         /*
1678          * 20111011: 16bit vs 16Bitの演算にする(XM7/ cpu_x86.asmより)
1679          */
1680         {
1681                 switch ((tb >> 4) & 15) {
1682                         case 0:
1683                                 t.w.l = D;
1684                                 break;
1685                         case 1:
1686                                 t.w.l = X;
1687                                 break;
1688                         case 2:
1689                                 t.w.l = Y;
1690                                 break;
1691                         case 3:
1692                                 t.w.l = U;
1693                                 break;
1694                         case 4:
1695                                 t.w.l = S;
1696                                 break;
1697                         case 5:
1698                                 t.w.l = PC;
1699                                 break;
1700                         case 8:
1701                                 t.b.l = A;
1702                                 t.b.h = 0xff;
1703                                 break;
1704                         case 9:
1705                                 t.b.l = B;
1706                                 t.b.h = 0xff;
1707                                 break;
1708                         case 10:
1709                                 t.b.l = CC;
1710                                 t.b.h = 0xff;
1711                                 break;
1712                         case 11:
1713                                 t.b.l = DP;
1714                                 t.b.h = 0xff;
1715                                 break;
1716                         default:
1717                                 t.w.l = 0xffff;
1718                                 break;
1719                 }
1720         }
1721         switch (tb & 15) {
1722                 case 0:
1723                         D = t.w.l;
1724                         break;
1725                 case 1:
1726                         X = t.w.l;
1727                         break;
1728                 case 2:
1729                         Y = t.w.l;
1730                         break;
1731                 case 3:
1732                         U = t.w.l;
1733                         break;
1734                 case 4:
1735                         S = t.w.l;
1736                         int_state |= MC6809_LDS;
1737                         break;
1738                 case 5:
1739                         PC = t.w.l;
1740                         break;
1741                 case 8:
1742                         A = t.b.l;
1743                         break;
1744                 case 9:
1745                         B = t.b.l;
1746                         break;
1747                 case 10:
1748                         CC = t.b.l;
1749                         break;
1750                 case 11:
1751                         DP = t.b.l;
1752                         break;
1753         }
1754 }
1755
1756 /* $20 BRA relative ----- */
1757 OP_HANDLER(bra) {
1758         BRANCH(true);
1759 }
1760
1761 /* $21 BRN relative ----- */
1762 OP_HANDLER(brn) {
1763         BRANCH(false);
1764 }
1765
1766 /* $1021 LBRN relative ----- */
1767 OP_HANDLER(lbrn) {
1768         LBRANCH(false);
1769 }
1770
1771 /* $22 BHI relative ----- */
1772 OP_HANDLER(bhi) {
1773         BRANCH(((CC & (CC_Z | CC_C)) == 0));
1774 }
1775
1776 /* $1022 LBHI relative ----- */
1777 OP_HANDLER(lbhi) {
1778         LBRANCH(((CC & (CC_Z | CC_C)) == 0));
1779 }
1780
1781 /* $23 BLS relative ----- */
1782 OP_HANDLER(bls) {
1783         BRANCH(((CC & (CC_Z | CC_C)) != 0));
1784 }
1785
1786 /* $1023 LBLS relative ----- */
1787 OP_HANDLER(lbls) {
1788         LBRANCH(((CC & (CC_Z | CC_C)) != 0));
1789         //LBRANCH((CC & (CC_Z | CC_C)));
1790 }
1791
1792 /* $24 BCC relative ----- */
1793 OP_HANDLER(bcc) {
1794         BRANCH((CC & CC_C) == 0);
1795 }
1796
1797 /* $1024 LBCC relative ----- */
1798 OP_HANDLER(lbcc) {
1799         LBRANCH((CC & CC_C) == 0);
1800 }
1801
1802 /* $25 BCS relative ----- */
1803 OP_HANDLER(bcs) {
1804         BRANCH((CC & CC_C) != 0);
1805 }
1806
1807 /* $1025 LBCS relative ----- */
1808 OP_HANDLER(lbcs) {
1809         LBRANCH((CC & CC_C) != 0);
1810 }
1811
1812 /* $26 BNE relative ----- */
1813 OP_HANDLER(bne) {
1814         BRANCH((CC & CC_Z) == 0);
1815 }
1816
1817 /* $1026 LBNE relative ----- */
1818 OP_HANDLER(lbne) {
1819         LBRANCH((CC & CC_Z) == 0);
1820 }
1821
1822 /* $27 BEQ relative ----- */
1823 OP_HANDLER(beq) {
1824         BRANCH((CC & CC_Z) != 0);
1825 }
1826
1827 /* $1027 LBEQ relative ----- */
1828 OP_HANDLER(lbeq) {
1829         LBRANCH((CC & CC_Z) != 0);
1830 }
1831
1832 /* $28 BVC relative ----- */
1833 OP_HANDLER(bvc) {
1834         BRANCH((CC & CC_V) == 0);
1835 }
1836
1837 /* $1028 LBVC relative ----- */
1838 OP_HANDLER(lbvc) {
1839         LBRANCH((CC & CC_V) == 0);
1840 }
1841
1842 /* $29 BVS relative ----- */
1843 OP_HANDLER(bvs) {
1844         BRANCH((CC & CC_V) != 0);
1845 }
1846
1847 /* $1029 LBVS relative ----- */
1848 OP_HANDLER(lbvs) {
1849         LBRANCH((CC & CC_V) != 0);
1850 }
1851
1852 /* $2A BPL relative ----- */
1853 OP_HANDLER(bpl) {
1854         BRANCH((CC & CC_N) == 0);
1855 }
1856
1857 /* $102A LBPL relative ----- */
1858 OP_HANDLER(lbpl) {
1859         LBRANCH((CC & CC_N) == 0);
1860 }
1861
1862 /* $2B BMI relative ----- */
1863 OP_HANDLER(bmi) {
1864         BRANCH((CC & CC_N) != 0);
1865 }
1866
1867 /* $102B LBMI relative ----- */
1868 OP_HANDLER(lbmi) {
1869         LBRANCH((CC & CC_N) != 0);
1870 }
1871
1872 /* $2C BGE relative ----- */
1873 OP_HANDLER(bge) {
1874         BRANCH(!NXORV);
1875 }
1876
1877 /* $102C LBGE relative ----- */
1878 OP_HANDLER(lbge) {
1879         LBRANCH(!NXORV);
1880 }
1881
1882 /* $2D BLT relative ----- */
1883 OP_HANDLER(blt) {
1884         BRANCH(NXORV);
1885 }
1886
1887 /* $102D LBLT relative ----- */
1888 OP_HANDLER(lblt) {
1889         LBRANCH(NXORV);
1890 }
1891
1892 /* $2E BGT relative ----- */
1893 OP_HANDLER(bgt) {
1894         BRANCH(!(NXORV || (CC & CC_Z)));
1895 }
1896
1897 /* $102E LBGT relative ----- */
1898 OP_HANDLER(lbgt) {
1899         LBRANCH(!(NXORV || (CC & CC_Z)));
1900 }
1901
1902 /* $2F BLE relative ----- */
1903 OP_HANDLER(ble) {
1904         BRANCH((NXORV || (CC & CC_Z)));
1905 }
1906
1907 /* $102F LBLE relative ----- */
1908 OP_HANDLER(lble) {
1909         LBRANCH((NXORV || (CC & CC_Z)));
1910 }
1911
1912 /* $30 LEAX indexed --*-- */
1913 OP_HANDLER(leax) {
1914         fetch_effective_address();
1915         X = EA;
1916         CLR_Z;
1917         SET_Z16(X);
1918 }
1919
1920 /* $31 LEAY indexed --*-- */
1921 OP_HANDLER(leay) {
1922         fetch_effective_address();
1923         Y = EA;
1924         CLR_Z;
1925         SET_Z16(Y);
1926 }
1927
1928 /* $32 LEAS indexed ----- */
1929 OP_HANDLER(leas) {
1930         fetch_effective_address();
1931         S = EA;
1932         int_state |= MC6809_LDS;
1933 }
1934
1935 /* $33 LEAU indexed ----- */
1936 OP_HANDLER(leau) {
1937         fetch_effective_address();
1938         U = EA;
1939 }
1940
1941 /* $34 PSHS inherent ----- */
1942 OP_HANDLER(pshs) {
1943                 uint8_t t;
1944                 IMMBYTE(t);
1945                 //dmy = RM(S);  // Add 20100825
1946                 RM(S);  // Add 20100825
1947                 if (t & 0x80) {
1948                         PUSHWORD(pPC);
1949                         icount -= 2;
1950                 }
1951                 if (t & 0x40) {
1952                         PUSHWORD(pU);
1953                         icount -= 2;
1954                 }
1955                 if (t & 0x20) {
1956                         PUSHWORD(pY);
1957                         icount -= 2;
1958                 }
1959                 if (t & 0x10) {
1960                         PUSHWORD(pX);
1961                         icount -= 2;
1962                 }
1963                 if (t & 0x08) {
1964                         PUSHBYTE(DP);
1965                         icount -= 1;
1966                 }
1967                 if (t & 0x04) {
1968                         PUSHBYTE(B);
1969                         icount -= 1;
1970                 }
1971                 if (t & 0x02) {
1972                         PUSHBYTE(A);
1973                         icount -= 1;
1974                 }
1975                 if (t & 0x01) {
1976                         PUSHBYTE(CC);
1977                         icount -= 1;
1978                 }
1979         }
1980
1981 /* 35 PULS inherent ----- */
1982 OP_HANDLER(puls) {
1983                 uint8_t t;
1984                 IMMBYTE(t);
1985                 if (t & 0x01) {
1986                         PULLBYTE(CC);
1987                         icount -= 1;
1988                 }
1989                 if (t & 0x02) {
1990                         PULLBYTE(A);
1991                         icount -= 1;
1992                 }
1993                 if (t & 0x04) {
1994                         PULLBYTE(B);
1995                         icount -= 1;
1996                 }
1997                 if (t & 0x08) {
1998                         PULLBYTE(DP);
1999                         icount -= 1;
2000                 }
2001                 if (t & 0x10) {
2002                         PULLWORD(pX);
2003                         icount -= 2;
2004                 }
2005                 if (t & 0x20) {
2006                         PULLWORD(pY);
2007                         icount -= 2;
2008                 }
2009                 if (t & 0x40) {
2010                         PULLWORD(pU);
2011                         icount -= 2;
2012                 }
2013                 if (t & 0x80) {
2014                         PULLWORD(pPC);
2015                         icount -= 2;
2016                 }
2017                 //dmy = RM(S);  // Add 20100825
2018                 RM(S);  // Add 20100825
2019                 /* HJB 990225: moved check after all PULLs */
2020 //  if( t&0x01 ) { check_irq_lines(); }
2021         }
2022
2023 /* $36 PSHU inherent ----- */
2024 OP_HANDLER(pshu) {
2025                 uint8_t t;
2026                 IMMBYTE(t);
2027                 //dmy = RM(U);  // Add 20100825
2028                 RM(U);  // Add 20100825
2029                 if (t & 0x80) {
2030                         PSHUWORD(pPC);
2031                         icount -= 2;
2032                 }
2033                 if (t & 0x40) {
2034                         PSHUWORD(pS);
2035                         icount -= 2;
2036                 }
2037                 if (t & 0x20) {
2038                         PSHUWORD(pY);
2039                         icount -= 2;
2040                 }
2041                 if (t & 0x10) {
2042                         PSHUWORD(pX);
2043                         icount -= 2;
2044                 }
2045                 if (t & 0x08) {
2046                         PSHUBYTE(DP);
2047                         icount -= 1;
2048                 }
2049                 if (t & 0x04) {
2050                         PSHUBYTE(B);
2051                         icount -= 1;
2052                 }
2053                 if (t & 0x02) {
2054                         PSHUBYTE(A);
2055                         icount -= 1;
2056                 }
2057                 if (t & 0x01) {
2058                         PSHUBYTE(CC);
2059                         icount -= 1;
2060                 }
2061         }
2062
2063 /* 37 PULU inherent ----- */
2064 OP_HANDLER(pulu) {
2065                 uint8_t t;
2066                 IMMBYTE(t);
2067                 if (t & 0x01) {
2068                         PULUBYTE(CC);
2069                         icount -= 1;
2070                 }
2071                 if (t & 0x02) {
2072                         PULUBYTE(A);
2073                         icount -= 1;
2074                 }
2075                 if (t & 0x04) {
2076                         PULUBYTE(B);
2077                         icount -= 1;
2078                 }
2079                 if (t & 0x08) {
2080                         PULUBYTE(DP);
2081                         icount -= 1;
2082                 }
2083                 if (t & 0x10) {
2084                         PULUWORD(pX);
2085                         icount -= 2;
2086                 }
2087                 if (t & 0x20) {
2088                         PULUWORD(pY);
2089                         icount -= 2;
2090                 }
2091                 if (t & 0x40) {
2092                         PULUWORD(pS);
2093                         icount -= 2;
2094                 }
2095                 if (t & 0x80) {
2096                         PULUWORD(pPC);
2097                         icount -= 2;
2098                 }
2099                 //dmy = RM(U);  // Add 20100825
2100                 RM(U);  // Add 20100825
2101                 /* HJB 990225: moved check after all PULLs */
2102                 //if( t&0x01 ) { check_irq_lines(); }
2103 }
2104
2105 /* $38 ILLEGAL */
2106
2107 /* $39 RTS inherent ----- */
2108 OP_HANDLER(rts) {
2109         //printf("RTS: Before PC=%04x", pPC.w.l);
2110         PULLWORD(pPC);
2111         //printf(" After PC=%04x\n", pPC.w.l);
2112 }
2113
2114 /* $3A ABX inherent ----- */
2115 OP_HANDLER(abx) {
2116         pair32_t bt;
2117         bt.d = 0;
2118         bt.b.l = B;
2119         X = X + bt.w.l;
2120 }
2121
2122 /* $3B RTI inherent ##### */
2123 OP_HANDLER(rti) {
2124                 PULLBYTE(CC);
2125 //  t = CC & CC_E;    /* HJB 990225: entire state saved? */
2126         if ((CC & CC_E) != 0) { // NMIIRQ
2127                 icount -= 9;
2128                 PULLBYTE(A);
2129                 PULLBYTE(B);
2130                 PULLBYTE(DP);
2131                 PULLWORD(pX);
2132                 PULLWORD(pY);
2133                 PULLWORD(pU);
2134         }
2135         PULLWORD(pPC);
2136 //  check_irq_lines(); /* HJB 990116 */
2137 }
2138
2139 /* $3C CWAI inherent ----1 */
2140 OP_HANDLER(cwai) {
2141         uint8_t t;
2142         IMMBYTE(t);
2143         CC = CC & t;
2144         CC |= CC_E;     /* HJB 990225: save entire state */
2145         PUSHWORD(pPC);
2146         PUSHWORD(pU);
2147         PUSHWORD(pY);
2148         PUSHWORD(pX);
2149         PUSHBYTE(DP);
2150         PUSHBYTE(B);
2151         PUSHBYTE(A);
2152         PUSHBYTE(CC);
2153
2154         int_state = int_state | MC6809_CWAI_IN;
2155         int_state &= ~MC6809_CWAI_OUT;  // 0xfeff
2156         return;
2157 }
2158
2159 /* $3D MUL inherent --*-@ */
2160 OP_HANDLER(mul) {
2161         pair32_t t, r;
2162         t.d = 0;
2163         r.d = 0;
2164         t.b.l = A;
2165         r.b.l = B;
2166         t.d = t.d * r.d;
2167         CLR_ZC;
2168         SET_Z16(t.w.l);
2169         if (t.b.l & 0x80) SEC;
2170         A = t.b.h;
2171         B = t.b.l;
2172 }
2173
2174 /* $3E RST */
2175 OP_HANDLER(rst) {
2176         this->reset();
2177 }
2178
2179
2180 /* $3F SWI (SWI2 SWI3) absolute indirect ----- */
2181 OP_HANDLER(swi) {
2182                 CC |= CC_E;     /* HJB 980225: save entire state */
2183                 PUSHWORD(pPC);
2184                 PUSHWORD(pU);
2185                 PUSHWORD(pY);
2186                 PUSHWORD(pX);
2187                 PUSHBYTE(DP);
2188                 PUSHBYTE(B);
2189                 PUSHBYTE(A);
2190                 PUSHBYTE(CC);
2191                 CC |= CC_IF | CC_II;    /* inhibit FIRQ and IRQ */
2192                 pPC = RM16_PAIR(0xfffa);
2193 }
2194
2195 /* $103F SWI2 absolute indirect ----- */
2196 OP_HANDLER(swi2) {
2197                 CC |= CC_E;     /* HJB 980225: save entire state */
2198                 PUSHWORD(pPC);
2199                 PUSHWORD(pU);
2200                 PUSHWORD(pY);
2201                 PUSHWORD(pX);
2202                 PUSHBYTE(DP);
2203                 PUSHBYTE(B);
2204                 PUSHBYTE(A);
2205                 PUSHBYTE(CC);
2206                 pPC = RM16_PAIR(0xfff4);
2207 }
2208
2209 /* $113F SWI3 absolute indirect ----- */
2210 OP_HANDLER(swi3) {
2211                 CC |= CC_E;     /* HJB 980225: save entire state */
2212                 PUSHWORD(pPC);
2213                 PUSHWORD(pU);
2214                 PUSHWORD(pY);
2215                 PUSHWORD(pX);
2216                 PUSHBYTE(DP);
2217                 PUSHBYTE(B);
2218                 PUSHBYTE(A);
2219                 PUSHBYTE(CC);
2220                 pPC = RM16_PAIR(0xfff2);
2221 }
2222
2223 /* $40 NEGA inherent ?**** */
2224 OP_HANDLER(nega) {
2225         A = NEG_REG(A);
2226 }
2227
2228 /* $41 NEGA */
2229
2230
2231 /* $43 COMA inherent -**01 */
2232 OP_HANDLER(coma) {
2233         A = COM_REG(A);
2234 }
2235
2236 /* $42 NGCA */
2237 OP_HANDLER(ngca) {
2238         if ((CC & CC_C) == 0) {
2239                 nega();
2240         } else {
2241                 coma();
2242         }
2243 }
2244
2245 /* $44 LSRA inherent -0*-* */
2246 OP_HANDLER(lsra) {
2247         A = LSR_REG(A);
2248 }
2249
2250 /* $45 LSRA */
2251
2252 /* $46 RORA inherent -**-* */
2253 OP_HANDLER(rora) {
2254         A = ROR_REG(A);
2255 }
2256
2257 /* $47 ASRA inherent ?**-* */
2258 OP_HANDLER(asra) {
2259         A = ASR_REG(A);
2260 }
2261
2262 /* $48 ASLA inherent ?**** */
2263 OP_HANDLER(asla) {
2264         A = ASL_REG(A);
2265 }
2266
2267 /* $49 ROLA inherent -**** */
2268 OP_HANDLER(rola) {
2269         A = ROL_REG(A);
2270 }
2271
2272 /* $4A DECA inherent -***- */
2273 OP_HANDLER(deca) {
2274         A = DEC_REG(A);
2275 }
2276
2277
2278 /* $4B DCCA */
2279 OP_HANDLER(dcca) {
2280         A = DCC_REG(A);
2281 }
2282
2283 /* $4C INCA inherent -***- */
2284 OP_HANDLER(inca) {
2285         A = INC_REG(A);
2286 }
2287
2288 /* $4D TSTA inherent -**0- */
2289 OP_HANDLER(tsta) {
2290         A = TST_REG(A);
2291 }
2292
2293 /* $4E ILLEGAL */
2294 OP_HANDLER(clca) {
2295         A = CLC_REG(A);
2296 }
2297
2298 /* $4F CLRA inherent -0100 */
2299 OP_HANDLER(clra) {
2300         A = CLR_REG(A);
2301 }
2302
2303 /* $50 NEGB inherent ?**** */
2304 OP_HANDLER(negb) {
2305         B = NEG_REG(B);
2306 }
2307
2308 /* $51 NEGB */
2309
2310 /* $52 NGCB */
2311
2312 /* $53 COMB inherent -**01 */
2313 OP_HANDLER(comb) {
2314         B = COM_REG(B);
2315 }
2316
2317 /* $52 NGCB */
2318 OP_HANDLER(ngcb) {
2319         if ((CC & CC_C) == 0) {
2320                 negb();
2321         } else {
2322                 comb();
2323         }
2324 }
2325
2326 /* $54 LSRB inherent -0*-* */
2327 OP_HANDLER(lsrb) {
2328         B = LSR_REG(B);
2329 }
2330
2331 /* $55 LSRB */
2332
2333 /* $56 RORB inherent -**-* */
2334 OP_HANDLER(rorb) {
2335         B = ROR_REG(B);
2336 }
2337
2338 /* $57 ASRB inherent ?**-* */
2339 OP_HANDLER(asrb) {
2340         B = ASR_REG(B);
2341 }
2342
2343 /* $58 ASLB inherent ?**** */
2344 OP_HANDLER(aslb) {
2345         B = ASL_REG(B);
2346 }
2347
2348 /* $59 ROLB inherent -**** */
2349 OP_HANDLER(rolb) {
2350         B = ROL_REG(B);
2351 }
2352
2353 /* $5A DECB inherent -***- */
2354 OP_HANDLER(decb) {
2355         B = DEC_REG(B);
2356 }
2357
2358 /* $5B DCCB */
2359 OP_HANDLER(dccb) {
2360         B = DCC_REG(B);
2361 }
2362
2363 /* $5C INCB inherent -***- */
2364 OP_HANDLER(incb) {
2365         B = INC_REG(B);
2366 }
2367
2368 /* $5D TSTB inherent -**0- */
2369 OP_HANDLER(tstb) {
2370         B = TST_REG(B);
2371 }
2372
2373 /* $5E ILLEGAL */
2374 OP_HANDLER(clcb) {
2375         B = CLC_REG(B);
2376 }
2377
2378 /* $5F CLRB inherent -0100 */
2379 OP_HANDLER(clrb) {
2380         B = CLR_REG(B);
2381 }
2382
2383 /* $60 NEG indexed ?**** */
2384 OP_HANDLER(neg_ix) {
2385         uint8_t t;
2386         t = GET_INDEXED_DATA();
2387         NEG_MEM(t);
2388 }
2389
2390 /* $61 ILLEGAL */
2391
2392
2393 /* $63 COM indexed -**01 */
2394 OP_HANDLER(com_ix) {
2395         uint8_t t;
2396         t = GET_INDEXED_DATA();
2397         COM_MEM(t);
2398 }
2399
2400 /* $62 ILLEGAL */
2401 OP_HANDLER(ngc_ix) {
2402         if ((CC & CC_C) == 0) {
2403                 neg_ix();
2404         } else {
2405                 com_ix();
2406         }
2407 }
2408
2409 /* $64 LSR indexed -0*-* */
2410 OP_HANDLER(lsr_ix) {
2411         uint8_t t;
2412         t = GET_INDEXED_DATA();
2413         LSR_MEM(t);
2414 }
2415
2416 /* $65 ILLEGAL */
2417
2418 /* $66 ROR indexed -**-* */
2419 OP_HANDLER(ror_ix) {
2420         uint8_t t;
2421         t = GET_INDEXED_DATA();
2422         ROR_MEM(t);
2423 }
2424
2425 /* $67 ASR indexed ?**-* */
2426 OP_HANDLER(asr_ix) {
2427         uint8_t t;
2428         t = GET_INDEXED_DATA();
2429         ASR_MEM(t);
2430 }
2431
2432 /* $68 ASL indexed ?**** */
2433 OP_HANDLER(asl_ix) {
2434         uint8_t t;
2435         t = GET_INDEXED_DATA();
2436         ASL_MEM(t);
2437 }
2438
2439 /* $69 ROL indexed -**** */
2440 OP_HANDLER(rol_ix) {
2441         uint8_t t;
2442         t = GET_INDEXED_DATA();
2443         ROL_MEM(t);
2444 }
2445
2446 /* $6A DEC indexed -***- */
2447 OP_HANDLER(dec_ix) {
2448         uint8_t t;
2449         t = GET_INDEXED_DATA();
2450         DEC_MEM(t);
2451 }
2452
2453 /* $6B DCC index */
2454 OP_HANDLER(dcc_ix) {
2455         uint8_t t;
2456         t = GET_INDEXED_DATA();
2457         DCC_MEM(t);
2458 }
2459
2460 /* $6C INC indexed -***- */
2461 OP_HANDLER(inc_ix) {
2462         uint8_t t;
2463         t = GET_INDEXED_DATA();
2464         INC_MEM(t);
2465 }
2466
2467 /* $6D TST indexed -**0- */
2468 OP_HANDLER(tst_ix) {
2469         uint8_t t;
2470         t = GET_INDEXED_DATA();
2471         TST_MEM(t);
2472 }
2473
2474 /* $6E JMP indexed ----- */
2475 OP_HANDLER(jmp_ix) {
2476         fetch_effective_address();
2477         PCD = EAD;
2478 }
2479
2480 /* $6F CLR indexed -0100 */
2481 OP_HANDLER(clr_ix) {
2482         uint8_t t;
2483         t = GET_INDEXED_DATA();
2484         //dummy = RM(EAD);      // Dummy Read(Alpha etc...)
2485         RM(EAD);        // Dummy Read(Alpha etc...)
2486         CLR_MEM(t);
2487 }
2488
2489 /* $70 NEG extended ?**** */
2490 OP_HANDLER(neg_ex) {
2491         uint8_t t;
2492         EXTBYTE(t);
2493         NEG_MEM(t);
2494 }
2495
2496
2497 /* $73 COM extended -**01 */
2498 OP_HANDLER(com_ex) {
2499         uint8_t t;
2500         EXTBYTE(t);
2501         COM_MEM(t);
2502 }
2503
2504 /* $72 NGC extended */
2505 OP_HANDLER(ngc_ex) {
2506         if ((CC & CC_C) == 0) {
2507                 neg_ex();
2508         } else {
2509                 com_ex();
2510         }
2511 }
2512
2513 /* $74 LSR extended -0*-* */
2514 OP_HANDLER(lsr_ex) {
2515         uint8_t t;
2516         EXTBYTE(t);
2517         LSR_MEM(t);
2518 }
2519
2520 /* $75 ILLEGAL */
2521
2522 /* $76 ROR extended -**-* */
2523 OP_HANDLER(ror_ex) {
2524         uint8_t t;
2525         EXTBYTE(t);
2526         ROR_MEM(t);
2527 }
2528
2529 /* $77 ASR extended ?**-* */
2530 OP_HANDLER(asr_ex) {
2531         uint8_t t;
2532         EXTBYTE(t);
2533         ASR_MEM(t);
2534 }
2535
2536 /* $78 ASL extended ?**** */
2537 OP_HANDLER(asl_ex) {
2538         uint8_t t;
2539         EXTBYTE(t);
2540         ASL_MEM(t);
2541 }
2542
2543 /* $79 ROL extended -**** */
2544 OP_HANDLER(rol_ex) {
2545         uint8_t t;
2546         EXTBYTE(t);
2547         ROL_MEM(t);
2548 }
2549
2550 /* $7A DEC extended -***- */
2551 OP_HANDLER(dec_ex) {
2552         uint8_t t;
2553         EXTBYTE(t);
2554         DEC_MEM(t);
2555 }
2556
2557 /* $7B ILLEGAL */
2558 /* $6B DCC index */
2559 OP_HANDLER(dcc_ex) {
2560         uint8_t t;
2561         EXTBYTE(t);
2562         DCC_MEM(t);
2563 }
2564
2565 /* $7C INC extended -***- */
2566 OP_HANDLER(inc_ex) {
2567         uint8_t t;
2568         EXTBYTE(t);
2569         INC_MEM(t);
2570 }
2571
2572 /* $7D TST extended -**0- */
2573 OP_HANDLER(tst_ex) {
2574         uint8_t t;
2575         EXTBYTE(t);
2576         TST_MEM(t);
2577 }
2578
2579 /* $7E JMP extended ----- */
2580 OP_HANDLER(jmp_ex) {
2581         EXTENDED;
2582         PCD = EAD;
2583 }
2584
2585 /* $7F CLR extended -0100 */
2586 OP_HANDLER(clr_ex) {
2587         uint8_t dummy;
2588         EXTENDED;
2589         dummy = RM(EAD);
2590         CLR_MEM(dummy);
2591 }
2592
2593 /* $80 SUBA immediate ?**** */
2594 OP_HANDLER(suba_im) {
2595         uint8_t t;
2596         IMMBYTE(t);
2597         A = SUB8_REG(A, t);
2598 }
2599
2600 /* $81 CMPA immediate ?**** */
2601 OP_HANDLER(cmpa_im) {
2602         uint8_t t;
2603         IMMBYTE(t);
2604         A = CMP8_REG(A, t);
2605 }
2606
2607 /* $82 SBCA immediate ?**** */
2608 OP_HANDLER(sbca_im) {
2609         uint8_t t;
2610         IMMBYTE(t);
2611         A = SBC8_REG(A, t);
2612 }
2613
2614 /* $83 SUBD (CMPD CMPU) immediate -**** */
2615 OP_HANDLER(subd_im) {
2616         pair32_t b;
2617         IMMWORD(b);
2618         D = SUB16_REG(D, b.w.l);
2619 }
2620
2621 /* $1083 CMPD immediate -**** */
2622 OP_HANDLER(cmpd_im) {
2623         pair32_t b;
2624         IMMWORD(b);
2625         D = CMP16_REG(D, b.w.l);
2626 }
2627
2628 /* $1183 CMPU immediate -**** */
2629 OP_HANDLER(cmpu_im) {
2630         pair32_t b;
2631         IMMWORD(b);
2632         U = CMP16_REG(U, b.w.l);
2633 }
2634
2635 /* $84 ANDA immediate -**0- */
2636 OP_HANDLER(anda_im) {
2637         uint8_t t;
2638         IMMBYTE(t);
2639         A = AND8_REG(A, t);
2640 }
2641
2642 /* $85 BITA immediate -**0- */
2643 OP_HANDLER(bita_im) {
2644         uint8_t t;
2645         IMMBYTE(t);
2646         A = BIT8_REG(A, t);
2647 }
2648
2649 /* $86 LDA immediate -**0- */
2650 OP_HANDLER(lda_im) {
2651         IMMBYTE(A);
2652         A = LOAD8_REG(A);
2653 }
2654
2655 /* is this a legal instruction? */
2656 /* $87 STA immediate -**0- */
2657 OP_HANDLER(sta_im) {
2658                 CLR_NZV;
2659                 SET_NZ8(A);
2660                 IMM8;
2661                 WM(EAD, A);
2662         }
2663
2664 /*
2665  * $87 , $C7: FLAG8
2666  */
2667 OP_HANDLER(flag8_im) {
2668                 // 20111117
2669                 //uint8_t t;
2670                 // IMMBYTE(t);
2671                 ROP_ARG(PCD);
2672                 PC++;
2673                 CLR_NZV;
2674                 CC |= CC_N;
2675         }
2676
2677
2678 /* $88 EORA immediate -**0- */
2679 OP_HANDLER(eora_im) {
2680                 uint8_t t;
2681                 IMMBYTE(t);
2682                 A = EOR8_REG(A, t);
2683 }
2684
2685 /* $89 ADCA immediate ***** */
2686 OP_HANDLER(adca_im) {
2687         uint8_t t;
2688         IMMBYTE(t);
2689         A = ADC8_REG(A, t);
2690 }
2691
2692 /* $8A ORA immediate -**0- */
2693 OP_HANDLER(ora_im) {
2694         uint8_t t;
2695         IMMBYTE(t);
2696         A = OR8_REG(A, t);
2697 }
2698
2699 /* $8B ADDA immediate ***** */
2700 OP_HANDLER(adda_im) {
2701         uint8_t t;
2702         IMMBYTE(t);
2703         A = ADD8_REG(A, t);
2704 }
2705
2706 /* $8C CMPX (CMPY CMPS) immediate -**** */
2707 OP_HANDLER(cmpx_im) {
2708         pair32_t b;
2709         IMMWORD(b);
2710         X = CMP16_REG(X, b.w.l);
2711 }
2712
2713 /* $108C CMPY immediate -**** */
2714 OP_HANDLER(cmpy_im) {
2715         pair32_t b;
2716         IMMWORD(b);
2717         Y = CMP16_REG(Y, b.w.l);
2718 }
2719
2720 /* $118C CMPS immediate -**** */
2721 OP_HANDLER(cmps_im) {
2722         pair32_t b;
2723         IMMWORD(b);
2724         S = CMP16_REG(S, b.w.l);
2725 }
2726
2727 /* $8D BSR ----- */
2728 OP_HANDLER(bsr) {
2729                 uint8_t t;
2730                 IMMBYTE(t);
2731                 PUSHWORD(pPC);
2732                 PC += SIGNED(t);
2733         }
2734
2735 /* $8E LDX (LDY) immediate -**0- */
2736 OP_HANDLER(ldx_im) {
2737         IMMWORD(pX);
2738         X = LOAD16_REG(X);
2739 }
2740
2741 /* $108E LDY immediate -**0- */
2742 OP_HANDLER(ldy_im) {
2743         IMMWORD(pY);
2744         Y = LOAD16_REG(Y);
2745 }
2746
2747 /* is this a legal instruction? */
2748 /* $8F STX (STY) immediate -**0- */
2749 OP_HANDLER(stx_im) {
2750                 CLR_NZV;
2751                 SET_NZ16(X);
2752                 IMM16;
2753                 WM16(EAD, &pX);
2754         }
2755
2756 /*
2757  * $8F , $CF: FLAG16
2758  */
2759 OP_HANDLER(flag16_im) {
2760                 pair32_t t;
2761                 IMMWORD(t);
2762                 CLR_NZV;
2763                 CC |= CC_N;
2764 }
2765
2766
2767 /* is this a legal instruction? */
2768 /* $108F STY immediate -**0- */
2769 OP_HANDLER(sty_im) {
2770                 CLR_NZV;
2771                 SET_NZ16(Y);
2772                 IMM16;
2773                 WM16(EAD, &pY);
2774         }
2775
2776 /* $90 SUBA direct ?**** */
2777 OP_HANDLER(suba_di) {
2778         uint8_t t;
2779         DIRBYTE(t);
2780         A = SUB8_REG(A, t);
2781 }
2782
2783 /* $91 CMPA direct ?**** */
2784 OP_HANDLER(cmpa_di) {
2785         uint8_t t;
2786         DIRBYTE(t);
2787         A = CMP8_REG(A, t);
2788 }
2789
2790 /* $92 SBCA direct ?**** */
2791 OP_HANDLER(sbca_di) {
2792         uint8_t t;
2793         DIRBYTE(t);
2794         A = SBC8_REG(A, t);
2795 }
2796
2797 /* $93 SUBD (CMPD CMPU) direct -**** */
2798 OP_HANDLER(subd_di) {
2799         pair32_t b;
2800         DIRWORD(b);
2801         D = SUB16_REG(D, b.w.l);
2802 }
2803
2804 /* $1093 CMPD direct -**** */
2805 OP_HANDLER(cmpd_di) {
2806         pair32_t b;
2807         DIRWORD(b);
2808         D = CMP16_REG(D, b.w.l);
2809 }
2810
2811 /* $1193 CMPU direct -**** */
2812 OP_HANDLER(cmpu_di) {
2813         pair32_t b;
2814         DIRWORD(b);
2815         U = CMP16_REG(U, b.w.l);
2816 }
2817
2818 /* $94 ANDA direct -**0- */
2819 OP_HANDLER(anda_di) {
2820         uint8_t t;
2821         DIRBYTE(t);
2822         A = AND8_REG(A, t);
2823 }
2824
2825 /* $95 BITA direct -**0- */
2826 OP_HANDLER(bita_di) {
2827         uint8_t t;
2828         DIRBYTE(t);
2829         A = BIT8_REG(A, t);
2830 }
2831
2832 /* $96 LDA direct -**0- */
2833 OP_HANDLER(lda_di) {
2834         DIRBYTE(A);
2835         A = LOAD8_REG(A);
2836 }
2837
2838 /* $97 STA direct -**0- */
2839 OP_HANDLER(sta_di) {
2840         DIRECT;
2841         STORE8_REG(A);
2842 }
2843
2844 /* $98 EORA direct -**0- */
2845 OP_HANDLER(eora_di) {
2846         uint8_t t;
2847         DIRBYTE(t);
2848         A = EOR8_REG(A, t);
2849 }
2850
2851 /* $99 ADCA direct ***** */
2852 OP_HANDLER(adca_di) {
2853         uint8_t t;
2854         DIRBYTE(t);
2855         A = ADC8_REG(A, t);
2856 }
2857
2858 /* $9A ORA direct -**0- */
2859 OP_HANDLER(ora_di) {
2860         uint8_t t;
2861         DIRBYTE(t);
2862         A = OR8_REG(A, t);
2863 }
2864
2865 /* $9B ADDA direct ***** */
2866 OP_HANDLER(adda_di) {
2867         uint8_t t;
2868         DIRBYTE(t);
2869         A = ADD8_REG(A, t);
2870 }
2871
2872 /* $9C CMPX (CMPY CMPS) direct -**** */
2873 OP_HANDLER(cmpx_di) {
2874         pair32_t b;
2875         DIRWORD(b);
2876         X = CMP16_REG(X, b.w.l);
2877 }
2878
2879 /* $109C CMPY direct -**** */
2880 OP_HANDLER(cmpy_di) {
2881         pair32_t b;
2882         DIRWORD(b);
2883         Y = CMP16_REG(Y, b.w.l);
2884 }
2885
2886 /* $119C CMPS direct -**** */
2887 OP_HANDLER(cmps_di) {
2888         pair32_t b;
2889         DIRWORD(b);
2890         S = CMP16_REG(S, b.w.l);
2891 }
2892
2893 /* $9D JSR direct ----- */
2894 OP_HANDLER(jsr_di) {
2895                 DIRECT;
2896                 PUSHWORD(pPC);
2897                 PCD = EAD;
2898         }
2899
2900 /* $9E LDX (LDY) direct -**0- */
2901 OP_HANDLER(ldx_di) {
2902         DIRWORD(pX);
2903         X = LOAD16_REG(X);
2904 }
2905
2906 /* $109E LDY direct -**0- */
2907 OP_HANDLER(ldy_di) {
2908         DIRWORD(pY);
2909         Y = LOAD16_REG(Y);
2910 }
2911
2912 /* $9F STX (STY) direct -**0- */
2913 OP_HANDLER(stx_di) {
2914         DIRECT;
2915         STORE16_REG(&pX);
2916 }
2917
2918 /* $109F STY direct -**0- */
2919 OP_HANDLER(sty_di) {
2920         DIRECT;
2921         STORE16_REG(&pY);
2922 }
2923
2924 /* $a0 SUBA indexed ?**** */
2925 OP_HANDLER(suba_ix) {
2926         uint8_t t;
2927         t = GET_INDEXED_DATA();
2928         A = SUB8_REG(A, t);
2929 }
2930
2931 /* $a1 CMPA indexed ?**** */
2932 OP_HANDLER(cmpa_ix) {
2933         uint8_t t;
2934         t = GET_INDEXED_DATA();
2935         A = CMP8_REG(A, t);
2936 }
2937
2938 /* $a2 SBCA indexed ?**** */
2939 OP_HANDLER(sbca_ix) {
2940         uint8_t t;
2941         t = GET_INDEXED_DATA();
2942         A = SBC8_REG(A, t);
2943 }
2944
2945 /* $a3 SUBD (CMPD CMPU) indexed -**** */
2946 OP_HANDLER(subd_ix) {
2947         pair32_t b;
2948         b = GET_INDEXED_DATA16();
2949         D = SUB16_REG(D, b.w.l);
2950 }
2951
2952 /* $10a3 CMPD indexed -**** */
2953 OP_HANDLER(cmpd_ix) {
2954         pair32_t b;
2955         b = GET_INDEXED_DATA16();
2956         D = CMP16_REG(D, b.w.l);
2957 }
2958
2959 /* $11a3 CMPU indexed -**** */
2960 OP_HANDLER(cmpu_ix) {
2961         pair32_t b;
2962         b = GET_INDEXED_DATA16();
2963         U = CMP16_REG(U, b.w.l);
2964 }
2965
2966 /* $a4 ANDA indexed -**0- */
2967 OP_HANDLER(anda_ix) {
2968         uint8_t t;
2969         t = GET_INDEXED_DATA();
2970         A = AND8_REG(A, t);
2971 }
2972
2973 /* $a5 BITA indexed -**0- */
2974 OP_HANDLER(bita_ix) {
2975         uint8_t t;
2976         t = GET_INDEXED_DATA();
2977         A = BIT8_REG(A, t);
2978 }
2979
2980 /* $a6 LDA indexed -**0- */
2981 OP_HANDLER(lda_ix) {
2982         A = GET_INDEXED_DATA();
2983         A = LOAD8_REG(A);
2984 }
2985
2986 /* $a7 STA indexed -**0- */
2987 OP_HANDLER(sta_ix) {
2988         fetch_effective_address();
2989         STORE8_REG(A);
2990 }
2991
2992 /* $a8 EORA indexed -**0- */
2993 OP_HANDLER(eora_ix) {
2994         uint8_t t;
2995         t = GET_INDEXED_DATA();
2996         A = EOR8_REG(A, t);
2997 }
2998
2999 /* $a9 ADCA indexed ***** */
3000 OP_HANDLER(adca_ix) {
3001         uint8_t t;
3002         t = GET_INDEXED_DATA();
3003         A = ADC8_REG(A, t);
3004 }
3005
3006 /* $aA ORA indexed -**0- */
3007 OP_HANDLER(ora_ix) {
3008         uint8_t t;
3009         t = GET_INDEXED_DATA();
3010         A = OR8_REG(A, t);
3011 }
3012
3013 /* $aB ADDA indexed ***** */
3014 OP_HANDLER(adda_ix) {
3015         uint8_t t;
3016         t = GET_INDEXED_DATA();
3017         A = ADD8_REG(A, t);
3018 }
3019
3020 /* $aC CMPX (CMPY CMPS) indexed -**** */
3021 OP_HANDLER(cmpx_ix) {
3022         pair32_t b;
3023         b = GET_INDEXED_DATA16();
3024         X = CMP16_REG(X, b.w.l);
3025 }
3026
3027 /* $10aC CMPY indexed -**** */
3028 OP_HANDLER(cmpy_ix) {
3029         pair32_t b;
3030         b = GET_INDEXED_DATA16();
3031         Y = CMP16_REG(Y, b.w.l);
3032 }
3033
3034 /* $11aC CMPS indexed -**** */
3035 OP_HANDLER(cmps_ix) {
3036         pair32_t b;
3037         b = GET_INDEXED_DATA16();
3038         S = CMP16_REG(S, b.w.l);
3039 }
3040
3041 /* $aD JSR indexed ----- */
3042 OP_HANDLER(jsr_ix) {
3043         fetch_effective_address();
3044         PUSHWORD(pPC);
3045         PCD = EAD;
3046 }
3047
3048 /* $aE LDX (LDY) indexed -**0- */
3049 OP_HANDLER(ldx_ix) {
3050         pair32_t t;
3051         t = GET_INDEXED_DATA16();
3052         X = t.w.l;
3053         X = LOAD16_REG(X);
3054 }
3055
3056 /* $10aE LDY indexed -**0- */
3057 OP_HANDLER(ldy_ix) {
3058         pair32_t t;
3059         t = GET_INDEXED_DATA16();
3060         Y = t.w.l;
3061         Y = LOAD16_REG(Y);
3062 }
3063
3064 /* $aF STX (STY) indexed -**0- */
3065 OP_HANDLER(stx_ix) {
3066         fetch_effective_address();
3067         STORE16_REG(&pX);
3068 }
3069
3070 /* $10aF STY indexed -**0- */
3071 OP_HANDLER(sty_ix) {
3072         fetch_effective_address();
3073         STORE16_REG(&pY);
3074 }
3075
3076 /* $b0 SUBA extended ?**** */
3077 OP_HANDLER(suba_ex) {
3078         uint8_t t;
3079         EXTBYTE(t);
3080         A = SUB8_REG(A, t);
3081 }
3082
3083 /* $b1 CMPA extended ?**** */
3084 OP_HANDLER(cmpa_ex) {
3085         uint8_t t;
3086         EXTBYTE(t);
3087         A = CMP8_REG(A, t);
3088 }
3089
3090 /* $b2 SBCA extended ?**** */
3091 OP_HANDLER(sbca_ex) {
3092         uint8_t t;
3093         EXTBYTE(t);
3094         A = SBC8_REG(A, t);
3095 }
3096
3097 /* $b3 SUBD (CMPD CMPU) extended -**** */
3098 OP_HANDLER(subd_ex) {
3099         pair32_t b;
3100         EXTWORD(b);
3101         D = SUB16_REG(D, b.w.l);
3102 }
3103
3104 /* $10b3 CMPD extended -**** */
3105 OP_HANDLER(cmpd_ex) {
3106         pair32_t b;
3107         EXTWORD(b);
3108         D = CMP16_REG(D, b.w.l);
3109 }
3110
3111 /* $11b3 CMPU extended -**** */
3112 OP_HANDLER(cmpu_ex) {
3113         pair32_t b;
3114         EXTWORD(b);
3115         U = CMP16_REG(U, b.w.l);
3116 }
3117
3118 /* $b4 ANDA extended -**0- */
3119 OP_HANDLER(anda_ex) {
3120         uint8_t t;
3121         EXTBYTE(t);
3122         A = AND8_REG(A, t);
3123 }
3124
3125 /* $b5 BITA extended -**0- */
3126 OP_HANDLER(bita_ex) {
3127         uint8_t t;
3128         EXTBYTE(t);
3129         A = BIT8_REG(A, t);
3130 }
3131
3132 /* $b6 LDA extended -**0- */
3133 OP_HANDLER(lda_ex) {
3134         EXTBYTE(A);
3135         A = LOAD8_REG(A);
3136 }
3137
3138 /* $b7 STA extended -**0- */
3139 OP_HANDLER(sta_ex) {
3140         EXTENDED;
3141         STORE8_REG(A);
3142 }
3143
3144 /* $b8 EORA extended -**0- */
3145 OP_HANDLER(eora_ex) {
3146         uint8_t t;
3147         EXTBYTE(t);
3148         A = EOR8_REG(A, t);
3149 }
3150
3151 /* $b9 ADCA extended ***** */
3152 OP_HANDLER(adca_ex) {
3153         uint8_t t;
3154         EXTBYTE(t);
3155         A = ADC8_REG(A, t);
3156 }
3157
3158 /* $bA ORA extended -**0- */
3159 OP_HANDLER(ora_ex) {
3160         uint8_t t;
3161         EXTBYTE(t);
3162         A = OR8_REG(A, t);
3163 }
3164
3165 /* $bB ADDA extended ***** */
3166 OP_HANDLER(adda_ex) {
3167         uint8_t t;
3168         EXTBYTE(t);
3169         A = ADD8_REG(A, t);
3170 }
3171
3172 /* $bC CMPX (CMPY CMPS) extended -**** */
3173 OP_HANDLER(cmpx_ex) {
3174         pair32_t b;
3175         EXTWORD(b);
3176         X = CMP16_REG(X, b.w.l);
3177 }
3178
3179 /* $10bC CMPY extended -**** */
3180 OP_HANDLER(cmpy_ex) {
3181         pair32_t b;
3182         EXTWORD(b);
3183         Y = CMP16_REG(Y, b.w.l);
3184 }
3185
3186 /* $11bC CMPS extended -**** */
3187 OP_HANDLER(cmps_ex) {
3188         pair32_t b;
3189         EXTWORD(b);
3190         S = CMP16_REG(S, b.w.l);
3191 }
3192
3193 /* $bD JSR extended ----- */
3194 OP_HANDLER(jsr_ex) {
3195                 EXTENDED;
3196                 PUSHWORD(pPC);
3197                 PCD = EAD;
3198 }
3199
3200 /* $bE LDX (LDY) extended -**0- */
3201 OP_HANDLER(ldx_ex) {
3202         EXTWORD(pX);
3203         X = LOAD16_REG(X);
3204 }
3205
3206 /* $10bE LDY extended -**0- */
3207 OP_HANDLER(ldy_ex) {
3208         EXTWORD(pY);
3209         Y = LOAD16_REG(Y);
3210 }
3211
3212 /* $bF STX (STY) extended -**0- */
3213 OP_HANDLER(stx_ex) {
3214         EXTENDED;
3215         STORE16_REG(&pX);
3216 }
3217
3218 /* $10bF STY extended -**0- */
3219 OP_HANDLER(sty_ex) {
3220         EXTENDED;
3221         STORE16_REG(&pY);
3222 }
3223
3224 /* $c0 SUBB immediate ?**** */
3225 OP_HANDLER(subb_im) {
3226         uint8_t t;
3227         IMMBYTE(t);
3228         B = SUB8_REG(B, t);
3229 }
3230
3231 /* $c1 CMPB immediate ?**** */
3232 OP_HANDLER(cmpb_im) {
3233         uint8_t t;
3234         IMMBYTE(t);
3235         B = CMP8_REG(B, t);
3236 }
3237
3238 /* $c2 SBCB immediate ?**** */
3239 OP_HANDLER(sbcb_im) {
3240         uint8_t t;
3241         IMMBYTE(t);
3242         B = SBC8_REG(B, t);
3243 }
3244
3245 /* $c3 ADDD immediate -**** */
3246 OP_HANDLER(addd_im) {
3247         pair32_t b;
3248         IMMWORD(b);
3249         D = ADD16_REG(D, b.w.l);
3250 }
3251
3252 /* $c4 ANDB immediate -**0- */
3253 OP_HANDLER(andb_im) {
3254         uint8_t t;
3255         IMMBYTE(t);
3256         B = AND8_REG(B, t);
3257 }
3258
3259 /* $c5 BITB immediate -**0- */
3260 OP_HANDLER(bitb_im) {
3261         uint8_t t;
3262         IMMBYTE(t);
3263         B = BIT8_REG(B, t);
3264 }
3265
3266 /* $c6 LDB immediate -**0- */
3267 OP_HANDLER(ldb_im) {
3268         IMMBYTE(B);
3269         B = LOAD8_REG(B);
3270 }
3271
3272 /* is this a legal instruction? */
3273 /* $c7 STB immediate -**0- */
3274 OP_HANDLER(stb_im) {
3275         CLR_NZV;
3276         SET_NZ8(B);
3277         IMM8;
3278         WM(EAD, B);
3279 }
3280
3281 /* $c8 EORB immediate -**0- */
3282 OP_HANDLER(eorb_im) {
3283         uint8_t t;
3284         IMMBYTE(t);
3285         B = EOR8_REG(B, t);
3286 }
3287
3288 /* $c9 ADCB immediate ***** */
3289 OP_HANDLER(adcb_im) {
3290         uint8_t t;
3291         IMMBYTE(t);
3292         B = ADC8_REG(B, t);
3293 }
3294
3295 /* $cA ORB immediate -**0- */
3296 OP_HANDLER(orb_im) {
3297         uint8_t t;
3298         IMMBYTE(t);
3299         B = OR8_REG(B, t);
3300 }
3301
3302 /* $cB ADDB immediate ***** */
3303 OP_HANDLER(addb_im) {
3304         uint8_t t;
3305         IMMBYTE(t);
3306         B = ADD8_REG(B, t);
3307 }
3308
3309 /* $cC LDD immediate -**0- */
3310 OP_HANDLER(ldd_im) {
3311         IMMWORD(pD);
3312         D = LOAD16_REG(D);
3313 }
3314
3315 /* is this a legal instruction? */
3316 /* $cD STD immediate -**0- */
3317 OP_HANDLER(std_im) {
3318                 CLR_NZV;
3319                 SET_NZ16(D);
3320                 IMM16;
3321                 WM(EAD, D);
3322 }
3323
3324 /* $cE LDU (LDS) immediate -**0- */
3325 OP_HANDLER(ldu_im) {
3326         IMMWORD(pU);
3327         U = LOAD16_REG(U);
3328 }
3329
3330 /* $10cE LDS immediate -**0- */
3331 OP_HANDLER(lds_im) {
3332         IMMWORD(pS);
3333         S = LOAD16_REG(S);
3334         int_state |= MC6809_LDS;
3335 }
3336
3337 /* is this a legal instruction? */
3338 /* $cF STU (STS) immediate -**0- */
3339 OP_HANDLER(stu_im) {
3340                 CLR_NZV;
3341                 SET_NZ16(U);
3342                 IMM16;
3343                 WM16(EAD, &pU);
3344         }
3345
3346 /* is this a legal instruction? */
3347 /* $10cF STS immediate -**0- */
3348 OP_HANDLER(sts_im) {
3349                 CLR_NZV;
3350                 SET_NZ16(S);
3351                 IMM16;
3352                 WM16(EAD, &pS);
3353         }
3354
3355 /* $d0 SUBB direct ?**** */
3356 OP_HANDLER(subb_di) {
3357         uint8_t t;
3358         DIRBYTE(t);
3359         B = SUB8_REG(B, t);
3360 }
3361 /* $d1 CMPB direct ?**** */
3362 OP_HANDLER(cmpb_di) {
3363         uint8_t t;
3364         DIRBYTE(t);
3365         B = CMP8_REG(B, t);
3366 }
3367
3368 /* $d2 SBCB direct ?**** */
3369 OP_HANDLER(sbcb_di) {
3370         uint8_t t;
3371         DIRBYTE(t);
3372         B = SBC8_REG(B, t);
3373 }
3374
3375 /* $d3 ADDD direct -**** */
3376 OP_HANDLER(addd_di) {
3377         pair32_t b;
3378         DIRWORD(b);
3379         D = ADD16_REG(D, b.w.l);
3380 }
3381
3382 /* $d4 ANDB direct -**0- */
3383 OP_HANDLER(andb_di) {
3384         uint8_t t;
3385         DIRBYTE(t);
3386         B = AND8_REG(B, t);
3387 }
3388
3389 /* $d5 BITB direct -**0- */
3390 OP_HANDLER(bitb_di) {
3391         uint8_t t;
3392         DIRBYTE(t);
3393         B = BIT8_REG(B, t);
3394 }
3395
3396 /* $d6 LDB direct -**0- */
3397 OP_HANDLER(ldb_di) {
3398         DIRBYTE(B);
3399         B = LOAD8_REG(B);
3400 }
3401
3402 /* $d7 STB direct -**0- */
3403 OP_HANDLER(stb_di) {
3404         DIRECT;
3405         STORE8_REG(B);
3406 }
3407
3408 /* $d8 EORB direct -**0- */
3409 OP_HANDLER(eorb_di) {
3410         uint8_t t;
3411         DIRBYTE(t);
3412         B = EOR8_REG(B, t);
3413 }
3414
3415 /* $d9 ADCB direct ***** */
3416 OP_HANDLER(adcb_di) {
3417         uint8_t t;
3418         DIRBYTE(t);
3419         B = ADC8_REG(B, t);
3420 }
3421
3422 /* $dA ORB direct -**0- */
3423 OP_HANDLER(orb_di) {
3424         uint8_t t;
3425         DIRBYTE(t);
3426         B = OR8_REG(B, t);
3427 }
3428
3429 /* $dB ADDB direct ***** */
3430 OP_HANDLER(addb_di) {
3431         uint8_t t;
3432         DIRBYTE(t);
3433         B = ADD8_REG(B, t);
3434 }
3435
3436 /* $dC LDD direct -**0- */
3437 OP_HANDLER(ldd_di) {
3438         DIRWORD(pD);
3439         D = LOAD16_REG(D);
3440 }
3441
3442 /* $dD STD direct -**0- */
3443 OP_HANDLER(std_di) {
3444         DIRECT;
3445         STORE16_REG(&pD);
3446 }
3447
3448 /* $dE LDU (LDS) direct -**0- */
3449 OP_HANDLER(ldu_di) {
3450         DIRWORD(pU);
3451         U = LOAD16_REG(U);
3452 }
3453
3454 /* $10dE LDS direct -**0- */
3455 OP_HANDLER(lds_di) {
3456         DIRWORD(pS);
3457         S = LOAD16_REG(S);
3458         int_state |= MC6809_LDS;
3459 }
3460
3461 /* $dF STU (STS) direct -**0- */
3462 OP_HANDLER(stu_di) {
3463         DIRECT;
3464         STORE16_REG(&pU);
3465 }
3466
3467 /* $10dF STS direct -**0- */
3468 OP_HANDLER(sts_di) {
3469         DIRECT;
3470         STORE16_REG(&pS);
3471 }
3472
3473 /* $e0 SUBB indexed ?**** */
3474 OP_HANDLER(subb_ix) {
3475         uint8_t t;
3476         t = GET_INDEXED_DATA();
3477         B = SUB8_REG(B, t);
3478 }
3479
3480 /* $e1 CMPB indexed ?**** */
3481 OP_HANDLER(cmpb_ix) {
3482         uint8_t t;
3483         t = GET_INDEXED_DATA();
3484         B = CMP8_REG(B, t);
3485 }
3486
3487 /* $e2 SBCB indexed ?**** */
3488 OP_HANDLER(sbcb_ix) {
3489         uint8_t t;
3490         t = GET_INDEXED_DATA();
3491         B = SBC8_REG(B, t);
3492 }
3493
3494 /* $e3 ADDD indexed -**** */
3495 OP_HANDLER(addd_ix) {
3496         pair32_t b;
3497         b = GET_INDEXED_DATA16();
3498         D = ADD16_REG(D, b.w.l);
3499 }
3500
3501 /* $e4 ANDB indexed -**0- */
3502 OP_HANDLER(andb_ix) {
3503         uint8_t t;
3504         t = GET_INDEXED_DATA();
3505         B = AND8_REG(B, t);
3506 }
3507
3508 /* $e5 BITB indexed -**0- */
3509 OP_HANDLER(bitb_ix) {
3510         uint8_t t;
3511         t = GET_INDEXED_DATA();
3512         B = BIT8_REG(B, t);
3513 }
3514
3515 /* $e6 LDB indexed -**0- */
3516 OP_HANDLER(ldb_ix) {
3517         B = GET_INDEXED_DATA();
3518         B = LOAD8_REG(B);
3519 }
3520
3521 /* $e7 STB indexed -**0- */
3522 OP_HANDLER(stb_ix) {
3523         fetch_effective_address();
3524         STORE8_REG(B);
3525 }
3526
3527 /* $e8 EORB indexed -**0- */
3528 OP_HANDLER(eorb_ix) {
3529         uint8_t t;
3530         t = GET_INDEXED_DATA();
3531         B = EOR8_REG(B, t);
3532 }
3533
3534 /* $e9 ADCB indexed ***** */
3535 OP_HANDLER(adcb_ix) {
3536         uint8_t t;
3537         t = GET_INDEXED_DATA();
3538         B = ADC8_REG(B, t);
3539 }
3540
3541 /* $eA ORB indexed -**0- */
3542 OP_HANDLER(orb_ix) {
3543         uint8_t t;
3544         t = GET_INDEXED_DATA();
3545         B = OR8_REG(B, t);
3546 }
3547
3548 /* $eB ADDB indexed ***** */
3549 OP_HANDLER(addb_ix) {
3550         uint8_t t;
3551         t = GET_INDEXED_DATA();
3552         B = ADD8_REG(B, t);
3553 }
3554
3555 /* $eC LDD indexed -**0- */
3556 OP_HANDLER(ldd_ix) {
3557         pair32_t t;
3558         t = GET_INDEXED_DATA16();
3559         D = t.w.l;
3560         D = LOAD16_REG(D);
3561 }
3562
3563 /* $eD STD indexed -**0- */
3564 OP_HANDLER(std_ix) {
3565         fetch_effective_address();
3566         STORE16_REG(&pD);
3567 }
3568
3569 /* $eE LDU (LDS) indexed -**0- */
3570 OP_HANDLER(ldu_ix) {
3571         pair32_t t;
3572         t = GET_INDEXED_DATA16();
3573         U = t.w.l;
3574         U = LOAD16_REG(U);
3575 }
3576
3577 /* $10eE LDS indexed -**0- */
3578 OP_HANDLER(lds_ix) {
3579         pair32_t t;
3580         t = GET_INDEXED_DATA16();
3581         S = t.w.l;
3582         S = LOAD16_REG(S);
3583         int_state |= MC6809_LDS;
3584 }
3585
3586 /* $eF STU (STS) indexed -**0- */
3587 OP_HANDLER(stu_ix) {
3588         fetch_effective_address();
3589         STORE16_REG(&pU);
3590 }
3591
3592 /* $10eF STS indexed -**0- */
3593 OP_HANDLER(sts_ix) {
3594         fetch_effective_address();
3595         STORE16_REG(&pS);
3596 }
3597
3598 /* $f0 SUBB extended ?**** */
3599 OP_HANDLER(subb_ex) {
3600         uint8_t t;
3601         EXTBYTE(t);
3602         B = SUB8_REG(B, t);
3603 }
3604
3605 /* $f1 CMPB extended ?**** */
3606 OP_HANDLER(cmpb_ex) {
3607         uint8_t t;
3608         EXTBYTE(t);
3609         B = CMP8_REG(B, t);
3610 }
3611
3612 /* $f2 SBCB extended ?**** */
3613 OP_HANDLER(sbcb_ex) {
3614         uint8_t t;
3615         EXTBYTE(t);
3616         B = SBC8_REG(B, t);
3617 }
3618
3619 /* $f3 ADDD extended -**** */
3620 OP_HANDLER(addd_ex) {
3621         pair32_t b;
3622         EXTWORD(b);
3623         D = ADD16_REG(D, b.w.l);
3624 }
3625
3626 /* $f4 ANDB extended -**0- */
3627 OP_HANDLER(andb_ex) {
3628         uint8_t t;
3629         EXTBYTE(t);
3630         B = AND8_REG(B, t);
3631 }
3632
3633 /* $f5 BITB extended -**0- */
3634 OP_HANDLER(bitb_ex) {
3635         uint8_t t;
3636         EXTBYTE(t);
3637         B = BIT8_REG(B, t);
3638 }
3639
3640 /* $f6 LDB extended -**0- */
3641 OP_HANDLER(ldb_ex) {
3642         EXTBYTE(B);
3643         B = LOAD8_REG(B);
3644 }
3645
3646 /* $f7 STB extended -**0- */
3647 OP_HANDLER(stb_ex) {
3648         EXTENDED;
3649         STORE8_REG(B);
3650 }
3651
3652 /* $f8 EORB extended -**0- */
3653 OP_HANDLER(eorb_ex) {
3654         uint8_t t;
3655         EXTBYTE(t);
3656         B = EOR8_REG(B, t);
3657 }
3658
3659 /* $f9 ADCB extended ***** */
3660 OP_HANDLER(adcb_ex) {
3661         uint8_t t;
3662         EXTBYTE(t);
3663         B = ADC8_REG(B, t);
3664 }
3665
3666 /* $fA ORB extended -**0- */
3667 OP_HANDLER(orb_ex) {
3668         uint8_t t;
3669         EXTBYTE(t);
3670         B = OR8_REG(B, t);
3671 }
3672
3673 /* $fB ADDB extended ***** */
3674 OP_HANDLER(addb_ex) {
3675         uint8_t t;
3676         EXTBYTE(t);
3677         B = ADD8_REG(B, t);
3678 }
3679
3680 /* $fC LDD extended -**0- */
3681 OP_HANDLER(ldd_ex) {
3682         EXTWORD(pD);
3683         D = LOAD16_REG(D);
3684 }
3685
3686 /* $fD STD extended -**0- */
3687 OP_HANDLER(std_ex) {
3688         EXTENDED;
3689         STORE16_REG(&pD);
3690 }
3691
3692 /* $fE LDU (LDS) extended -**0- */
3693 OP_HANDLER(ldu_ex) {
3694         EXTWORD(pU);
3695         U = LOAD16_REG(U);
3696 }
3697
3698 /* $10fE LDS extended -**0- */
3699 OP_HANDLER(lds_ex) {
3700         EXTWORD(pS);
3701         S = LOAD16_REG(S);
3702         int_state |= MC6809_LDS;
3703 }
3704
3705 /* $fF STU (STS) extended -**0- */
3706 OP_HANDLER(stu_ex) {
3707         EXTENDED;
3708         STORE16_REG(&pU);
3709 }
3710
3711 /* $10fF STS extended -**0- */
3712 OP_HANDLER(sts_ex) {
3713         EXTENDED;
3714         STORE16_REG(&pS);
3715 }
3716
3717
3718 /* $10xx opcodes */
3719 OP_HANDLER(pref10) {
3720         uint8_t ireg2 = ROP_ARG(PCD);
3721         PC++;
3722         switch (ireg2) {
3723                 case 0x20:
3724                         lbra();
3725                         icount -= 5;
3726                         break;  // 20111217
3727                 case 0x21:
3728                         lbrn();
3729                         icount -= 5;
3730                         break;
3731                 case 0x22:
3732                         lbhi();
3733                         icount -= 5;
3734                         break;
3735                 case 0x23:
3736                         lbls();
3737                         icount -= 5;
3738                         break;
3739                 case 0x24:
3740                         lbcc();
3741                         icount -= 5;
3742                         break;
3743                 case 0x25:
3744                         lbcs();
3745                         icount -= 5;
3746                         break;
3747                 case 0x26:
3748                         lbne();
3749                         icount -= 5;
3750                         break;
3751                 case 0x27:
3752                         lbeq();
3753                         icount -= 5;
3754                         break;
3755                 case 0x28:
3756                         lbvc();
3757                         icount -= 5;
3758                         break;
3759                 case 0x29:
3760                         lbvs();
3761                         icount -= 5;
3762                         break;
3763                 case 0x2a:
3764                         lbpl();
3765                         icount -= 5;
3766                         break;
3767                 case 0x2b:
3768                         lbmi();
3769                         icount -= 5;
3770                         break;
3771                 case 0x2c:
3772                         lbge();
3773                         icount -= 5;
3774                         break;
3775                 case 0x2d:
3776                         lblt();
3777                         icount -= 5;
3778                         break;
3779                 case 0x2e:
3780                         lbgt();
3781                         icount -= 5;
3782                         break;
3783                 case 0x2f:
3784                         lble();
3785                         icount -= 5;
3786                         break;
3787                 case 0x3f:
3788                         swi2();
3789                         icount -= 20;
3790                         break;
3791                 case 0x83:
3792                         cmpd_im();
3793                         icount -= 5;
3794                         break;
3795                 case 0x8c:
3796                         cmpy_im();
3797                         icount -= 5;
3798                         break;
3799                 case 0x8d:
3800                         lbsr();
3801                         icount -= 9;
3802                         break;
3803                 case 0x8e:
3804                         ldy_im();
3805                         icount -= 4;
3806                         break;
3807 //    case 0x8f: flag16_im();->cycle=4; break; // 20130417
3808                 case 0x93:
3809                         cmpd_di();
3810                         icount -= 7;
3811                         break;
3812                 case 0x9c:
3813                         cmpy_di();
3814                         icount -= 7;
3815                         break;
3816                 case 0x9e:
3817                         ldy_di();
3818                         icount -= 6;
3819                         break;
3820                 case 0x9f:
3821                         sty_di();
3822                         icount -= 6;
3823                         break;
3824                 case 0xa3:
3825                         cmpd_ix();
3826                         icount -= 7;
3827                         break;
3828                 case 0xac:
3829                         cmpy_ix();
3830                         icount -= 7;
3831                         break;
3832                 case 0xae:
3833                         ldy_ix();
3834                         icount -= 6;
3835                         break;
3836                 case 0xaf:
3837                         sty_ix();
3838                         icount -= 6;
3839                         break;
3840                 case 0xb3:
3841                         cmpd_ex();
3842                         icount -= 8;
3843                         break;
3844                 case 0xbc:
3845                         cmpy_ex();
3846                         icount -= 8;
3847                         break;
3848                 case 0xbe:
3849                         ldy_ex();
3850                         icount -= 7;
3851                         break;
3852                 case 0xbf:
3853                         sty_ex();
3854                         icount -= 7;
3855                         break;
3856                 case 0xce:
3857                         lds_im();
3858                         icount -= 4;
3859                         break;
3860 //    case 0xcf: flag16_im();->cycle=4; break;
3861                 case 0xde:
3862                         lds_di();
3863                         icount -= 6;
3864                         break;
3865                 case 0xdf:
3866                         sts_di();
3867                         icount -= 6;
3868                         break;
3869                 case 0xee:
3870                         lds_ix();
3871                         icount -= 6;
3872                         break;
3873                 case 0xef:
3874                         sts_ix();
3875                         icount -= 6;
3876                         break;
3877                 case 0xfe:
3878                         lds_ex();
3879                         icount -= 7;
3880                         break;
3881                 case 0xff:
3882                         sts_ex();
3883                         icount -= 7;
3884                         break;
3885                 default:
3886                         PC--;
3887                         IIError();
3888                         break;
3889         }
3890 }
3891
3892 /* $11xx opcodes */
3893 OP_HANDLER(pref11) {
3894                 uint8_t ireg2 = ROP_ARG(PCD);
3895                 PC++;
3896                 switch (ireg2) {
3897                         case 0x3f:
3898                                 swi3();
3899                                 icount -= 20;
3900                                 break;
3901
3902                         case 0x83:
3903                                 cmpu_im();
3904                                 icount -= 5;
3905                                 break;
3906                         case 0x8c:
3907                                 cmps_im();
3908                                 icount -= 5;
3909                                 break;
3910
3911                         case 0x93:
3912                                 cmpu_di();
3913                                 icount -= 7;
3914                                 break;
3915                         case 0x9c:
3916                                 cmps_di();
3917                                 icount -= 7;
3918                                 break;
3919
3920                         case 0xa3:
3921                                 cmpu_ix();
3922                                 icount -= 7;
3923                                 break;
3924                         case 0xac:
3925                                 cmps_ix();
3926                                 icount -= 7;
3927                                 break;
3928
3929                         case 0xb3:
3930                                 cmpu_ex();
3931                                 icount -= 8;
3932                                 break;
3933                         case 0xbc:
3934                                 cmps_ex();
3935                                 icount -= 8;
3936                                 break;
3937
3938                         default:
3939                                 PC--;
3940                                 IIError();
3941                                 break;
3942                 }
3943         }
3944
3945 #define STATE_VERSION   5
3946
3947 bool MC6809_BASE::process_state(FILEIO* state_fio, bool loading)
3948 {
3949         if(!state_fio->StateCheckUint32(STATE_VERSION)) {
3950                 return false;
3951         }
3952         if(!state_fio->StateCheckInt32(this_device_id)) {
3953                 return false;
3954         }
3955         state_fio->StateInt32(icount);
3956         state_fio->StateInt32(extra_icount);
3957         state_fio->StateUint32(int_state);
3958
3959         state_fio->StateUint32(pc.d);
3960         state_fio->StateUint32(ppc.d);
3961         state_fio->StateUint32(acc.d);
3962         state_fio->StateUint32(dp.d);
3963         state_fio->StateUint32(u.d);
3964         state_fio->StateUint32(s.d);
3965         state_fio->StateUint32(x.d);
3966         state_fio->StateUint32(y.d);
3967         state_fio->StateUint8(cc);
3968         state_fio->StateUint32(ea.d);
3969
3970         // V2
3971         state_fio->StateBool(req_halt_on);
3972         state_fio->StateBool(req_halt_off);
3973         state_fio->StateBool(busreq);
3974
3975         state_fio->StateUint64(total_icount);
3976         state_fio->StateUint32(waitfactor);
3977         state_fio->StateUint32(waitcount);
3978
3979         // post process
3980         if(loading) {
3981                 prev_total_icount = total_icount;
3982                 // Post process for collecting statistics.
3983                 cycles_tmp_count = total_icount;
3984                 extra_tmp_count = 0;
3985                 insns_count = 0;
3986                 frames_count = 0;
3987                 nmi_count = 0;
3988                 firq_count = 0;
3989                 irq_count = 0;
3990         }
3991         return true;
3992 }
3993
3994