2 Skelton for retropc emulator
4 Author : Takeda.Toshiya
12 #define ADDR_MASK (MEMORY_ADDR_MAX - 1)
13 #define BANK_MASK (MEMORY_BANK_SIZE - 1)
15 void MEMORY::release()
21 uint32 MEMORY::read_data8(uint32 addr)
23 int bank = (addr & ADDR_MASK) >> addr_shift;
25 if(read_table[bank].dev != NULL) {
26 return read_table[bank].dev->read_memory_mapped_io8(addr);
28 return read_table[bank].memory[addr & BANK_MASK];
32 void MEMORY::write_data8(uint32 addr, uint32 data)
34 int bank = (addr & ADDR_MASK) >> addr_shift;
36 if(write_table[bank].dev != NULL) {
37 write_table[bank].dev->write_memory_mapped_io8(addr, data);
39 write_table[bank].memory[addr & BANK_MASK] = data;
43 uint32 MEMORY::read_data16(uint32 addr)
45 int bank = (addr & ADDR_MASK) >> addr_shift;
47 if(read_table[bank].dev != NULL) {
48 return read_table[bank].dev->read_memory_mapped_io16(addr);
50 uint32 val = read_data8(addr);
51 val |= read_data8(addr + 1) << 8;
56 void MEMORY::write_data16(uint32 addr, uint32 data)
58 int bank = (addr & ADDR_MASK) >> addr_shift;
60 if(write_table[bank].dev != NULL) {
61 write_table[bank].dev->write_memory_mapped_io16(addr, data);
63 write_data8(addr, data & 0xff);
64 write_data8(addr + 1, (data >> 8) & 0xff);
68 uint32 MEMORY::read_data32(uint32 addr)
70 int bank = (addr & ADDR_MASK) >> addr_shift;
72 if(read_table[bank].dev != NULL) {
73 return read_table[bank].dev->read_memory_mapped_io32(addr);
75 uint32 val = read_data16(addr);
76 val |= read_data16(addr + 2) << 16;
81 void MEMORY::write_data32(uint32 addr, uint32 data)
83 int bank = (addr & ADDR_MASK) >> addr_shift;
85 if(write_table[bank].dev != NULL) {
86 write_table[bank].dev->write_memory_mapped_io32(addr, data);
88 write_data16(addr, data & 0xffff);
89 write_data16(addr + 2, (data >> 16) & 0xffff);
93 uint32 MEMORY::read_data8w(uint32 addr, int* wait)
95 int bank = (addr & ADDR_MASK) >> addr_shift;
97 *wait = read_table[bank].wait;
98 if(read_table[bank].dev != NULL) {
99 return read_table[bank].dev->read_memory_mapped_io8(addr);
101 return read_table[bank].memory[addr & BANK_MASK];
105 void MEMORY::write_data8w(uint32 addr, uint32 data, int* wait)
107 int bank = (addr & ADDR_MASK) >> addr_shift;
109 *wait = write_table[bank].wait;
110 if(write_table[bank].dev != NULL) {
111 write_table[bank].dev->write_memory_mapped_io8(addr, data);
113 write_table[bank].memory[addr & BANK_MASK] = data;
117 uint32 MEMORY::read_data16w(uint32 addr, int* wait)
120 uint32 val = read_data8w(addr, &wait_l);
121 val |= read_data8w(addr + 1, &wait_h) << 8;
122 *wait = wait_l + wait_h;
126 void MEMORY::write_data16w(uint32 addr, uint32 data, int* wait)
129 write_data8w(addr, data & 0xff, &wait_l);
130 write_data8w(addr + 1, (data >> 8) & 0xff, &wait_h);
131 *wait = wait_l + wait_h;
134 uint32 MEMORY::read_data32w(uint32 addr, int* wait)
137 uint32 val = read_data16w(addr, &wait_l);
138 val |= read_data16w(addr + 2, &wait_h) << 16;
139 *wait = wait_l + wait_h;
143 void MEMORY::write_data32w(uint32 addr, uint32 data, int* wait)
146 write_data16w(addr, data & 0xffff, &wait_l);
147 write_data16w(addr + 2, (data >> 16) & 0xffff, &wait_h);
148 *wait = wait_l + wait_h;
153 void MEMORY::set_memory_r(uint32 start, uint32 end, uint8 *memory)
155 uint32 start_bank = start >> addr_shift;
156 uint32 end_bank = end >> addr_shift;
158 for(uint32 i = start_bank; i <= end_bank; i++) {
159 read_table[i].dev = NULL;
160 read_table[i].memory = memory + MEMORY_BANK_SIZE * (i - start_bank);
164 void MEMORY::set_memory_w(uint32 start, uint32 end, uint8 *memory)
166 uint32 start_bank = start >> addr_shift;
167 uint32 end_bank = end >> addr_shift;
169 for(uint32 i = start_bank; i <= end_bank; i++) {
170 write_table[i].dev = NULL;
171 write_table[i].memory = memory + MEMORY_BANK_SIZE * (i - start_bank);
175 void MEMORY::set_memory_mapped_io_r(uint32 start, uint32 end, DEVICE *device)
177 uint32 start_bank = start >> addr_shift;
178 uint32 end_bank = end >> addr_shift;
180 for(uint32 i = start_bank; i <= end_bank; i++) {
181 read_table[i].dev = device;
185 void MEMORY::set_memory_mapped_io_w(uint32 start, uint32 end, DEVICE *device)
187 uint32 start_bank = start >> addr_shift;
188 uint32 end_bank = end >> addr_shift;
190 for(uint32 i = start_bank; i <= end_bank; i++) {
191 write_table[i].dev = device;
195 void MEMORY::set_wait_r(uint32 start, uint32 end, int wait)
197 uint32 start_bank = start >> addr_shift;
198 uint32 end_bank = end >> addr_shift;
200 for(uint32 i = start_bank; i <= end_bank; i++) {
201 read_table[i].wait = wait;
205 void MEMORY::set_wait_w(uint32 start, uint32 end, int wait)
207 uint32 start_bank = start >> addr_shift;
208 uint32 end_bank = end >> addr_shift;
210 for(uint32 i = start_bank; i <= end_bank; i++) {
211 write_table[i].wait = wait;
215 void MEMORY::unset_memory_r(uint32 start, uint32 end)
217 uint32 start_bank = start >> addr_shift;
218 uint32 end_bank = end >> addr_shift;
220 for(uint32 i = start_bank; i <= end_bank; i++) {
221 read_table[i].dev = NULL;
222 read_table[i].memory = read_dummy;
226 void MEMORY::unset_memory_w(uint32 start, uint32 end)
228 uint32 start_bank = start >> addr_shift;
229 uint32 end_bank = end >> addr_shift;
231 for(uint32 i = start_bank; i <= end_bank; i++) {
232 write_table[i].dev = NULL;
233 write_table[i].memory = write_dummy;
239 int MEMORY::read_bios(_TCHAR *file_name, uint8 *buffer, int size)
241 FILEIO* fio = new FILEIO();
244 if(fio->Fopen(emu->bios_path(file_name), FILEIO_READ_BINARY)) {
245 fio->Fread(buffer, size, 1);
246 length = fio->Ftell();
253 bool MEMORY::write_bios(_TCHAR *file_name, uint8 *buffer, int size)
255 FILEIO* fio = new FILEIO();
258 if(fio->Fopen(emu->bios_path(file_name), FILEIO_WRITE_BINARY)) {
259 fio->Fwrite(buffer, size, 1);
267 bool MEMORY::read_image(_TCHAR *file_path, uint8 *buffer, int size)
269 FILEIO* fio = new FILEIO();
272 if(fio->Fopen(file_path, FILEIO_READ_BINARY)) {
273 fio->Fread(buffer, size, 1);
281 bool MEMORY::write_image(_TCHAR* file_path, uint8* buffer, int size)
283 FILEIO* fio = new FILEIO();
286 if(fio->Fopen(file_path, FILEIO_WRITE_BINARY)) {
287 fio->Fwrite(buffer, size, 1);