1 /****************************************************************************
3 emu2212.c -- S.C.C. emulator by Mitsutaka Okazaki 2001
5 2001 09-30 : Version 1.00
6 2001 10-03 : Version 1.01 -- Added SCC_set_quality().
7 2002 02-14 : Version 1.10 -- Added SCC_writeReg(), SCC_set_type().
9 2002 02-17 : Version 1.11 -- Fixed SCC_write().
10 2002 03-02 : Version 1.12 -- Removed SCC_init & SCC_close.
11 2003 09-19 : Version 1.13 -- Added SCC_setMask() and SCC_toggleMask()
12 2004 10-21 : Version 1.14 -- Fixed the problem where SCC+ is disabled.
13 2015 12-13 : Version 1.15 -- Changed own integer types to C99 stdint.h types.
15 Registar map for SCC_writeReg()
17 $00-1F : WaveTable CH.A
18 $20-3F : WaveTable CH.B
19 $40-5F : WaveTable CH.C
20 $60-7F : WaveTable CH.D&E(SCC), CH.D(SCC+)
21 $80-9F : WaveTable CH.E
40 $E0 : Bit0 = 0:SCC, 1:SCC+
44 *****************************************************************************/
49 #include "../../types/util_sound.h"
58 internal_refresh (SCC * scc)
62 scc->base_incr = 2 << GETA_BITS;
63 scc->realstep = (uint32_t) ((1 << 31) / scc->rate);
64 scc->sccstep = (uint32_t) ((1 << 31) / (scc->clk / 2));
69 scc->base_incr = (uint32_t) ((double) scc->clk * (1 << GETA_BITS) / scc->rate);
74 SCC_setMask (SCC *scc, uint32_t mask)
86 SCC_toggleMask (SCC *scc, uint32_t mask)
98 SCC_set_quality (SCC * scc, uint32_t q)
101 internal_refresh (scc);
105 SCC_set_rate (SCC * scc, uint32_t r)
107 scc->rate = r ? r : 44100;
108 internal_refresh (scc);
112 SCC_new (uint32_t c, uint32_t r)
116 scc = (SCC *) malloc (sizeof (SCC));
119 memset(scc, 0, sizeof (SCC));
122 scc->rate = r ? r : 44100;
123 SCC_set_quality (scc, 0);
124 scc->type = SCC_ENHANCED;
129 SCC_reset (SCC * scc)
138 scc->base_adr = 0x9000;
140 for (i = 0; i < 5; i++)
142 for (j = 0; j < 5; j++)
152 memset(scc->reg,0,0x100-0xC0);
156 scc->ch_enable = 0xff;
157 scc->ch_enable_next = 0xff;
171 SCC_delete (SCC * scc)
177 static inline int16_t
183 for (i = 0; i < 5; i++)
185 scc->count[i] = (scc->count[i] + scc->incr[i]);
187 if (scc->count[i] & (1 << (GETA_BITS + 5)))
189 scc->count[i] &= ((1 << (GETA_BITS + 5)) - 1);
190 scc->offset[i] = (scc->offset[i] + 31) & scc->rotate[i];
191 scc->ch_enable &= ~(1 << i);
192 scc->ch_enable |= scc->ch_enable_next & (1 << i);
195 if (scc->ch_enable & (1 << i))
197 scc->phase[i] = ((scc->count[i] >> (GETA_BITS)) + scc->offset[i]) & 0x1F;
198 if(!(scc->mask&SCC_MASK_CH(i)))
199 mix += ((((int8_t) (scc->wave[i][scc->phase[i]]) * (int8_t) scc->volume[i]))) >> 4;
203 return (int16_t) (mix << 4);
212 while (scc->realstep > scc->scctime)
214 scc->scctime += scc->sccstep;
215 scc->prev = scc->next;
216 scc->next = calc (scc);
219 scc->scctime -= scc->realstep;
220 scc->out = (int16_t) (((double) scc->next * (scc->sccstep - scc->scctime) + (double) scc->prev * scc->scctime) / scc->sccstep);
222 return (int16_t) (scc->out);
226 SCC_readReg (SCC * scc, uint32_t adr)
229 return scc->wave[adr >> 5][adr & 0x1f];
230 else if( 0xC0 < adr && adr < 0xF0 )
231 return scc->reg[adr-0xC0];
237 SCC_writeReg (SCC * scc, uint32_t adr, uint32_t val)
246 ch = (adr & 0xF0) >> 5;
247 if (!scc->rotate[ch])
249 scc->wave[ch][adr & 0x1F] = (int8_t) val;
250 if (scc->mode == 0 && ch == 3)
251 scc->wave[4][adr & 0x1F] = (int8_t) val;
254 else if (0xC0 <= adr && adr <= 0xC9)
256 scc->reg[adr-0xC0] = val;
257 ch = (adr & 0x0F) >> 1;
259 scc->freq[ch] = ((val & 0xF) << 8) | (scc->freq[ch] & 0xFF);
261 scc->freq[ch] = (scc->freq[ch] & 0xF00) | (val & 0xFF);
265 freq = scc->freq[ch];
273 scc->incr[ch] = scc->base_incr / (freq + 1);
275 else if (0xD0 <= adr && adr <= 0xD4)
277 scc->reg[adr-0xC0] = val;
278 scc->volume[adr & 0x0F] = (uint8_t) (val & 0xF);
280 else if (adr == 0xE0)
282 scc->reg[adr-0xC0] = val;
283 scc->mode = (uint8_t) val & 1;
285 else if (adr == 0xE1)
287 scc->reg[adr-0xC0] = val;
288 scc->ch_enable_next = (uint8_t) val & 0x1F;
290 else if (adr == 0xE2)
292 scc->reg[adr-0xC0] = val;
293 scc->cycle_4bit = val & 1;
294 scc->cycle_8bit = val & 2;
295 scc->refresh = val & 32;
297 for (ch = 0; ch < 5; ch++)
298 scc->rotate[ch] = 0x1F;
300 for (ch = 0; ch < 5; ch++)
303 scc->rotate[3] = scc->rotate[4] = 0x1F;
310 write_standard (SCC * scc, uint32_t adr, uint32_t val)
314 if (adr < 0x80) /* wave */
316 SCC_writeReg (scc, adr, val);
318 else if (adr < 0x8A) /* freq */
320 SCC_writeReg (scc, adr + 0xC0 - 0x80, val);
322 else if (adr < 0x8F) /* volume */
324 SCC_writeReg (scc, adr + 0xD0 - 0x8A, val);
326 else if (adr == 0x8F) /* ch enable */
328 SCC_writeReg (scc, 0xE1, val);
330 else if (0xE0 <= adr) /* flags */
332 SCC_writeReg (scc, 0xE2, val);
337 write_enhanced (SCC * scc, uint32_t adr, uint32_t val)
341 if (adr < 0xA0) /* wave */
343 SCC_writeReg (scc, adr, val);
345 else if (adr < 0xAA) /* freq */
347 SCC_writeReg (scc, adr + 0xC0 - 0xA0, val);
349 else if (adr < 0xAF) /* volume */
351 SCC_writeReg (scc, adr + 0xD0 - 0xAA, val);
353 else if (adr == 0xAF) /* ch enable */
355 SCC_writeReg (scc, 0xE1, val);
357 else if (0xC0 <= adr && adr <= 0xDF) /* flags */
359 SCC_writeReg (scc, 0xE2, val);
363 static inline uint32_t
364 read_enhanced (SCC * scc, uint32_t adr)
368 return SCC_readReg (scc, adr);
370 return SCC_readReg (scc, adr + 0xC0 - 0xA0);
372 return SCC_readReg (scc, adr + 0xD0 - 0xAA);
373 else if (adr == 0xAF)
374 return SCC_readReg (scc, 0xE1);
375 else if (0xC0 <= adr && adr <= 0xDF)
376 return SCC_readReg (scc, 0xE2);
381 static inline uint32_t
382 read_standard (SCC * scc, uint32_t adr)
386 return SCC_readReg (scc, adr);
387 else if (0xA0<=adr&&adr<=0xBF)
388 return SCC_readReg (scc, 0x80+(adr&0x1F));
390 return SCC_readReg (scc, adr + 0xC0 - 0x80);
392 return SCC_readReg (scc, adr + 0xD0 - 0x8A);
393 else if (adr == 0x8F)
394 return SCC_readReg (scc, 0xE1);
395 else if (0xE0 <= adr)
396 return SCC_readReg (scc, 0xE2);
401 SCC_read (SCC * scc, uint32_t adr)
403 if( scc->type == SCC_ENHANCED && (adr&0xFFFE) == 0xBFFE )
404 return (scc->base_adr>>8)&0x20;
406 if( adr < scc->base_adr ) return 0;
407 adr -= scc->base_adr;
411 if(scc->mode) return 0x80; else return 0x3F;
414 if(!scc->active||adr<0x800||0x8FF<adr) return 0;
419 return read_standard (scc, adr);
423 return read_standard (scc, adr);
425 return read_enhanced (scc, adr);
435 SCC_write (SCC * scc, uint32_t adr, uint32_t val)
439 if( scc->type == SCC_ENHANCED && (adr&0xFFFE) == 0xBFFE )
441 scc->base_adr = 0x9000 | ((val&0x20)<<8);
445 if( adr < scc->base_adr ) return;
446 adr -= scc->base_adr;
455 else if( val&0x80 && scc->type == SCC_ENHANCED)
468 if(!scc->active||adr<0x800||0x8FF<adr) return;
473 write_standard (scc, adr, val);
477 write_enhanced (scc, adr, val);
479 write_standard (scc, adr, val);
488 SCC_set_type (SCC * scc, uint32_t type)
496 Common Source Code Project
497 MSX Series (experimental)
507 SCC::SCC(VM_TEMPLATE* parent_vm, EMU_TEMPLATE* parent_emu) : DEVICE(parent_vm, parent_emu)
509 emu2212 = SCC_new(3579545, 48000);
510 volume_l = volume_r = 1024;
511 set_device_name(_T("SCC"));
514 void SCC::write_data8(uint32_t addr, uint32_t data)
516 SCC_write(emu2212, addr, data);
519 uint32_t SCC::read_data8(uint32_t addr)
521 return SCC_read(emu2212, addr);
524 void SCC::initialize()
526 SCC_set_type(emu2212, SCC_STANDARD);
539 void SCC::mix(int32_t* buffer, int cnt)
542 for(i=0; i<cnt; i++) {
543 int16_t c = (SCC_calc(emu2212)) << 1;
544 buffer[i*2 ] += apply_volume(c, volume_l); // L
545 buffer[i*2+1] += apply_volume(c, volume_r); // R
549 void SCC::initialize_sound(int rate, int clock, int samples)
552 emu2212 = SCC_new(clock, rate);
557 void SCC::set_volume(int ch, int decibel_l, int decibel_r)
559 volume_l = decibel_to_volume(decibel_l);
560 volume_r = decibel_to_volume(decibel_r);
563 #define STATE_VERSION 1
565 bool SCC::process_state(FILEIO* state_fio, bool loading)
567 if(!state_fio->StateCheckUint32(STATE_VERSION)) {
570 if(!state_fio->StateCheckInt32(this_device_id)) {
573 save_load_state(state_fio, !loading);
578 void SCC::decl_state_scc()
580 DECL_STATE_ENTRY_UINT32((emu2212->clk));
581 DECL_STATE_ENTRY_UINT32((emu2212->rate));
582 DECL_STATE_ENTRY_UINT32((emu2212->base_incr));
583 DECL_STATE_ENTRY_UINT32((emu2212->quality));
585 DECL_STATE_ENTRY_INT32((emu2212->out));
586 DECL_STATE_ENTRY_INT32((emu2212->prev));
587 DECL_STATE_ENTRY_INT32((emu2212->next));
588 DECL_STATE_ENTRY_UINT32((emu2212->type));
589 DECL_STATE_ENTRY_UINT32((emu2212->mode));
590 DECL_STATE_ENTRY_UINT32((emu2212->active));
591 DECL_STATE_ENTRY_UINT32((emu2212->base_adr));
592 DECL_STATE_ENTRY_UINT32((emu2212->mask));
594 DECL_STATE_ENTRY_UINT32((emu2212->realstep));
595 DECL_STATE_ENTRY_UINT32((emu2212->scctime));
596 DECL_STATE_ENTRY_UINT32((emu2212->sccstep));
598 DECL_STATE_ENTRY_1D_ARRAY(emu2212->incr, 5);
600 DECL_STATE_ENTRY_2D_ARRAY(emu2212->wave, 5, 32);
602 DECL_STATE_ENTRY_1D_ARRAY(emu2212->count, 5);
603 DECL_STATE_ENTRY_1D_ARRAY(emu2212->freq, 5);
604 DECL_STATE_ENTRY_1D_ARRAY(emu2212->phase, 5);
605 DECL_STATE_ENTRY_1D_ARRAY(emu2212->volume, 5);
606 DECL_STATE_ENTRY_1D_ARRAY(emu2212->offset, 5);
607 DECL_STATE_ENTRY_1D_ARRAY(emu2212->reg, 0x100-0xC0);
609 DECL_STATE_ENTRY_INT32((emu2212->ch_enable));
610 DECL_STATE_ENTRY_INT32((emu2212->ch_enable_next));
612 DECL_STATE_ENTRY_INT32((emu2212->cycle_4bit));
613 DECL_STATE_ENTRY_INT32((emu2212->cycle_8bit));
614 DECL_STATE_ENTRY_INT32((emu2212->refresh));
615 DECL_STATE_ENTRY_1D_ARRAY(emu2212->rotate, 5) ;
619 // ToDo: Dedicate endianness. 20181017 K.O.
620 void SCC::save_load_state(FILEIO* state_fio, bool is_save)
622 #define STATE_ENTRY(x) {&(x), sizeof(x)}
627 t_state_table state_table[] = {
628 STATE_ENTRY(*emu2212),
632 for(i=0; state_table[i].size>0; i++) {
634 state_fio->Fwrite(state_table[i].address, state_table[i].size, 1);
637 state_fio->Fread(state_table[i].address, state_table[i].size, 1);