source/src/vm/upd71071.cpp

   1 /*
   2         Skelton for retropc emulator
   3
   4         Author : Takeda.Toshiya
   5         Date   : 2007.08.14 -
   6
   7         [ uPD71071 ]
   8 */
   9
  10 #include "upd71071.h"
  11 #include "debugger.h"
  12
  13 void UPD71071::initialize()
  14 {
  15         DEVICE::initialize();
  16         _SINGLE_MODE_DMA = osd->check_feature(_T("SINGLE_MODE_DMA"));
  17         for(int i = 0; i < 4; i++) {
  18                 dma[i].areg = dma[i].bareg = 0;
  19                 dma[i].creg = dma[i].bcreg = 0;
  20         }
  21         if(__USE_DEBUGGER) {
  22                 if(d_debugger != NULL) {
  23                         d_debugger->set_device_name(_T("Debugger (uPD71071 DMAC)"));
  24                         d_debugger->set_context_mem(this);
  25                         d_debugger->set_context_io(vm->dummy);
  26                 }
  27         }
  28         for(int i = 0; i < 4; i++) {
  29                 inputs_ube[i] = false; // This is input, maybe not initialize at reset().
  30         }
  31 }
  32
  33 void UPD71071::reset()
  34 {
  35         for(int i = 0; i < 4; i++) {
  36                 dma[i].mode = 0x04;
  37                 dma[i].is_16bit = false;
  38                 dma[i].end = false;
  39                 dma[i].endreq = false;
  40                 reset_ube(i);
  41         }
  42         b16 = selch = base = 0;
  43         cmd = tmp = 0;
  44         req = sreq = 0;
  45         mask = 0x0f;
  46 //      mask = 0x00;
  47         running = false;
  48         reset_all_tc();
  49 }
  50 #if 0
  51 void UPD71071::write_io16(uint32_t addr, uint32_t data)
  52 {
  53         pair32_t _d, _bd;
  54 //      if(b16 != 0) {
  55                 switch(addr & 0x0e) {
  56                 case 0x02:
  57                         if(base == 0) {
  58                                 dma[selch].creg = data & 0xffff;
  59                         }
  60                         dma[selch].bcreg = data & 0xffff;
  61                         return;
  62                         break;
  63                 case 0x04:
  64                         if(base == 0) {
  65                                 _d.d = dma[selch].areg;
  66                                 _d.w.l = data;
  67                                 dma[selch].areg = _d.d;
  68                         }
  69                         _d.d = dma[selch].bareg;
  70                         _d.w.l = data;
  71                         dma[selch].bareg = _d.d;
  72                         break;
  73                 case 0x06:
  74                         if(base == 0) {
  75                                 _d.d = dma[selch].areg;
  76                                 _d.b.h2 = data;
  77                                 dma[selch].areg = _d.d;
  78                         }
  79                         _d.d = dma[selch].bareg;
  80                         _d.b.h2 = data;
  81                         dma[selch].bareg = _d.d;
  82                         break;
  83                 case 0x08:
  84                         cmd = data & 0xffff;
  85                         break;
  86                 default:
  87                         write_io8(addr & 0x0e, data);
  88 //                      write_io8(addr, data);
  89                         break;
  90                 }
  91 //      } else {
  92 //              write_io8(addr, data);
  93 ////            write_io8((addr & 0x0e) + 0, data & 0xff);
  94 ////            write_io8((addr & 0x0e) + 1, (data >> 8) & 0xff);
  95 //      }
  96 }
  97 #endif
  98
  99 void UPD71071::write_io8(uint32_t addr, uint32_t data)
 100 {
 101         pair32_t _d;
 102         uint8_t ad[4];
 103         switch(addr & 0x0f) {
 104         case 0x00:
 105                 b16 = data & 2;
 106                 if(data & 1) {
 107                         // dma reset
 108 //                      b16 = 0;
 109                         for(int i = 0; i < 4; i++) {
 110                                 dma[i].mode = 0x04;
 111                                 dma[i].is_16bit = false;
 112                                 dma[i].end = false;
 113                                 dma[i].endreq = false;
 114                                 reset_ube(i);
 115                         }
 116                         selch = base = 0;
 117                         cmd = tmp = 0;
 118                         sreq = 0;
 119                         mask = 0x0f;
 120 //                      mask = 0x00;
 121                         reset_all_tc();
 122                 }
 123                 break;
 124         case 0x01:
 125                 selch = data & 3;
 126                 base = data & 4;
 127                 break;
 128         case 0x02:
 129         case 0x03:
 130                 dma[selch].bcreg = manipulate_a_byte_from_word_le(dma[selch].bcreg, (addr & 0x0f) - 2, data);
 131                 if(base == 0) {
 132                         dma[selch].creg = manipulate_a_byte_from_word_le(dma[selch].creg, (addr & 0x0f) - 2, data);
 133                 }
 134                 dma[selch].end = false; // OK?
 135                 dma[selch].endreq = false; // OK?
 136                 reset_tc(selch);
 137                 break;
 138         case 0x04:
 139         case 0x05:
 140         case 0x06:
 141                 dma[selch].bareg = manipulate_a_byte_from_dword_le(dma[selch].bareg, (addr & 0x0f) - 4, data);
 142                 if(base == 0) {
 143                         dma[selch].areg = manipulate_a_byte_from_dword_le(dma[selch].areg, (addr & 0x0f) - 4, data);
 144                 }
 145                 break;
 146         case 0x08:
 147                 cmd = (cmd & 0xff00) | (data & 0x00ff);
 148                 break;
 149         case 0x09:
 150                 cmd = (cmd & 0xff) | ((data & 0x00ff) << 8);
 151                 break;
 152         case 0x0a:
 153                 dma[selch].mode = data;
 154                 //dma[selch].is_16bit = ((data & 1) != 0) ? true : false;
 155                 if((data & 0x04) == 0) {
 156                         dma[selch].end = false;
 157                         dma[selch].endreq = false;
 158                 }
 159                 set_ube(selch);
 160                 break;
 161         case 0x0e:
 162                 sreq = data;
 163                 for(int _ch = 0; _ch < 4; _ch++) {
 164                         if((sreq & (1 << _ch)) != 0) {
 165                                 //if((dma[_ch].mode & 0xc0) == 0x40) { // Single
 166                                 do_dma_per_channel(_ch);
 167                                 //}
 168                         }
 169                 }
 170                 break;
 171         case 0x0f:
 172                 mask = data;
 173                 for(int _ch = 0; _ch < 4; _ch++) {
 174                         if(((sreq | req) & (1 << _ch)) != 0) {
 175                                 if((mask & (1 << _ch)) == 0) {
 176                                         do_dma_per_channel(_ch);
 177                                 }
 178                         }
 179                 }
 180                 set_ube(selch);
 181                 break;
 182         }
 183 }
 184 #if 0
 185 uint32_t UPD71071::read_io16(uint32_t addr)
 186 {
 187 //      if(b16 != 0) {
 188         switch(addr & 0x0e) {
 189         case 0x02:
 190                 if(base == 0) {
 191                         return (dma[selch].creg & 0xffff);
 192                 } else {
 193                         return (dma[selch].bcreg & 0xffff);
 194                 }
 195                 break;
 196         case 0x04:
 197                 if(base == 0) {
 198                         return (dma[selch].areg & 0xffff);
 199                 } else {
 200                         return (dma[selch].bareg & 0xffff);
 201                 }
 202                 break;
 203         case 0x06:
 204                 if(base == 0) {
 205                         return ((dma[selch].areg >> 16) & 0xff);
 206                 } else {
 207                         return ((dma[selch].bareg >> 16) & 0xff);
 208                 }
 209                 break;
 210         case 0x08:
 211                 return (uint32_t)(cmd & 0xffff);
 212                 break;
 213         default:
 214 //                      return read_io8(addr & 0x0e);
 215                 break;
 216         }
 217         return read_io8(addr);
 218 }
 219 #endif
 220 uint32_t UPD71071::read_io8(uint32_t addr)
 221 {
 222         uint32_t val;
 223         pair32_t _d;
 224 //      _d.d = 0;
 225 //      _bd.d = 0;
 226         switch(addr & 0x0f) {
 227         case 0x00:
 228                 return b16;
 229         case 0x01:
 230                 // Q: Should be right BIT shift of BASE bit? 20200315 K.O
 231                 return ((base != 0) ? 0x10 : 0x00) | (1 << selch);
 232         case 0x02:
 233                 if(base != 0) {
 234                         return dma[selch].bcreg & 0xff;
 235                 } else {
 236                         return dma[selch].creg & 0xff;
 237                 }
 238         case 0x03:
 239                 if(base != 0) {
 240                         return (dma[selch].bcreg >> 8) & 0xff;
 241                 } else {
 242                         return (dma[selch].creg >> 8) & 0xff;
 243                 }
 244         case 0x04:
 245         case 0x05:
 246         case 0x06:
 247                 if(base == 0) {
 248                         _d.d = dma[selch].areg;
 249                 } else {
 250                         _d.d = dma[selch].bareg;
 251                 }
 252                 switch(addr & 0x0f) {
 253                 case 4:
 254                         return _d.b.l;
 255                         break;
 256                 case 5:
 257                         return _d.b.h;
 258                         break;
 259                 case 6:
 260                         return _d.b.h2;
 261                         break;
 262                 }
 263                 return 0x00;
 264                 break;
 265         case 0x08:
 266                 return cmd & 0xff;
 267         case 0x09:
 268                 return (cmd >> 8) & 0xff;
 269         case 0x0a:
 270                 return dma[selch].mode;
 271         case 0x0b:
 272                 val = (req << 4) | tc;
 273                 reset_all_tc();
 274                 return val;
 275         case 0x0c:
 276                 return tmp & 0xff;
 277         case 0x0d:
 278                 return (tmp >> 8) & 0xff;
 279         case 0x0e:
 280                 return sreq;
 281         case 0x0f:
 282                 return mask;
 283         }
 284         return 0xff;
 285 }
 286
 287 void UPD71071::write_signal(int id, uint32_t data, uint32_t _mask)
 288 {
 289         int ch = id & 3;
 290         uint8_t bit = 1 << ch;
 291         if((id >= SIG_UPD71071_CH0) && (id <= SIG_UPD71071_CH3)) {
 292 //              out_debug_log(_T("DRQ#%d %s"), ch, ((data & _mask) != 0) ? _T("ON ") : _T("OFF"));
 293                 if(data & _mask) {
 294                         if(!(req & bit)) {
 295                                 req |= bit;
 296                                 if(!(_SINGLE_MODE_DMA)) {
 297                                         if((mask & (1 << ch)) == 0) { // MASK register MASKS DRQ.20200918 K.O
 298                                                 // Without #define SINGLE_MODE_DMA ,
 299                                                 // DMA trasfer is triggerd by SIGNAL or writing I/O 0Eh.
 300                                                 do_dma_per_channel(ch);
 301                                                 req &= ~bit;
 302                                         }
 303                                 }
 304                         }
 305                 } else {
 306                         req &= ~bit;
 307                 }
 308         } else if((id >= SIG_UPD71071_UBE_CH0) && (id <= SIG_UPD71071_UBE_CH3)) {
 309                 inputs_ube[ch] = ((data & _mask) != 0) ? true : false;
 310         } else if((id >= SIG_UPD71071_EOT_CH0) && (id <= SIG_UPD71071_EOT_CH3)) {
 311                 if((cmd & 0x04) == 0) {
 312                         switch(dma[ch].mode & 0xc0) {
 313                         case 0x00: // Demand
 314                                 dma[ch].endreq = true;
 315                                 break;
 316                         case 0x40: // Single -> Noop
 317                                 break;
 318                         case 0x80: // Demand
 319                                 dma[ch].endreq = true;
 320                                 break;
 321                         default:
 322                                 break;
 323                         }
 324                 }
 325         }
 326 }
 327
 328 uint32_t UPD71071::read_signal(int ch)
 329 {
 330         if((ch >= (SIG_UPD71071_IS_TRANSFERING + 0)) && (ch < (SIG_UPD71071_IS_TRANSFERING + 4))) {
 331                 int _nch = ch - SIG_UPD71071_IS_TRANSFERING;
 332                 if((cmd & 0x04) != 0) return 0x00; // Not transfering
 333                 if(dma[_nch].creg == 0xffffffff) return 0x00; //
 334                 return 0xffffffff;
 335         } else if((ch >= (SIG_UPD71071_IS_16BITS_TRANSFER + 0)) && (ch < (SIG_UPD71071_IS_16BITS_TRANSFER + 4))) {
 336                 int _nch = ch - SIG_UPD71071_IS_16BITS_TRANSFER;
 337                 bool stat = stats_ube[_nch];
 338                 return (stat) ? 0xffffffff : 0;
 339         } else if((ch >= SIG_UPD71071_UBE_CH0) && (ch <= SIG_UPD71071_UBE_CH3)) {
 340                 return (inputs_ube[ch - SIG_UPD71071_UBE_CH0]) ? 0xffffffff : 0x00000000;
 341         } else if((ch >= (SIG_UPD71071_CREG + 0)) && (ch < (SIG_UPD71071_CREG + 4))) {
 342                 return dma[ch - SIG_UPD71071_CREG].creg;
 343         } else if((ch >= (SIG_UPD71071_BCREG + 0)) && (ch < (SIG_UPD71071_BCREG + 4))) {
 344                 return dma[ch - SIG_UPD71071_BCREG].creg;
 345         } else if((ch >= (SIG_UPD71071_AREG + 0)) && (ch < (SIG_UPD71071_AREG + 4))) {
 346                 return dma[ch - SIG_UPD71071_AREG].creg;
 347         } else if((ch >= (SIG_UPD71071_BAREG + 0)) && (ch < (SIG_UPD71071_BAREG + 4))) {
 348                 return dma[ch - SIG_UPD71071_BAREG].creg;
 349         }
 350         return 0;
 351 }
 352
 353 void UPD71071::write_via_debugger_data8w(uint32_t addr, uint32_t data, int *wait)
 354 {
 355         d_mem->write_dma_data8w(addr, data, wait);
 356 }
 357
 358 uint32_t UPD71071::read_via_debugger_data8w(uint32_t addr, int *wait)
 359 {
 360         return d_mem->read_dma_data8w(addr, wait);
 361 }
 362
 363 void UPD71071::write_via_debugger_data16w(uint32_t addr, uint32_t data, int *wait)
 364 {
 365         d_mem->write_dma_data16w(addr, data, wait);
 366 }
 367
 368 uint32_t UPD71071::read_via_debugger_data16w(uint32_t addr, int *wait)
 369 {
 370         return d_mem->read_dma_data16w(addr, wait);
 371 }
 372
 373 // note: if SINGLE_MODE_DMA is defined, do_dma() is called in every machine cycle
 374
 375
 376 void UPD71071::do_dma_verify_8bit(int c, bool extended, bool compressed, int& wait)
 377 {
 378         bool __debugging = false;
 379         int wait_1 = 0, wait_2 = 0;
 380         __LIKELY_IF((__USE_DEBUGGER) && (d_debugger != NULL)) {
 381                 __debugging = d_debugger->now_device_debugging;
 382         }
 383         // verify
 384         uint32_t val = dma[c].dev->read_dma_io8w(0, &wait_1);
 385         reset_ube(c);
 386
 387         uint32_t val2;
 388         __UNLIKELY_IF(__debugging) {
 389                 val2 = d_debugger->read_via_debugger_data8w(dma[c].areg, &wait_2);
 390         } else {
 391                 val2 = read_via_debugger_data8w(dma[c].areg,  &wait_2);
 392         }
 393
 394         // ToDo: Compare val1 and val2.
 395         // update temporary register
 396         tmp = (tmp >> 8) | (val2 << 8);
 397
 398         wait += compressed ? 5 : 7;
 399         if(extended) {
 400                 wait += wait_1 + wait_2;
 401         }
 402 }
 403
 404 void UPD71071::do_dma_dev_to_mem_8bit(int c, bool extended, bool compressed, int& wait)
 405 {
 406         reset_ube(c);
 407         // io -> memory
 408         bool __debugging = false;
 409         int wait_r = 0, wait_w = 0;
 410         __LIKELY_IF((__USE_DEBUGGER) && (d_debugger != NULL)) {
 411                 __debugging = d_debugger->now_device_debugging;
 412         }
 413         uint32_t val;
 414         //reset_ube(c);
 415         val = dma[c].dev->read_dma_io8w(0, &wait_r);
 416         // update temporary register
 417         tmp = (tmp >> 8) | (val << 8);
 418
 419         __UNLIKELY_IF(__debugging) {
 420                 d_debugger->write_via_debugger_data8w(dma[c].areg, val, &wait_w);
 421         } else {
 422                 write_via_debugger_data8w(dma[c].areg,  val, &wait_w);
 423         }
 424
 425         wait += compressed ? 5 : 7;
 426         if(extended) {
 427                 wait += wait_r + wait_w;
 428         }
 429 }
 430
 431 void UPD71071::do_dma_mem_to_dev_8bit(int c, bool extended, bool compressed, int& wait)
 432 {
 433         // memory -> io
 434         bool __debugging = false;
 435         int wait_r = 0, wait_w = 0;
 436         __LIKELY_IF((__USE_DEBUGGER) && (d_debugger != NULL)) {
 437                 __debugging = d_debugger->now_device_debugging;
 438         }
 439         uint32_t val;
 440         reset_ube(c);
 441         __UNLIKELY_IF(__debugging) {
 442                 val = d_debugger->read_via_debugger_data8w(dma[c].areg, &wait_r);
 443         } else {
 444                 val = read_via_debugger_data8w(dma[c].areg, &wait_r);
 445         }
 446         // update temporary register
 447         tmp = (tmp >> 8) | (val << 8);
 448
 449         dma[c].dev->write_dma_io8w(0, val, &wait_w);
 450
 451         wait += compressed ? 5 : 7;
 452         if(extended) {
 453                 wait += wait_r + wait_w;
 454         }
 455 }
 456
 457 void UPD71071::do_dma_inc_dec_ptr_8bit(int c)
 458 {
 459         // Note: FM-Towns may extend to 32bit.
 460         if(dma[c].mode & 0x20) {
 461                 dma[c].areg = (dma[c].areg - 1) & 0xffffff;
 462         } else {
 463                 dma[c].areg = (dma[c].areg + 1) & 0xffffff;
 464         }
 465 }
 466
 467 void UPD71071::do_dma_verify_16bit(int c, bool extended, bool compressed, int& wait)
 468 {
 469         // verify
 470         bool __debugging = false;
 471         int wait_1 = 0, wait_2 = 0;
 472         set_ube(c);
 473         __LIKELY_IF((__USE_DEBUGGER) && (d_debugger != NULL)) {
 474                 __debugging = d_debugger->now_device_debugging;
 475         }
 476         // verify
 477         uint32_t val = dma[c].dev->read_dma_io16w(0, &wait_1);
 478
 479         uint32_t val2;
 480         __UNLIKELY_IF(__debugging) {
 481                 val2 = d_debugger->read_via_debugger_data16w(dma[c].areg, &wait_2);
 482         } else {
 483                 val2 = read_via_debugger_data16w(dma[c].areg,  &wait_2);
 484         }
 485
 486         // ToDo: Compare val1 and val2.
 487         // update temporary register
 488         tmp = val2;
 489
 490         wait += compressed ? 5 : 7;
 491         if(extended) {
 492                 wait += wait_1 + wait_2;
 493         }
 494 }
 495
 496 void UPD71071::do_dma_dev_to_mem_16bit(int c, bool extended, bool compressed, int& wait)
 497 {
 498         // io -> memory
 499         bool __debugging = false;
 500         int wait_r = 0, wait_w = 0;
 501         __LIKELY_IF((__USE_DEBUGGER) && (d_debugger != NULL)) {
 502                 __debugging = d_debugger->now_device_debugging;
 503         }
 504         // ToDo: For odd address.
 505         uint32_t val;
 506         set_ube(c);
 507         val = dma[c].dev->read_dma_io16w(0, &wait_r);
 508         // update temporary register
 509         tmp = val;
 510
 511         __UNLIKELY_IF(__debugging) {
 512                 d_debugger->write_via_debugger_data16w(dma[c].areg, val, &wait_w);
 513         } else {
 514                 write_via_debugger_data16w(dma[c].areg,  val, &wait_w);
 515         }
 516
 517         wait += compressed ? 5 : 7;
 518         if(extended) {
 519                 wait += wait_r + wait_w;
 520         }
 521 }
 522
 523 void UPD71071::do_dma_mem_to_dev_16bit(int c, bool extended, bool compressed, int& wait)
 524 {
 525         // memory -> io
 526         bool __debugging = false;
 527         int wait_r = 0, wait_w = 0;
 528         __LIKELY_IF((__USE_DEBUGGER) && (d_debugger != NULL)) {
 529                 __debugging = d_debugger->now_device_debugging;
 530         }
 531         // ToDo: For odd address.
 532         uint32_t val;
 533         set_ube(c);
 534         __UNLIKELY_IF(__debugging) {
 535                 val = d_debugger->read_via_debugger_data16w(dma[c].areg, &wait_r);
 536         } else {
 537                 val = read_via_debugger_data16w(dma[c].areg, &wait_r);
 538         }
 539         // update temporary register
 540         tmp = val;
 541
 542         dma[c].dev->write_dma_io16w(0, val, &wait_w);
 543
 544         wait += compressed ? 5 : 7;
 545         if(extended) {
 546                 wait += wait_r + wait_w;
 547         }
 548 }
 549
 550 void UPD71071::do_dma_inc_dec_ptr_16bit(int c)
 551 {
 552         // Note: FM-Towns may extend to 32bit.
 553         if(dma[c].mode & 0x20) {
 554                 dma[c].areg = (dma[c].areg - 2) & 0xffffff;
 555         } else {
 556                 dma[c].areg = (dma[c].areg + 2) & 0xffffff;
 557         }
 558 }
 559
 560 bool UPD71071::do_dma_epilogue(int c)
 561 {
 562         c = c & 3;
 563         uint8_t bit = 1 << c;
 564
 565 #if 0 /* SYNC TO UPSTREAM */
 566         if(dma[c].creg-- == 0) {
 567                 //if(dma[c].endreq) dma[c].end = true;
 568                 if(dma[c].mode & 0x10) {
 569                         // auto initialize
 570                         dma[c].areg = dma[c].bareg;
 571                         dma[c].creg = dma[c].bcreg;
 572                 } else {
 573                         mask |= bit;
 574                 }
 575                 req &= ~bit;
 576                 sreq &= ~bit;
 577                 running = false;
 578                 set_tc(c);
 579                 //write_signals(&outputs_tc, 0xffffffff);
 580                 if((dma[c].mode & 0xc0) == 0x40) {
 581                         // Single mode
 582                         return true;
 583                 } else {
 584                         return false;
 585                 }
 586         } else if((dma[c].mode & 0xc0) == 0x40) {
 587                 // Single mode
 588                 return true;
 589         }
 590         return false;
 591
 592         // Note: At FM-Towns, SCSI's DMAC will be set after
 593         //       SCSI bus phase become DATA IN/DATA OUT.
 594         //       Before bus phase became DATA IN/DATA OUT,
 595         //       DMAC mode and state was unstable (and ASSERTED
 596         //       DRQ came from SCSI before this state change).
 597         // ToDo: Stop correctly before setting.
 598         //       -- 20200316 K.O
 599 #else
 600 //      if(dma[c].end) return true; // OK?
 601         if((dma[c].creg == 0) || ((dma[c].endreq) && !(dma[c].end) && ((dma[c].mode & 0xc0) != 0x40))) {  // OK?
 602                 if(dma[c].endreq) dma[c].end = true;
 603                 bool is_tc = false;
 604                 dma[c].creg--;
 605                 if(dma[c].end) is_tc = true;
 606                 // TC
 607                 if(dma[c].bcreg < dma[c].creg) {
 608                         is_tc = true;
 609                 }
 610                 if(dma[c].mode & 0x10) {
 611                         // auto initialize
 612                         dma[c].areg = dma[c].bareg;
 613                         dma[c].creg = dma[c].bcreg;
 614                 } else {
 615                         mask |= bit;
 616                 }
 617                 req &= ~bit;
 618                 sreq &= ~bit;
 619                 running = false;
 620                 if(is_tc) {
 621                         set_tc(c);
 622                 }
 623                 if((dma[c].mode & 0xc0) == 0x40) {
 624                         // Single mode
 625                         return true;
 626                 } else {
 627                         return false;
 628                 }
 629         }
 630         dma[c].creg--;
 631         // Note: At FM-Towns, SCSI's DMAC will be set after
 632         //       SCSI bus phase become DATA IN/DATA OUT.
 633         //       Before bus phase became DATA IN/DATA OUT,
 634         //       DMAC mode and state was unstable (and ASSERTED
 635         //       DRQ came from SCSI before this state change).
 636         // ToDo: Stop correctly before setting.
 637         //       -- 20200316 K.O
 638         if((dma[c].mode & 0xc0) == 0x40){
 639                 // single mode
 640 //              req &= ~bit;
 641 //              sreq &= ~bit;
 642                 running = false;
 643                 return true;
 644         }
 645 #endif
 646         return false;
 647 }
 648
 649 bool UPD71071::do_dma_per_channel(int c)
 650 {
 651         reset_dma_ack(c);
 652         if(cmd & 4) {
 653                 return true;
 654         }
 655         if(dma[c].end) {
 656                 if((dma[c].mode & 0xc0) != 0x40) { // Without Single
 657                         return true;
 658                 }
 659         }
 660         uint8_t bit = 1 << c;
 661         bool dmastat = false;
 662         if(((req | sreq) & bit) /*&& !(mask & bit)*/) {
 663                 // execute dma
 664                 //while((req | sreq) & bit) { // Q: Will use burst transfer? 20230319 K.O
 665                         int wait = 0;
 666                         bool compressed = ((cmd & 0x08) != 0);
 667                         bool extended = ((cmd & 0x20) != 0);
 668                         //reset_dma_ack(c);
 669                         if(!running) {
 670                                 wait += 2; // S0
 671                                 running = true;
 672                         }
 673                         // SINGLE
 674                         // Will check WORD transfer mode for FM-Towns.(mode.bit0 = '1).
 675                         // Note: At FM-Towns, may set bit0 of mode register (B/W),
 676                         //       but transferring per 8bit from/to SCSI HOST...
 677                         ///      I wonder this...
 678                         // 2020-03-16 K.O
 679                         if((dma[c].is_16bit) && (inputs_ube[c]) /*&& (b16 != 0)*/) {
 680                                 // This channel transferr makes 16bit.
 681                                 if((dma[c].mode & 0x0c) == 0x00) {
 682                                         do_dma_verify_16bit(c, extended, compressed, wait);
 683                                 } else if((dma[c].mode & 0x0c) == 0x04) {
 684                                         do_dma_dev_to_mem_16bit(c, extended, compressed, wait);
 685                                 } else if((dma[c].mode & 0x0c) == 0x08) {
 686                                         do_dma_mem_to_dev_16bit(c, extended, compressed, wait);
 687                                 }
 688                                 do_dma_inc_dec_ptr_16bit(c);
 689                         } else {
 690                                 // 8bit transfer mode
 691                                 if((dma[c].mode & 0x0c) == 0x00) {
 692                                         do_dma_verify_8bit(c, extended, compressed, wait);
 693                                 } else if((dma[c].mode & 0x0c) == 0x04) {
 694                                         do_dma_dev_to_mem_8bit(c, extended, compressed, wait);
 695                                 } else if((dma[c].mode & 0x0c) == 0x08) {
 696                                         do_dma_mem_to_dev_8bit(c, extended, compressed, wait);
 697                                 }
 698                                 do_dma_inc_dec_ptr_8bit(c);
 699                         }
 700                         if(d_cpu != NULL) d_cpu->set_extra_clock(wait);
 701
 702                         set_dma_ack(c);
 703                         if(do_dma_epilogue(c)) {
 704 //                              //break;
 705 //                              if(_SINGLE_MODE_DMA) {
 706                                         return true;
 707 //                              }
 708 //                      set_dma_ack(c);
 709                         }
 710                 //}
 711         }
 712         return false;
 713 }
 714
 715 void UPD71071::do_dma()
 716 {
 717         // check DDMA
 718         if(cmd & 4) {
 719                 return;
 720         }
 721
 722         // run dma
 723         for(int c = 0; c < 4; c++) {
 724                 if((mask & (1 << c)) == 0) { // MASK
 725                         if((dma[c].mode & 0xc0) == 0x00) { // Demand
 726                                 if(!(dma[c].end)) {
 727                                         do_dma_per_channel(c);
 728                                 }
 729                         } else if((dma[c].mode & 0xc0) == 0x40) { // Single
 730                                 if(do_dma_per_channel(c)) break;
 731                         } else if((dma[c].mode & 0xc0) == 0xc0) { // Block (ToDo)
 732                                 if(do_dma_per_channel(c)) break;
 733                         }
 734                 }
 735         }
 736 //#ifdef SINGLE_MODE_DMA
 737         if(_SINGLE_MODE_DMA) {
 738                 if(d_dma) {
 739                         d_dma->do_dma();
 740                 }
 741         }
 742 //#endif
 743 }
 744
 745 bool UPD71071::get_debug_regs_info(_TCHAR *buffer, size_t buffer_len)
 746 {
 747 /*
 748 CH0 AREG=FFFF CREG=FFFF BAREG=FFFF BCREG=FFFF REQ=1 MASK=1 MODE=FF MEM->I/O
 749 CH1 AREG=FFFF CREG=FFFF BAREG=FFFF BCREG=FFFF REQ=1 MASK=1 MODE=FF I/O->MEM
 750 CH2 AREG=FFFF CREG=FFFF BAREG=FFFF BCREG=FFFF REQ=1 MASK=1 MODE=FF VERIFY
 751 CH3 AREG=FFFF CREG=FFFF BAREG=FFFF BCREG=FFFF REQ=1 MASK=1 MODE=FF INVALID
 752 */
 753         static const _TCHAR *dir[4] = {
 754                 _T("VERIFY"), _T("I/O->MEM"), _T("MEM->I/O"), _T("INVALID")
 755         };
 756         my_stprintf_s(buffer, buffer_len,
 757         _T("16Bit=%s\n")
 758         _T("SELECT CH=%d BASE=%02X REQ=%02X SREQ=%02X MASK=%02X TC=%02X ")
 759         _T("CMD=%04X TMP=%04X\n")
 760         _T("CH0 AREG=%04X CREG=%04X BAREG=%04X BCREG=%04X REQ=%d MASK=%d MODE=%02X %s\n")
 761         _T("CH1 AREG=%04X CREG=%04X BAREG=%04X BCREG=%04X REQ=%d MASK=%d MODE=%02X %s\n")
 762         _T("CH2 AREG=%04X CREG=%04X BAREG=%04X BCREG=%04X REQ=%d MASK=%d MODE=%02X %s\n")
 763         _T("CH3 AREG=%04X CREG=%04X BAREG=%04X BCREG=%04X REQ=%d MASK=%d MODE=%02X %s"),
 764         (b16 != 0) ? _T("YES") : _T("NO"),
 765         selch, base, req, sreq, mask, tc,
 766         cmd, tmp,
 767         dma[0].areg, dma[0].creg, dma[0].bareg, dma[0].bcreg, ((req | sreq) >> 0) & 1, (mask >> 0) & 1, dma[0].mode, dir[(dma[0].mode >> 2) & 3],
 768         dma[1].areg, dma[1].creg, dma[1].bareg, dma[1].bcreg, ((req | sreq) >> 1) & 1, (mask >> 1) & 1, dma[1].mode, dir[(dma[1].mode >> 2) & 3],
 769         dma[2].areg, dma[2].creg, dma[2].bareg, dma[2].bcreg, ((req | sreq) >> 2) & 1, (mask >> 2) & 1, dma[2].mode, dir[(dma[2].mode >> 2) & 3],
 770         dma[3].areg, dma[3].creg, dma[3].bareg, dma[3].bcreg, ((req | sreq) >> 3) & 1, (mask >> 3) & 1, dma[3].mode, dir[(dma[3].mode >> 2) & 3]);
 771         return true;
 772 }
 773
 774 #define STATE_VERSION   6
 775
 776 bool UPD71071::process_state(FILEIO* state_fio, bool loading)
 777 {
 778         if(!state_fio->StateCheckUint32(STATE_VERSION)) {
 779                 return false;
 780         }
 781         if(!state_fio->StateCheckInt32(this_device_id)) {
 782                 return false;
 783         }
 784         for(int i = 0; i < 4; i++) {
 785                 state_fio->StateValue(dma[i].areg);
 786                 state_fio->StateValue(dma[i].bareg);
 787                 state_fio->StateValue(dma[i].creg);
 788                 state_fio->StateValue(dma[i].bcreg);
 789                 state_fio->StateValue(dma[i].mode);
 790                 state_fio->StateValue(dma[i].is_16bit);
 791                 state_fio->StateValue(dma[i].endreq);
 792                 state_fio->StateValue(dma[i].end);
 793         }
 794         state_fio->StateValue(b16);
 795         state_fio->StateValue(selch);
 796         state_fio->StateValue(base);
 797         state_fio->StateValue(cmd);
 798         state_fio->StateValue(tmp);
 799         state_fio->StateValue(req);
 800         state_fio->StateValue(sreq);
 801         state_fio->StateValue(mask);
 802         state_fio->StateValue(tc);
 803         state_fio->StateValue(running);
 804
 805         state_fio->StateArray(inputs_ube, sizeof(inputs_ube), 1);
 806         state_fio->StateArray(stats_ube, sizeof(stats_ube), 1);
 807
 808         return true;
 809 }