2 Skelton for retropc emulator
5 Author : Takeda.Toshiya
17 #define SIG_NSC800_INT 0
18 #define SIG_NSC800_RSTA 1
19 #define SIG_NSC800_RSTB 2
20 #define SIG_NSC800_RSTC 3
22 //#if defined(USE_SHARED_DLL) || defined(USE_QT)
25 //#define Z80_INLINE inline
30 class Z80_BASE : public DEVICE
33 /* ---------------------------------------------------------------------------
35 --------------------------------------------------------------------------- */
37 DEVICE *d_mem, *d_io, *d_pic;
38 //#ifdef Z80_PSEUDO_BIOS
41 //#ifdef SINGLE_MODE_DMA
46 DEVICE *d_mem_stored, *d_io_stored;
48 outputs_t outputs_busack;
55 bool has_single_mode_dma;
56 bool flags_initialized;
61 /* ---------------------------------------------------------------------------
63 --------------------------------------------------------------------------- */
65 uint64_t total_icount;
66 uint64_t prev_total_icount;
71 pair32_t pc, sp, af, bc, de, hl, ix, iy, wz;
72 pair32_t af2, bc2, de2, hl2;
76 bool busreq, after_halt;
77 uint8_t im, iff1, iff2, icr;
78 bool after_ei, after_ldair;
79 uint32_t intr_req_bit, intr_pend_bit;
81 Z80_INLINE uint8_t RM8(uint32_t addr);
82 Z80_INLINE void WM8(uint32_t addr, uint8_t val);
83 Z80_INLINE void RM16(uint32_t addr, pair32_t *r);
84 Z80_INLINE void WM16(uint32_t addr, pair32_t *r);
85 Z80_INLINE uint8_t FETCHOP();
86 Z80_INLINE uint8_t FETCH8();
87 Z80_INLINE uint32_t FETCH16();
88 Z80_INLINE uint8_t IN8(uint32_t addr);
89 Z80_INLINE void OUT8(uint32_t addr, uint8_t val);
91 Z80_INLINE uint8_t INC(uint8_t value);
92 Z80_INLINE uint8_t DEC(uint8_t value);
94 Z80_INLINE uint8_t RLC(uint8_t value);
95 Z80_INLINE uint8_t RRC(uint8_t value);
96 Z80_INLINE uint8_t RL(uint8_t value);
97 Z80_INLINE uint8_t RR(uint8_t value);
98 Z80_INLINE uint8_t SLA(uint8_t value);
99 Z80_INLINE uint8_t SRA(uint8_t value);
100 Z80_INLINE uint8_t SLL(uint8_t value);
101 Z80_INLINE uint8_t SRL(uint8_t value);
103 Z80_INLINE uint8_t RES(uint8_t bit, uint8_t value);
104 Z80_INLINE uint8_t SET(uint8_t bit, uint8_t value);
106 void OP_CB(uint8_t code);
107 void OP_XY(uint8_t code);
108 void OP_DD(uint8_t code);
109 void OP_FD(uint8_t code);
110 void OP_ED(uint8_t code);
111 void OP(uint8_t code);
112 virtual void run_one_opecode();
113 virtual void debugger_hook(void);
115 uint8_t SZ[256]; /* zero and sign flags */
116 uint8_t SZ_BIT[256]; /* zero, sign and parity/overflow (=zero) flags for BIT opcode */
117 uint8_t SZP[256]; /* zero, sign and parity flags */
118 uint8_t SZHV_inc[256]; /* zero, sign, half carry and overflow flags INC r8 */
119 uint8_t SZHV_dec[256]; /* zero, sign, half carry and overflow flags DEC r8 */
121 uint8_t SZHVC_add[2 * 256 * 256];
122 uint8_t SZHVC_sub[2 * 256 * 256];
124 const uint8_t cc_op[0x100] = {
125 4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4,
126 8,10, 7, 6, 4, 4, 7, 4,12,11, 7, 6, 4, 4, 7, 4,
127 7,10,16, 6, 4, 4, 7, 4, 7,11,16, 6, 4, 4, 7, 4,
128 7,10,13, 6,11,11,10, 4, 7,11,13, 6, 4, 4, 7, 4,
129 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
130 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
131 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
132 7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,
133 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
134 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
135 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
136 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
137 5,10,10,10,10,11, 7,11, 5,10,10, 0,10,17, 7,11,
138 5,10,10,11,10,11, 7,11, 5, 4,10,11,10, 0, 7,11,
139 5,10,10,19,10,11, 7,11, 5, 4,10, 4,10, 0, 7,11,
140 5,10,10, 4,10,11, 7,11, 5, 6,10, 4,10, 0, 7,11
143 const uint8_t cc_cb[0x100] = {
144 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
145 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
146 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
147 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
148 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
149 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
150 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
151 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
152 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
153 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
154 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
155 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
156 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
157 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
158 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
159 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8
162 const uint8_t cc_ed[0x100] = {
163 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
164 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
165 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
166 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
167 12,12,15,20, 8,14, 8, 9,12,12,15,20, 8,14, 8, 9,
168 12,12,15,20, 8,14, 8, 9,12,12,15,20, 8,14, 8, 9,
169 12,12,15,20, 8,14, 8,18,12,12,15,20, 8,14, 8,18,
170 12,12,15,20, 8,14, 8, 8,12,12,15,20, 8,14, 8, 8,
171 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
172 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
173 16,16,16,16, 8, 8, 8, 8,16,16,16,16, 8, 8, 8, 8,
174 16,16,16,16, 8, 8, 8, 8,16,16,16,16, 8, 8, 8, 8,
175 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
176 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
177 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
178 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8
181 const uint8_t cc_xy[0x100] = {
182 4, 4, 4, 4, 4, 4, 4, 4, 4,15, 4, 4, 4, 4, 4, 4,
183 4, 4, 4, 4, 4, 4, 4, 4, 4,15, 4, 4, 4, 4, 4, 4,
184 4,14,20,10, 9, 9,11, 4, 4,15,20,10, 9, 9,11, 4,
185 4, 4, 4, 4,23,23,19, 4, 4,15, 4, 4, 4, 4, 4, 4,
186 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
187 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
188 9, 9, 9, 9, 9, 9,19, 9, 9, 9, 9, 9, 9, 9,19, 9,
189 19,19,19,19,19,19, 4,19, 4, 4, 4, 4, 9, 9,19, 4,
190 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
191 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
192 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
193 4, 4, 4, 4, 9, 9,19, 4, 4, 4, 4, 4, 9, 9,19, 4,
194 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 4, 4, 4, 4,
195 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
196 4,14, 4,23, 4,15, 4, 4, 4, 8, 4, 4, 4, 4, 4, 4,
197 4, 4, 4, 4, 4, 4, 4, 4, 4,10, 4, 4, 4, 4, 4, 4
200 const uint8_t cc_xycb[0x100] = {
201 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
202 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
203 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
204 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
205 20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
206 20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
207 20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
208 20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,
209 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
210 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
211 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
212 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
213 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
214 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
215 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,
216 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23
219 const uint8_t cc_ex[0x100] = {
220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
221 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* DJNZ */
222 5, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, /* JR NZ/JR Z */
223 5, 0, 0, 0, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0, 0, 0, /* JR NC/JR C */
224 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
225 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
226 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
227 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
228 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
229 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
230 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
231 5, 5, 5, 5, 0, 0, 0, 0, 5, 5, 5, 5, 0, 0, 0, 0, /* LDIR/CPIR/INIR/OTIR LDDR/CPDR/INDR/OTDR */
232 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2,
233 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2,
234 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2,
235 6, 0, 0, 0, 7, 0, 0, 2, 6, 0, 0, 0, 7, 0, 0, 2
238 /* ---------------------------------------------------------------------------
240 --------------------------------------------------------------------------- */
242 uint64_t cycles_tmp_count;
243 uint64_t extra_tmp_count;
244 uint32_t insns_count;
248 int nsc800_int_count;
249 int nsc800_rsta_count;
250 int nsc800_rstb_count;
251 int nsc800_rstc_count;
254 Z80_BASE(VM_TEMPLATE* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)
256 flags_initialized = false;
258 //#ifdef Z80_PSEUDO_BIOS
261 //#ifdef SINGLE_MODE_DMA
270 has_memory_wait = false;
271 has_pseudo_bios = false;
272 has_ldair_quirk = false;
273 has_single_mode_dma = false;
274 total_icount = prev_total_icount = 0;
275 initialize_output_signals(&outputs_busack);
277 set_device_name(_T("Z80 CPU"));
283 virtual void initialize();
284 virtual void reset();
288 virtual bool process_state(FILEIO* state_fio, bool loading);
290 void write_signal(int id, uint32_t data, uint32_t mask);
291 uint32_t read_signal(int id);
292 void set_intr_line(bool line, bool pending, uint32_t bit)
294 uint32_t mask = 1 << bit;
295 intr_req_bit = line ? (intr_req_bit | mask) : (intr_req_bit & ~mask);
296 intr_pend_bit = pending ? (intr_pend_bit | mask) : (intr_pend_bit & ~mask);
297 if(line) irq_count++;
299 void set_extra_clock(int clock)
301 extra_icount += clock;
303 int get_extra_clock()
311 uint32_t get_next_pc()
315 //#ifdef USE_DEBUGGER
320 bool is_debugger_available()
328 uint32_t get_debug_prog_addr_mask()
332 uint32_t get_debug_data_addr_mask()
336 bool write_debug_reg(const _TCHAR *reg, uint32_t data);
337 bool get_debug_regs_info(_TCHAR *buffer, size_t buffer_len);
338 virtual int debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len);
341 void set_context_mem(DEVICE* device)
345 void set_context_io(DEVICE* device)
349 DEVICE *get_context_child()
353 void set_context_intr(DEVICE* device)
357 void set_context_busack(DEVICE* device, int id, uint32_t mask)
359 register_output_signal(&outputs_busack, device, id, mask);
361 void set_pc(uint16_t value)
365 void set_sp(uint16_t value)
371 class Z80 : public Z80_BASE
374 void check_interrupt();
375 void run_one_opecode() override;
376 void debugger_hook(void) override;
378 Z80(VM_TEMPLATE* parent_vm, EMU* parent_emu);
382 int run(int clock) override;
384 int debug_dasm(uint32_t pc, _TCHAR *buffer, size_t buffer_len);
386 void write_debug_data8(uint32_t addr, uint32_t data);
387 uint32_t read_debug_data8(uint32_t addr);
388 void write_debug_io8(uint32_t addr, uint32_t data);
389 uint32_t read_debug_io8(uint32_t addr);
391 #ifdef Z80_PSEUDO_BIOS
392 void set_context_bios(DEVICE* device)
397 #ifdef SINGLE_MODE_DMA
398 void set_context_dma(DEVICE* device)
404 void set_context_debugger(DEBUGGER* device)