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[DOC] For release 2017-01-24.
[csp-qt/common_source_project-fm7.git] / source / src / vm / z80ctc.h
1 /*
2         Skelton for retropc emulator
3
4         Author : Takeda.Toshiya
5         Date   : 2006.08.18 -
6
7         [ Z80CTC ]
8 */
9
10 #ifndef _Z80CTC_H_
11 #define _Z80CTC_H_
12
13 #include "vm.h"
14 #include "../emu.h"
15 #include "device.h"
16
17 #define SIG_Z80CTC_TRIG_0       0
18 #define SIG_Z80CTC_TRIG_1       1
19 #define SIG_Z80CTC_TRIG_2       2
20 #define SIG_Z80CTC_TRIG_3       3
21
22 class Z80CTC : public DEVICE
23 {
24 private:
25         struct {
26                 uint8_t control;
27                 bool slope;
28                 uint16_t count;
29                 uint16_t constant;
30                 uint8_t vector;
31                 int clocks;
32                 int prescaler;
33                 bool freeze;
34                 bool start;
35                 bool latch;
36                 bool prev_in;
37                 bool first_constant;
38                 // constant clock
39                 uint64_t freq;
40                 int clock_id;
41                 int sysclock_id;
42                 uint32_t input;
43                 uint32_t period;
44                 uint32_t prev;
45                 // interrupt
46                 bool req_intr;
47                 bool in_service;
48                 // output signals
49                 outputs_t outputs;
50         } counter[4];
51         uint64_t cpu_clocks;
52         
53         void input_clock(int ch, int clock);
54         void input_sysclock(int ch, int clock);
55         void update_event(int ch, int err);
56         
57         // daisy chain
58         DEVICE *d_cpu, *d_child;
59         bool iei, oei;
60         uint32_t intr_bit;
61         void update_intr();
62         
63 public:
64         Z80CTC(VM* parent_vm, EMU* parent_emu) : DEVICE(parent_vm, parent_emu)
65         {
66                 memset(counter, 0, sizeof(counter));
67                 for(int i = 0; i < 4; i++) {
68                         initialize_output_signals(&counter[i].outputs);
69                         counter[i].freq = 0;
70                         counter[i].prev_in = false;
71                 }
72                 d_cpu = d_child = NULL;
73                 set_device_name(_T("Z80 CTC"));
74         }
75         ~Z80CTC() {}
76         
77         // common functions
78         void reset();
79         void write_io8(uint32_t addr, uint32_t data);
80         uint32_t read_io8(uint32_t addr);
81         void write_signal(int id, uint32_t data, uint32_t mask);
82         void event_callback(int event_id, int err);
83         void update_timing(int new_clocks, double new_frames_per_sec, int new_lines_per_frame)
84         {
85                 cpu_clocks = new_clocks;
86         }
87         void save_state(FILEIO* state_fio);
88         bool load_state(FILEIO* state_fio);
89         // interrupt common functions
90         void set_context_intr(DEVICE* device, uint32_t bit)
91         {
92                 d_cpu = device;
93                 intr_bit = bit;
94         }
95         void set_context_child(DEVICE* device)
96         {
97                 d_child = device;
98         }
99         void set_intr_iei(bool val);
100         uint32_t get_intr_ack();
101         void notify_intr_reti();
102         
103         // unique functions
104         void set_context_zc0(DEVICE* device, int id, uint32_t mask)
105         {
106                 register_output_signal(&counter[0].outputs, device, id, mask);
107         }
108         void set_context_zc1(DEVICE* device, int id, uint32_t mask)
109         {
110                 register_output_signal(&counter[1].outputs, device, id, mask);
111         }
112         void set_context_zc2(DEVICE* device, int id, uint32_t mask)
113         {
114                 register_output_signal(&counter[2].outputs, device, id, mask);
115         }
116         void set_constant_clock(int ch, uint32_t hz)
117         {
118                 counter[ch].freq = hz;
119         }
120 };
121
122 #endif