1 // Copyright 2018 The SwiftShader Authors. All Rights Reserved.
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
15 #ifndef sw_SpirvShader_hpp
16 #define sw_SpirvShader_hpp
18 #include "ShaderCore.hpp"
19 #include "SpirvID.hpp"
20 #include "System/Types.hpp"
21 #include "Vulkan/VkDebug.hpp"
22 #include "Vulkan/VkConfig.h"
28 #include <unordered_map>
30 #include <type_traits>
32 #include <spirv/unified1/spirv.hpp>
33 #include <Device/Config.hpp>
42 // Forward declarations.
46 // SIMD contains types that represent multiple scalars packed into a single
47 // vector data type. Types in the SIMD namespace provide a semantic hint
48 // that the data should be treated as a per-execution-lane scalar instead of
49 // a typical euclidean-style vector type.
52 // Width is the number of per-lane scalars packed into each SIMD vector.
53 static constexpr int Width = 4;
55 using Float = rr::Float4;
57 using UInt = rr::UInt4;
60 // Incrementally constructed complex bundle of rvalues
61 // Effectively a restricted vector, supporting only:
62 // - allocation to a (runtime-known) fixed size
63 // - in-place construction of elements
68 using Scalar = RValue<SIMD::Float>;
70 Intermediate(uint32_t size) : contents(new ContentsType[size]), size(size) {
71 #if !defined(NDEBUG) || defined(DCHECK_ALWAYS_ON)
72 memset(contents, 0, sizeof(ContentsType) * size);
78 for (auto i = 0u; i < size; i++)
79 reinterpret_cast<Scalar *>(&contents[i])->~Scalar();
83 void emplace(uint32_t n, Scalar&& value)
86 ASSERT(reinterpret_cast<Scalar const *>(&contents[n])->value == nullptr);
87 new (&contents[n]) Scalar(value);
90 void emplace(uint32_t n, const Scalar& value)
93 ASSERT(reinterpret_cast<Scalar const *>(&contents[n])->value == nullptr);
94 new (&contents[n]) Scalar(value);
97 // Emplace with cast helpers.
98 void emplace(uint32_t n, const RValue<SIMD::Int>& value) { emplace(n, As<SIMD::Float>(value)); }
99 void emplace(uint32_t n, const RValue<SIMD::UInt>& value) { emplace(n, As<SIMD::Float>(value)); }
101 // Value retrieval functions.
102 RValue<SIMD::Float> Float(uint32_t i) const
105 auto scalar = reinterpret_cast<Scalar const *>(&contents[i]);
106 ASSERT(scalar->value != nullptr);
109 RValue<SIMD::Int> Int(uint32_t i) const { return As<SIMD::Int>(Float(i)); }
110 RValue<SIMD::UInt> UInt(uint32_t i) const { return As<SIMD::UInt>(Float(i)); }
112 // No copy/move construction or assignment
113 Intermediate(Intermediate const &) = delete;
114 Intermediate(Intermediate &&) = delete;
115 Intermediate & operator=(Intermediate const &) = delete;
116 Intermediate & operator=(Intermediate &&) = delete;
119 using ContentsType = std::aligned_storage<sizeof(Scalar), alignof(Scalar)>::type;
121 ContentsType *contents;
128 using InsnStore = std::vector<uint32_t>;
131 /* Pseudo-iterator over SPIRV instructions, designed to support range-based-for. */
134 InsnStore::const_iterator iter;
137 spv::Op opcode() const
139 return static_cast<spv::Op>(*iter & spv::OpCodeMask);
142 uint32_t wordCount() const
144 return *iter >> spv::WordCountShift;
147 uint32_t word(uint32_t n) const
149 ASSERT(n < wordCount());
153 uint32_t const * wordPointer(uint32_t n) const
155 ASSERT(n < wordCount());
159 bool operator!=(InsnIterator const &other) const
161 return iter != other.iter;
164 InsnIterator operator*() const
169 InsnIterator &operator++()
175 InsnIterator const operator++(int)
177 InsnIterator ret{*this};
182 InsnIterator(InsnIterator const &other) = default;
184 InsnIterator() = default;
186 explicit InsnIterator(InsnStore::const_iterator iter) : iter{iter}
191 /* range-based-for interface */
192 InsnIterator begin() const
194 return InsnIterator{insns.cbegin() + 5};
197 InsnIterator end() const
199 return InsnIterator{insns.cend()};
205 using ID = SpirvID<Type>;
207 InsnIterator definition;
208 spv::StorageClass storageClass = static_cast<spv::StorageClass>(-1);
209 uint32_t sizeInComponents = 0;
210 bool isBuiltInBlock = false;
212 // Inner element type for pointers, arrays, vectors and matrices.
219 using ID = SpirvID<Object>;
221 InsnIterator definition;
224 std::unique_ptr<uint32_t[]> constantValue = nullptr;
228 Unknown, /* for paranoia -- if we get left with an object in this state, the module was broken */
229 Variable, // TODO: Document
230 InterfaceVariable, // TODO: Document
231 Constant, // Values held by Object::constantValue
232 Value, // Values held by SpirvRoutine::intermediates
233 PhysicalPointer, // Pointer held by SpirvRoutine::physicalPointers
234 } kind = Kind::Unknown;
237 // Block is an interval of SPIR-V instructions, starting with the
238 // opening OpLabel, and ending with a termination instruction.
242 using ID = SpirvID<Block>;
245 Block(const Block& other) = default;
246 explicit Block(InsnIterator begin, InsnIterator end) : begin_(begin), end_(end) {}
248 /* range-based-for interface */
249 inline InsnIterator begin() const { return begin_; }
250 inline InsnIterator end() const { return end_; }
257 struct TypeOrObject {}; // Dummy struct to represent a Type or Object.
259 // TypeOrObjectID is an identifier that represents a Type or an Object,
260 // and supports implicit casting to and from Type::ID or Object::ID.
261 class TypeOrObjectID : public SpirvID<TypeOrObject>
264 using Hash = std::hash<SpirvID<TypeOrObject>>;
266 inline TypeOrObjectID(uint32_t id) : SpirvID(id) {}
267 inline TypeOrObjectID(Type::ID id) : SpirvID(id.value()) {}
268 inline TypeOrObjectID(Object::ID id) : SpirvID(id.value()) {}
269 inline operator Type::ID() const { return Type::ID(value()); }
270 inline operator Object::ID() const { return Object::ID(value()); }
273 int getSerialID() const
278 explicit SpirvShader(InsnStore const &insns);
282 bool EarlyFragmentTests : 1;
283 bool DepthReplacing : 1;
284 bool DepthGreater : 1;
286 bool DepthUnchanged : 1;
287 bool ContainsKill : 1;
288 bool NeedsCentroid : 1;
290 // Compute workgroup dimensions
291 int LocalSizeX, LocalSizeY, LocalSizeZ;
294 Modes const &getModes() const
299 enum AttribType : unsigned char
306 ATTRIBTYPE_LAST = ATTRIBTYPE_UINT
309 bool hasBuiltinInput(spv::BuiltIn b) const
311 return inputBuiltins.find(b) != inputBuiltins.end();
318 int32_t DescriptorSet;
320 spv::BuiltIn BuiltIn;
323 int32_t MatrixStride;
324 bool HasLocation : 1;
325 bool HasComponent : 1;
326 bool HasDescriptorSet : 1;
331 bool NoPerspective : 1;
333 bool BufferBlock : 1;
335 bool HasArrayStride : 1;
336 bool HasMatrixStride : 1;
339 : Location{-1}, Component{0}, DescriptorSet{-1}, Binding{-1},
340 BuiltIn{static_cast<spv::BuiltIn>(-1)},
341 Offset{-1}, ArrayStride{-1}, MatrixStride{-1},
342 HasLocation{false}, HasComponent{false},
343 HasDescriptorSet{false}, HasBinding{false},
344 HasBuiltIn{false}, Flat{false}, Centroid{false},
345 NoPerspective{false}, Block{false}, BufferBlock{false},
346 HasOffset{false}, HasArrayStride{false}, HasMatrixStride{false}
350 Decorations(Decorations const &) = default;
352 void Apply(Decorations const &src);
354 void Apply(spv::Decoration decoration, uint32_t arg);
357 std::unordered_map<TypeOrObjectID, Decorations, TypeOrObjectID::Hash> decorations;
358 std::unordered_map<Type::ID, std::vector<Decorations>> memberDecorations;
360 struct InterfaceComponent
365 bool NoPerspective : 1;
368 : Type{ATTRIBTYPE_UNUSED}, Flat{false}, Centroid{false}, NoPerspective{false}
373 struct BuiltinMapping
376 uint32_t FirstComponent;
377 uint32_t SizeInComponents;
380 std::vector<InterfaceComponent> inputs;
381 std::vector<InterfaceComponent> outputs;
383 void emitProlog(SpirvRoutine *routine) const;
384 void emit(SpirvRoutine *routine) const;
385 void emitEpilog(SpirvRoutine *routine) const;
387 using BuiltInHash = std::hash<std::underlying_type<spv::BuiltIn>::type>;
388 std::unordered_map<spv::BuiltIn, BuiltinMapping, BuiltInHash> inputBuiltins;
389 std::unordered_map<spv::BuiltIn, BuiltinMapping, BuiltInHash> outputBuiltins;
391 Type const &getType(Type::ID id) const
393 auto it = types.find(id);
394 ASSERT(it != types.end());
398 Object const &getObject(Object::ID id) const
400 auto it = defs.find(id);
401 ASSERT(it != defs.end());
405 Block const &getBlock(Block::ID id) const
407 auto it = blocks.find(id);
408 ASSERT(it != blocks.end());
414 static volatile int serialCounter;
416 HandleMap<Type> types;
417 HandleMap<Object> defs;
418 HandleMap<Block> blocks;
419 Block::ID mainBlockId; // Block of the entry point function.
421 void EmitBlock(SpirvRoutine *routine, Block const &block) const;
422 void EmitInstruction(SpirvRoutine *routine, InsnIterator insn) const;
424 // DeclareType creates a Type for the given OpTypeX instruction, storing
425 // it into the types map. It is called from the analysis pass (constructor).
426 void DeclareType(InsnIterator insn);
428 void ProcessExecutionMode(InsnIterator it);
430 uint32_t ComputeTypeSize(InsnIterator insn);
431 void ApplyDecorationsForId(Decorations *d, TypeOrObjectID id) const;
432 void ApplyDecorationsForIdMember(Decorations *d, Type::ID id, uint32_t member) const;
434 // Returns true if data in the given storage class is word-interleaved
435 // by each SIMD vector lane, otherwise data is linerally stored.
437 // A 'lane' is a component of a SIMD vector register.
438 // Given 4 consecutive loads/stores of 4 SIMD vector registers:
440 // "StorageInterleavedByLane":
442 // Ptr+0:Reg0.x | Ptr+1:Reg0.y | Ptr+2:Reg0.z | Ptr+3:Reg0.w
443 // --------------+--------------+--------------+--------------
444 // Ptr+4:Reg1.x | Ptr+5:Reg1.y | Ptr+6:Reg1.z | Ptr+7:Reg1.w
445 // --------------+--------------+--------------+--------------
446 // Ptr+8:Reg2.x | Ptr+9:Reg2.y | Ptr+a:Reg2.z | Ptr+b:Reg2.w
447 // --------------+--------------+--------------+--------------
448 // Ptr+c:Reg3.x | Ptr+d:Reg3.y | Ptr+e:Reg3.z | Ptr+f:Reg3.w
450 // Not "StorageInterleavedByLane":
452 // Ptr+0:Reg0.x | Ptr+0:Reg0.y | Ptr+0:Reg0.z | Ptr+0:Reg0.w
453 // --------------+--------------+--------------+--------------
454 // Ptr+1:Reg1.x | Ptr+1:Reg1.y | Ptr+1:Reg1.z | Ptr+1:Reg1.w
455 // --------------+--------------+--------------+--------------
456 // Ptr+2:Reg2.x | Ptr+2:Reg2.y | Ptr+2:Reg2.z | Ptr+2:Reg2.w
457 // --------------+--------------+--------------+--------------
458 // Ptr+3:Reg3.x | Ptr+3:Reg3.y | Ptr+3:Reg3.z | Ptr+3:Reg3.w
460 static bool IsStorageInterleavedByLane(spv::StorageClass storageClass);
463 int VisitInterfaceInner(Type::ID id, Decorations d, F f) const;
466 void VisitInterface(Object::ID id, F f) const;
468 uint32_t GetConstantInt(Object::ID id) const;
469 Object& CreateConstant(InsnIterator it);
471 void ProcessInterfaceVariable(Object &object);
473 SIMD::Int WalkAccessChain(Object::ID id, uint32_t numIndexes, uint32_t const *indexIds, SpirvRoutine *routine) const;
474 uint32_t WalkLiteralAccessChain(Type::ID id, uint32_t numIndexes, uint32_t const *indexes) const;
476 // Emit pass instructions:
477 void EmitVariable(InsnIterator insn, SpirvRoutine *routine) const;
478 void EmitLoad(InsnIterator insn, SpirvRoutine *routine) const;
479 void EmitStore(InsnIterator insn, SpirvRoutine *routine) const;
480 void EmitAccessChain(InsnIterator insn, SpirvRoutine *routine) const;
481 void EmitCompositeConstruct(InsnIterator insn, SpirvRoutine *routine) const;
482 void EmitCompositeInsert(InsnIterator insn, SpirvRoutine *routine) const;
483 void EmitCompositeExtract(InsnIterator insn, SpirvRoutine *routine) const;
484 void EmitVectorShuffle(InsnIterator insn, SpirvRoutine *routine) const;
485 void EmitVectorTimesScalar(InsnIterator insn, SpirvRoutine *routine) const;
486 void EmitUnaryOp(InsnIterator insn, SpirvRoutine *routine) const;
487 void EmitBinaryOp(InsnIterator insn, SpirvRoutine *routine) const;
488 void EmitDot(InsnIterator insn, SpirvRoutine *routine) const;
489 void EmitSelect(InsnIterator insn, SpirvRoutine *routine) const;
490 void EmitExtendedInstruction(InsnIterator insn, SpirvRoutine *routine) const;
491 void EmitAny(InsnIterator insn, SpirvRoutine *routine) const;
492 void EmitAll(InsnIterator insn, SpirvRoutine *routine) const;
494 // OpcodeName returns the name of the opcode op.
495 // If NDEBUG is defined, then OpcodeName will only return the numerical code.
496 static std::string OpcodeName(spv::Op op);
498 // Helper as we often need to take dot products as part of doing other things.
499 SIMD::Float Dot(unsigned numComponents, GenericValue const & x, GenericValue const & y) const;
505 SpirvRoutine(vk::PipelineLayout const *pipelineLayout);
507 using Value = Array<SIMD::Float>;
509 vk::PipelineLayout const * const pipelineLayout;
511 std::unordered_map<SpirvShader::Object::ID, Value> lvalues;
513 std::unordered_map<SpirvShader::Object::ID, Intermediate> intermediates;
515 std::unordered_map<SpirvShader::Object::ID, Pointer<Byte> > physicalPointers;
517 Value inputs = Value{MAX_INTERFACE_COMPONENTS};
518 Value outputs = Value{MAX_INTERFACE_COMPONENTS};
520 std::array<Pointer<Byte>, vk::MAX_BOUND_DESCRIPTOR_SETS> descriptorSets;
522 void createLvalue(SpirvShader::Object::ID id, uint32_t size)
524 lvalues.emplace(id, Value(size));
527 Intermediate& createIntermediate(SpirvShader::Object::ID id, uint32_t size)
529 auto it = intermediates.emplace(std::piecewise_construct,
530 std::forward_as_tuple(id),
531 std::forward_as_tuple(size));
532 return it.first->second;
535 Value& getValue(SpirvShader::Object::ID id)
537 auto it = lvalues.find(id);
538 ASSERT(it != lvalues.end());
542 Intermediate const& getIntermediate(SpirvShader::Object::ID id) const
544 auto it = intermediates.find(id);
545 ASSERT(it != intermediates.end());
549 Pointer<Byte>& getPhysicalPointer(SpirvShader::Object::ID id)
551 auto it = physicalPointers.find(id);
552 assert(it != physicalPointers.end());
559 // Generic wrapper over either per-lane intermediate value, or a constant.
560 // Constants are transparently widened to per-lane values in operator[].
561 // This is appropriate in most cases -- if we're not going to do something
562 // significantly different based on whether the value is uniform across lanes.
564 SpirvShader::Object const &obj;
565 Intermediate const *intermediate;
568 GenericValue(SpirvShader const *shader, SpirvRoutine const *routine, SpirvShader::Object::ID objId) :
569 obj(shader->getObject(objId)),
570 intermediate(obj.kind == SpirvShader::Object::Kind::Value ? &routine->getIntermediate(objId) : nullptr) {}
572 RValue<SIMD::Float> Float(uint32_t i) const
574 if (intermediate != nullptr)
576 return intermediate->Float(i);
578 auto constantValue = reinterpret_cast<float *>(obj.constantValue.get());
579 return RValue<SIMD::Float>(constantValue[i]);
582 RValue<SIMD::Int> Int(uint32_t i) const
584 return As<SIMD::Int>(Float(i));
587 RValue<SIMD::UInt> UInt(uint32_t i) const
589 return As<SIMD::UInt>(Float(i));
595 #endif // sw_SpirvShader_hpp