1 // Copyright 2018 The SwiftShader Authors. All Rights Reserved.
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
15 #ifndef sw_SpirvShader_hpp
16 #define sw_SpirvShader_hpp
18 #include "ShaderCore.hpp"
19 #include "SpirvID.hpp"
20 #include "System/Types.hpp"
21 #include "Vulkan/VkDebug.hpp"
22 #include "Vulkan/VkConfig.h"
23 #include "Device/Config.hpp"
25 #include <spirv/unified1/spirv.hpp>
32 #include <unordered_set>
33 #include <unordered_map>
35 #include <type_traits>
45 // Forward declarations.
49 // SIMD contains types that represent multiple scalars packed into a single
50 // vector data type. Types in the SIMD namespace provide a semantic hint
51 // that the data should be treated as a per-execution-lane scalar instead of
52 // a typical euclidean-style vector type.
55 // Width is the number of per-lane scalars packed into each SIMD vector.
56 static constexpr int Width = 4;
58 using Float = rr::Float4;
60 using UInt = rr::UInt4;
63 // Incrementally constructed complex bundle of rvalues
64 // Effectively a restricted vector, supporting only:
65 // - allocation to a (runtime-known) fixed size
66 // - in-place construction of elements
71 Intermediate(uint32_t size) : scalar(new rr::Value*[size]), size(size) {
72 memset(scalar, 0, sizeof(rr::Value*) * size);
80 void move(uint32_t i, RValue<SIMD::Float> &&scalar) { emplace(i, scalar.value); }
81 void move(uint32_t i, RValue<SIMD::Int> &&scalar) { emplace(i, scalar.value); }
82 void move(uint32_t i, RValue<SIMD::UInt> &&scalar) { emplace(i, scalar.value); }
84 void move(uint32_t i, const RValue<SIMD::Float> &scalar) { emplace(i, scalar.value); }
85 void move(uint32_t i, const RValue<SIMD::Int> &scalar) { emplace(i, scalar.value); }
86 void move(uint32_t i, const RValue<SIMD::UInt> &scalar) { emplace(i, scalar.value); }
88 void replace(uint32_t i, RValue<SIMD::Float> &&scalar) { replace(i, scalar.value); }
89 void replace(uint32_t i, RValue<SIMD::Int> &&scalar) { replace(i, scalar.value); }
90 void replace(uint32_t i, RValue<SIMD::UInt> &&scalar) { replace(i, scalar.value); }
92 void replace(uint32_t i, const RValue<SIMD::Float> &scalar) { replace(i, scalar.value); }
93 void replace(uint32_t i, const RValue<SIMD::Int> &scalar) { replace(i, scalar.value); }
94 void replace(uint32_t i, const RValue<SIMD::UInt> &scalar) { replace(i, scalar.value); }
96 // Value retrieval functions.
97 RValue<SIMD::Float> Float(uint32_t i) const
100 ASSERT(scalar[i] != nullptr);
101 return As<SIMD::Float>(scalar[i]); // TODO(b/128539387): RValue<SIMD::Float>(scalar)
104 RValue<SIMD::Int> Int(uint32_t i) const
107 ASSERT(scalar[i] != nullptr);
108 return As<SIMD::Int>(scalar[i]); // TODO(b/128539387): RValue<SIMD::Int>(scalar)
111 RValue<SIMD::UInt> UInt(uint32_t i) const
114 ASSERT(scalar[i] != nullptr);
115 return As<SIMD::UInt>(scalar[i]); // TODO(b/128539387): RValue<SIMD::UInt>(scalar)
118 // No copy/move construction or assignment
119 Intermediate(Intermediate const &) = delete;
120 Intermediate(Intermediate &&) = delete;
121 Intermediate & operator=(Intermediate const &) = delete;
122 Intermediate & operator=(Intermediate &&) = delete;
125 void emplace(uint32_t i, rr::Value *value)
128 ASSERT(scalar[i] == nullptr);
132 void replace(uint32_t i, rr::Value *value)
138 rr::Value **const scalar;
145 using InsnStore = std::vector<uint32_t>;
148 /* Pseudo-iterator over SPIRV instructions, designed to support range-based-for. */
151 InsnStore::const_iterator iter;
154 spv::Op opcode() const
156 return static_cast<spv::Op>(*iter & spv::OpCodeMask);
159 uint32_t wordCount() const
161 return *iter >> spv::WordCountShift;
164 uint32_t word(uint32_t n) const
166 ASSERT(n < wordCount());
170 uint32_t const * wordPointer(uint32_t n) const
172 ASSERT(n < wordCount());
176 bool operator==(InsnIterator const &other) const
178 return iter == other.iter;
181 bool operator!=(InsnIterator const &other) const
183 return iter != other.iter;
186 InsnIterator operator*() const
191 InsnIterator &operator++()
197 InsnIterator const operator++(int)
199 InsnIterator ret{*this};
204 InsnIterator(InsnIterator const &other) = default;
206 InsnIterator() = default;
208 explicit InsnIterator(InsnStore::const_iterator iter) : iter{iter}
213 /* range-based-for interface */
214 InsnIterator begin() const
216 return InsnIterator{insns.cbegin() + 5};
219 InsnIterator end() const
221 return InsnIterator{insns.cend()};
227 using ID = SpirvID<Type>;
229 spv::Op opcode() const { return definition.opcode(); }
231 InsnIterator definition;
232 spv::StorageClass storageClass = static_cast<spv::StorageClass>(-1);
233 uint32_t sizeInComponents = 0;
234 bool isBuiltInBlock = false;
236 // Inner element type for pointers, arrays, vectors and matrices.
243 using ID = SpirvID<Object>;
245 spv::Op opcode() const { return definition.opcode(); }
247 InsnIterator definition;
250 std::unique_ptr<uint32_t[]> constantValue = nullptr;
254 Unknown, /* for paranoia -- if we get left with an object in this state, the module was broken */
255 Variable, // TODO: Document
256 InterfaceVariable, // TODO: Document
257 Constant, // Values held by Object::constantValue
258 Value, // Values held by SpirvRoutine::intermediates
259 PhysicalPointer, // Pointer held by SpirvRoutine::physicalPointers
260 } kind = Kind::Unknown;
263 // Block is an interval of SPIR-V instructions, starting with the
264 // opening OpLabel, and ending with a termination instruction.
268 using ID = SpirvID<Block>;
269 using Set = std::unordered_set<ID>;
271 // Edge represents the graph edge between two blocks.
277 bool operator == (const Edge& other) const { return from == other.from && to == other.to; }
281 std::size_t operator()(const Edge& edge) const noexcept
283 return std::hash<uint32_t>()(edge.from.value() * 31 + edge.to.value());
289 Block(const Block& other) = default;
290 explicit Block(InsnIterator begin, InsnIterator end);
292 /* range-based-for interface */
293 inline InsnIterator begin() const { return begin_; }
294 inline InsnIterator end() const { return end_; }
298 Simple, // OpBranch or other simple terminator.
299 StructuredBranchConditional, // OpSelectionMerge + OpBranchConditional
300 UnstructuredBranchConditional, // OpBranchConditional
301 StructuredSwitch, // OpSelectionMerge + OpSwitch
302 UnstructuredSwitch, // OpSwitch
303 Loop, // OpLoopMerge + [OpBranchConditional | OpBranch]
307 InsnIterator mergeInstruction; // Merge instruction.
308 InsnIterator branchInstruction; //
309 ID mergeBlock; // Structured flow merge block.
310 ID continueTarget; // Loop continue block.
311 Set ins; // Blocks that branch into this block.
312 Set outs; // Blocks that this block branches to.
319 struct TypeOrObject {}; // Dummy struct to represent a Type or Object.
321 // TypeOrObjectID is an identifier that represents a Type or an Object,
322 // and supports implicit casting to and from Type::ID or Object::ID.
323 class TypeOrObjectID : public SpirvID<TypeOrObject>
326 using Hash = std::hash<SpirvID<TypeOrObject>>;
328 inline TypeOrObjectID(uint32_t id) : SpirvID(id) {}
329 inline TypeOrObjectID(Type::ID id) : SpirvID(id.value()) {}
330 inline TypeOrObjectID(Object::ID id) : SpirvID(id.value()) {}
331 inline operator Type::ID() const { return Type::ID(value()); }
332 inline operator Object::ID() const { return Object::ID(value()); }
335 int getSerialID() const
340 explicit SpirvShader(InsnStore const &insns);
344 bool EarlyFragmentTests : 1;
345 bool DepthReplacing : 1;
346 bool DepthGreater : 1;
348 bool DepthUnchanged : 1;
349 bool ContainsKill : 1;
350 bool NeedsCentroid : 1;
352 // Compute workgroup dimensions
353 int WorkgroupSizeX = 1, WorkgroupSizeY = 1, WorkgroupSizeZ = 1;
356 Modes const &getModes() const
361 enum AttribType : unsigned char
368 ATTRIBTYPE_LAST = ATTRIBTYPE_UINT
371 bool hasBuiltinInput(spv::BuiltIn b) const
373 return inputBuiltins.find(b) != inputBuiltins.end();
380 int32_t DescriptorSet;
382 spv::BuiltIn BuiltIn;
385 int32_t MatrixStride;
386 bool HasLocation : 1;
387 bool HasComponent : 1;
388 bool HasDescriptorSet : 1;
393 bool NoPerspective : 1;
395 bool BufferBlock : 1;
397 bool HasArrayStride : 1;
398 bool HasMatrixStride : 1;
401 : Location{-1}, Component{0}, DescriptorSet{-1}, Binding{-1},
402 BuiltIn{static_cast<spv::BuiltIn>(-1)},
403 Offset{-1}, ArrayStride{-1}, MatrixStride{-1},
404 HasLocation{false}, HasComponent{false},
405 HasDescriptorSet{false}, HasBinding{false},
406 HasBuiltIn{false}, Flat{false}, Centroid{false},
407 NoPerspective{false}, Block{false}, BufferBlock{false},
408 HasOffset{false}, HasArrayStride{false}, HasMatrixStride{false}
412 Decorations(Decorations const &) = default;
414 void Apply(Decorations const &src);
416 void Apply(spv::Decoration decoration, uint32_t arg);
419 std::unordered_map<TypeOrObjectID, Decorations, TypeOrObjectID::Hash> decorations;
420 std::unordered_map<Type::ID, std::vector<Decorations>> memberDecorations;
422 struct InterfaceComponent
427 bool NoPerspective : 1;
430 : Type{ATTRIBTYPE_UNUSED}, Flat{false}, Centroid{false}, NoPerspective{false}
435 struct BuiltinMapping
438 uint32_t FirstComponent;
439 uint32_t SizeInComponents;
442 std::vector<InterfaceComponent> inputs;
443 std::vector<InterfaceComponent> outputs;
445 void emitProlog(SpirvRoutine *routine) const;
446 void emit(SpirvRoutine *routine, RValue<SIMD::Int> const &activeLaneMask) const;
447 void emitEpilog(SpirvRoutine *routine) const;
449 using BuiltInHash = std::hash<std::underlying_type<spv::BuiltIn>::type>;
450 std::unordered_map<spv::BuiltIn, BuiltinMapping, BuiltInHash> inputBuiltins;
451 std::unordered_map<spv::BuiltIn, BuiltinMapping, BuiltInHash> outputBuiltins;
453 Type const &getType(Type::ID id) const
455 auto it = types.find(id);
456 ASSERT_MSG(it != types.end(), "Unknown type %d", id.value());
460 Object const &getObject(Object::ID id) const
462 auto it = defs.find(id);
463 ASSERT_MSG(it != defs.end(), "Unknown object %d", id.value());
467 Block const &getBlock(Block::ID id) const
469 auto it = blocks.find(id);
470 ASSERT_MSG(it != blocks.end(), "Unknown block %d", id.value());
476 static volatile int serialCounter;
478 HandleMap<Type> types;
479 HandleMap<Object> defs;
480 HandleMap<Block> blocks;
481 Block::ID mainBlockId; // Block of the entry point function.
483 // DeclareType creates a Type for the given OpTypeX instruction, storing
484 // it into the types map. It is called from the analysis pass (constructor).
485 void DeclareType(InsnIterator insn);
487 void ProcessExecutionMode(InsnIterator it);
489 uint32_t ComputeTypeSize(InsnIterator insn);
490 void ApplyDecorationsForId(Decorations *d, TypeOrObjectID id) const;
491 void ApplyDecorationsForIdMember(Decorations *d, Type::ID id, uint32_t member) const;
493 // Returns true if data in the given storage class is word-interleaved
494 // by each SIMD vector lane, otherwise data is linerally stored.
496 // A 'lane' is a component of a SIMD vector register.
497 // Given 4 consecutive loads/stores of 4 SIMD vector registers:
499 // "StorageInterleavedByLane":
501 // Ptr+0:Reg0.x | Ptr+1:Reg0.y | Ptr+2:Reg0.z | Ptr+3:Reg0.w
502 // --------------+--------------+--------------+--------------
503 // Ptr+4:Reg1.x | Ptr+5:Reg1.y | Ptr+6:Reg1.z | Ptr+7:Reg1.w
504 // --------------+--------------+--------------+--------------
505 // Ptr+8:Reg2.x | Ptr+9:Reg2.y | Ptr+a:Reg2.z | Ptr+b:Reg2.w
506 // --------------+--------------+--------------+--------------
507 // Ptr+c:Reg3.x | Ptr+d:Reg3.y | Ptr+e:Reg3.z | Ptr+f:Reg3.w
509 // Not "StorageInterleavedByLane":
511 // Ptr+0:Reg0.x | Ptr+0:Reg0.y | Ptr+0:Reg0.z | Ptr+0:Reg0.w
512 // --------------+--------------+--------------+--------------
513 // Ptr+1:Reg1.x | Ptr+1:Reg1.y | Ptr+1:Reg1.z | Ptr+1:Reg1.w
514 // --------------+--------------+--------------+--------------
515 // Ptr+2:Reg2.x | Ptr+2:Reg2.y | Ptr+2:Reg2.z | Ptr+2:Reg2.w
516 // --------------+--------------+--------------+--------------
517 // Ptr+3:Reg3.x | Ptr+3:Reg3.y | Ptr+3:Reg3.z | Ptr+3:Reg3.w
519 static bool IsStorageInterleavedByLane(spv::StorageClass storageClass);
522 int VisitInterfaceInner(Type::ID id, Decorations d, F f) const;
525 void VisitInterface(Object::ID id, F f) const;
527 uint32_t GetConstantInt(Object::ID id) const;
528 Object& CreateConstant(InsnIterator it);
530 void ProcessInterfaceVariable(Object &object);
532 SIMD::Int WalkExplicitLayoutAccessChain(Object::ID id, uint32_t numIndexes, uint32_t const *indexIds, SpirvRoutine *routine) const;
533 SIMD::Int WalkAccessChain(Object::ID id, uint32_t numIndexes, uint32_t const *indexIds, SpirvRoutine *routine) const;
534 uint32_t WalkLiteralAccessChain(Type::ID id, uint32_t numIndexes, uint32_t const *indexes) const;
536 // EmitState holds control-flow state for the emit() pass.
540 RValue<SIMD::Int> activeLaneMask() const
542 ASSERT(activeLaneMaskValue != nullptr);
543 return RValue<SIMD::Int>(activeLaneMaskValue);
546 void setActiveLaneMask(RValue<SIMD::Int> mask)
548 activeLaneMaskValue = mask.value;
551 // Add a new active lane mask edge from the current block to out.
552 // The edge mask value will be (mask AND activeLaneMaskValue).
553 // If multiple active lane masks are added for the same edge, then
554 // they will be ORed together.
555 void addOutputActiveLaneMaskEdge(Block::ID out, RValue<SIMD::Int> mask);
557 // Add a new active lane mask for the edge from -> to.
558 // If multiple active lane masks are added for the same edge, then
559 // they will be ORed together.
560 void addActiveLaneMaskEdge(Block::ID from, Block::ID to, RValue<SIMD::Int> mask);
562 // Lookup the active lane mask for the edge from -> to.
563 // Asserts if the edge does not exist.
564 RValue<SIMD::Int> getActiveLaneMaskEdge(Block::ID from, Block::ID to);
566 SpirvRoutine *routine = nullptr; // The current routine being built.
567 rr::Value *activeLaneMaskValue = nullptr; // The current active lane mask.
568 Block::ID currentBlock; // The current block being built.
569 Block::Set visited; // Blocks already built.
570 std::unordered_map<Block::Edge, RValue<SIMD::Int>, Block::Edge::Hash> edgeActiveLaneMasks;
573 // EmitResult is an enumerator of result values from the Emit functions.
574 enum class EmitResult
576 Continue, // No termination instructions.
577 Terminator, // Reached a termination instruction.
580 // existsPath returns true if there's a direct or indirect flow from
581 // the 'from' block to the 'to' block.
582 bool existsPath(Block::ID from, Block::ID to) const;
584 void EmitBlock(Block::ID id, EmitState *state) const;
585 void EmitInstructions(InsnIterator begin, InsnIterator end, EmitState *state) const;
586 void EmitLoop(EmitState *state) const;
587 EmitResult EmitInstruction(InsnIterator insn, EmitState *state) const;
589 // Emit pass instructions:
590 EmitResult EmitVariable(InsnIterator insn, EmitState *state) const;
591 EmitResult EmitLoad(InsnIterator insn, EmitState *state) const;
592 EmitResult EmitStore(InsnIterator insn, EmitState *state) const;
593 EmitResult EmitAccessChain(InsnIterator insn, EmitState *state) const;
594 EmitResult EmitCompositeConstruct(InsnIterator insn, EmitState *state) const;
595 EmitResult EmitCompositeInsert(InsnIterator insn, EmitState *state) const;
596 EmitResult EmitCompositeExtract(InsnIterator insn, EmitState *state) const;
597 EmitResult EmitVectorShuffle(InsnIterator insn, EmitState *state) const;
598 EmitResult EmitVectorTimesScalar(InsnIterator insn, EmitState *state) const;
599 EmitResult EmitMatrixTimesVector(InsnIterator insn, EmitState *state) const;
600 EmitResult EmitVectorTimesMatrix(InsnIterator insn, EmitState *state) const;
601 EmitResult EmitMatrixTimesMatrix(InsnIterator insn, EmitState *state) const;
602 EmitResult EmitVectorExtractDynamic(InsnIterator insn, EmitState *state) const;
603 EmitResult EmitVectorInsertDynamic(InsnIterator insn, EmitState *state) const;
604 EmitResult EmitUnaryOp(InsnIterator insn, EmitState *state) const;
605 EmitResult EmitBinaryOp(InsnIterator insn, EmitState *state) const;
606 EmitResult EmitDot(InsnIterator insn, EmitState *state) const;
607 EmitResult EmitSelect(InsnIterator insn, EmitState *state) const;
608 EmitResult EmitExtendedInstruction(InsnIterator insn, EmitState *state) const;
609 EmitResult EmitAny(InsnIterator insn, EmitState *state) const;
610 EmitResult EmitAll(InsnIterator insn, EmitState *state) const;
611 EmitResult EmitBranch(InsnIterator insn, EmitState *state) const;
612 EmitResult EmitBranchConditional(InsnIterator insn, EmitState *state) const;
613 EmitResult EmitSwitch(InsnIterator insn, EmitState *state) const;
614 EmitResult EmitUnreachable(InsnIterator insn, EmitState *state) const;
615 EmitResult EmitReturn(InsnIterator insn, EmitState *state) const;
616 EmitResult EmitPhi(InsnIterator insn, EmitState *state) const;
618 // OpcodeName() returns the name of the opcode op.
619 // If NDEBUG is defined, then OpcodeName() will only return the numerical code.
620 static std::string OpcodeName(spv::Op op);
621 static std::memory_order MemoryOrder(spv::MemorySemanticsMask memorySemantics);
623 // Helper as we often need to take dot products as part of doing other things.
624 SIMD::Float Dot(unsigned numComponents, GenericValue const & x, GenericValue const & y) const;
630 SpirvRoutine(vk::PipelineLayout const *pipelineLayout);
632 using Value = Array<SIMD::Float>;
634 vk::PipelineLayout const * const pipelineLayout;
636 std::unordered_map<SpirvShader::Object::ID, Value> lvalues;
638 std::unordered_map<SpirvShader::Object::ID, Intermediate> intermediates;
640 std::unordered_map<SpirvShader::Object::ID, Pointer<Byte> > physicalPointers;
642 Value inputs = Value{MAX_INTERFACE_COMPONENTS};
643 Value outputs = Value{MAX_INTERFACE_COMPONENTS};
645 std::array<Pointer<Byte>, vk::MAX_BOUND_DESCRIPTOR_SETS> descriptorSets;
646 Pointer<Byte> pushConstants;
648 void createLvalue(SpirvShader::Object::ID id, uint32_t size)
650 lvalues.emplace(id, Value(size));
653 Intermediate& createIntermediate(SpirvShader::Object::ID id, uint32_t size)
655 auto it = intermediates.emplace(std::piecewise_construct,
656 std::forward_as_tuple(id),
657 std::forward_as_tuple(size));
658 return it.first->second;
661 Value& getValue(SpirvShader::Object::ID id)
663 auto it = lvalues.find(id);
664 ASSERT_MSG(it != lvalues.end(), "Unknown value %d", id.value());
668 Intermediate const& getIntermediate(SpirvShader::Object::ID id) const
670 auto it = intermediates.find(id);
671 ASSERT_MSG(it != intermediates.end(), "Unknown intermediate %d", id.value());
675 Pointer<Byte>& getPhysicalPointer(SpirvShader::Object::ID id)
677 auto it = physicalPointers.find(id);
678 ASSERT_MSG(it != physicalPointers.end(), "Unknown physical pointer %d", id.value());
685 // Generic wrapper over either per-lane intermediate value, or a constant.
686 // Constants are transparently widened to per-lane values in operator[].
687 // This is appropriate in most cases -- if we're not going to do something
688 // significantly different based on whether the value is uniform across lanes.
690 SpirvShader::Object const &obj;
691 Intermediate const *intermediate;
694 GenericValue(SpirvShader const *shader, SpirvRoutine const *routine, SpirvShader::Object::ID objId) :
695 obj(shader->getObject(objId)),
696 intermediate(obj.kind == SpirvShader::Object::Kind::Value ? &routine->getIntermediate(objId) : nullptr) {}
698 RValue<SIMD::Float> Float(uint32_t i) const
700 if (intermediate != nullptr)
702 return intermediate->Float(i);
704 auto constantValue = reinterpret_cast<float *>(obj.constantValue.get());
705 return RValue<SIMD::Float>(constantValue[i]);
708 RValue<SIMD::Int> Int(uint32_t i) const
710 return As<SIMD::Int>(Float(i));
713 RValue<SIMD::UInt> UInt(uint32_t i) const
715 return As<SIMD::UInt>(Float(i));
721 #endif // sw_SpirvShader_hpp