1 // Copyright 2018 The SwiftShader Authors. All Rights Reserved.
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
7 // http://www.apache.org/licenses/LICENSE-2.0
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
15 #ifndef sw_SpirvShader_hpp
16 #define sw_SpirvShader_hpp
18 #include "ShaderCore.hpp"
19 #include "SpirvID.hpp"
20 #include "System/Types.hpp"
21 #include "Vulkan/VkDebug.hpp"
22 #include "Vulkan/VkConfig.h"
29 #include <unordered_map>
31 #include <type_traits>
33 #include <spirv/unified1/spirv.hpp>
34 #include <Device/Config.hpp>
43 // Forward declarations.
47 // SIMD contains types that represent multiple scalars packed into a single
48 // vector data type. Types in the SIMD namespace provide a semantic hint
49 // that the data should be treated as a per-execution-lane scalar instead of
50 // a typical euclidean-style vector type.
53 // Width is the number of per-lane scalars packed into each SIMD vector.
54 static constexpr int Width = 4;
56 using Float = rr::Float4;
58 using UInt = rr::UInt4;
61 // Incrementally constructed complex bundle of rvalues
62 // Effectively a restricted vector, supporting only:
63 // - allocation to a (runtime-known) fixed size
64 // - in-place construction of elements
69 using Scalar = RValue<SIMD::Float>;
71 Intermediate(uint32_t size) : contents(new ContentsType[size]), size(size) {
72 #if !defined(NDEBUG) || defined(DCHECK_ALWAYS_ON)
73 memset(contents, 0, sizeof(ContentsType) * size);
79 for (auto i = 0u; i < size; i++)
80 reinterpret_cast<Scalar *>(&contents[i])->~Scalar();
84 void emplace(uint32_t n, Scalar&& value)
87 ASSERT(reinterpret_cast<Scalar const *>(&contents[n])->value == nullptr);
88 new (&contents[n]) Scalar(value);
91 void emplace(uint32_t n, const Scalar& value)
94 ASSERT(reinterpret_cast<Scalar const *>(&contents[n])->value == nullptr);
95 new (&contents[n]) Scalar(value);
98 // Emplace with cast helpers.
99 void emplace(uint32_t n, const RValue<SIMD::Int>& value) { emplace(n, As<SIMD::Float>(value)); }
100 void emplace(uint32_t n, const RValue<SIMD::UInt>& value) { emplace(n, As<SIMD::Float>(value)); }
102 // Value retrieval functions.
103 RValue<SIMD::Float> Float(uint32_t i) const
106 auto scalar = reinterpret_cast<Scalar const *>(&contents[i]);
107 ASSERT(scalar->value != nullptr);
110 RValue<SIMD::Int> Int(uint32_t i) const { return As<SIMD::Int>(Float(i)); }
111 RValue<SIMD::UInt> UInt(uint32_t i) const { return As<SIMD::UInt>(Float(i)); }
113 // No copy/move construction or assignment
114 Intermediate(Intermediate const &) = delete;
115 Intermediate(Intermediate &&) = delete;
116 Intermediate & operator=(Intermediate const &) = delete;
117 Intermediate & operator=(Intermediate &&) = delete;
120 using ContentsType = std::aligned_storage<sizeof(Scalar), alignof(Scalar)>::type;
122 ContentsType *contents;
129 using InsnStore = std::vector<uint32_t>;
132 /* Pseudo-iterator over SPIRV instructions, designed to support range-based-for. */
135 InsnStore::const_iterator iter;
138 spv::Op opcode() const
140 return static_cast<spv::Op>(*iter & spv::OpCodeMask);
143 uint32_t wordCount() const
145 return *iter >> spv::WordCountShift;
148 uint32_t word(uint32_t n) const
150 ASSERT(n < wordCount());
154 uint32_t const * wordPointer(uint32_t n) const
156 ASSERT(n < wordCount());
160 bool operator!=(InsnIterator const &other) const
162 return iter != other.iter;
165 InsnIterator operator*() const
170 InsnIterator &operator++()
176 InsnIterator const operator++(int)
178 InsnIterator ret{*this};
183 InsnIterator(InsnIterator const &other) = default;
185 InsnIterator() = default;
187 explicit InsnIterator(InsnStore::const_iterator iter) : iter{iter}
192 /* range-based-for interface */
193 InsnIterator begin() const
195 return InsnIterator{insns.cbegin() + 5};
198 InsnIterator end() const
200 return InsnIterator{insns.cend()};
206 using ID = SpirvID<Type>;
208 InsnIterator definition;
209 spv::StorageClass storageClass = static_cast<spv::StorageClass>(-1);
210 uint32_t sizeInComponents = 0;
211 bool isBuiltInBlock = false;
213 // Inner element type for pointers, arrays, vectors and matrices.
220 using ID = SpirvID<Object>;
222 InsnIterator definition;
225 std::unique_ptr<uint32_t[]> constantValue = nullptr;
229 Unknown, /* for paranoia -- if we get left with an object in this state, the module was broken */
230 Variable, // TODO: Document
231 InterfaceVariable, // TODO: Document
232 Constant, // Values held by Object::constantValue
233 Value, // Values held by SpirvRoutine::intermediates
234 PhysicalPointer, // Pointer held by SpirvRoutine::physicalPointers
235 } kind = Kind::Unknown;
238 // Block is an interval of SPIR-V instructions, starting with the
239 // opening OpLabel, and ending with a termination instruction.
243 using ID = SpirvID<Block>;
246 Block(const Block& other) = default;
247 explicit Block(InsnIterator begin, InsnIterator end) : begin_(begin), end_(end) {}
249 /* range-based-for interface */
250 inline InsnIterator begin() const { return begin_; }
251 inline InsnIterator end() const { return end_; }
258 struct TypeOrObject {}; // Dummy struct to represent a Type or Object.
260 // TypeOrObjectID is an identifier that represents a Type or an Object,
261 // and supports implicit casting to and from Type::ID or Object::ID.
262 class TypeOrObjectID : public SpirvID<TypeOrObject>
265 using Hash = std::hash<SpirvID<TypeOrObject>>;
267 inline TypeOrObjectID(uint32_t id) : SpirvID(id) {}
268 inline TypeOrObjectID(Type::ID id) : SpirvID(id.value()) {}
269 inline TypeOrObjectID(Object::ID id) : SpirvID(id.value()) {}
270 inline operator Type::ID() const { return Type::ID(value()); }
271 inline operator Object::ID() const { return Object::ID(value()); }
274 int getSerialID() const
279 explicit SpirvShader(InsnStore const &insns);
283 bool EarlyFragmentTests : 1;
284 bool DepthReplacing : 1;
285 bool DepthGreater : 1;
287 bool DepthUnchanged : 1;
288 bool ContainsKill : 1;
289 bool NeedsCentroid : 1;
291 // Compute workgroup dimensions
292 int WorkgroupSizeX = 1, WorkgroupSizeY = 1, WorkgroupSizeZ = 1;
295 Modes const &getModes() const
300 enum AttribType : unsigned char
307 ATTRIBTYPE_LAST = ATTRIBTYPE_UINT
310 bool hasBuiltinInput(spv::BuiltIn b) const
312 return inputBuiltins.find(b) != inputBuiltins.end();
319 int32_t DescriptorSet;
321 spv::BuiltIn BuiltIn;
324 int32_t MatrixStride;
325 bool HasLocation : 1;
326 bool HasComponent : 1;
327 bool HasDescriptorSet : 1;
332 bool NoPerspective : 1;
334 bool BufferBlock : 1;
336 bool HasArrayStride : 1;
337 bool HasMatrixStride : 1;
340 : Location{-1}, Component{0}, DescriptorSet{-1}, Binding{-1},
341 BuiltIn{static_cast<spv::BuiltIn>(-1)},
342 Offset{-1}, ArrayStride{-1}, MatrixStride{-1},
343 HasLocation{false}, HasComponent{false},
344 HasDescriptorSet{false}, HasBinding{false},
345 HasBuiltIn{false}, Flat{false}, Centroid{false},
346 NoPerspective{false}, Block{false}, BufferBlock{false},
347 HasOffset{false}, HasArrayStride{false}, HasMatrixStride{false}
351 Decorations(Decorations const &) = default;
353 void Apply(Decorations const &src);
355 void Apply(spv::Decoration decoration, uint32_t arg);
358 std::unordered_map<TypeOrObjectID, Decorations, TypeOrObjectID::Hash> decorations;
359 std::unordered_map<Type::ID, std::vector<Decorations>> memberDecorations;
361 struct InterfaceComponent
366 bool NoPerspective : 1;
369 : Type{ATTRIBTYPE_UNUSED}, Flat{false}, Centroid{false}, NoPerspective{false}
374 struct BuiltinMapping
377 uint32_t FirstComponent;
378 uint32_t SizeInComponents;
381 std::vector<InterfaceComponent> inputs;
382 std::vector<InterfaceComponent> outputs;
384 void emitProlog(SpirvRoutine *routine) const;
385 void emit(SpirvRoutine *routine) const;
386 void emitEpilog(SpirvRoutine *routine) const;
388 using BuiltInHash = std::hash<std::underlying_type<spv::BuiltIn>::type>;
389 std::unordered_map<spv::BuiltIn, BuiltinMapping, BuiltInHash> inputBuiltins;
390 std::unordered_map<spv::BuiltIn, BuiltinMapping, BuiltInHash> outputBuiltins;
392 Type const &getType(Type::ID id) const
394 auto it = types.find(id);
395 ASSERT(it != types.end());
399 Object const &getObject(Object::ID id) const
401 auto it = defs.find(id);
402 ASSERT(it != defs.end());
406 Block const &getBlock(Block::ID id) const
408 auto it = blocks.find(id);
409 ASSERT(it != blocks.end());
415 static volatile int serialCounter;
417 HandleMap<Type> types;
418 HandleMap<Object> defs;
419 HandleMap<Block> blocks;
420 Block::ID mainBlockId; // Block of the entry point function.
422 void EmitBlock(SpirvRoutine *routine, Block const &block) const;
423 void EmitInstruction(SpirvRoutine *routine, InsnIterator insn) const;
425 // DeclareType creates a Type for the given OpTypeX instruction, storing
426 // it into the types map. It is called from the analysis pass (constructor).
427 void DeclareType(InsnIterator insn);
429 void ProcessExecutionMode(InsnIterator it);
431 uint32_t ComputeTypeSize(InsnIterator insn);
432 void ApplyDecorationsForId(Decorations *d, TypeOrObjectID id) const;
433 void ApplyDecorationsForIdMember(Decorations *d, Type::ID id, uint32_t member) const;
435 // Returns true if data in the given storage class is word-interleaved
436 // by each SIMD vector lane, otherwise data is linerally stored.
438 // A 'lane' is a component of a SIMD vector register.
439 // Given 4 consecutive loads/stores of 4 SIMD vector registers:
441 // "StorageInterleavedByLane":
443 // Ptr+0:Reg0.x | Ptr+1:Reg0.y | Ptr+2:Reg0.z | Ptr+3:Reg0.w
444 // --------------+--------------+--------------+--------------
445 // Ptr+4:Reg1.x | Ptr+5:Reg1.y | Ptr+6:Reg1.z | Ptr+7:Reg1.w
446 // --------------+--------------+--------------+--------------
447 // Ptr+8:Reg2.x | Ptr+9:Reg2.y | Ptr+a:Reg2.z | Ptr+b:Reg2.w
448 // --------------+--------------+--------------+--------------
449 // Ptr+c:Reg3.x | Ptr+d:Reg3.y | Ptr+e:Reg3.z | Ptr+f:Reg3.w
451 // Not "StorageInterleavedByLane":
453 // Ptr+0:Reg0.x | Ptr+0:Reg0.y | Ptr+0:Reg0.z | Ptr+0:Reg0.w
454 // --------------+--------------+--------------+--------------
455 // Ptr+1:Reg1.x | Ptr+1:Reg1.y | Ptr+1:Reg1.z | Ptr+1:Reg1.w
456 // --------------+--------------+--------------+--------------
457 // Ptr+2:Reg2.x | Ptr+2:Reg2.y | Ptr+2:Reg2.z | Ptr+2:Reg2.w
458 // --------------+--------------+--------------+--------------
459 // Ptr+3:Reg3.x | Ptr+3:Reg3.y | Ptr+3:Reg3.z | Ptr+3:Reg3.w
461 static bool IsStorageInterleavedByLane(spv::StorageClass storageClass);
464 int VisitInterfaceInner(Type::ID id, Decorations d, F f) const;
467 void VisitInterface(Object::ID id, F f) const;
469 uint32_t GetConstantInt(Object::ID id) const;
470 Object& CreateConstant(InsnIterator it);
472 void ProcessInterfaceVariable(Object &object);
474 SIMD::Int WalkAccessChain(Object::ID id, uint32_t numIndexes, uint32_t const *indexIds, SpirvRoutine *routine) const;
475 uint32_t WalkLiteralAccessChain(Type::ID id, uint32_t numIndexes, uint32_t const *indexes) const;
477 // Emit pass instructions:
478 void EmitVariable(InsnIterator insn, SpirvRoutine *routine) const;
479 void EmitLoad(InsnIterator insn, SpirvRoutine *routine) const;
480 void EmitStore(InsnIterator insn, SpirvRoutine *routine) const;
481 void EmitAccessChain(InsnIterator insn, SpirvRoutine *routine) const;
482 void EmitCompositeConstruct(InsnIterator insn, SpirvRoutine *routine) const;
483 void EmitCompositeInsert(InsnIterator insn, SpirvRoutine *routine) const;
484 void EmitCompositeExtract(InsnIterator insn, SpirvRoutine *routine) const;
485 void EmitVectorShuffle(InsnIterator insn, SpirvRoutine *routine) const;
486 void EmitVectorTimesScalar(InsnIterator insn, SpirvRoutine *routine) const;
487 void EmitVectorExtractDynamic(InsnIterator insn, SpirvRoutine *routine) const;
488 void EmitVectorInsertDynamic(InsnIterator insn, SpirvRoutine *routine) const;
489 void EmitUnaryOp(InsnIterator insn, SpirvRoutine *routine) const;
490 void EmitBinaryOp(InsnIterator insn, SpirvRoutine *routine) const;
491 void EmitDot(InsnIterator insn, SpirvRoutine *routine) const;
492 void EmitSelect(InsnIterator insn, SpirvRoutine *routine) const;
493 void EmitExtendedInstruction(InsnIterator insn, SpirvRoutine *routine) const;
494 void EmitAny(InsnIterator insn, SpirvRoutine *routine) const;
495 void EmitAll(InsnIterator insn, SpirvRoutine *routine) const;
496 void EmitBranch(InsnIterator insn, SpirvRoutine *routine) const;
498 // OpcodeName returns the name of the opcode op.
499 // If NDEBUG is defined, then OpcodeName will only return the numerical code.
500 static std::string OpcodeName(spv::Op op);
502 // Helper as we often need to take dot products as part of doing other things.
503 SIMD::Float Dot(unsigned numComponents, GenericValue const & x, GenericValue const & y) const;
509 SpirvRoutine(vk::PipelineLayout const *pipelineLayout);
511 using Value = Array<SIMD::Float>;
513 vk::PipelineLayout const * const pipelineLayout;
515 std::unordered_map<SpirvShader::Object::ID, Value> lvalues;
517 std::unordered_map<SpirvShader::Object::ID, Intermediate> intermediates;
519 std::unordered_map<SpirvShader::Object::ID, Pointer<Byte> > physicalPointers;
521 Value inputs = Value{MAX_INTERFACE_COMPONENTS};
522 Value outputs = Value{MAX_INTERFACE_COMPONENTS};
524 SIMD::Int activeLaneMask = SIMD::Int(0xFFFFFFFF);
526 std::array<Pointer<Byte>, vk::MAX_BOUND_DESCRIPTOR_SETS> descriptorSets;
528 void createLvalue(SpirvShader::Object::ID id, uint32_t size)
530 lvalues.emplace(id, Value(size));
533 Intermediate& createIntermediate(SpirvShader::Object::ID id, uint32_t size)
535 auto it = intermediates.emplace(std::piecewise_construct,
536 std::forward_as_tuple(id),
537 std::forward_as_tuple(size));
538 return it.first->second;
541 Value& getValue(SpirvShader::Object::ID id)
543 auto it = lvalues.find(id);
544 ASSERT(it != lvalues.end());
548 Intermediate const& getIntermediate(SpirvShader::Object::ID id) const
550 auto it = intermediates.find(id);
551 ASSERT(it != intermediates.end());
555 Pointer<Byte>& getPhysicalPointer(SpirvShader::Object::ID id)
557 auto it = physicalPointers.find(id);
558 assert(it != physicalPointers.end());
565 // Generic wrapper over either per-lane intermediate value, or a constant.
566 // Constants are transparently widened to per-lane values in operator[].
567 // This is appropriate in most cases -- if we're not going to do something
568 // significantly different based on whether the value is uniform across lanes.
570 SpirvShader::Object const &obj;
571 Intermediate const *intermediate;
574 GenericValue(SpirvShader const *shader, SpirvRoutine const *routine, SpirvShader::Object::ID objId) :
575 obj(shader->getObject(objId)),
576 intermediate(obj.kind == SpirvShader::Object::Kind::Value ? &routine->getIntermediate(objId) : nullptr) {}
578 RValue<SIMD::Float> Float(uint32_t i) const
580 if (intermediate != nullptr)
582 return intermediate->Float(i);
584 auto constantValue = reinterpret_cast<float *>(obj.constantValue.get());
585 return RValue<SIMD::Float>(constantValue[i]);
588 RValue<SIMD::Int> Int(uint32_t i) const
590 return As<SIMD::Int>(Float(i));
593 RValue<SIMD::UInt> UInt(uint32_t i) const
595 return As<SIMD::UInt>(Float(i));
601 #endif // sw_SpirvShader_hpp