src/amd/common/ac_gpu_info.c

   1 /*
   2  * Copyright © 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining
   5  * a copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  13  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  15  * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
  16  * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  17  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  */
  25
  26 #include "ac_gpu_info.h"
  27 #include "sid.h"
  28 #include "gfx9d.h"
  29
  30 #include "util/u_math.h"
  31
  32 #include <stdio.h>
  33
  34 #include <xf86drm.h>
  35 #include <amdgpu_drm.h>
  36
  37 #include <amdgpu.h>
  38
  39 #define CIK_TILE_MODE_COLOR_2D                  14
  40
  41 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x)        (((x) >> 6) & 0x1f)
  42 #define     CIK__PIPE_CONFIG__ADDR_SURF_P2               0
  43 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16          4
  44 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16         5
  45 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32         6
  46 #define     CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32         7
  47 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16    8
  48 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16    9
  49 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16    10
  50 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16   11
  51 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16   12
  52 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32   13
  53 #define     CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32   14
  54 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16   16
  55 #define     CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16  17
  56
  57 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
  58 {
  59    unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
  60
  61    switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
  62    case CIK__PIPE_CONFIG__ADDR_SURF_P2:
  63        return 2;
  64    case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
  65    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
  66    case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
  67    case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
  68        return 4;
  69    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
  70    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
  71    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
  72    case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
  73    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
  74    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
  75    case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
  76        return 8;
  77    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
  78    case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
  79        return 16;
  80    default:
  81        fprintf(stderr, "Invalid CIK pipe configuration, assuming P2\n");
  82        assert(!"this should never occur");
  83        return 2;
  84    }
  85 }
  86
  87 static bool has_syncobj(int fd)
  88 {
  89         uint64_t value;
  90         if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
  91                 return false;
  92         return value ? true : false;
  93 }
  94
  95 bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
  96                        struct radeon_info *info,
  97                        struct amdgpu_gpu_info *amdinfo)
  98 {
  99         struct drm_amdgpu_info_device device_info = {};
 100         struct amdgpu_buffer_size_alignments alignment_info = {};
 101         struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {};
 102         struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {};
 103         struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {};
 104         struct amdgpu_gds_resource_info gds = {};
 105         uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
 106         int r, i, j;
 107         drmDevicePtr devinfo;
 108
 109         /* Get PCI info. */
 110         r = drmGetDevice2(fd, 0, &devinfo);
 111         if (r) {
 112                 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
 113                 return false;
 114         }
 115         info->pci_domain = devinfo->businfo.pci->domain;
 116         info->pci_bus = devinfo->businfo.pci->bus;
 117         info->pci_dev = devinfo->businfo.pci->dev;
 118         info->pci_func = devinfo->businfo.pci->func;
 119         drmFreeDevice(&devinfo);
 120
 121         /* Query hardware and driver information. */
 122         r = amdgpu_query_gpu_info(dev, amdinfo);
 123         if (r) {
 124                 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
 125                 return false;
 126         }
 127
 128         r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info),
 129                               &device_info);
 130         if (r) {
 131                 fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
 132                 return false;
 133         }
 134
 135         r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
 136         if (r) {
 137                 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
 138                 return false;
 139         }
 140
 141         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
 142         if (r) {
 143                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
 144                 return false;
 145         }
 146
 147         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
 148         if (r) {
 149                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
 150                 return false;
 151         }
 152
 153         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
 154         if (r) {
 155                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
 156                 return false;
 157         }
 158
 159         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
 160         if (r) {
 161                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
 162                 return false;
 163         }
 164
 165         if (info->drm_major == 3 && info->drm_minor >= 17) {
 166                 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
 167                 if (r) {
 168                         fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
 169                         return false;
 170                 }
 171         }
 172
 173         if (info->drm_major == 3 && info->drm_minor >= 17) {
 174                 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
 175                 if (r) {
 176                         fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
 177                         return false;
 178                 }
 179         }
 180
 181         if (info->drm_major == 3 && info->drm_minor >= 17) {
 182                 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
 183                 if (r) {
 184                         fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
 185                         return false;
 186                 }
 187         }
 188
 189         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
 190                                         &info->me_fw_version,
 191                                         &info->me_fw_feature);
 192         if (r) {
 193                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
 194                 return false;
 195         }
 196
 197         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
 198                                         &info->pfp_fw_version,
 199                                         &info->pfp_fw_feature);
 200         if (r) {
 201                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
 202                 return false;
 203         }
 204
 205         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
 206                                         &info->ce_fw_version,
 207                                         &info->ce_fw_feature);
 208         if (r) {
 209                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
 210                 return false;
 211         }
 212
 213         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0,
 214                                         &uvd_version, &uvd_feature);
 215         if (r) {
 216                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
 217                 return false;
 218         }
 219
 220         r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
 221         if (r) {
 222                 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
 223                 return false;
 224         }
 225
 226         r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0,
 227                                         &vce_version, &vce_feature);
 228         if (r) {
 229                 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
 230                 return false;
 231         }
 232
 233         r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
 234         if (r) {
 235                 fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
 236                 return false;
 237         }
 238
 239         r = amdgpu_query_gds_info(dev, &gds);
 240         if (r) {
 241                 fprintf(stderr, "amdgpu: amdgpu_query_gds_info failed.\n");
 242                 return false;
 243         }
 244
 245         if (info->drm_minor >= 9) {
 246                 struct drm_amdgpu_memory_info meminfo = {};
 247
 248                 r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
 249                 if (r) {
 250                         fprintf(stderr, "amdgpu: amdgpu_query_info(memory) failed.\n");
 251                         return false;
 252                 }
 253
 254                 /* Note: usable_heap_size values can be random and can't be relied on. */
 255                 info->gart_size = meminfo.gtt.total_heap_size;
 256                 info->vram_size = meminfo.vram.total_heap_size;
 257                 info->vram_vis_size = meminfo.cpu_accessible_vram.total_heap_size;
 258
 259                 info->max_alloc_size = MAX2(meminfo.vram.max_allocation,
 260                                             meminfo.gtt.max_allocation);
 261         } else {
 262                 /* This is a deprecated interface, which reports usable sizes
 263                  * (total minus pinned), but the pinned size computation is
 264                  * buggy, so the values returned from these functions can be
 265                  * random.
 266                  */
 267                 struct amdgpu_heap_info vram, vram_vis, gtt;
 268
 269                 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
 270                 if (r) {
 271                         fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
 272                         return false;
 273                 }
 274
 275                 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM,
 276                                         AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 277                                         &vram_vis);
 278                 if (r) {
 279                         fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
 280                         return false;
 281                 }
 282
 283                 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, &gtt);
 284                 if (r) {
 285                         fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
 286                         return false;
 287                 }
 288
 289                 info->gart_size = gtt.heap_size;
 290                 info->vram_size = vram.heap_size;
 291                 info->vram_vis_size = vram_vis.heap_size;
 292
 293                 /* The kernel can split large buffers in VRAM but not in GTT, so large
 294                  * allocations can fail or cause buffer movement failures in the kernel.
 295                  */
 296                 info->max_alloc_size = MAX2(info->vram_size * 0.9, info->gart_size * 0.7);
 297         }
 298
 299         /* Set chip identification. */
 300         info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
 301         info->vce_harvest_config = amdinfo->vce_harvest_config;
 302
 303         switch (info->pci_id) {
 304 #define CHIPSET(pci_id, cfamily) \
 305         case pci_id: \
 306                 info->family = CHIP_##cfamily; \
 307                 info->name = #cfamily; \
 308                 break;
 309 #include "pci_ids/radeonsi_pci_ids.h"
 310 #undef CHIPSET
 311
 312         default:
 313                 fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
 314                 return false;
 315         }
 316
 317         if (info->family >= CHIP_VEGA10)
 318                 info->chip_class = GFX9;
 319         else if (info->family >= CHIP_TONGA)
 320                 info->chip_class = VI;
 321         else if (info->family >= CHIP_BONAIRE)
 322                 info->chip_class = CIK;
 323         else if (info->family >= CHIP_TAHITI)
 324                 info->chip_class = SI;
 325         else {
 326                 fprintf(stderr, "amdgpu: Unknown family.\n");
 327                 return false;
 328         }
 329
 330         /* Set which chips have dedicated VRAM. */
 331         info->has_dedicated_vram =
 332                 !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
 333
 334         /* Set hardware information. */
 335         info->gds_size = gds.gds_total_size;
 336         info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
 337         /* convert the shader clock from KHz to MHz */
 338         info->max_shader_clock = amdinfo->max_engine_clk / 1000;
 339         info->num_tcc_blocks = device_info.num_tcc_blocks;
 340         info->max_se = amdinfo->num_shader_engines;
 341         info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
 342         info->has_hw_decode =
 343                 (uvd.available_rings != 0) || (vcn_dec.available_rings != 0);
 344         info->uvd_fw_version =
 345                 uvd.available_rings ? uvd_version : 0;
 346         info->vce_fw_version =
 347                 vce.available_rings ? vce_version : 0;
 348         info->uvd_enc_supported =
 349                 uvd_enc.available_rings ? true : false;
 350         info->has_userptr = true;
 351         info->has_syncobj = has_syncobj(fd);
 352         info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
 353         info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
 354         info->has_ctx_priority = info->drm_minor >= 22;
 355         /* TODO: Enable this once the kernel handles it efficiently. */
 356         info->has_local_buffers = info->drm_minor >= 20 &&
 357                                   !info->has_dedicated_vram;
 358         info->kernel_flushes_hdp_before_ib = true;
 359         info->htile_cmask_support_1d_tiling = true;
 360         info->si_TA_CS_BC_BASE_ADDR_allowed = true;
 361         info->has_bo_metadata = true;
 362         info->has_gpu_reset_status_query = true;
 363         info->has_gpu_reset_counter_query = false;
 364         info->has_eqaa_surface_allocator = true;
 365         info->has_format_bc1_through_bc7 = true;
 366         /* DRM 3.1.0 doesn't flush TC for VI correctly. */
 367         info->kernel_flushes_tc_l2_after_ib = info->chip_class != VI ||
 368                                               info->drm_minor >= 2;
 369         info->has_indirect_compute_dispatch = true;
 370         /* SI doesn't support unaligned loads. */
 371         info->has_unaligned_shader_loads = info->chip_class != SI;
 372         /* Disable sparse mappings on SI due to VM faults in CP DMA. Enable them once
 373          * these faults are mitigated in software.
 374          * Disable sparse mappings on GFX9 due to hangs.
 375          */
 376         info->has_sparse_vm_mappings =
 377                 info->chip_class >= CIK && info->chip_class <= VI &&
 378                 info->drm_minor >= 13;
 379         info->has_2d_tiling = true;
 380         info->has_read_registers_query = true;
 381
 382         info->num_render_backends = amdinfo->rb_pipes;
 383         /* The value returned by the kernel driver was wrong. */
 384         if (info->family == CHIP_KAVERI)
 385                 info->num_render_backends = 2;
 386
 387         info->clock_crystal_freq = amdinfo->gpu_counter_freq;
 388         if (!info->clock_crystal_freq) {
 389                 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
 390                 info->clock_crystal_freq = 1;
 391         }
 392         info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
 393         info->gb_addr_config = amdinfo->gb_addr_cfg;
 394         if (info->chip_class == GFX9) {
 395                 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
 396                 info->pipe_interleave_bytes =
 397                         256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
 398         } else {
 399                 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
 400                 info->pipe_interleave_bytes =
 401                         256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
 402         }
 403         info->r600_has_virtual_memory = true;
 404
 405         assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
 406         assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
 407
 408         info->num_sdma_rings = util_bitcount(dma.available_rings);
 409         info->num_compute_rings = util_bitcount(compute.available_rings);
 410
 411         /* Get the number of good compute units. */
 412         info->num_good_compute_units = 0;
 413         for (i = 0; i < info->max_se; i++)
 414                 for (j = 0; j < info->max_sh_per_se; j++)
 415                         info->num_good_compute_units +=
 416                                 util_bitcount(amdinfo->cu_bitmap[i][j]);
 417
 418         memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode,
 419                 sizeof(amdinfo->gb_tile_mode));
 420         info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
 421
 422         memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
 423                 sizeof(amdinfo->gb_macro_tile_mode));
 424
 425         info->pte_fragment_size = alignment_info.size_local;
 426         info->gart_page_size = alignment_info.size_remote;
 427
 428         if (info->chip_class == SI)
 429                 info->gfx_ib_pad_with_type2 = TRUE;
 430
 431         unsigned ib_align = 0;
 432         ib_align = MAX2(ib_align, gfx.ib_start_alignment);
 433         ib_align = MAX2(ib_align, compute.ib_start_alignment);
 434         ib_align = MAX2(ib_align, dma.ib_start_alignment);
 435         ib_align = MAX2(ib_align, uvd.ib_start_alignment);
 436         ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
 437         ib_align = MAX2(ib_align, vce.ib_start_alignment);
 438         ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
 439         ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
 440        assert(ib_align);
 441         info->ib_start_alignment = ib_align;
 442
 443         return true;
 444 }
 445
 446 void ac_compute_driver_uuid(char *uuid, size_t size)
 447 {
 448         char amd_uuid[] = "AMD-MESA-DRV";
 449
 450         assert(size >= sizeof(amd_uuid));
 451
 452         memset(uuid, 0, size);
 453         strncpy(uuid, amd_uuid, size);
 454 }
 455
 456 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
 457 {
 458         uint32_t *uint_uuid = (uint32_t*)uuid;
 459
 460         assert(size >= sizeof(uint32_t)*4);
 461
 462         /**
 463          * Use the device info directly instead of using a sha1. GL/VK UUIDs
 464          * are 16 byte vs 20 byte for sha1, and the truncation that would be
 465          * required would get rid of part of the little entropy we have.
 466          * */
 467         memset(uuid, 0, size);
 468         uint_uuid[0] = info->pci_domain;
 469         uint_uuid[1] = info->pci_bus;
 470         uint_uuid[2] = info->pci_dev;
 471         uint_uuid[3] = info->pci_func;
 472 }
 473
 474 void ac_print_gpu_info(struct radeon_info *info)
 475 {
 476         printf("Device info:\n");
 477         printf("    pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n",
 478                info->pci_domain, info->pci_bus,
 479                info->pci_dev, info->pci_func);
 480         printf("    pci_id = 0x%x\n", info->pci_id);
 481         printf("    family = %i\n", info->family);
 482         printf("    chip_class = %i\n", info->chip_class);
 483         printf("    num_compute_rings = %u\n", info->num_compute_rings);
 484         printf("    num_sdma_rings = %i\n", info->num_sdma_rings);
 485         printf("    clock_crystal_freq = %i\n", info->clock_crystal_freq);
 486         printf("    tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
 487
 488         printf("Memory info:\n");
 489         printf("    pte_fragment_size = %u\n", info->pte_fragment_size);
 490         printf("    gart_page_size = %u\n", info->gart_page_size);
 491         printf("    gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024*1024));
 492         printf("    vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024*1024));
 493         printf("    vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024*1024));
 494         printf("    gds_size = %u kB\n", info->gds_size / 1024);
 495         printf("    gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
 496         printf("    max_alloc_size = %i MB\n",
 497                (int)DIV_ROUND_UP(info->max_alloc_size, 1024*1024));
 498         printf("    min_alloc_size = %u\n", info->min_alloc_size);
 499         printf("    address32_hi = %u\n", info->address32_hi);
 500         printf("    has_dedicated_vram = %u\n", info->has_dedicated_vram);
 501
 502         printf("CP info:\n");
 503         printf("    gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
 504         printf("    ib_start_alignment = %u\n", info->ib_start_alignment);
 505         printf("    me_fw_version = %i\n", info->me_fw_version);
 506         printf("    me_fw_feature = %i\n", info->me_fw_feature);
 507         printf("    pfp_fw_version = %i\n", info->pfp_fw_version);
 508         printf("    pfp_fw_feature = %i\n", info->pfp_fw_feature);
 509         printf("    ce_fw_version = %i\n", info->ce_fw_version);
 510         printf("    ce_fw_feature = %i\n", info->ce_fw_feature);
 511
 512         printf("Multimedia info:\n");
 513         printf("    has_hw_decode = %u\n", info->has_hw_decode);
 514         printf("    uvd_enc_supported = %u\n", info->uvd_enc_supported);
 515         printf("    uvd_fw_version = %u\n", info->uvd_fw_version);
 516         printf("    vce_fw_version = %u\n", info->vce_fw_version);
 517         printf("    vce_harvest_config = %i\n", info->vce_harvest_config);
 518
 519         printf("Kernel & winsys capabilities:\n");
 520         printf("    drm = %i.%i.%i\n", info->drm_major,
 521                info->drm_minor, info->drm_patchlevel);
 522         printf("    has_userptr = %i\n", info->has_userptr);
 523         printf("    has_syncobj = %u\n", info->has_syncobj);
 524         printf("    has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
 525         printf("    has_fence_to_handle = %u\n", info->has_fence_to_handle);
 526         printf("    has_ctx_priority = %u\n", info->has_ctx_priority);
 527         printf("    has_local_buffers = %u\n", info->has_local_buffers);
 528         printf("    kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
 529         printf("    htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
 530         printf("    si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
 531         printf("    has_bo_metadata = %u\n", info->has_bo_metadata);
 532         printf("    has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
 533         printf("    has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query);
 534         printf("    has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
 535         printf("    has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
 536         printf("    kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
 537         printf("    has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
 538         printf("    has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
 539         printf("    has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
 540         printf("    has_2d_tiling = %u\n", info->has_2d_tiling);
 541         printf("    has_read_registers_query = %u\n", info->has_read_registers_query);
 542
 543         printf("Shader core info:\n");
 544         printf("    max_shader_clock = %i\n", info->max_shader_clock);
 545         printf("    num_good_compute_units = %i\n", info->num_good_compute_units);
 546         printf("    num_tcc_blocks = %i\n", info->num_tcc_blocks);
 547         printf("    max_se = %i\n", info->max_se);
 548         printf("    max_sh_per_se = %i\n", info->max_sh_per_se);
 549
 550         printf("Render backend info:\n");
 551         printf("    num_render_backends = %i\n", info->num_render_backends);
 552         printf("    num_tile_pipes = %i\n", info->num_tile_pipes);
 553         printf("    pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
 554         printf("    enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
 555         printf("    max_alignment = %u\n", (unsigned)info->max_alignment);
 556
 557         printf("GB_ADDR_CONFIG:\n");
 558         if (info->chip_class >= GFX9) {
 559                 printf("    num_pipes = %u\n",
 560                        1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
 561                 printf("    pipe_interleave_size = %u\n",
 562                        256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
 563                 printf("    max_compressed_frags = %u\n",
 564                        1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
 565                 printf("    bank_interleave_size = %u\n",
 566                        1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
 567                 printf("    num_banks = %u\n",
 568                        1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
 569                 printf("    shader_engine_tile_size = %u\n",
 570                        16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
 571                 printf("    num_shader_engines = %u\n",
 572                        1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
 573                 printf("    num_gpus = %u (raw)\n",
 574                        G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
 575                 printf("    multi_gpu_tile_size = %u (raw)\n",
 576                        G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
 577                 printf("    num_rb_per_se = %u\n",
 578                        1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
 579                 printf("    row_size = %u\n",
 580                        1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
 581                 printf("    num_lower_pipes = %u (raw)\n",
 582                        G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
 583                 printf("    se_enable = %u (raw)\n",
 584                        G_0098F8_SE_ENABLE(info->gb_addr_config));
 585         } else {
 586                 printf("    num_pipes = %u\n",
 587                        1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
 588                 printf("    pipe_interleave_size = %u\n",
 589                        256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
 590                 printf("    bank_interleave_size = %u\n",
 591                        1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
 592                 printf("    num_shader_engines = %u\n",
 593                        1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
 594                 printf("    shader_engine_tile_size = %u\n",
 595                        16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
 596                 printf("    num_gpus = %u (raw)\n",
 597                        G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
 598                 printf("    multi_gpu_tile_size = %u (raw)\n",
 599                        G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
 600                 printf("    row_size = %u\n",
 601                        1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
 602                 printf("    num_lower_pipes = %u (raw)\n",
 603                        G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
 604         }
 605 }
 606
 607 int
 608 ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
 609 {
 610         if (chip_class >= GFX9)
 611                 return -1;
 612
 613         switch (family) {
 614         case CHIP_OLAND:
 615         case CHIP_HAINAN:
 616         case CHIP_KAVERI:
 617         case CHIP_KABINI:
 618         case CHIP_MULLINS:
 619         case CHIP_ICELAND:
 620         case CHIP_CARRIZO:
 621         case CHIP_STONEY:
 622                 return 16;
 623         case CHIP_TAHITI:
 624         case CHIP_PITCAIRN:
 625         case CHIP_VERDE:
 626         case CHIP_BONAIRE:
 627         case CHIP_HAWAII:
 628         case CHIP_TONGA:
 629         case CHIP_FIJI:
 630         case CHIP_POLARIS10:
 631         case CHIP_POLARIS11:
 632         case CHIP_POLARIS12:
 633         case CHIP_VEGAM:
 634                 return 32;
 635         default:
 636                 unreachable("Unknown GPU");
 637         }
 638 }
 639
 640 void
 641 ac_get_raster_config(struct radeon_info *info,
 642                      uint32_t *raster_config_p,
 643                      uint32_t *raster_config_1_p)
 644 {
 645         unsigned raster_config, raster_config_1;
 646
 647         switch (info->family) {
 648         /* 1 SE / 1 RB */
 649         case CHIP_HAINAN:
 650         case CHIP_KABINI:
 651         case CHIP_MULLINS:
 652         case CHIP_STONEY:
 653                 raster_config = 0x00000000;
 654                 raster_config_1 = 0x00000000;
 655                 break;
 656         /* 1 SE / 4 RBs */
 657         case CHIP_VERDE:
 658                 raster_config = 0x0000124a;
 659                 raster_config_1 = 0x00000000;
 660                 break;
 661         /* 1 SE / 2 RBs (Oland is special) */
 662         case CHIP_OLAND:
 663                 raster_config = 0x00000082;
 664                 raster_config_1 = 0x00000000;
 665                 break;
 666         /* 1 SE / 2 RBs */
 667         case CHIP_KAVERI:
 668         case CHIP_ICELAND:
 669         case CHIP_CARRIZO:
 670                 raster_config = 0x00000002;
 671                 raster_config_1 = 0x00000000;
 672                 break;
 673         /* 2 SEs / 4 RBs */
 674         case CHIP_BONAIRE:
 675         case CHIP_POLARIS11:
 676         case CHIP_POLARIS12:
 677                 raster_config = 0x16000012;
 678                 raster_config_1 = 0x00000000;
 679                 break;
 680         /* 2 SEs / 8 RBs */
 681         case CHIP_TAHITI:
 682         case CHIP_PITCAIRN:
 683                 raster_config = 0x2a00126a;
 684                 raster_config_1 = 0x00000000;
 685                 break;
 686         /* 4 SEs / 8 RBs */
 687         case CHIP_TONGA:
 688         case CHIP_POLARIS10:
 689                 raster_config = 0x16000012;
 690                 raster_config_1 = 0x0000002a;
 691                 break;
 692         /* 4 SEs / 16 RBs */
 693         case CHIP_HAWAII:
 694         case CHIP_FIJI:
 695         case CHIP_VEGAM:
 696                 raster_config = 0x3a00161a;
 697                 raster_config_1 = 0x0000002e;
 698                 break;
 699         default:
 700                 fprintf(stderr,
 701                         "ac: Unknown GPU, using 0 for raster_config\n");
 702                 raster_config = 0x00000000;
 703                 raster_config_1 = 0x00000000;
 704                 break;
 705         }
 706
 707         /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
 708          * This decreases performance by up to 50% when the RB is the bottleneck.
 709          */
 710         if (info->family == CHIP_KAVERI && info->drm_major == 2)
 711                 raster_config = 0x00000000;
 712
 713         /* Fiji: Old kernels have incorrect tiling config. This decreases
 714          * RB performance by 25%. (it disables 1 RB in the second packer)
 715          */
 716         if (info->family == CHIP_FIJI &&
 717             info->cik_macrotile_mode_array[0] == 0x000000e8) {
 718                 raster_config = 0x16000012;
 719                 raster_config_1 = 0x0000002a;
 720         }
 721
 722         *raster_config_p = raster_config;
 723         *raster_config_1_p = raster_config_1;
 724 }
 725
 726 void
 727 ac_get_harvested_configs(struct radeon_info *info,
 728                          unsigned raster_config,
 729                          unsigned *cik_raster_config_1_p,
 730                          unsigned *raster_config_se)
 731 {
 732         unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
 733         unsigned num_se = MAX2(info->max_se, 1);
 734         unsigned rb_mask = info->enabled_rb_mask;
 735         unsigned num_rb = MIN2(info->num_render_backends, 16);
 736         unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
 737         unsigned rb_per_se = num_rb / num_se;
 738         unsigned se_mask[4];
 739         unsigned se;
 740
 741         se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
 742         se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
 743         se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
 744         se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
 745
 746         assert(num_se == 1 || num_se == 2 || num_se == 4);
 747         assert(sh_per_se == 1 || sh_per_se == 2);
 748         assert(rb_per_pkr == 1 || rb_per_pkr == 2);
 749
 750
 751         if (info->chip_class >= CIK) {
 752                 unsigned raster_config_1 = *cik_raster_config_1_p;
 753                 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
 754                                      (!se_mask[2] && !se_mask[3]))) {
 755                         raster_config_1 &= C_028354_SE_PAIR_MAP;
 756
 757                         if (!se_mask[0] && !se_mask[1]) {
 758                                 raster_config_1 |=
 759                                         S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
 760                         } else {
 761                                 raster_config_1 |=
 762                                         S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
 763                         }
 764                         *cik_raster_config_1_p = raster_config_1;
 765                 }
 766         }
 767
 768         for (se = 0; se < num_se; se++) {
 769                 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
 770                 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
 771                 int idx = (se / 2) * 2;
 772
 773                 raster_config_se[se] = raster_config;
 774                 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
 775                         raster_config_se[se] &= C_028350_SE_MAP;
 776
 777                         if (!se_mask[idx]) {
 778                                 raster_config_se[se] |=
 779                                         S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
 780                         } else {
 781                                 raster_config_se[se] |=
 782                                         S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
 783                         }
 784                 }
 785
 786                 pkr0_mask &= rb_mask;
 787                 pkr1_mask &= rb_mask;
 788                 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
 789                         raster_config_se[se] &= C_028350_PKR_MAP;
 790
 791                         if (!pkr0_mask) {
 792                                 raster_config_se[se] |=
 793                                         S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
 794                         } else {
 795                                 raster_config_se[se] |=
 796                                         S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
 797                         }
 798                 }
 799
 800                 if (rb_per_se >= 2) {
 801                         unsigned rb0_mask = 1 << (se * rb_per_se);
 802                         unsigned rb1_mask = rb0_mask << 1;
 803
 804                         rb0_mask &= rb_mask;
 805                         rb1_mask &= rb_mask;
 806                         if (!rb0_mask || !rb1_mask) {
 807                                 raster_config_se[se] &= C_028350_RB_MAP_PKR0;
 808
 809                                 if (!rb0_mask) {
 810                                         raster_config_se[se] |=
 811                                                 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
 812                                 } else {
 813                                         raster_config_se[se] |=
 814                                                 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
 815                                 }
 816                         }
 817
 818                         if (rb_per_se > 2) {
 819                                 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
 820                                 rb1_mask = rb0_mask << 1;
 821                                 rb0_mask &= rb_mask;
 822                                 rb1_mask &= rb_mask;
 823                                 if (!rb0_mask || !rb1_mask) {
 824                                         raster_config_se[se] &= C_028350_RB_MAP_PKR1;
 825
 826                                         if (!rb0_mask) {
 827                                                 raster_config_se[se] |=
 828                                                         S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
 829                                         } else {
 830                                                 raster_config_se[se] |=
 831                                                         S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
 832                                         }
 833                                 }
 834                         }
 835                 }
 836         }
 837 }