src/amd/vulkan/radv_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "radv_private.h"
  29 #include "radv_radeon_winsys.h"
  30 #include "radv_shader.h"
  31 #include "radv_cs.h"
  32 #include "sid.h"
  33 #include "gfx9d.h"
  34 #include "vk_format.h"
  35 #include "radv_debug.h"
  36 #include "radv_meta.h"
  37
  38 #include "ac_debug.h"
  39
  40 enum {
  41         RADV_PREFETCH_VBO_DESCRIPTORS   = (1 << 0),
  42         RADV_PREFETCH_VS                = (1 << 1),
  43         RADV_PREFETCH_TCS               = (1 << 2),
  44         RADV_PREFETCH_TES               = (1 << 3),
  45         RADV_PREFETCH_GS                = (1 << 4),
  46         RADV_PREFETCH_PS                = (1 << 5),
  47         RADV_PREFETCH_SHADERS           = (RADV_PREFETCH_VS  |
  48                                            RADV_PREFETCH_TCS |
  49                                            RADV_PREFETCH_TES |
  50                                            RADV_PREFETCH_GS  |
  51                                            RADV_PREFETCH_PS)
  52 };
  53
  54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
  55                                          struct radv_image *image,
  56                                          VkImageLayout src_layout,
  57                                          VkImageLayout dst_layout,
  58                                          uint32_t src_family,
  59                                          uint32_t dst_family,
  60                                          const VkImageSubresourceRange *range,
  61                                          VkImageAspectFlags pending_clears);
  62
  63 const struct radv_dynamic_state default_dynamic_state = {
  64         .viewport = {
  65                 .count = 0,
  66         },
  67         .scissor = {
  68                 .count = 0,
  69         },
  70         .line_width = 1.0f,
  71         .depth_bias = {
  72                 .bias = 0.0f,
  73                 .clamp = 0.0f,
  74                 .slope = 0.0f,
  75         },
  76         .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
  77         .depth_bounds = {
  78                 .min = 0.0f,
  79                 .max = 1.0f,
  80         },
  81         .stencil_compare_mask = {
  82                 .front = ~0u,
  83                 .back = ~0u,
  84         },
  85         .stencil_write_mask = {
  86                 .front = ~0u,
  87                 .back = ~0u,
  88         },
  89         .stencil_reference = {
  90                 .front = 0u,
  91                 .back = 0u,
  92         },
  93 };
  94
  95 static void
  96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
  97                         const struct radv_dynamic_state *src)
  98 {
  99         struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
 100         uint32_t copy_mask = src->mask;
 101         uint32_t dest_mask = 0;
 102
 103         /* Make sure to copy the number of viewports/scissors because they can
 104          * only be specified at pipeline creation time.
 105          */
 106         dest->viewport.count = src->viewport.count;
 107         dest->scissor.count = src->scissor.count;
 108         dest->discard_rectangle.count = src->discard_rectangle.count;
 109
 110         if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
 111                 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
 112                            src->viewport.count * sizeof(VkViewport))) {
 113                         typed_memcpy(dest->viewport.viewports,
 114                                      src->viewport.viewports,
 115                                      src->viewport.count);
 116                         dest_mask |= RADV_DYNAMIC_VIEWPORT;
 117                 }
 118         }
 119
 120         if (copy_mask & RADV_DYNAMIC_SCISSOR) {
 121                 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
 122                            src->scissor.count * sizeof(VkRect2D))) {
 123                         typed_memcpy(dest->scissor.scissors,
 124                                      src->scissor.scissors, src->scissor.count);
 125                         dest_mask |= RADV_DYNAMIC_SCISSOR;
 126                 }
 127         }
 128
 129         if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
 130                 if (dest->line_width != src->line_width) {
 131                         dest->line_width = src->line_width;
 132                         dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
 133                 }
 134         }
 135
 136         if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
 137                 if (memcmp(&dest->depth_bias, &src->depth_bias,
 138                            sizeof(src->depth_bias))) {
 139                         dest->depth_bias = src->depth_bias;
 140                         dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
 141                 }
 142         }
 143
 144         if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
 145                 if (memcmp(&dest->blend_constants, &src->blend_constants,
 146                            sizeof(src->blend_constants))) {
 147                         typed_memcpy(dest->blend_constants,
 148                                      src->blend_constants, 4);
 149                         dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
 150                 }
 151         }
 152
 153         if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
 154                 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
 155                            sizeof(src->depth_bounds))) {
 156                         dest->depth_bounds = src->depth_bounds;
 157                         dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
 158                 }
 159         }
 160
 161         if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
 162                 if (memcmp(&dest->stencil_compare_mask,
 163                            &src->stencil_compare_mask,
 164                            sizeof(src->stencil_compare_mask))) {
 165                         dest->stencil_compare_mask = src->stencil_compare_mask;
 166                         dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
 167                 }
 168         }
 169
 170         if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
 171                 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
 172                            sizeof(src->stencil_write_mask))) {
 173                         dest->stencil_write_mask = src->stencil_write_mask;
 174                         dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
 175                 }
 176         }
 177
 178         if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
 179                 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
 180                            sizeof(src->stencil_reference))) {
 181                         dest->stencil_reference = src->stencil_reference;
 182                         dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
 183                 }
 184         }
 185
 186         if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
 187                 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
 188                            src->discard_rectangle.count * sizeof(VkRect2D))) {
 189                         typed_memcpy(dest->discard_rectangle.rectangles,
 190                                      src->discard_rectangle.rectangles,
 191                                      src->discard_rectangle.count);
 192                         dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
 193                 }
 194         }
 195
 196         cmd_buffer->state.dirty |= dest_mask;
 197 }
 198
 199 static void
 200 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
 201                           struct radv_pipeline *pipeline)
 202 {
 203         struct radv_streamout_state *so = &cmd_buffer->state.streamout;
 204         struct radv_shader_info *info;
 205
 206         if (!pipeline->streamout_shader)
 207                 return;
 208
 209         info = &pipeline->streamout_shader->info.info;
 210         for (int i = 0; i < MAX_SO_BUFFERS; i++)
 211                 so->stride_in_dw[i] = info->so.strides[i];
 212
 213         so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
 214 }
 215
 216 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
 217 {
 218         return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
 219                cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
 220 }
 221
 222 enum ring_type radv_queue_family_to_ring(int f) {
 223         switch (f) {
 224         case RADV_QUEUE_GENERAL:
 225                 return RING_GFX;
 226         case RADV_QUEUE_COMPUTE:
 227                 return RING_COMPUTE;
 228         case RADV_QUEUE_TRANSFER:
 229                 return RING_DMA;
 230         default:
 231                 unreachable("Unknown queue family");
 232         }
 233 }
 234
 235 static VkResult radv_create_cmd_buffer(
 236         struct radv_device *                         device,
 237         struct radv_cmd_pool *                       pool,
 238         VkCommandBufferLevel                        level,
 239         VkCommandBuffer*                            pCommandBuffer)
 240 {
 241         struct radv_cmd_buffer *cmd_buffer;
 242         unsigned ring;
 243         cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
 244                                VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 245         if (cmd_buffer == NULL)
 246                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 247
 248         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
 249         cmd_buffer->device = device;
 250         cmd_buffer->pool = pool;
 251         cmd_buffer->level = level;
 252
 253         if (pool) {
 254                 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
 255                 cmd_buffer->queue_family_index = pool->queue_family_index;
 256
 257         } else {
 258                 /* Init the pool_link so we can safely call list_del when we destroy
 259                  * the command buffer
 260                  */
 261                 list_inithead(&cmd_buffer->pool_link);
 262                 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
 263         }
 264
 265         ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
 266
 267         cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
 268         if (!cmd_buffer->cs) {
 269                 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 270                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 271         }
 272
 273         *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
 274
 275         list_inithead(&cmd_buffer->upload.list);
 276
 277         return VK_SUCCESS;
 278 }
 279
 280 static void
 281 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
 282 {
 283         list_del(&cmd_buffer->pool_link);
 284
 285         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 286                                  &cmd_buffer->upload.list, list) {
 287                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 288                 list_del(&up->list);
 289                 free(up);
 290         }
 291
 292         if (cmd_buffer->upload.upload_bo)
 293                 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
 294         cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
 295
 296         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
 297                 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
 298
 299         vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 300 }
 301
 302 static VkResult
 303 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 304 {
 305
 306         cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
 307
 308         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 309                                  &cmd_buffer->upload.list, list) {
 310                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 311                 list_del(&up->list);
 312                 free(up);
 313         }
 314
 315         cmd_buffer->push_constant_stages = 0;
 316         cmd_buffer->scratch_size_needed = 0;
 317         cmd_buffer->compute_scratch_size_needed = 0;
 318         cmd_buffer->esgs_ring_size_needed = 0;
 319         cmd_buffer->gsvs_ring_size_needed = 0;
 320         cmd_buffer->tess_rings_needed = false;
 321         cmd_buffer->sample_positions_needed = false;
 322
 323         if (cmd_buffer->upload.upload_bo)
 324                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 325                                    cmd_buffer->upload.upload_bo);
 326         cmd_buffer->upload.offset = 0;
 327
 328         cmd_buffer->record_result = VK_SUCCESS;
 329
 330         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
 331                 cmd_buffer->descriptors[i].dirty = 0;
 332                 cmd_buffer->descriptors[i].valid = 0;
 333                 cmd_buffer->descriptors[i].push_dirty = false;
 334         }
 335
 336         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 337                 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
 338                 unsigned eop_bug_offset;
 339                 void *fence_ptr;
 340
 341                 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
 342                                              &cmd_buffer->gfx9_fence_offset,
 343                                              &fence_ptr);
 344                 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
 345
 346                 /* Allocate a buffer for the EOP bug on GFX9. */
 347                 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
 348                                              &eop_bug_offset, &fence_ptr);
 349                 cmd_buffer->gfx9_eop_bug_va =
 350                         radv_buffer_get_va(cmd_buffer->upload.upload_bo);
 351                 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
 352         }
 353
 354         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
 355
 356         return cmd_buffer->record_result;
 357 }
 358
 359 static bool
 360 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
 361                                   uint64_t min_needed)
 362 {
 363         uint64_t new_size;
 364         struct radeon_winsys_bo *bo;
 365         struct radv_cmd_buffer_upload *upload;
 366         struct radv_device *device = cmd_buffer->device;
 367
 368         new_size = MAX2(min_needed, 16 * 1024);
 369         new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
 370
 371         bo = device->ws->buffer_create(device->ws,
 372                                        new_size, 4096,
 373                                        RADEON_DOMAIN_GTT,
 374                                        RADEON_FLAG_CPU_ACCESS|
 375                                        RADEON_FLAG_NO_INTERPROCESS_SHARING |
 376                                        RADEON_FLAG_32BIT);
 377
 378         if (!bo) {
 379                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 380                 return false;
 381         }
 382
 383         radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
 384         if (cmd_buffer->upload.upload_bo) {
 385                 upload = malloc(sizeof(*upload));
 386
 387                 if (!upload) {
 388                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
 389                         device->ws->buffer_destroy(bo);
 390                         return false;
 391                 }
 392
 393                 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
 394                 list_add(&upload->list, &cmd_buffer->upload.list);
 395         }
 396
 397         cmd_buffer->upload.upload_bo = bo;
 398         cmd_buffer->upload.size = new_size;
 399         cmd_buffer->upload.offset = 0;
 400         cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
 401
 402         if (!cmd_buffer->upload.map) {
 403                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 404                 return false;
 405         }
 406
 407         return true;
 408 }
 409
 410 bool
 411 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
 412                              unsigned size,
 413                              unsigned alignment,
 414                              unsigned *out_offset,
 415                              void **ptr)
 416 {
 417         uint64_t offset = align(cmd_buffer->upload.offset, alignment);
 418         if (offset + size > cmd_buffer->upload.size) {
 419                 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
 420                         return false;
 421                 offset = 0;
 422         }
 423
 424         *out_offset = offset;
 425         *ptr = cmd_buffer->upload.map + offset;
 426
 427         cmd_buffer->upload.offset = offset + size;
 428         return true;
 429 }
 430
 431 bool
 432 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
 433                             unsigned size, unsigned alignment,
 434                             const void *data, unsigned *out_offset)
 435 {
 436         uint8_t *ptr;
 437
 438         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
 439                                           out_offset, (void **)&ptr))
 440                 return false;
 441
 442         if (ptr)
 443                 memcpy(ptr, data, size);
 444
 445         return true;
 446 }
 447
 448 static void
 449 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
 450                             unsigned count, const uint32_t *data)
 451 {
 452         struct radeon_cmdbuf *cs = cmd_buffer->cs;
 453
 454         radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
 455
 456         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
 457         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
 458                     S_370_WR_CONFIRM(1) |
 459                     S_370_ENGINE_SEL(V_370_ME));
 460         radeon_emit(cs, va);
 461         radeon_emit(cs, va >> 32);
 462         radeon_emit_array(cs, data, count);
 463 }
 464
 465 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
 466 {
 467         struct radv_device *device = cmd_buffer->device;
 468         struct radeon_cmdbuf *cs = cmd_buffer->cs;
 469         uint64_t va;
 470
 471         va = radv_buffer_get_va(device->trace_bo);
 472         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
 473                 va += 4;
 474
 475         ++cmd_buffer->state.trace_id;
 476         radv_emit_write_data_packet(cmd_buffer, va, 1,
 477                                     &cmd_buffer->state.trace_id);
 478
 479         radeon_check_space(cmd_buffer->device->ws, cs, 2);
 480
 481         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
 482         radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
 483 }
 484
 485 static void
 486 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
 487                            enum radv_cmd_flush_bits flags)
 488 {
 489         if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
 490                 uint32_t *ptr = NULL;
 491                 uint64_t va = 0;
 492
 493                 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
 494                                 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
 495
 496                 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
 497                         va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
 498                              cmd_buffer->gfx9_fence_offset;
 499                         ptr = &cmd_buffer->gfx9_fence_idx;
 500                 }
 501
 502                 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
 503
 504                 /* Force wait for graphics or compute engines to be idle. */
 505                 si_cs_emit_cache_flush(cmd_buffer->cs,
 506                                        cmd_buffer->device->physical_device->rad_info.chip_class,
 507                                        ptr, va,
 508                                        radv_cmd_buffer_uses_mec(cmd_buffer),
 509                                        flags, cmd_buffer->gfx9_eop_bug_va);
 510         }
 511
 512         if (unlikely(cmd_buffer->device->trace_bo))
 513                 radv_cmd_buffer_trace_emit(cmd_buffer);
 514 }
 515
 516 static void
 517 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
 518                    struct radv_pipeline *pipeline, enum ring_type ring)
 519 {
 520         struct radv_device *device = cmd_buffer->device;
 521         uint32_t data[2];
 522         uint64_t va;
 523
 524         va = radv_buffer_get_va(device->trace_bo);
 525
 526         switch (ring) {
 527         case RING_GFX:
 528                 va += 8;
 529                 break;
 530         case RING_COMPUTE:
 531                 va += 16;
 532                 break;
 533         default:
 534                 assert(!"invalid ring type");
 535         }
 536
 537         data[0] = (uintptr_t)pipeline;
 538         data[1] = (uintptr_t)pipeline >> 32;
 539
 540         radv_emit_write_data_packet(cmd_buffer, va, 2, data);
 541 }
 542
 543 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 544                              VkPipelineBindPoint bind_point,
 545                              struct radv_descriptor_set *set,
 546                              unsigned idx)
 547 {
 548         struct radv_descriptor_state *descriptors_state =
 549                 radv_get_descriptors_state(cmd_buffer, bind_point);
 550
 551         descriptors_state->sets[idx] = set;
 552
 553         descriptors_state->valid |= (1u << idx); /* active descriptors */
 554         descriptors_state->dirty |= (1u << idx);
 555 }
 556
 557 static void
 558 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
 559                       VkPipelineBindPoint bind_point)
 560 {
 561         struct radv_descriptor_state *descriptors_state =
 562                 radv_get_descriptors_state(cmd_buffer, bind_point);
 563         struct radv_device *device = cmd_buffer->device;
 564         uint32_t data[MAX_SETS * 2] = {};
 565         uint64_t va;
 566         unsigned i;
 567         va = radv_buffer_get_va(device->trace_bo) + 24;
 568
 569         for_each_bit(i, descriptors_state->valid) {
 570                 struct radv_descriptor_set *set = descriptors_state->sets[i];
 571                 data[i * 2] = (uintptr_t)set;
 572                 data[i * 2 + 1] = (uintptr_t)set >> 32;
 573         }
 574
 575         radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
 576 }
 577
 578 struct radv_userdata_info *
 579 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
 580                       gl_shader_stage stage,
 581                       int idx)
 582 {
 583         struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
 584         return &shader->info.user_sgprs_locs.shader_data[idx];
 585 }
 586
 587 static void
 588 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
 589                            struct radv_pipeline *pipeline,
 590                            gl_shader_stage stage,
 591                            int idx, uint64_t va)
 592 {
 593         struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
 594         uint32_t base_reg = pipeline->user_data_0[stage];
 595         if (loc->sgpr_idx == -1)
 596                 return;
 597
 598         assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
 599         assert(!loc->indirect);
 600
 601         radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
 602                                  base_reg + loc->sgpr_idx * 4, va, false);
 603 }
 604
 605 static void
 606 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
 607                               struct radv_pipeline *pipeline,
 608                               struct radv_descriptor_state *descriptors_state,
 609                               gl_shader_stage stage)
 610 {
 611         struct radv_device *device = cmd_buffer->device;
 612         struct radeon_cmdbuf *cs = cmd_buffer->cs;
 613         uint32_t sh_base = pipeline->user_data_0[stage];
 614         struct radv_userdata_locations *locs =
 615                 &pipeline->shaders[stage]->info.user_sgprs_locs;
 616         unsigned mask = locs->descriptor_sets_enabled;
 617
 618         mask &= descriptors_state->dirty & descriptors_state->valid;
 619
 620         while (mask) {
 621                 int start, count;
 622
 623                 u_bit_scan_consecutive_range(&mask, &start, &count);
 624
 625                 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
 626                 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
 627
 628                 radv_emit_shader_pointer_head(cs, sh_offset, count,
 629                                               HAVE_32BIT_POINTERS);
 630                 for (int i = 0; i < count; i++) {
 631                         struct radv_descriptor_set *set =
 632                                 descriptors_state->sets[start + i];
 633
 634                         radv_emit_shader_pointer_body(device, cs, set->va,
 635                                                       HAVE_32BIT_POINTERS);
 636                 }
 637         }
 638 }
 639
 640 static void
 641 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
 642                               struct radv_pipeline *pipeline)
 643 {
 644         int num_samples = pipeline->graphics.ms.num_samples;
 645         struct radv_multisample_state *ms = &pipeline->graphics.ms;
 646         struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
 647
 648         if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
 649                 cmd_buffer->sample_positions_needed = true;
 650
 651         if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
 652                 return;
 653
 654         radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
 655         radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
 656         radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
 657
 658         radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
 659
 660         radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
 661
 662         /* GFX9: Flush DFSM when the AA mode changes. */
 663         if (cmd_buffer->device->dfsm_allowed) {
 664                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 665                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
 666         }
 667 }
 668
 669 static void
 670 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
 671                           struct radv_shader_variant *shader)
 672 {
 673         uint64_t va;
 674
 675         if (!shader)
 676                 return;
 677
 678         va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 679
 680         si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
 681 }
 682
 683 static void
 684 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
 685                       struct radv_pipeline *pipeline,
 686                       bool vertex_stage_only)
 687 {
 688         struct radv_cmd_state *state = &cmd_buffer->state;
 689         uint32_t mask = state->prefetch_L2_mask;
 690
 691         if (vertex_stage_only) {
 692                 /* Fast prefetch path for starting draws as soon as possible.
 693                  */
 694                 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
 695                                                   RADV_PREFETCH_VBO_DESCRIPTORS);
 696         }
 697
 698         if (mask & RADV_PREFETCH_VS)
 699                 radv_emit_shader_prefetch(cmd_buffer,
 700                                           pipeline->shaders[MESA_SHADER_VERTEX]);
 701
 702         if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
 703                 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
 704
 705         if (mask & RADV_PREFETCH_TCS)
 706                 radv_emit_shader_prefetch(cmd_buffer,
 707                                           pipeline->shaders[MESA_SHADER_TESS_CTRL]);
 708
 709         if (mask & RADV_PREFETCH_TES)
 710                 radv_emit_shader_prefetch(cmd_buffer,
 711                                           pipeline->shaders[MESA_SHADER_TESS_EVAL]);
 712
 713         if (mask & RADV_PREFETCH_GS) {
 714                 radv_emit_shader_prefetch(cmd_buffer,
 715                                           pipeline->shaders[MESA_SHADER_GEOMETRY]);
 716                 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
 717         }
 718
 719         if (mask & RADV_PREFETCH_PS)
 720                 radv_emit_shader_prefetch(cmd_buffer,
 721                                           pipeline->shaders[MESA_SHADER_FRAGMENT]);
 722
 723         state->prefetch_L2_mask &= ~mask;
 724 }
 725
 726 static void
 727 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
 728 {
 729         if (!cmd_buffer->device->physical_device->rbplus_allowed)
 730                 return;
 731
 732         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 733         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
 734         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 735
 736         unsigned sx_ps_downconvert = 0;
 737         unsigned sx_blend_opt_epsilon = 0;
 738         unsigned sx_blend_opt_control = 0;
 739
 740         for (unsigned i = 0; i < subpass->color_count; ++i) {
 741                 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
 742                         sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 743                         sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 744                         continue;
 745                 }
 746
 747                 int idx = subpass->color_attachments[i].attachment;
 748                 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
 749
 750                 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
 751                 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
 752                 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
 753                 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
 754
 755                 bool has_alpha, has_rgb;
 756
 757                 /* Set if RGB and A are present. */
 758                 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
 759
 760                 if (format == V_028C70_COLOR_8 ||
 761                     format == V_028C70_COLOR_16 ||
 762                     format == V_028C70_COLOR_32)
 763                         has_rgb = !has_alpha;
 764                 else
 765                         has_rgb = true;
 766
 767                 /* Check the colormask and export format. */
 768                 if (!(colormask & 0x7))
 769                         has_rgb = false;
 770                 if (!(colormask & 0x8))
 771                         has_alpha = false;
 772
 773                 if (spi_format == V_028714_SPI_SHADER_ZERO) {
 774                         has_rgb = false;
 775                         has_alpha = false;
 776                 }
 777
 778                 /* Disable value checking for disabled channels. */
 779                 if (!has_rgb)
 780                         sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 781                 if (!has_alpha)
 782                         sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 783
 784                 /* Enable down-conversion for 32bpp and smaller formats. */
 785                 switch (format) {
 786                 case V_028C70_COLOR_8:
 787                 case V_028C70_COLOR_8_8:
 788                 case V_028C70_COLOR_8_8_8_8:
 789                         /* For 1 and 2-channel formats, use the superset thereof. */
 790                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
 791                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 792                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 793                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
 794                                 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
 795                         }
 796                         break;
 797
 798                 case V_028C70_COLOR_5_6_5:
 799                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 800                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
 801                                 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
 802                         }
 803                         break;
 804
 805                 case V_028C70_COLOR_1_5_5_5:
 806                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 807                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
 808                                 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
 809                         }
 810                         break;
 811
 812                 case V_028C70_COLOR_4_4_4_4:
 813                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 814                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
 815                                 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
 816                         }
 817                         break;
 818
 819                 case V_028C70_COLOR_32:
 820                         if (swap == V_028C70_SWAP_STD &&
 821                             spi_format == V_028714_SPI_SHADER_32_R)
 822                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
 823                         else if (swap == V_028C70_SWAP_ALT_REV &&
 824                                  spi_format == V_028714_SPI_SHADER_32_AR)
 825                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
 826                         break;
 827
 828                 case V_028C70_COLOR_16:
 829                 case V_028C70_COLOR_16_16:
 830                         /* For 1-channel formats, use the superset thereof. */
 831                         if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
 832                             spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
 833                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 834                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 835                                 if (swap == V_028C70_SWAP_STD ||
 836                                     swap == V_028C70_SWAP_STD_REV)
 837                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
 838                                 else
 839                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
 840                         }
 841                         break;
 842
 843                 case V_028C70_COLOR_10_11_11:
 844                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 845                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
 846                                 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
 847                         }
 848                         break;
 849
 850                 case V_028C70_COLOR_2_10_10_10:
 851                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 852                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
 853                                 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
 854                         }
 855                         break;
 856                 }
 857         }
 858
 859         for (unsigned i = subpass->color_count; i < 8; ++i) {
 860                 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 861                 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 862         }
 863         radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
 864         radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
 865         radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
 866         radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
 867 }
 868
 869 static void
 870 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
 871 {
 872         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 873
 874         if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
 875                 return;
 876
 877         radv_update_multisample_state(cmd_buffer, pipeline);
 878
 879         cmd_buffer->scratch_size_needed =
 880                                   MAX2(cmd_buffer->scratch_size_needed,
 881                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
 882
 883         if (!cmd_buffer->state.emitted_pipeline ||
 884             cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
 885              pipeline->graphics.can_use_guardband)
 886                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
 887
 888         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
 889
 890         for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
 891                 if (!pipeline->shaders[i])
 892                         continue;
 893
 894                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 895                                    pipeline->shaders[i]->bo);
 896         }
 897
 898         if (radv_pipeline_has_gs(pipeline))
 899                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 900                                    pipeline->gs_copy_shader->bo);
 901
 902         if (unlikely(cmd_buffer->device->trace_bo))
 903                 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
 904
 905         cmd_buffer->state.emitted_pipeline = pipeline;
 906
 907         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
 908 }
 909
 910 static void
 911 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
 912 {
 913         si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
 914                           cmd_buffer->state.dynamic.viewport.viewports);
 915 }
 916
 917 static void
 918 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
 919 {
 920         uint32_t count = cmd_buffer->state.dynamic.scissor.count;
 921
 922         si_write_scissors(cmd_buffer->cs, 0, count,
 923                           cmd_buffer->state.dynamic.scissor.scissors,
 924                           cmd_buffer->state.dynamic.viewport.viewports,
 925                           cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
 926 }
 927
 928 static void
 929 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
 930 {
 931         if (!cmd_buffer->state.dynamic.discard_rectangle.count)
 932                 return;
 933
 934         radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
 935                                    cmd_buffer->state.dynamic.discard_rectangle.count * 2);
 936         for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
 937                 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
 938                 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
 939                 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
 940                                             S_028214_BR_Y(rect.offset.y + rect.extent.height));
 941         }
 942 }
 943
 944 static void
 945 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
 946 {
 947         unsigned width = cmd_buffer->state.dynamic.line_width * 8;
 948
 949         radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
 950                                S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
 951 }
 952
 953 static void
 954 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
 955 {
 956         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 957
 958         radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
 959         radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
 960 }
 961
 962 static void
 963 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
 964 {
 965         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 966
 967         radeon_set_context_reg_seq(cmd_buffer->cs,
 968                                    R_028430_DB_STENCILREFMASK, 2);
 969         radeon_emit(cmd_buffer->cs,
 970                     S_028430_STENCILTESTVAL(d->stencil_reference.front) |
 971                     S_028430_STENCILMASK(d->stencil_compare_mask.front) |
 972                     S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
 973                     S_028430_STENCILOPVAL(1));
 974         radeon_emit(cmd_buffer->cs,
 975                     S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
 976                     S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
 977                     S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
 978                     S_028434_STENCILOPVAL_BF(1));
 979 }
 980
 981 static void
 982 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
 983 {
 984         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 985
 986         radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
 987                                fui(d->depth_bounds.min));
 988         radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
 989                                fui(d->depth_bounds.max));
 990 }
 991
 992 static void
 993 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
 994 {
 995         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 996         unsigned slope = fui(d->depth_bias.slope * 16.0f);
 997         unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
 998
 999
1000         radeon_set_context_reg_seq(cmd_buffer->cs,
1001                                    R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1002         radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1003         radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1004         radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1005         radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1006         radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1007 }
1008
1009 static void
1010 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1011                          int index,
1012                          struct radv_attachment_info *att,
1013                          struct radv_image *image,
1014                          VkImageLayout layout)
1015 {
1016         bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1017         struct radv_color_buffer_info *cb = &att->cb;
1018         uint32_t cb_color_info = cb->cb_color_info;
1019
1020         if (!radv_layout_dcc_compressed(image, layout,
1021                                         radv_image_queue_family_mask(image,
1022                                                                      cmd_buffer->queue_family_index,
1023                                                                      cmd_buffer->queue_family_index))) {
1024                 cb_color_info &= C_028C70_DCC_ENABLE;
1025         }
1026
1027         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1028                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1029                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1030                 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1031                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1032                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1033                 radeon_emit(cmd_buffer->cs, cb_color_info);
1034                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1035                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1036                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1037                 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1038                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1039                 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1040
1041                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1042                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1043                 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1044
1045                 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1046                                        S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1047         } else {
1048                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1049                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1050                 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1051                 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1052                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1053                 radeon_emit(cmd_buffer->cs, cb_color_info);
1054                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1055                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1056                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1057                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1058                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1059                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1060
1061                 if (is_vi) { /* DCC BASE */
1062                         radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1063                 }
1064         }
1065 }
1066
1067 static void
1068 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1069                              struct radv_ds_buffer_info *ds,
1070                              struct radv_image *image, VkImageLayout layout,
1071                              bool requires_cond_write)
1072 {
1073         uint32_t db_z_info = ds->db_z_info;
1074         uint32_t db_z_info_reg;
1075
1076         if (!radv_image_is_tc_compat_htile(image))
1077                 return;
1078
1079         if (!radv_layout_has_htile(image, layout,
1080                                    radv_image_queue_family_mask(image,
1081                                                                 cmd_buffer->queue_family_index,
1082                                                                 cmd_buffer->queue_family_index))) {
1083                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1084         }
1085
1086         db_z_info &= C_028040_ZRANGE_PRECISION;
1087
1088         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1089                 db_z_info_reg = R_028038_DB_Z_INFO;
1090         } else {
1091                 db_z_info_reg = R_028040_DB_Z_INFO;
1092         }
1093
1094         /* When we don't know the last fast clear value we need to emit a
1095          * conditional packet, otherwise we can update DB_Z_INFO directly.
1096          */
1097         if (requires_cond_write) {
1098                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1099
1100                 const uint32_t write_space = 0 << 8;    /* register */
1101                 const uint32_t poll_space = 1 << 4;     /* memory */
1102                 const uint32_t function = 3 << 0;       /* equal to the reference */
1103                 const uint32_t options = write_space | poll_space | function;
1104                 radeon_emit(cmd_buffer->cs, options);
1105
1106                 /* poll address - location of the depth clear value */
1107                 uint64_t va = radv_buffer_get_va(image->bo);
1108                 va += image->offset + image->clear_value_offset;
1109
1110                 /* In presence of stencil format, we have to adjust the base
1111                  * address because the first value is the stencil clear value.
1112                  */
1113                 if (vk_format_is_stencil(image->vk_format))
1114                         va += 4;
1115
1116                 radeon_emit(cmd_buffer->cs, va);
1117                 radeon_emit(cmd_buffer->cs, va >> 32);
1118
1119                 radeon_emit(cmd_buffer->cs, fui(0.0f));          /* reference value */
1120                 radeon_emit(cmd_buffer->cs, (uint32_t)-1);       /* comparison mask */
1121                 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1122                 radeon_emit(cmd_buffer->cs, 0u);                 /* write address high */
1123                 radeon_emit(cmd_buffer->cs, db_z_info);
1124         } else {
1125                 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1126         }
1127 }
1128
1129 static void
1130 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1131                       struct radv_ds_buffer_info *ds,
1132                       struct radv_image *image,
1133                       VkImageLayout layout)
1134 {
1135         uint32_t db_z_info = ds->db_z_info;
1136         uint32_t db_stencil_info = ds->db_stencil_info;
1137
1138         if (!radv_layout_has_htile(image, layout,
1139                                    radv_image_queue_family_mask(image,
1140                                                                 cmd_buffer->queue_family_index,
1141                                                                 cmd_buffer->queue_family_index))) {
1142                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1143                 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1144         }
1145
1146         radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1147         radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1148
1149
1150         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1151                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1152                 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1153                 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1154                 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1155
1156                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1157                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* DB_Z_INFO */
1158                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* DB_STENCIL_INFO */
1159                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* DB_Z_READ_BASE */
1160                 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32));        /* DB_Z_READ_BASE_HI */
1161                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* DB_STENCIL_READ_BASE */
1162                 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1163                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* DB_Z_WRITE_BASE */
1164                 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32));       /* DB_Z_WRITE_BASE_HI */
1165                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1166                 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1167
1168                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1169                 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1170                 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1171         } else {
1172                 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1173
1174                 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1175                 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1176                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* R_028040_DB_Z_INFO */
1177                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* R_028044_DB_STENCIL_INFO */
1178                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* R_028048_DB_Z_READ_BASE */
1179                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* R_02804C_DB_STENCIL_READ_BASE */
1180                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* R_028050_DB_Z_WRITE_BASE */
1181                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1182                 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1183                 radeon_emit(cmd_buffer->cs, ds->db_depth_slice);        /* R_02805C_DB_DEPTH_SLICE */
1184
1185         }
1186
1187         /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1188         radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1189
1190         radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1191                                ds->pa_su_poly_offset_db_fmt_cntl);
1192 }
1193
1194 /**
1195  * Update the fast clear depth/stencil values if the image is bound as a
1196  * depth/stencil buffer.
1197  */
1198 static void
1199 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1200                                 struct radv_image *image,
1201                                 VkClearDepthStencilValue ds_clear_value,
1202                                 VkImageAspectFlags aspects)
1203 {
1204         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1205         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1206         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1207         struct radv_attachment_info *att;
1208         uint32_t att_idx;
1209
1210         if (!framebuffer || !subpass)
1211                 return;
1212
1213         att_idx = subpass->depth_stencil_attachment.attachment;
1214         if (att_idx == VK_ATTACHMENT_UNUSED)
1215                 return;
1216
1217         att = &framebuffer->attachments[att_idx];
1218         if (att->attachment->image != image)
1219                 return;
1220
1221         radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1222         radeon_emit(cs, ds_clear_value.stencil);
1223         radeon_emit(cs, fui(ds_clear_value.depth));
1224
1225         /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1226          * only needed when clearing Z to 0.0.
1227          */
1228         if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1229             ds_clear_value.depth == 0.0) {
1230                 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1231
1232                 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1233                                              layout, false);
1234         }
1235 }
1236
1237 /**
1238  * Set the clear depth/stencil values to the image's metadata.
1239  */
1240 static void
1241 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1242                            struct radv_image *image,
1243                            VkClearDepthStencilValue ds_clear_value,
1244                            VkImageAspectFlags aspects)
1245 {
1246         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1247         uint64_t va = radv_buffer_get_va(image->bo);
1248         unsigned reg_offset = 0, reg_count = 0;
1249
1250         va += image->offset + image->clear_value_offset;
1251
1252         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1253                 ++reg_count;
1254         } else {
1255                 ++reg_offset;
1256                 va += 4;
1257         }
1258         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1259                 ++reg_count;
1260
1261         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1262         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1263                         S_370_WR_CONFIRM(1) |
1264                         S_370_ENGINE_SEL(V_370_PFP));
1265         radeon_emit(cs, va);
1266         radeon_emit(cs, va >> 32);
1267         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1268                 radeon_emit(cs, ds_clear_value.stencil);
1269         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1270                 radeon_emit(cs, fui(ds_clear_value.depth));
1271 }
1272
1273 /**
1274  * Update the clear depth/stencil values for this image.
1275  */
1276 void
1277 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1278                               struct radv_image *image,
1279                               VkClearDepthStencilValue ds_clear_value,
1280                               VkImageAspectFlags aspects)
1281 {
1282         assert(radv_image_has_htile(image));
1283
1284         radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1285
1286         radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1287                                         aspects);
1288 }
1289
1290 /**
1291  * Load the clear depth/stencil values from the image's metadata.
1292  */
1293 static void
1294 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1295                             struct radv_image *image)
1296 {
1297         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1298         VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1299         uint64_t va = radv_buffer_get_va(image->bo);
1300         unsigned reg_offset = 0, reg_count = 0;
1301
1302         va += image->offset + image->clear_value_offset;
1303
1304         if (!radv_image_has_htile(image))
1305                 return;
1306
1307         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1308                 ++reg_count;
1309         } else {
1310                 ++reg_offset;
1311                 va += 4;
1312         }
1313         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1314                 ++reg_count;
1315
1316         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1317         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1318                         COPY_DATA_DST_SEL(COPY_DATA_REG) |
1319                         (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1320         radeon_emit(cs, va);
1321         radeon_emit(cs, va >> 32);
1322         radeon_emit(cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1323         radeon_emit(cs, 0);
1324
1325         radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1326         radeon_emit(cs, 0);
1327 }
1328
1329 /*
1330  * With DCC some colors don't require CMASK elimination before being
1331  * used as a texture. This sets a predicate value to determine if the
1332  * cmask eliminate is required.
1333  */
1334 void
1335 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1336                                   struct radv_image *image,
1337                                   bool value)
1338 {
1339         uint64_t pred_val = value;
1340         uint64_t va = radv_buffer_get_va(image->bo);
1341         va += image->offset + image->dcc_pred_offset;
1342
1343         assert(radv_image_has_dcc(image));
1344
1345         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1346         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1347                                     S_370_WR_CONFIRM(1) |
1348                                     S_370_ENGINE_SEL(V_370_PFP));
1349         radeon_emit(cmd_buffer->cs, va);
1350         radeon_emit(cmd_buffer->cs, va >> 32);
1351         radeon_emit(cmd_buffer->cs, pred_val);
1352         radeon_emit(cmd_buffer->cs, pred_val >> 32);
1353 }
1354
1355 /**
1356  * Update the fast clear color values if the image is bound as a color buffer.
1357  */
1358 static void
1359 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1360                                    struct radv_image *image,
1361                                    int cb_idx,
1362                                    uint32_t color_values[2])
1363 {
1364         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1365         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1366         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1367         struct radv_attachment_info *att;
1368         uint32_t att_idx;
1369
1370         if (!framebuffer || !subpass)
1371                 return;
1372
1373         att_idx = subpass->color_attachments[cb_idx].attachment;
1374         if (att_idx == VK_ATTACHMENT_UNUSED)
1375                 return;
1376
1377         att = &framebuffer->attachments[att_idx];
1378         if (att->attachment->image != image)
1379                 return;
1380
1381         radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1382         radeon_emit(cs, color_values[0]);
1383         radeon_emit(cs, color_values[1]);
1384 }
1385
1386 /**
1387  * Set the clear color values to the image's metadata.
1388  */
1389 static void
1390 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1391                               struct radv_image *image,
1392                               uint32_t color_values[2])
1393 {
1394         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1395         uint64_t va = radv_buffer_get_va(image->bo);
1396
1397         va += image->offset + image->clear_value_offset;
1398
1399         assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1400
1401         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1402         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1403                         S_370_WR_CONFIRM(1) |
1404                         S_370_ENGINE_SEL(V_370_PFP));
1405         radeon_emit(cs, va);
1406         radeon_emit(cs, va >> 32);
1407         radeon_emit(cs, color_values[0]);
1408         radeon_emit(cs, color_values[1]);
1409 }
1410
1411 /**
1412  * Update the clear color values for this image.
1413  */
1414 void
1415 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1416                                  struct radv_image *image,
1417                                  int cb_idx,
1418                                  uint32_t color_values[2])
1419 {
1420         assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1421
1422         radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1423
1424         radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1425                                            color_values);
1426 }
1427
1428 /**
1429  * Load the clear color values from the image's metadata.
1430  */
1431 static void
1432 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1433                                struct radv_image *image,
1434                                int cb_idx)
1435 {
1436         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1437         uint64_t va = radv_buffer_get_va(image->bo);
1438
1439         va += image->offset + image->clear_value_offset;
1440
1441         if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1442                 return;
1443
1444         uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1445
1446         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1447         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1448                         COPY_DATA_DST_SEL(COPY_DATA_REG) |
1449                         COPY_DATA_COUNT_SEL);
1450         radeon_emit(cs, va);
1451         radeon_emit(cs, va >> 32);
1452         radeon_emit(cs, reg >> 2);
1453         radeon_emit(cs, 0);
1454
1455         radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1456         radeon_emit(cs, 0);
1457 }
1458
1459 static void
1460 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1461 {
1462         int i;
1463         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1464         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1465
1466         /* this may happen for inherited secondary recording */
1467         if (!framebuffer)
1468                 return;
1469
1470         for (i = 0; i < 8; ++i) {
1471                 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1472                         radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1473                                        S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1474                         continue;
1475                 }
1476
1477                 int idx = subpass->color_attachments[i].attachment;
1478                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1479                 struct radv_image *image = att->attachment->image;
1480                 VkImageLayout layout = subpass->color_attachments[i].layout;
1481
1482                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1483
1484                 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1485                 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1486
1487                 radv_load_color_clear_metadata(cmd_buffer, image, i);
1488         }
1489
1490         if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1491                 int idx = subpass->depth_stencil_attachment.attachment;
1492                 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1493                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1494                 struct radv_image *image = att->attachment->image;
1495                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1496                 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1497                                                                                 cmd_buffer->queue_family_index,
1498                                                                                 cmd_buffer->queue_family_index);
1499                 /* We currently don't support writing decompressed HTILE */
1500                 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1501                        radv_layout_is_htile_compressed(image, layout, queue_mask));
1502
1503                 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1504
1505                 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1506                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1507                         cmd_buffer->state.offset_scale = att->ds.offset_scale;
1508                 }
1509                 radv_load_ds_clear_metadata(cmd_buffer, image);
1510         } else {
1511                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1512                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1513                 else
1514                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1515
1516                 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1517                 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1518         }
1519         radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1520                                S_028208_BR_X(framebuffer->width) |
1521                                S_028208_BR_Y(framebuffer->height));
1522
1523         if (cmd_buffer->device->dfsm_allowed) {
1524                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1525                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1526         }
1527
1528         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1529 }
1530
1531 static void
1532 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1533 {
1534         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1535         struct radv_cmd_state *state = &cmd_buffer->state;
1536
1537         if (state->index_type != state->last_index_type) {
1538                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1539                         radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1540                                                    2, state->index_type);
1541                 } else {
1542                         radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1543                         radeon_emit(cs, state->index_type);
1544                 }
1545
1546                 state->last_index_type = state->index_type;
1547         }
1548
1549         radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1550         radeon_emit(cs, state->index_va);
1551         radeon_emit(cs, state->index_va >> 32);
1552
1553         radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1554         radeon_emit(cs, state->max_index_count);
1555
1556         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1557 }
1558
1559 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1560 {
1561         bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1562         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1563         uint32_t pa_sc_mode_cntl_1 =
1564                 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1565         uint32_t db_count_control;
1566
1567         if(!cmd_buffer->state.active_occlusion_queries) {
1568                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1569                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1570                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1571                             has_perfect_queries) {
1572                                 /* Re-enable out-of-order rasterization if the
1573                                  * bound pipeline supports it and if it's has
1574                                  * been disabled before starting any perfect
1575                                  * occlusion queries.
1576                                  */
1577                                 radeon_set_context_reg(cmd_buffer->cs,
1578                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1579                                                        pa_sc_mode_cntl_1);
1580                         }
1581                 }
1582                 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1583         } else {
1584                 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1585                 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1586
1587                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1588                         db_count_control =
1589                                 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1590                                 S_028004_SAMPLE_RATE(sample_rate) |
1591                                 S_028004_ZPASS_ENABLE(1) |
1592                                 S_028004_SLICE_EVEN_ENABLE(1) |
1593                                 S_028004_SLICE_ODD_ENABLE(1);
1594
1595                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1596                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1597                             has_perfect_queries) {
1598                                 /* If the bound pipeline has enabled
1599                                  * out-of-order rasterization, we should
1600                                  * disable it before starting any perfect
1601                                  * occlusion queries.
1602                                  */
1603                                 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1604
1605                                 radeon_set_context_reg(cmd_buffer->cs,
1606                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1607                                                        pa_sc_mode_cntl_1);
1608                         }
1609                 } else {
1610                         db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1611                                 S_028004_SAMPLE_RATE(sample_rate);
1612                 }
1613         }
1614
1615         radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1616 }
1617
1618 static void
1619 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1620 {
1621         uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1622
1623         if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1624                 radv_emit_viewport(cmd_buffer);
1625
1626         if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1627             !cmd_buffer->device->physical_device->has_scissor_bug)
1628                 radv_emit_scissor(cmd_buffer);
1629
1630         if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1631                 radv_emit_line_width(cmd_buffer);
1632
1633         if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1634                 radv_emit_blend_constants(cmd_buffer);
1635
1636         if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1637                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1638                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1639                 radv_emit_stencil(cmd_buffer);
1640
1641         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1642                 radv_emit_depth_bounds(cmd_buffer);
1643
1644         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1645                 radv_emit_depth_bias(cmd_buffer);
1646
1647         if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1648                 radv_emit_discard_rectangle(cmd_buffer);
1649
1650         cmd_buffer->state.dirty &= ~states;
1651 }
1652
1653 static void
1654 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1655                             VkPipelineBindPoint bind_point)
1656 {
1657         struct radv_descriptor_state *descriptors_state =
1658                 radv_get_descriptors_state(cmd_buffer, bind_point);
1659         struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1660         unsigned bo_offset;
1661
1662         if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1663                                          set->mapped_ptr,
1664                                          &bo_offset))
1665                 return;
1666
1667         set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1668         set->va += bo_offset;
1669 }
1670
1671 static void
1672 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1673                                     VkPipelineBindPoint bind_point)
1674 {
1675         struct radv_descriptor_state *descriptors_state =
1676                 radv_get_descriptors_state(cmd_buffer, bind_point);
1677         uint8_t ptr_size = HAVE_32BIT_POINTERS ? 1 : 2;
1678         uint32_t size = MAX_SETS * 4 * ptr_size;
1679         uint32_t offset;
1680         void *ptr;
1681
1682         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1683                                           256, &offset, &ptr))
1684                 return;
1685
1686         for (unsigned i = 0; i < MAX_SETS; i++) {
1687                 uint32_t *uptr = ((uint32_t *)ptr) + i * ptr_size;
1688                 uint64_t set_va = 0;
1689                 struct radv_descriptor_set *set = descriptors_state->sets[i];
1690                 if (descriptors_state->valid & (1u << i))
1691                         set_va = set->va;
1692                 uptr[0] = set_va & 0xffffffff;
1693                 if (ptr_size == 2)
1694                         uptr[1] = set_va >> 32;
1695         }
1696
1697         uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1698         va += offset;
1699
1700         if (cmd_buffer->state.pipeline) {
1701                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1702                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1703                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1704
1705                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1706                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1707                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1708
1709                 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1710                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1711                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1712
1713                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1714                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1715                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1716
1717                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1718                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1719                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1720         }
1721
1722         if (cmd_buffer->state.compute_pipeline)
1723                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1724                                            AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1725 }
1726
1727 static void
1728 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1729                        VkShaderStageFlags stages)
1730 {
1731         VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1732                                          VK_PIPELINE_BIND_POINT_COMPUTE :
1733                                          VK_PIPELINE_BIND_POINT_GRAPHICS;
1734         struct radv_descriptor_state *descriptors_state =
1735                 radv_get_descriptors_state(cmd_buffer, bind_point);
1736         struct radv_cmd_state *state = &cmd_buffer->state;
1737         bool flush_indirect_descriptors;
1738
1739         if (!descriptors_state->dirty)
1740                 return;
1741
1742         if (descriptors_state->push_dirty)
1743                 radv_flush_push_descriptors(cmd_buffer, bind_point);
1744
1745         flush_indirect_descriptors =
1746                 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1747                  state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1748                 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1749                  state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1750
1751         if (flush_indirect_descriptors)
1752                 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1753
1754         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1755                                                            cmd_buffer->cs,
1756                                                            MAX_SETS * MESA_SHADER_STAGES * 4);
1757
1758         if (cmd_buffer->state.pipeline) {
1759                 radv_foreach_stage(stage, stages) {
1760                         if (!cmd_buffer->state.pipeline->shaders[stage])
1761                                 continue;
1762
1763                         radv_emit_descriptor_pointers(cmd_buffer,
1764                                                       cmd_buffer->state.pipeline,
1765                                                       descriptors_state, stage);
1766                 }
1767         }
1768
1769         if (cmd_buffer->state.compute_pipeline &&
1770             (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1771                 radv_emit_descriptor_pointers(cmd_buffer,
1772                                               cmd_buffer->state.compute_pipeline,
1773                                               descriptors_state,
1774                                               MESA_SHADER_COMPUTE);
1775         }
1776
1777         descriptors_state->dirty = 0;
1778         descriptors_state->push_dirty = false;
1779
1780         assert(cmd_buffer->cs->cdw <= cdw_max);
1781
1782         if (unlikely(cmd_buffer->device->trace_bo))
1783                 radv_save_descriptors(cmd_buffer, bind_point);
1784 }
1785
1786 static void
1787 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1788                      VkShaderStageFlags stages)
1789 {
1790         struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1791                                          ? cmd_buffer->state.compute_pipeline
1792                                          : cmd_buffer->state.pipeline;
1793         VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1794                                          VK_PIPELINE_BIND_POINT_COMPUTE :
1795                                          VK_PIPELINE_BIND_POINT_GRAPHICS;
1796         struct radv_descriptor_state *descriptors_state =
1797                 radv_get_descriptors_state(cmd_buffer, bind_point);
1798         struct radv_pipeline_layout *layout = pipeline->layout;
1799         struct radv_shader_variant *shader, *prev_shader;
1800         unsigned offset;
1801         void *ptr;
1802         uint64_t va;
1803
1804         stages &= cmd_buffer->push_constant_stages;
1805         if (!stages ||
1806             (!layout->push_constant_size && !layout->dynamic_offset_count))
1807                 return;
1808
1809         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1810                                           16 * layout->dynamic_offset_count,
1811                                           256, &offset, &ptr))
1812                 return;
1813
1814         memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1815         memcpy((char*)ptr + layout->push_constant_size,
1816                descriptors_state->dynamic_buffers,
1817                16 * layout->dynamic_offset_count);
1818
1819         va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1820         va += offset;
1821
1822         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1823                                                            cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1824
1825         prev_shader = NULL;
1826         radv_foreach_stage(stage, stages) {
1827                 shader = radv_get_shader(pipeline, stage);
1828
1829                 /* Avoid redundantly emitting the address for merged stages. */
1830                 if (shader && shader != prev_shader) {
1831                         radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1832                                                    AC_UD_PUSH_CONSTANTS, va);
1833
1834                         prev_shader = shader;
1835                 }
1836         }
1837
1838         cmd_buffer->push_constant_stages &= ~stages;
1839         assert(cmd_buffer->cs->cdw <= cdw_max);
1840 }
1841
1842 static void
1843 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1844                               bool pipeline_is_dirty)
1845 {
1846         if ((pipeline_is_dirty ||
1847             (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1848             cmd_buffer->state.pipeline->vertex_elements.count &&
1849             radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1850                 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1851                 unsigned vb_offset;
1852                 void *vb_ptr;
1853                 uint32_t i = 0;
1854                 uint32_t count = velems->count;
1855                 uint64_t va;
1856
1857                 /* allocate some descriptor state for vertex buffers */
1858                 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1859                                                   &vb_offset, &vb_ptr))
1860                         return;
1861
1862                 for (i = 0; i < count; i++) {
1863                         uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1864                         uint32_t offset;
1865                         int vb = velems->binding[i];
1866                         struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1867                         uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1868
1869                         va = radv_buffer_get_va(buffer->bo);
1870
1871                         offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1872                         va += offset + buffer->offset;
1873                         desc[0] = va;
1874                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1875                         if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1876                                 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1877                         else
1878                                 desc[2] = buffer->size - offset;
1879                         desc[3] = velems->rsrc_word3[i];
1880                 }
1881
1882                 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1883                 va += vb_offset;
1884
1885                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1886                                            AC_UD_VS_VERTEX_BUFFERS, va);
1887
1888                 cmd_buffer->state.vb_va = va;
1889                 cmd_buffer->state.vb_size = count * 16;
1890                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1891         }
1892         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1893 }
1894
1895 static void
1896 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
1897 {
1898         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1899         struct radv_userdata_info *loc;
1900         uint32_t base_reg;
1901
1902         for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
1903                 if (!radv_get_shader(pipeline, stage))
1904                         continue;
1905
1906                 loc = radv_lookup_user_sgpr(pipeline, stage,
1907                                             AC_UD_STREAMOUT_BUFFERS);
1908                 if (loc->sgpr_idx == -1)
1909                         continue;
1910
1911                 base_reg = pipeline->user_data_0[stage];
1912
1913                 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
1914                                          base_reg + loc->sgpr_idx * 4, va, false);
1915         }
1916
1917         if (pipeline->gs_copy_shader) {
1918                 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
1919                 if (loc->sgpr_idx != -1) {
1920                         base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
1921
1922                         radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
1923                                                  base_reg + loc->sgpr_idx * 4, va, false);
1924                 }
1925         }
1926 }
1927
1928 static void
1929 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
1930 {
1931         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
1932                 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
1933                 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
1934                 unsigned so_offset;
1935                 void *so_ptr;
1936                 uint64_t va;
1937
1938                 /* Allocate some descriptor state for streamout buffers. */
1939                 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
1940                                                   MAX_SO_BUFFERS * 16, 256,
1941                                                   &so_offset, &so_ptr))
1942                         return;
1943
1944                 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
1945                         struct radv_buffer *buffer = sb[i].buffer;
1946                         uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
1947
1948                         if (!(so->enabled_mask & (1 << i)))
1949                                 continue;
1950
1951                         va = radv_buffer_get_va(buffer->bo) + buffer->offset;
1952
1953                         va += sb[i].offset;
1954
1955                         /* Set the descriptor.
1956                          *
1957                          * On VI, the format must be non-INVALID, otherwise
1958                          * the buffer will be considered not bound and store
1959                          * instructions will be no-ops.
1960                          */
1961                         desc[0] = va;
1962                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
1963                         desc[2] = 0xffffffff;
1964                         desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1965                                   S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1966                                   S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1967                                   S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1968                                   S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1969                 }
1970
1971                 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1972                 va += so_offset;
1973
1974                 radv_emit_streamout_buffers(cmd_buffer, va);
1975         }
1976
1977         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
1978 }
1979
1980 static void
1981 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1982 {
1983         radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1984         radv_flush_streamout_descriptors(cmd_buffer);
1985         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1986         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1987 }
1988
1989 static void
1990 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1991                          bool instanced_draw, bool indirect_draw,
1992                          uint32_t draw_vertex_count)
1993 {
1994         struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1995         struct radv_cmd_state *state = &cmd_buffer->state;
1996         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1997         uint32_t ia_multi_vgt_param;
1998         int32_t primitive_reset_en;
1999
2000         /* Draw state. */
2001         ia_multi_vgt_param =
2002                 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
2003                                           indirect_draw, draw_vertex_count);
2004
2005         if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2006                 if (info->chip_class >= GFX9) {
2007                         radeon_set_uconfig_reg_idx(cs,
2008                                                    R_030960_IA_MULTI_VGT_PARAM,
2009                                                    4, ia_multi_vgt_param);
2010                 } else if (info->chip_class >= CIK) {
2011                         radeon_set_context_reg_idx(cs,
2012                                                    R_028AA8_IA_MULTI_VGT_PARAM,
2013                                                    1, ia_multi_vgt_param);
2014                 } else {
2015                         radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2016                                                ia_multi_vgt_param);
2017                 }
2018                 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2019         }
2020
2021         /* Primitive restart. */
2022         primitive_reset_en =
2023                 indexed_draw && state->pipeline->graphics.prim_restart_enable;
2024
2025         if (primitive_reset_en != state->last_primitive_reset_en) {
2026                 state->last_primitive_reset_en = primitive_reset_en;
2027                 if (info->chip_class >= GFX9) {
2028                         radeon_set_uconfig_reg(cs,
2029                                                R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2030                                                primitive_reset_en);
2031                 } else {
2032                         radeon_set_context_reg(cs,
2033                                                R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2034                                                primitive_reset_en);
2035                 }
2036         }
2037
2038         if (primitive_reset_en) {
2039                 uint32_t primitive_reset_index =
2040                         state->index_type ? 0xffffffffu : 0xffffu;
2041
2042                 if (primitive_reset_index != state->last_primitive_reset_index) {
2043                         radeon_set_context_reg(cs,
2044                                                R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2045                                                primitive_reset_index);
2046                         state->last_primitive_reset_index = primitive_reset_index;
2047                 }
2048         }
2049 }
2050
2051 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2052                              VkPipelineStageFlags src_stage_mask)
2053 {
2054         if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2055                               VK_PIPELINE_STAGE_TRANSFER_BIT |
2056                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2057                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2058                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2059         }
2060
2061         if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2062                               VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2063                               VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2064                               VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2065                               VK_PIPELINE_STAGE_TRANSFER_BIT |
2066                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2067                               VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2068                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2069                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2070         } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2071                                      VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2072                                      VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2073                                      VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2074                                      VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2075                                      VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2076                                      VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2077                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2078         }
2079 }
2080
2081 static enum radv_cmd_flush_bits
2082 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2083                       VkAccessFlags src_flags,
2084                       struct radv_image *image)
2085 {
2086         bool flush_CB_meta = true, flush_DB_meta = true;
2087         enum radv_cmd_flush_bits flush_bits = 0;
2088         uint32_t b;
2089
2090         if (image) {
2091                 if (!radv_image_has_CB_metadata(image))
2092                         flush_CB_meta = false;
2093                 if (!radv_image_has_htile(image))
2094                         flush_DB_meta = false;
2095         }
2096
2097         for_each_bit(b, src_flags) {
2098                 switch ((VkAccessFlagBits)(1 << b)) {
2099                 case VK_ACCESS_SHADER_WRITE_BIT:
2100                 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2101                 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2102                         flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2103                         break;
2104                 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2105                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2106                         if (flush_CB_meta)
2107                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2108                         break;
2109                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2110                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2111                         if (flush_DB_meta)
2112                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2113                         break;
2114                 case VK_ACCESS_TRANSFER_WRITE_BIT:
2115                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2116                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2117                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
2118
2119                         if (flush_CB_meta)
2120                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2121                         if (flush_DB_meta)
2122                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2123                         break;
2124                 default:
2125                         break;
2126                 }
2127         }
2128         return flush_bits;
2129 }
2130
2131 static enum radv_cmd_flush_bits
2132 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2133                       VkAccessFlags dst_flags,
2134                       struct radv_image *image)
2135 {
2136         bool flush_CB_meta = true, flush_DB_meta = true;
2137         enum radv_cmd_flush_bits flush_bits = 0;
2138         bool flush_CB = true, flush_DB = true;
2139         bool image_is_coherent = false;
2140         uint32_t b;
2141
2142         if (image) {
2143                 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2144                         flush_CB = false;
2145                         flush_DB = false;
2146                 }
2147
2148                 if (!radv_image_has_CB_metadata(image))
2149                         flush_CB_meta = false;
2150                 if (!radv_image_has_htile(image))
2151                         flush_DB_meta = false;
2152
2153                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2154                         if (image->info.samples == 1 &&
2155                             (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2156                                              VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2157                             !vk_format_is_stencil(image->vk_format)) {
2158                                 /* Single-sample color and single-sample depth
2159                                  * (not stencil) are coherent with shaders on
2160                                  * GFX9.
2161                                  */
2162                                 image_is_coherent = true;
2163                         }
2164                 }
2165         }
2166
2167         for_each_bit(b, dst_flags) {
2168                 switch ((VkAccessFlagBits)(1 << b)) {
2169                 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2170                 case VK_ACCESS_INDEX_READ_BIT:
2171                 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2172                         break;
2173                 case VK_ACCESS_UNIFORM_READ_BIT:
2174                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2175                         break;
2176                 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2177                 case VK_ACCESS_TRANSFER_READ_BIT:
2178                 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2179                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2180                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
2181                         break;
2182                 case VK_ACCESS_SHADER_READ_BIT:
2183                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2184
2185                         if (!image_is_coherent)
2186                                 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2187                         break;
2188                 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2189                         if (flush_CB)
2190                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2191                         if (flush_CB_meta)
2192                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2193                         break;
2194                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2195                         if (flush_DB)
2196                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2197                         if (flush_DB_meta)
2198                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2199                         break;
2200                 default:
2201                         break;
2202                 }
2203         }
2204         return flush_bits;
2205 }
2206
2207 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2208                           const struct radv_subpass_barrier *barrier)
2209 {
2210         cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2211                                                               NULL);
2212         radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2213         cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2214                                                               NULL);
2215 }
2216
2217 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2218                                                  struct radv_subpass_attachment att)
2219 {
2220         unsigned idx = att.attachment;
2221         struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2222         VkImageSubresourceRange range;
2223         range.aspectMask = 0;
2224         range.baseMipLevel = view->base_mip;
2225         range.levelCount = 1;
2226         range.baseArrayLayer = view->base_layer;
2227         range.layerCount = cmd_buffer->state.framebuffer->layers;
2228
2229         radv_handle_image_transition(cmd_buffer,
2230                                      view->image,
2231                                      cmd_buffer->state.attachments[idx].current_layout,
2232                                      att.layout, 0, 0, &range,
2233                                      cmd_buffer->state.attachments[idx].pending_clear_aspects);
2234
2235         cmd_buffer->state.attachments[idx].current_layout = att.layout;
2236
2237
2238 }
2239
2240 void
2241 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2242                             const struct radv_subpass *subpass, bool transitions)
2243 {
2244         if (transitions) {
2245                 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2246
2247                 for (unsigned i = 0; i < subpass->color_count; ++i) {
2248                         if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2249                                 radv_handle_subpass_image_transition(cmd_buffer,
2250                                                                      subpass->color_attachments[i]);
2251                 }
2252
2253                 for (unsigned i = 0; i < subpass->input_count; ++i) {
2254                         radv_handle_subpass_image_transition(cmd_buffer,
2255                                                         subpass->input_attachments[i]);
2256                 }
2257
2258                 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2259                         radv_handle_subpass_image_transition(cmd_buffer,
2260                                                         subpass->depth_stencil_attachment);
2261                 }
2262         }
2263
2264         cmd_buffer->state.subpass = subpass;
2265
2266         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2267 }
2268
2269 static VkResult
2270 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2271                                  struct radv_render_pass *pass,
2272                                  const VkRenderPassBeginInfo *info)
2273 {
2274         struct radv_cmd_state *state = &cmd_buffer->state;
2275
2276         if (pass->attachment_count == 0) {
2277                 state->attachments = NULL;
2278                 return VK_SUCCESS;
2279         }
2280
2281         state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2282                                         pass->attachment_count *
2283                                         sizeof(state->attachments[0]),
2284                                         8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2285         if (state->attachments == NULL) {
2286                 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2287                 return cmd_buffer->record_result;
2288         }
2289
2290         for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2291                 struct radv_render_pass_attachment *att = &pass->attachments[i];
2292                 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2293                 VkImageAspectFlags clear_aspects = 0;
2294
2295                 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2296                         /* color attachment */
2297                         if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2298                                 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2299                         }
2300                 } else {
2301                         /* depthstencil attachment */
2302                         if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2303                             att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2304                                 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2305                                 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2306                                     att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2307                                         clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2308                         }
2309                         if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2310                             att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2311                                 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2312                         }
2313                 }
2314
2315                 state->attachments[i].pending_clear_aspects = clear_aspects;
2316                 state->attachments[i].cleared_views = 0;
2317                 if (clear_aspects && info) {
2318                         assert(info->clearValueCount > i);
2319                         state->attachments[i].clear_value = info->pClearValues[i];
2320                 }
2321
2322                 state->attachments[i].current_layout = att->initial_layout;
2323         }
2324
2325         return VK_SUCCESS;
2326 }
2327
2328 VkResult radv_AllocateCommandBuffers(
2329         VkDevice _device,
2330         const VkCommandBufferAllocateInfo *pAllocateInfo,
2331         VkCommandBuffer *pCommandBuffers)
2332 {
2333         RADV_FROM_HANDLE(radv_device, device, _device);
2334         RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2335
2336         VkResult result = VK_SUCCESS;
2337         uint32_t i;
2338
2339         for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2340
2341                 if (!list_empty(&pool->free_cmd_buffers)) {
2342                         struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2343
2344                         list_del(&cmd_buffer->pool_link);
2345                         list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2346
2347                         result = radv_reset_cmd_buffer(cmd_buffer);
2348                         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2349                         cmd_buffer->level = pAllocateInfo->level;
2350
2351                         pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2352                 } else {
2353                         result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2354                                                         &pCommandBuffers[i]);
2355                 }
2356                 if (result != VK_SUCCESS)
2357                         break;
2358         }
2359
2360         if (result != VK_SUCCESS) {
2361                 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2362                                         i, pCommandBuffers);
2363
2364                 /* From the Vulkan 1.0.66 spec:
2365                  *
2366                  * "vkAllocateCommandBuffers can be used to create multiple
2367                  *  command buffers. If the creation of any of those command
2368                  *  buffers fails, the implementation must destroy all
2369                  *  successfully created command buffer objects from this
2370                  *  command, set all entries of the pCommandBuffers array to
2371                  *  NULL and return the error."
2372                  */
2373                 memset(pCommandBuffers, 0,
2374                        sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2375         }
2376
2377         return result;
2378 }
2379
2380 void radv_FreeCommandBuffers(
2381         VkDevice device,
2382         VkCommandPool commandPool,
2383         uint32_t commandBufferCount,
2384         const VkCommandBuffer *pCommandBuffers)
2385 {
2386         for (uint32_t i = 0; i < commandBufferCount; i++) {
2387                 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2388
2389                 if (cmd_buffer) {
2390                         if (cmd_buffer->pool) {
2391                                 list_del(&cmd_buffer->pool_link);
2392                                 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2393                         } else
2394                                 radv_cmd_buffer_destroy(cmd_buffer);
2395
2396                 }
2397         }
2398 }
2399
2400 VkResult radv_ResetCommandBuffer(
2401         VkCommandBuffer commandBuffer,
2402         VkCommandBufferResetFlags flags)
2403 {
2404         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2405         return radv_reset_cmd_buffer(cmd_buffer);
2406 }
2407
2408 VkResult radv_BeginCommandBuffer(
2409         VkCommandBuffer commandBuffer,
2410         const VkCommandBufferBeginInfo *pBeginInfo)
2411 {
2412         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2413         VkResult result = VK_SUCCESS;
2414
2415         if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2416                 /* If the command buffer has already been resetted with
2417                  * vkResetCommandBuffer, no need to do it again.
2418                  */
2419                 result = radv_reset_cmd_buffer(cmd_buffer);
2420                 if (result != VK_SUCCESS)
2421                         return result;
2422         }
2423
2424         memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2425         cmd_buffer->state.last_primitive_reset_en = -1;
2426         cmd_buffer->state.last_index_type = -1;
2427         cmd_buffer->state.last_num_instances = -1;
2428         cmd_buffer->state.last_vertex_offset = -1;
2429         cmd_buffer->state.last_first_instance = -1;
2430         cmd_buffer->state.predication_type = -1;
2431         cmd_buffer->usage_flags = pBeginInfo->flags;
2432
2433         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2434             (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2435                 assert(pBeginInfo->pInheritanceInfo);
2436                 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2437                 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2438
2439                 struct radv_subpass *subpass =
2440                         &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2441
2442                 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2443                 if (result != VK_SUCCESS)
2444                         return result;
2445
2446                 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2447         }
2448
2449         if (unlikely(cmd_buffer->device->trace_bo)) {
2450                 struct radv_device *device = cmd_buffer->device;
2451
2452                 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2453                                    device->trace_bo);
2454
2455                 radv_cmd_buffer_trace_emit(cmd_buffer);
2456         }
2457
2458         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2459
2460         return result;
2461 }
2462
2463 void radv_CmdBindVertexBuffers(
2464         VkCommandBuffer                             commandBuffer,
2465         uint32_t                                    firstBinding,
2466         uint32_t                                    bindingCount,
2467         const VkBuffer*                             pBuffers,
2468         const VkDeviceSize*                         pOffsets)
2469 {
2470         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2471         struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2472         bool changed = false;
2473
2474         /* We have to defer setting up vertex buffer since we need the buffer
2475          * stride from the pipeline. */
2476
2477         assert(firstBinding + bindingCount <= MAX_VBS);
2478         for (uint32_t i = 0; i < bindingCount; i++) {
2479                 uint32_t idx = firstBinding + i;
2480
2481                 if (!changed &&
2482                     (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2483                      vb[idx].offset != pOffsets[i])) {
2484                         changed = true;
2485                 }
2486
2487                 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2488                 vb[idx].offset = pOffsets[i];
2489
2490                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2491                                    vb[idx].buffer->bo);
2492         }
2493
2494         if (!changed) {
2495                 /* No state changes. */
2496                 return;
2497         }
2498
2499         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2500 }
2501
2502 void radv_CmdBindIndexBuffer(
2503         VkCommandBuffer                             commandBuffer,
2504         VkBuffer buffer,
2505         VkDeviceSize offset,
2506         VkIndexType indexType)
2507 {
2508         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2509         RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2510
2511         if (cmd_buffer->state.index_buffer == index_buffer &&
2512             cmd_buffer->state.index_offset == offset &&
2513             cmd_buffer->state.index_type == indexType) {
2514                 /* No state changes. */
2515                 return;
2516         }
2517
2518         cmd_buffer->state.index_buffer = index_buffer;
2519         cmd_buffer->state.index_offset = offset;
2520         cmd_buffer->state.index_type = indexType; /* vk matches hw */
2521         cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2522         cmd_buffer->state.index_va += index_buffer->offset + offset;
2523
2524         int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2525         cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2526         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2527         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2528 }
2529
2530
2531 static void
2532 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2533                          VkPipelineBindPoint bind_point,
2534                          struct radv_descriptor_set *set, unsigned idx)
2535 {
2536         struct radeon_winsys *ws = cmd_buffer->device->ws;
2537
2538         radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2539
2540         assert(set);
2541         assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2542
2543         if (!cmd_buffer->device->use_global_bo_list) {
2544                 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2545                         if (set->descriptors[j])
2546                                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2547         }
2548
2549         if(set->bo)
2550                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2551 }
2552
2553 void radv_CmdBindDescriptorSets(
2554         VkCommandBuffer                             commandBuffer,
2555         VkPipelineBindPoint                         pipelineBindPoint,
2556         VkPipelineLayout                            _layout,
2557         uint32_t                                    firstSet,
2558         uint32_t                                    descriptorSetCount,
2559         const VkDescriptorSet*                      pDescriptorSets,
2560         uint32_t                                    dynamicOffsetCount,
2561         const uint32_t*                             pDynamicOffsets)
2562 {
2563         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2564         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2565         unsigned dyn_idx = 0;
2566
2567         const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2568         struct radv_descriptor_state *descriptors_state =
2569                 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2570
2571         for (unsigned i = 0; i < descriptorSetCount; ++i) {
2572                 unsigned idx = i + firstSet;
2573                 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2574                 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2575
2576                 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2577                         unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2578                         uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2579                         assert(dyn_idx < dynamicOffsetCount);
2580
2581                         struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2582                         uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2583                         dst[0] = va;
2584                         dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2585                         dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2586                         dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2587                                  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2588                                  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2589                                  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2590                                  S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2591                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2592                         cmd_buffer->push_constant_stages |=
2593                                              set->layout->dynamic_shader_stages;
2594                 }
2595         }
2596 }
2597
2598 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2599                                           struct radv_descriptor_set *set,
2600                                           struct radv_descriptor_set_layout *layout,
2601                                           VkPipelineBindPoint bind_point)
2602 {
2603         struct radv_descriptor_state *descriptors_state =
2604                 radv_get_descriptors_state(cmd_buffer, bind_point);
2605         set->size = layout->size;
2606         set->layout = layout;
2607
2608         if (descriptors_state->push_set.capacity < set->size) {
2609                 size_t new_size = MAX2(set->size, 1024);
2610                 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2611                 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2612
2613                 free(set->mapped_ptr);
2614                 set->mapped_ptr = malloc(new_size);
2615
2616                 if (!set->mapped_ptr) {
2617                         descriptors_state->push_set.capacity = 0;
2618                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2619                         return false;
2620                 }
2621
2622                 descriptors_state->push_set.capacity = new_size;
2623         }
2624
2625         return true;
2626 }
2627
2628 void radv_meta_push_descriptor_set(
2629         struct radv_cmd_buffer*              cmd_buffer,
2630         VkPipelineBindPoint                  pipelineBindPoint,
2631         VkPipelineLayout                     _layout,
2632         uint32_t                             set,
2633         uint32_t                             descriptorWriteCount,
2634         const VkWriteDescriptorSet*          pDescriptorWrites)
2635 {
2636         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2637         struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2638         unsigned bo_offset;
2639
2640         assert(set == 0);
2641         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2642
2643         push_set->size = layout->set[set].layout->size;
2644         push_set->layout = layout->set[set].layout;
2645
2646         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2647                                           &bo_offset,
2648                                           (void**) &push_set->mapped_ptr))
2649                 return;
2650
2651         push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2652         push_set->va += bo_offset;
2653
2654         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2655                                     radv_descriptor_set_to_handle(push_set),
2656                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2657
2658         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2659 }
2660
2661 void radv_CmdPushDescriptorSetKHR(
2662         VkCommandBuffer                             commandBuffer,
2663         VkPipelineBindPoint                         pipelineBindPoint,
2664         VkPipelineLayout                            _layout,
2665         uint32_t                                    set,
2666         uint32_t                                    descriptorWriteCount,
2667         const VkWriteDescriptorSet*                 pDescriptorWrites)
2668 {
2669         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2670         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2671         struct radv_descriptor_state *descriptors_state =
2672                 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2673         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2674
2675         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2676
2677         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2678                                            layout->set[set].layout,
2679                                            pipelineBindPoint))
2680                 return;
2681
2682         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2683                                     radv_descriptor_set_to_handle(push_set),
2684                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2685
2686         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2687         descriptors_state->push_dirty = true;
2688 }
2689
2690 void radv_CmdPushDescriptorSetWithTemplateKHR(
2691         VkCommandBuffer                             commandBuffer,
2692         VkDescriptorUpdateTemplateKHR               descriptorUpdateTemplate,
2693         VkPipelineLayout                            _layout,
2694         uint32_t                                    set,
2695         const void*                                 pData)
2696 {
2697         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2698         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2699         RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2700         struct radv_descriptor_state *descriptors_state =
2701                 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2702         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2703
2704         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2705
2706         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2707                                            layout->set[set].layout,
2708                                            templ->bind_point))
2709                 return;
2710
2711         radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2712                                                  descriptorUpdateTemplate, pData);
2713
2714         radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2715         descriptors_state->push_dirty = true;
2716 }
2717
2718 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2719                            VkPipelineLayout layout,
2720                            VkShaderStageFlags stageFlags,
2721                            uint32_t offset,
2722                            uint32_t size,
2723                            const void* pValues)
2724 {
2725         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2726         memcpy(cmd_buffer->push_constants + offset, pValues, size);
2727         cmd_buffer->push_constant_stages |= stageFlags;
2728 }
2729
2730 VkResult radv_EndCommandBuffer(
2731         VkCommandBuffer                             commandBuffer)
2732 {
2733         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2734
2735         if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2736                 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2737                         cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2738                 si_emit_cache_flush(cmd_buffer);
2739         }
2740
2741         /* Make sure CP DMA is idle at the end of IBs because the kernel
2742          * doesn't wait for it.
2743          */
2744         si_cp_dma_wait_for_idle(cmd_buffer);
2745
2746         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2747
2748         if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2749                 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2750
2751         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2752
2753         return cmd_buffer->record_result;
2754 }
2755
2756 static void
2757 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2758 {
2759         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2760
2761         if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2762                 return;
2763
2764         cmd_buffer->state.emitted_compute_pipeline = pipeline;
2765
2766         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2767         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2768
2769         cmd_buffer->compute_scratch_size_needed =
2770                                   MAX2(cmd_buffer->compute_scratch_size_needed,
2771                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2772
2773         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2774                            pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2775
2776         if (unlikely(cmd_buffer->device->trace_bo))
2777                 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2778 }
2779
2780 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2781                                             VkPipelineBindPoint bind_point)
2782 {
2783         struct radv_descriptor_state *descriptors_state =
2784                 radv_get_descriptors_state(cmd_buffer, bind_point);
2785
2786         descriptors_state->dirty |= descriptors_state->valid;
2787 }
2788
2789 void radv_CmdBindPipeline(
2790         VkCommandBuffer                             commandBuffer,
2791         VkPipelineBindPoint                         pipelineBindPoint,
2792         VkPipeline                                  _pipeline)
2793 {
2794         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2795         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2796
2797         switch (pipelineBindPoint) {
2798         case VK_PIPELINE_BIND_POINT_COMPUTE:
2799                 if (cmd_buffer->state.compute_pipeline == pipeline)
2800                         return;
2801                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2802
2803                 cmd_buffer->state.compute_pipeline = pipeline;
2804                 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2805                 break;
2806         case VK_PIPELINE_BIND_POINT_GRAPHICS:
2807                 if (cmd_buffer->state.pipeline == pipeline)
2808                         return;
2809                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2810
2811                 cmd_buffer->state.pipeline = pipeline;
2812                 if (!pipeline)
2813                         break;
2814
2815                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2816                 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2817
2818                 /* the new vertex shader might not have the same user regs */
2819                 cmd_buffer->state.last_first_instance = -1;
2820                 cmd_buffer->state.last_vertex_offset = -1;
2821
2822                 /* Prefetch all pipeline shaders at first draw time. */
2823                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2824
2825                 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2826                 radv_bind_streamout_state(cmd_buffer, pipeline);
2827
2828                 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2829                         cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2830                 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2831                         cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2832
2833                 if (radv_pipeline_has_tess(pipeline))
2834                         cmd_buffer->tess_rings_needed = true;
2835                 break;
2836         default:
2837                 assert(!"invalid bind point");
2838                 break;
2839         }
2840 }
2841
2842 void radv_CmdSetViewport(
2843         VkCommandBuffer                             commandBuffer,
2844         uint32_t                                    firstViewport,
2845         uint32_t                                    viewportCount,
2846         const VkViewport*                           pViewports)
2847 {
2848         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2849         struct radv_cmd_state *state = &cmd_buffer->state;
2850         MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2851
2852         assert(firstViewport < MAX_VIEWPORTS);
2853         assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2854
2855         memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2856                viewportCount * sizeof(*pViewports));
2857
2858         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2859 }
2860
2861 void radv_CmdSetScissor(
2862         VkCommandBuffer                             commandBuffer,
2863         uint32_t                                    firstScissor,
2864         uint32_t                                    scissorCount,
2865         const VkRect2D*                             pScissors)
2866 {
2867         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2868         struct radv_cmd_state *state = &cmd_buffer->state;
2869         MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2870
2871         assert(firstScissor < MAX_SCISSORS);
2872         assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2873
2874         memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2875                scissorCount * sizeof(*pScissors));
2876
2877         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2878 }
2879
2880 void radv_CmdSetLineWidth(
2881         VkCommandBuffer                             commandBuffer,
2882         float                                       lineWidth)
2883 {
2884         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2885         cmd_buffer->state.dynamic.line_width = lineWidth;
2886         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2887 }
2888
2889 void radv_CmdSetDepthBias(
2890         VkCommandBuffer                             commandBuffer,
2891         float                                       depthBiasConstantFactor,
2892         float                                       depthBiasClamp,
2893         float                                       depthBiasSlopeFactor)
2894 {
2895         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2896
2897         cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2898         cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2899         cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2900
2901         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2902 }
2903
2904 void radv_CmdSetBlendConstants(
2905         VkCommandBuffer                             commandBuffer,
2906         const float                                 blendConstants[4])
2907 {
2908         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2909
2910         memcpy(cmd_buffer->state.dynamic.blend_constants,
2911                blendConstants, sizeof(float) * 4);
2912
2913         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2914 }
2915
2916 void radv_CmdSetDepthBounds(
2917         VkCommandBuffer                             commandBuffer,
2918         float                                       minDepthBounds,
2919         float                                       maxDepthBounds)
2920 {
2921         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2922
2923         cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2924         cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2925
2926         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2927 }
2928
2929 void radv_CmdSetStencilCompareMask(
2930         VkCommandBuffer                             commandBuffer,
2931         VkStencilFaceFlags                          faceMask,
2932         uint32_t                                    compareMask)
2933 {
2934         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2935
2936         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2937                 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2938         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2939                 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2940
2941         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2942 }
2943
2944 void radv_CmdSetStencilWriteMask(
2945         VkCommandBuffer                             commandBuffer,
2946         VkStencilFaceFlags                          faceMask,
2947         uint32_t                                    writeMask)
2948 {
2949         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2950
2951         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2952                 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2953         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2954                 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2955
2956         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2957 }
2958
2959 void radv_CmdSetStencilReference(
2960         VkCommandBuffer                             commandBuffer,
2961         VkStencilFaceFlags                          faceMask,
2962         uint32_t                                    reference)
2963 {
2964         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2965
2966         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2967                 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2968         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2969                 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2970
2971         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2972 }
2973
2974 void radv_CmdSetDiscardRectangleEXT(
2975         VkCommandBuffer                             commandBuffer,
2976         uint32_t                                    firstDiscardRectangle,
2977         uint32_t                                    discardRectangleCount,
2978         const VkRect2D*                             pDiscardRectangles)
2979 {
2980         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2981         struct radv_cmd_state *state = &cmd_buffer->state;
2982         MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2983
2984         assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2985         assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2986
2987         typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2988                      pDiscardRectangles, discardRectangleCount);
2989
2990         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2991 }
2992
2993 void radv_CmdExecuteCommands(
2994         VkCommandBuffer                             commandBuffer,
2995         uint32_t                                    commandBufferCount,
2996         const VkCommandBuffer*                      pCmdBuffers)
2997 {
2998         RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2999
3000         assert(commandBufferCount > 0);
3001
3002         /* Emit pending flushes on primary prior to executing secondary */
3003         si_emit_cache_flush(primary);
3004
3005         for (uint32_t i = 0; i < commandBufferCount; i++) {
3006                 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3007
3008                 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3009                                                     secondary->scratch_size_needed);
3010                 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3011                                                             secondary->compute_scratch_size_needed);
3012
3013                 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3014                         primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3015                 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3016                         primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3017                 if (secondary->tess_rings_needed)
3018                         primary->tess_rings_needed = true;
3019                 if (secondary->sample_positions_needed)
3020                         primary->sample_positions_needed = true;
3021
3022                 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3023
3024
3025                 /* When the secondary command buffer is compute only we don't
3026                  * need to re-emit the current graphics pipeline.
3027                  */
3028                 if (secondary->state.emitted_pipeline) {
3029                         primary->state.emitted_pipeline =
3030                                 secondary->state.emitted_pipeline;
3031                 }
3032
3033                 /* When the secondary command buffer is graphics only we don't
3034                  * need to re-emit the current compute pipeline.
3035                  */
3036                 if (secondary->state.emitted_compute_pipeline) {
3037                         primary->state.emitted_compute_pipeline =
3038                                 secondary->state.emitted_compute_pipeline;
3039                 }
3040
3041                 /* Only re-emit the draw packets when needed. */
3042                 if (secondary->state.last_primitive_reset_en != -1) {
3043                         primary->state.last_primitive_reset_en =
3044                                 secondary->state.last_primitive_reset_en;
3045                 }
3046
3047                 if (secondary->state.last_primitive_reset_index) {
3048                         primary->state.last_primitive_reset_index =
3049                                 secondary->state.last_primitive_reset_index;
3050                 }
3051
3052                 if (secondary->state.last_ia_multi_vgt_param) {
3053                         primary->state.last_ia_multi_vgt_param =
3054                                 secondary->state.last_ia_multi_vgt_param;
3055                 }
3056
3057                 primary->state.last_first_instance = secondary->state.last_first_instance;
3058                 primary->state.last_num_instances = secondary->state.last_num_instances;
3059                 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3060
3061                 if (secondary->state.last_index_type != -1) {
3062                         primary->state.last_index_type =
3063                                 secondary->state.last_index_type;
3064                 }
3065         }
3066
3067         /* After executing commands from secondary buffers we have to dirty
3068          * some states.
3069          */
3070         primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3071                                 RADV_CMD_DIRTY_INDEX_BUFFER |
3072                                 RADV_CMD_DIRTY_DYNAMIC_ALL;
3073         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3074         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3075 }
3076
3077 VkResult radv_CreateCommandPool(
3078         VkDevice                                    _device,
3079         const VkCommandPoolCreateInfo*              pCreateInfo,
3080         const VkAllocationCallbacks*                pAllocator,
3081         VkCommandPool*                              pCmdPool)
3082 {
3083         RADV_FROM_HANDLE(radv_device, device, _device);
3084         struct radv_cmd_pool *pool;
3085
3086         pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3087                            VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3088         if (pool == NULL)
3089                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3090
3091         if (pAllocator)
3092                 pool->alloc = *pAllocator;
3093         else
3094                 pool->alloc = device->alloc;
3095
3096         list_inithead(&pool->cmd_buffers);
3097         list_inithead(&pool->free_cmd_buffers);
3098
3099         pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3100
3101         *pCmdPool = radv_cmd_pool_to_handle(pool);
3102
3103         return VK_SUCCESS;
3104
3105 }
3106
3107 void radv_DestroyCommandPool(
3108         VkDevice                                    _device,
3109         VkCommandPool                               commandPool,
3110         const VkAllocationCallbacks*                pAllocator)
3111 {
3112         RADV_FROM_HANDLE(radv_device, device, _device);
3113         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3114
3115         if (!pool)
3116                 return;
3117
3118         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3119                                  &pool->cmd_buffers, pool_link) {
3120                 radv_cmd_buffer_destroy(cmd_buffer);
3121         }
3122
3123         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3124                                  &pool->free_cmd_buffers, pool_link) {
3125                 radv_cmd_buffer_destroy(cmd_buffer);
3126         }
3127
3128         vk_free2(&device->alloc, pAllocator, pool);
3129 }
3130
3131 VkResult radv_ResetCommandPool(
3132         VkDevice                                    device,
3133         VkCommandPool                               commandPool,
3134         VkCommandPoolResetFlags                     flags)
3135 {
3136         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3137         VkResult result;
3138
3139         list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3140                             &pool->cmd_buffers, pool_link) {
3141                 result = radv_reset_cmd_buffer(cmd_buffer);
3142                 if (result != VK_SUCCESS)
3143                         return result;
3144         }
3145
3146         return VK_SUCCESS;
3147 }
3148
3149 void radv_TrimCommandPool(
3150     VkDevice                                    device,
3151     VkCommandPool                               commandPool,
3152     VkCommandPoolTrimFlagsKHR                   flags)
3153 {
3154         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3155
3156         if (!pool)
3157                 return;
3158
3159         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3160                                  &pool->free_cmd_buffers, pool_link) {
3161                 radv_cmd_buffer_destroy(cmd_buffer);
3162         }
3163 }
3164
3165 void radv_CmdBeginRenderPass(
3166         VkCommandBuffer                             commandBuffer,
3167         const VkRenderPassBeginInfo*                pRenderPassBegin,
3168         VkSubpassContents                           contents)
3169 {
3170         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3171         RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3172         RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3173
3174         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3175                                                            cmd_buffer->cs, 2048);
3176         MAYBE_UNUSED VkResult result;
3177
3178         cmd_buffer->state.framebuffer = framebuffer;
3179         cmd_buffer->state.pass = pass;
3180         cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3181
3182         result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3183         if (result != VK_SUCCESS)
3184                 return;
3185
3186         radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3187         assert(cmd_buffer->cs->cdw <= cdw_max);
3188
3189         radv_cmd_buffer_clear_subpass(cmd_buffer);
3190 }
3191
3192 void radv_CmdBeginRenderPass2KHR(
3193     VkCommandBuffer                             commandBuffer,
3194     const VkRenderPassBeginInfo*                pRenderPassBeginInfo,
3195     const VkSubpassBeginInfoKHR*                pSubpassBeginInfo)
3196 {
3197         radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3198                                 pSubpassBeginInfo->contents);
3199 }
3200
3201 void radv_CmdNextSubpass(
3202     VkCommandBuffer                             commandBuffer,
3203     VkSubpassContents                           contents)
3204 {
3205         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3206
3207         radv_cmd_buffer_resolve_subpass(cmd_buffer);
3208
3209         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3210                                               2048);
3211
3212         radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3213         radv_cmd_buffer_clear_subpass(cmd_buffer);
3214 }
3215
3216 void radv_CmdNextSubpass2KHR(
3217     VkCommandBuffer                             commandBuffer,
3218     const VkSubpassBeginInfoKHR*                pSubpassBeginInfo,
3219     const VkSubpassEndInfoKHR*                  pSubpassEndInfo)
3220 {
3221         radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3222 }
3223
3224 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3225 {
3226         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3227         for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3228                 if (!radv_get_shader(pipeline, stage))
3229                         continue;
3230
3231                 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3232                 if (loc->sgpr_idx == -1)
3233                         continue;
3234                 uint32_t base_reg = pipeline->user_data_0[stage];
3235                 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3236
3237         }
3238         if (pipeline->gs_copy_shader) {
3239                 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3240                 if (loc->sgpr_idx != -1) {
3241                         uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3242                         radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3243                 }
3244         }
3245 }
3246
3247 static void
3248 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3249                          uint32_t vertex_count,
3250                          bool use_opaque)
3251 {
3252         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3253         radeon_emit(cmd_buffer->cs, vertex_count);
3254         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3255                                     S_0287F0_USE_OPAQUE(use_opaque));
3256 }
3257
3258 static void
3259 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3260                                  uint64_t index_va,
3261                                  uint32_t index_count)
3262 {
3263         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3264         radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3265         radeon_emit(cmd_buffer->cs, index_va);
3266         radeon_emit(cmd_buffer->cs, index_va >> 32);
3267         radeon_emit(cmd_buffer->cs, index_count);
3268         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3269 }
3270
3271 static void
3272 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3273                                   bool indexed,
3274                                   uint32_t draw_count,
3275                                   uint64_t count_va,
3276                                   uint32_t stride)
3277 {
3278         struct radeon_cmdbuf *cs = cmd_buffer->cs;
3279         unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3280                                       : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3281         bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3282         uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3283         bool predicating = cmd_buffer->state.predicating;
3284         assert(base_reg);
3285
3286         /* just reset draw state for vertex data */
3287         cmd_buffer->state.last_first_instance = -1;
3288         cmd_buffer->state.last_num_instances = -1;
3289         cmd_buffer->state.last_vertex_offset = -1;
3290
3291         if (draw_count == 1 && !count_va && !draw_id_enable) {
3292                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3293                                      PKT3_DRAW_INDIRECT, 3, predicating));
3294                 radeon_emit(cs, 0);
3295                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3296                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3297                 radeon_emit(cs, di_src_sel);
3298         } else {
3299                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3300                                      PKT3_DRAW_INDIRECT_MULTI,
3301                                      8, predicating));
3302                 radeon_emit(cs, 0);
3303                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3304                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3305                 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3306                             S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3307                             S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3308                 radeon_emit(cs, draw_count); /* count */
3309                 radeon_emit(cs, count_va); /* count_addr */
3310                 radeon_emit(cs, count_va >> 32);
3311                 radeon_emit(cs, stride); /* stride */
3312                 radeon_emit(cs, di_src_sel);
3313         }
3314 }
3315
3316 struct radv_draw_info {
3317         /**
3318          * Number of vertices.
3319          */
3320         uint32_t count;
3321
3322         /**
3323          * Index of the first vertex.
3324          */
3325         int32_t vertex_offset;
3326
3327         /**
3328          * First instance id.
3329          */
3330         uint32_t first_instance;
3331
3332         /**
3333          * Number of instances.
3334          */
3335         uint32_t instance_count;
3336
3337         /**
3338          * First index (indexed draws only).
3339          */
3340         uint32_t first_index;
3341
3342         /**
3343          * Whether it's an indexed draw.
3344          */
3345         bool indexed;
3346
3347         /**
3348          * Indirect draw parameters resource.
3349          */
3350         struct radv_buffer *indirect;
3351         uint64_t indirect_offset;
3352         uint32_t stride;
3353
3354         /**
3355          * Draw count parameters resource.
3356          */
3357         struct radv_buffer *count_buffer;
3358         uint64_t count_buffer_offset;
3359
3360         /**
3361          * Stream output parameters resource.
3362          */
3363         struct radv_buffer *strmout_buffer;
3364         uint64_t strmout_buffer_offset;
3365 };
3366
3367 static void
3368 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3369                        const struct radv_draw_info *info)
3370 {
3371         struct radv_cmd_state *state = &cmd_buffer->state;
3372         struct radeon_winsys *ws = cmd_buffer->device->ws;
3373         struct radeon_cmdbuf *cs = cmd_buffer->cs;
3374
3375         if (info->strmout_buffer) {
3376                 uint64_t va = radv_buffer_get_va(info->strmout_buffer->bo);
3377
3378                 va += info->strmout_buffer->offset +
3379                       info->strmout_buffer_offset;
3380
3381                 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
3382                                        info->stride);
3383
3384                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3385                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3386                                 COPY_DATA_DST_SEL(COPY_DATA_REG) |
3387                                 COPY_DATA_WR_CONFIRM);
3388                 radeon_emit(cs, va);
3389                 radeon_emit(cs, va >> 32);
3390                 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
3391                 radeon_emit(cs, 0); /* unused */
3392
3393                 radv_cs_add_buffer(ws, cs, info->strmout_buffer->bo);
3394         }
3395
3396         if (info->indirect) {
3397                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3398                 uint64_t count_va = 0;
3399
3400                 va += info->indirect->offset + info->indirect_offset;
3401
3402                 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3403
3404                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3405                 radeon_emit(cs, 1);
3406                 radeon_emit(cs, va);
3407                 radeon_emit(cs, va >> 32);
3408
3409                 if (info->count_buffer) {
3410                         count_va = radv_buffer_get_va(info->count_buffer->bo);
3411                         count_va += info->count_buffer->offset +
3412                                     info->count_buffer_offset;
3413
3414                         radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3415                 }
3416
3417                 if (!state->subpass->view_mask) {
3418                         radv_cs_emit_indirect_draw_packet(cmd_buffer,
3419                                                           info->indexed,
3420                                                           info->count,
3421                                                           count_va,
3422                                                           info->stride);
3423                 } else {
3424                         unsigned i;
3425                         for_each_bit(i, state->subpass->view_mask) {
3426                                 radv_emit_view_index(cmd_buffer, i);
3427
3428                                 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3429                                                                   info->indexed,
3430                                                                   info->count,
3431                                                                   count_va,
3432                                                                   info->stride);
3433                         }
3434                 }
3435         } else {
3436                 assert(state->pipeline->graphics.vtx_base_sgpr);
3437
3438                 if (info->vertex_offset != state->last_vertex_offset ||
3439                     info->first_instance != state->last_first_instance) {
3440                         radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3441                                               state->pipeline->graphics.vtx_emit_num);
3442
3443                         radeon_emit(cs, info->vertex_offset);
3444                         radeon_emit(cs, info->first_instance);
3445                         if (state->pipeline->graphics.vtx_emit_num == 3)
3446                                 radeon_emit(cs, 0);
3447                         state->last_first_instance = info->first_instance;
3448                         state->last_vertex_offset = info->vertex_offset;
3449                 }
3450
3451                 if (state->last_num_instances != info->instance_count) {
3452                         radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3453                         radeon_emit(cs, info->instance_count);
3454                         state->last_num_instances = info->instance_count;
3455                 }
3456
3457                 if (info->indexed) {
3458                         int index_size = state->index_type ? 4 : 2;
3459                         uint64_t index_va;
3460
3461                         index_va = state->index_va;
3462                         index_va += info->first_index * index_size;
3463
3464                         if (!state->subpass->view_mask) {
3465                                 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3466                                                                  index_va,
3467                                                                  info->count);
3468                         } else {
3469                                 unsigned i;
3470                                 for_each_bit(i, state->subpass->view_mask) {
3471                                         radv_emit_view_index(cmd_buffer, i);
3472
3473                                         radv_cs_emit_draw_indexed_packet(cmd_buffer,
3474                                                                          index_va,
3475                                                                          info->count);
3476                                 }
3477                         }
3478                 } else {
3479                         if (!state->subpass->view_mask) {
3480                                 radv_cs_emit_draw_packet(cmd_buffer,
3481                                                          info->count,
3482                                                          !!info->strmout_buffer);
3483                         } else {
3484                                 unsigned i;
3485                                 for_each_bit(i, state->subpass->view_mask) {
3486                                         radv_emit_view_index(cmd_buffer, i);
3487
3488                                         radv_cs_emit_draw_packet(cmd_buffer,
3489                                                                  info->count,
3490                                                                  !!info->strmout_buffer);
3491                                 }
3492                         }
3493                 }
3494         }
3495 }
3496
3497 /*
3498  * Vega and raven have a bug which triggers if there are multiple context
3499  * register contexts active at the same time with different scissor values.
3500  *
3501  * There are two possible workarounds:
3502  * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3503  *    there is only ever 1 active set of scissor values at the same time.
3504  *
3505  * 2) Whenever the hardware switches contexts we have to set the scissor
3506  *    registers again even if it is a noop. That way the new context gets
3507  *    the correct scissor values.
3508  *
3509  * This implements option 2. radv_need_late_scissor_emission needs to
3510  * return true on affected HW if radv_emit_all_graphics_states sets
3511  * any context registers.
3512  */
3513 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3514                                             bool indexed_draw)
3515 {
3516         struct radv_cmd_state *state = &cmd_buffer->state;
3517
3518         if (!cmd_buffer->device->physical_device->has_scissor_bug)
3519                 return false;
3520
3521         uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3522
3523         /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
3524         used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER | RADV_CMD_DIRTY_VERTEX_BUFFER | RADV_CMD_DIRTY_PIPELINE);
3525
3526         /* Assume all state changes except  these two can imply context rolls. */
3527         if (cmd_buffer->state.dirty & used_states)
3528                 return true;
3529
3530         if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3531                 return true;
3532
3533         if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3534             (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3535                 return true;
3536
3537         return false;
3538 }
3539
3540 static void
3541 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3542                               const struct radv_draw_info *info)
3543 {
3544         bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3545
3546         if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3547             cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3548                 radv_emit_rbplus_state(cmd_buffer);
3549
3550         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3551                 radv_emit_graphics_pipeline(cmd_buffer);
3552
3553         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3554                 radv_emit_framebuffer_state(cmd_buffer);
3555
3556         if (info->indexed) {
3557                 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3558                         radv_emit_index_buffer(cmd_buffer);
3559         } else {
3560                 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3561                  * so the state must be re-emitted before the next indexed
3562                  * draw.
3563                  */
3564                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3565                         cmd_buffer->state.last_index_type = -1;
3566                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3567                 }
3568         }
3569
3570         radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3571
3572         radv_emit_draw_registers(cmd_buffer, info->indexed,
3573                                  info->instance_count > 1, info->indirect,
3574                                  info->indirect ? 0 : info->count);
3575
3576         if (late_scissor_emission)
3577                 radv_emit_scissor(cmd_buffer);
3578 }
3579
3580 static void
3581 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3582           const struct radv_draw_info *info)
3583 {
3584         struct radeon_info *rad_info =
3585                 &cmd_buffer->device->physical_device->rad_info;
3586         bool has_prefetch =
3587                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3588         bool pipeline_is_dirty =
3589                 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3590                 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3591
3592         MAYBE_UNUSED unsigned cdw_max =
3593                 radeon_check_space(cmd_buffer->device->ws,
3594                                    cmd_buffer->cs, 4096);
3595
3596         /* Use optimal packet order based on whether we need to sync the
3597          * pipeline.
3598          */
3599         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3600                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3601                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3602                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3603                 /* If we have to wait for idle, set all states first, so that
3604                  * all SET packets are processed in parallel with previous draw
3605                  * calls. Then upload descriptors, set shader pointers, and
3606                  * draw, and prefetch at the end. This ensures that the time
3607                  * the CUs are idle is very short. (there are only SET_SH
3608                  * packets between the wait and the draw)
3609                  */
3610                 radv_emit_all_graphics_states(cmd_buffer, info);
3611                 si_emit_cache_flush(cmd_buffer);
3612                 /* <-- CUs are idle here --> */
3613
3614                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3615
3616                 radv_emit_draw_packets(cmd_buffer, info);
3617                 /* <-- CUs are busy here --> */
3618
3619                 /* Start prefetches after the draw has been started. Both will
3620                  * run in parallel, but starting the draw first is more
3621                  * important.
3622                  */
3623                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3624                         radv_emit_prefetch_L2(cmd_buffer,
3625                                               cmd_buffer->state.pipeline, false);
3626                 }
3627         } else {
3628                 /* If we don't wait for idle, start prefetches first, then set
3629                  * states, and draw at the end.
3630                  */
3631                 si_emit_cache_flush(cmd_buffer);
3632
3633                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3634                         /* Only prefetch the vertex shader and VBO descriptors
3635                          * in order to start the draw as soon as possible.
3636                          */
3637                         radv_emit_prefetch_L2(cmd_buffer,
3638                                               cmd_buffer->state.pipeline, true);
3639                 }
3640
3641                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3642
3643                 radv_emit_all_graphics_states(cmd_buffer, info);
3644                 radv_emit_draw_packets(cmd_buffer, info);
3645
3646                 /* Prefetch the remaining shaders after the draw has been
3647                  * started.
3648                  */
3649                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3650                         radv_emit_prefetch_L2(cmd_buffer,
3651                                               cmd_buffer->state.pipeline, false);
3652                 }
3653         }
3654
3655         /* Workaround for a VGT hang when streamout is enabled.
3656          * It must be done after drawing.
3657          */
3658         if (cmd_buffer->state.streamout.streamout_enabled &&
3659             (rad_info->family == CHIP_HAWAII ||
3660              rad_info->family == CHIP_TONGA ||
3661              rad_info->family == CHIP_FIJI)) {
3662                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3663         }
3664
3665         assert(cmd_buffer->cs->cdw <= cdw_max);
3666         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3667 }
3668
3669 void radv_CmdDraw(
3670         VkCommandBuffer                             commandBuffer,
3671         uint32_t                                    vertexCount,
3672         uint32_t                                    instanceCount,
3673         uint32_t                                    firstVertex,
3674         uint32_t                                    firstInstance)
3675 {
3676         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3677         struct radv_draw_info info = {};
3678
3679         info.count = vertexCount;
3680         info.instance_count = instanceCount;
3681         info.first_instance = firstInstance;
3682         info.vertex_offset = firstVertex;
3683
3684         radv_draw(cmd_buffer, &info);
3685 }
3686
3687 void radv_CmdDrawIndexed(
3688         VkCommandBuffer                             commandBuffer,
3689         uint32_t                                    indexCount,
3690         uint32_t                                    instanceCount,
3691         uint32_t                                    firstIndex,
3692         int32_t                                     vertexOffset,
3693         uint32_t                                    firstInstance)
3694 {
3695         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3696         struct radv_draw_info info = {};
3697
3698         info.indexed = true;
3699         info.count = indexCount;
3700         info.instance_count = instanceCount;
3701         info.first_index = firstIndex;
3702         info.vertex_offset = vertexOffset;
3703         info.first_instance = firstInstance;
3704
3705         radv_draw(cmd_buffer, &info);
3706 }
3707
3708 void radv_CmdDrawIndirect(
3709         VkCommandBuffer                             commandBuffer,
3710         VkBuffer                                    _buffer,
3711         VkDeviceSize                                offset,
3712         uint32_t                                    drawCount,
3713         uint32_t                                    stride)
3714 {
3715         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3716         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3717         struct radv_draw_info info = {};
3718
3719         info.count = drawCount;
3720         info.indirect = buffer;
3721         info.indirect_offset = offset;
3722         info.stride = stride;
3723
3724         radv_draw(cmd_buffer, &info);
3725 }
3726
3727 void radv_CmdDrawIndexedIndirect(
3728         VkCommandBuffer                             commandBuffer,
3729         VkBuffer                                    _buffer,
3730         VkDeviceSize                                offset,
3731         uint32_t                                    drawCount,
3732         uint32_t                                    stride)
3733 {
3734         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3735         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3736         struct radv_draw_info info = {};
3737
3738         info.indexed = true;
3739         info.count = drawCount;
3740         info.indirect = buffer;
3741         info.indirect_offset = offset;
3742         info.stride = stride;
3743
3744         radv_draw(cmd_buffer, &info);
3745 }
3746
3747 void radv_CmdDrawIndirectCountAMD(
3748         VkCommandBuffer                             commandBuffer,
3749         VkBuffer                                    _buffer,
3750         VkDeviceSize                                offset,
3751         VkBuffer                                    _countBuffer,
3752         VkDeviceSize                                countBufferOffset,
3753         uint32_t                                    maxDrawCount,
3754         uint32_t                                    stride)
3755 {
3756         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3757         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3758         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3759         struct radv_draw_info info = {};
3760
3761         info.count = maxDrawCount;
3762         info.indirect = buffer;
3763         info.indirect_offset = offset;
3764         info.count_buffer = count_buffer;
3765         info.count_buffer_offset = countBufferOffset;
3766         info.stride = stride;
3767
3768         radv_draw(cmd_buffer, &info);
3769 }
3770
3771 void radv_CmdDrawIndexedIndirectCountAMD(
3772         VkCommandBuffer                             commandBuffer,
3773         VkBuffer                                    _buffer,
3774         VkDeviceSize                                offset,
3775         VkBuffer                                    _countBuffer,
3776         VkDeviceSize                                countBufferOffset,
3777         uint32_t                                    maxDrawCount,
3778         uint32_t                                    stride)
3779 {
3780         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3781         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3782         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3783         struct radv_draw_info info = {};
3784
3785         info.indexed = true;
3786         info.count = maxDrawCount;
3787         info.indirect = buffer;
3788         info.indirect_offset = offset;
3789         info.count_buffer = count_buffer;
3790         info.count_buffer_offset = countBufferOffset;
3791         info.stride = stride;
3792
3793         radv_draw(cmd_buffer, &info);
3794 }
3795
3796 void radv_CmdDrawIndirectCountKHR(
3797         VkCommandBuffer                             commandBuffer,
3798         VkBuffer                                    _buffer,
3799         VkDeviceSize                                offset,
3800         VkBuffer                                    _countBuffer,
3801         VkDeviceSize                                countBufferOffset,
3802         uint32_t                                    maxDrawCount,
3803         uint32_t                                    stride)
3804 {
3805         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3806         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3807         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3808         struct radv_draw_info info = {};
3809
3810         info.count = maxDrawCount;
3811         info.indirect = buffer;
3812         info.indirect_offset = offset;
3813         info.count_buffer = count_buffer;
3814         info.count_buffer_offset = countBufferOffset;
3815         info.stride = stride;
3816
3817         radv_draw(cmd_buffer, &info);
3818 }
3819
3820 void radv_CmdDrawIndexedIndirectCountKHR(
3821         VkCommandBuffer                             commandBuffer,
3822         VkBuffer                                    _buffer,
3823         VkDeviceSize                                offset,
3824         VkBuffer                                    _countBuffer,
3825         VkDeviceSize                                countBufferOffset,
3826         uint32_t                                    maxDrawCount,
3827         uint32_t                                    stride)
3828 {
3829         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3830         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3831         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3832         struct radv_draw_info info = {};
3833
3834         info.indexed = true;
3835         info.count = maxDrawCount;
3836         info.indirect = buffer;
3837         info.indirect_offset = offset;
3838         info.count_buffer = count_buffer;
3839         info.count_buffer_offset = countBufferOffset;
3840         info.stride = stride;
3841
3842         radv_draw(cmd_buffer, &info);
3843 }
3844
3845 struct radv_dispatch_info {
3846         /**
3847          * Determine the layout of the grid (in block units) to be used.
3848          */
3849         uint32_t blocks[3];
3850
3851         /**
3852          * A starting offset for the grid. If unaligned is set, the offset
3853          * must still be aligned.
3854          */
3855         uint32_t offsets[3];
3856         /**
3857          * Whether it's an unaligned compute dispatch.
3858          */
3859         bool unaligned;
3860
3861         /**
3862          * Indirect compute parameters resource.
3863          */
3864         struct radv_buffer *indirect;
3865         uint64_t indirect_offset;
3866 };
3867
3868 static void
3869 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3870                            const struct radv_dispatch_info *info)
3871 {
3872         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3873         struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3874         unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3875         struct radeon_winsys *ws = cmd_buffer->device->ws;
3876         bool predicating = cmd_buffer->state.predicating;
3877         struct radeon_cmdbuf *cs = cmd_buffer->cs;
3878         struct radv_userdata_info *loc;
3879
3880         loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3881                                     AC_UD_CS_GRID_SIZE);
3882
3883         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3884
3885         if (info->indirect) {
3886                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3887
3888                 va += info->indirect->offset + info->indirect_offset;
3889
3890                 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3891
3892                 if (loc->sgpr_idx != -1) {
3893                         for (unsigned i = 0; i < 3; ++i) {
3894                                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3895                                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
3896                                                 COPY_DATA_DST_SEL(COPY_DATA_REG));
3897                                 radeon_emit(cs, (va +  4 * i));
3898                                 radeon_emit(cs, (va + 4 * i) >> 32);
3899                                 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3900                                                  + loc->sgpr_idx * 4) >> 2) + i);
3901                                 radeon_emit(cs, 0);
3902                         }
3903                 }
3904
3905                 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3906                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
3907                                         PKT3_SHADER_TYPE_S(1));
3908                         radeon_emit(cs, va);
3909                         radeon_emit(cs, va >> 32);
3910                         radeon_emit(cs, dispatch_initiator);
3911                 } else {
3912                         radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3913                                         PKT3_SHADER_TYPE_S(1));
3914                         radeon_emit(cs, 1);
3915                         radeon_emit(cs, va);
3916                         radeon_emit(cs, va >> 32);
3917
3918                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
3919                                         PKT3_SHADER_TYPE_S(1));
3920                         radeon_emit(cs, 0);
3921                         radeon_emit(cs, dispatch_initiator);
3922                 }
3923         } else {
3924                 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3925                 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3926
3927                 if (info->unaligned) {
3928                         unsigned *cs_block_size = compute_shader->info.cs.block_size;
3929                         unsigned remainder[3];
3930
3931                         /* If aligned, these should be an entire block size,
3932                          * not 0.
3933                          */
3934                         remainder[0] = blocks[0] + cs_block_size[0] -
3935                                        align_u32_npot(blocks[0], cs_block_size[0]);
3936                         remainder[1] = blocks[1] + cs_block_size[1] -
3937                                        align_u32_npot(blocks[1], cs_block_size[1]);
3938                         remainder[2] = blocks[2] + cs_block_size[2] -
3939                                        align_u32_npot(blocks[2], cs_block_size[2]);
3940
3941                         blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3942                         blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3943                         blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3944
3945                         for(unsigned i = 0; i < 3; ++i) {
3946                                 assert(offsets[i] % cs_block_size[i] == 0);
3947                                 offsets[i] /= cs_block_size[i];
3948                         }
3949
3950                         radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3951                         radeon_emit(cs,
3952                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3953                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3954                         radeon_emit(cs,
3955                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3956                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3957                         radeon_emit(cs,
3958                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3959                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3960
3961                         dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3962                 }
3963
3964                 if (loc->sgpr_idx != -1) {
3965                         assert(!loc->indirect);
3966                         assert(loc->num_sgprs == 3);
3967
3968                         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3969                                                   loc->sgpr_idx * 4, 3);
3970                         radeon_emit(cs, blocks[0]);
3971                         radeon_emit(cs, blocks[1]);
3972                         radeon_emit(cs, blocks[2]);
3973                 }
3974
3975                 if (offsets[0] || offsets[1] || offsets[2]) {
3976                         radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3977                         radeon_emit(cs, offsets[0]);
3978                         radeon_emit(cs, offsets[1]);
3979                         radeon_emit(cs, offsets[2]);
3980
3981                         /* The blocks in the packet are not counts but end values. */
3982                         for (unsigned i = 0; i < 3; ++i)
3983                                 blocks[i] += offsets[i];
3984                 } else {
3985                         dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3986                 }
3987
3988                 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
3989                                 PKT3_SHADER_TYPE_S(1));
3990                 radeon_emit(cs, blocks[0]);
3991                 radeon_emit(cs, blocks[1]);
3992                 radeon_emit(cs, blocks[2]);
3993                 radeon_emit(cs, dispatch_initiator);
3994         }
3995
3996         assert(cmd_buffer->cs->cdw <= cdw_max);
3997 }
3998
3999 static void
4000 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4001 {
4002         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4003         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4004 }
4005
4006 static void
4007 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4008               const struct radv_dispatch_info *info)
4009 {
4010         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4011         bool has_prefetch =
4012                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4013         bool pipeline_is_dirty = pipeline &&
4014                                  pipeline != cmd_buffer->state.emitted_compute_pipeline;
4015
4016         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4017                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4018                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4019                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4020                 /* If we have to wait for idle, set all states first, so that
4021                  * all SET packets are processed in parallel with previous draw
4022                  * calls. Then upload descriptors, set shader pointers, and
4023                  * dispatch, and prefetch at the end. This ensures that the
4024                  * time the CUs are idle is very short. (there are only SET_SH
4025                  * packets between the wait and the draw)
4026                  */
4027                 radv_emit_compute_pipeline(cmd_buffer);
4028                 si_emit_cache_flush(cmd_buffer);
4029                 /* <-- CUs are idle here --> */
4030
4031                 radv_upload_compute_shader_descriptors(cmd_buffer);
4032
4033                 radv_emit_dispatch_packets(cmd_buffer, info);
4034                 /* <-- CUs are busy here --> */
4035
4036                 /* Start prefetches after the dispatch has been started. Both
4037                  * will run in parallel, but starting the dispatch first is
4038                  * more important.
4039                  */
4040                 if (has_prefetch && pipeline_is_dirty) {
4041                         radv_emit_shader_prefetch(cmd_buffer,
4042                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
4043                 }
4044         } else {
4045                 /* If we don't wait for idle, start prefetches first, then set
4046                  * states, and dispatch at the end.
4047                  */
4048                 si_emit_cache_flush(cmd_buffer);
4049
4050                 if (has_prefetch && pipeline_is_dirty) {
4051                         radv_emit_shader_prefetch(cmd_buffer,
4052                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
4053                 }
4054
4055                 radv_upload_compute_shader_descriptors(cmd_buffer);
4056
4057                 radv_emit_compute_pipeline(cmd_buffer);
4058                 radv_emit_dispatch_packets(cmd_buffer, info);
4059         }
4060
4061         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4062 }
4063
4064 void radv_CmdDispatchBase(
4065         VkCommandBuffer                             commandBuffer,
4066         uint32_t                                    base_x,
4067         uint32_t                                    base_y,
4068         uint32_t                                    base_z,
4069         uint32_t                                    x,
4070         uint32_t                                    y,
4071         uint32_t                                    z)
4072 {
4073         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4074         struct radv_dispatch_info info = {};
4075
4076         info.blocks[0] = x;
4077         info.blocks[1] = y;
4078         info.blocks[2] = z;
4079
4080         info.offsets[0] = base_x;
4081         info.offsets[1] = base_y;
4082         info.offsets[2] = base_z;
4083         radv_dispatch(cmd_buffer, &info);
4084 }
4085
4086 void radv_CmdDispatch(
4087         VkCommandBuffer                             commandBuffer,
4088         uint32_t                                    x,
4089         uint32_t                                    y,
4090         uint32_t                                    z)
4091 {
4092         radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4093 }
4094
4095 void radv_CmdDispatchIndirect(
4096         VkCommandBuffer                             commandBuffer,
4097         VkBuffer                                    _buffer,
4098         VkDeviceSize                                offset)
4099 {
4100         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4101         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4102         struct radv_dispatch_info info = {};
4103
4104         info.indirect = buffer;
4105         info.indirect_offset = offset;
4106
4107         radv_dispatch(cmd_buffer, &info);
4108 }
4109
4110 void radv_unaligned_dispatch(
4111         struct radv_cmd_buffer                      *cmd_buffer,
4112         uint32_t                                    x,
4113         uint32_t                                    y,
4114         uint32_t                                    z)
4115 {
4116         struct radv_dispatch_info info = {};
4117
4118         info.blocks[0] = x;
4119         info.blocks[1] = y;
4120         info.blocks[2] = z;
4121         info.unaligned = 1;
4122
4123         radv_dispatch(cmd_buffer, &info);
4124 }
4125
4126 void radv_CmdEndRenderPass(
4127         VkCommandBuffer                             commandBuffer)
4128 {
4129         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4130
4131         radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4132
4133         radv_cmd_buffer_resolve_subpass(cmd_buffer);
4134
4135         for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
4136                 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
4137                 radv_handle_subpass_image_transition(cmd_buffer,
4138                                       (struct radv_subpass_attachment){i, layout});
4139         }
4140
4141         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4142
4143         cmd_buffer->state.pass = NULL;
4144         cmd_buffer->state.subpass = NULL;
4145         cmd_buffer->state.attachments = NULL;
4146         cmd_buffer->state.framebuffer = NULL;
4147 }
4148
4149 void radv_CmdEndRenderPass2KHR(
4150     VkCommandBuffer                             commandBuffer,
4151     const VkSubpassEndInfoKHR*                  pSubpassEndInfo)
4152 {
4153         radv_CmdEndRenderPass(commandBuffer);
4154 }
4155
4156 /*
4157  * For HTILE we have the following interesting clear words:
4158  *   0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4159  *   0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4160  *   0xfffffff0: Clear depth to 1.0
4161  *   0x00000000: Clear depth to 0.0
4162  */
4163 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4164                                   struct radv_image *image,
4165                                   const VkImageSubresourceRange *range,
4166                                   uint32_t clear_word)
4167 {
4168         assert(range->baseMipLevel == 0);
4169         assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4170         unsigned layer_count = radv_get_layerCount(image, range);
4171         uint64_t size = image->surface.htile_slice_size * layer_count;
4172         VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4173         uint64_t offset = image->offset + image->htile_offset +
4174                           image->surface.htile_slice_size * range->baseArrayLayer;
4175         struct radv_cmd_state *state = &cmd_buffer->state;
4176         VkClearDepthStencilValue value = {};
4177
4178         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4179                              RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4180
4181         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4182                                               size, clear_word);
4183
4184         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4185
4186         if (vk_format_is_stencil(image->vk_format))
4187                 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4188
4189         radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4190 }
4191
4192 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4193                                                struct radv_image *image,
4194                                                VkImageLayout src_layout,
4195                                                VkImageLayout dst_layout,
4196                                                unsigned src_queue_mask,
4197                                                unsigned dst_queue_mask,
4198                                                const VkImageSubresourceRange *range,
4199                                                VkImageAspectFlags pending_clears)
4200 {
4201         if (!radv_image_has_htile(image))
4202                 return;
4203
4204         if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4205                    radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4206                 /* TODO: merge with the clear if applicable */
4207                 radv_initialize_htile(cmd_buffer, image, range, 0);
4208         } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4209                    radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4210                 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4211                 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4212         } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4213                    !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4214                 VkImageSubresourceRange local_range = *range;
4215                 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4216                 local_range.baseMipLevel = 0;
4217                 local_range.levelCount = 1;
4218
4219                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4220                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4221
4222                 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4223
4224                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4225                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4226         }
4227 }
4228
4229 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4230                                   struct radv_image *image, uint32_t value)
4231 {
4232         struct radv_cmd_state *state = &cmd_buffer->state;
4233
4234         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4235                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4236
4237         state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4238
4239         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4240 }
4241
4242 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4243                          struct radv_image *image, uint32_t value)
4244 {
4245         struct radv_cmd_state *state = &cmd_buffer->state;
4246
4247         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4248                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4249
4250         state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4251
4252         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4253                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4254 }
4255
4256 /**
4257  * Initialize DCC/FMASK/CMASK metadata for a color image.
4258  */
4259 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4260                                            struct radv_image *image,
4261                                            VkImageLayout src_layout,
4262                                            VkImageLayout dst_layout,
4263                                            unsigned src_queue_mask,
4264                                            unsigned dst_queue_mask)
4265 {
4266         if (radv_image_has_cmask(image)) {
4267                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4268
4269                 /*  TODO: clarify this. */
4270                 if (radv_image_has_fmask(image)) {
4271                         value = 0xccccccccu;
4272                 }
4273
4274                 radv_initialise_cmask(cmd_buffer, image, value);
4275         }
4276
4277         if (radv_image_has_dcc(image)) {
4278                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4279                 bool need_decompress_pass = false;
4280
4281                 if (radv_layout_dcc_compressed(image, dst_layout,
4282                                                dst_queue_mask)) {
4283                         value = 0x20202020u;
4284                         need_decompress_pass = true;
4285                 }
4286
4287                 radv_initialize_dcc(cmd_buffer, image, value);
4288
4289                 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, image,
4290                                                   need_decompress_pass);
4291         }
4292
4293         if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4294                 uint32_t color_values[2] = {};
4295                 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4296         }
4297 }
4298
4299 /**
4300  * Handle color image transitions for DCC/FMASK/CMASK.
4301  */
4302 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4303                                                struct radv_image *image,
4304                                                VkImageLayout src_layout,
4305                                                VkImageLayout dst_layout,
4306                                                unsigned src_queue_mask,
4307                                                unsigned dst_queue_mask,
4308                                                const VkImageSubresourceRange *range)
4309 {
4310         if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4311                 radv_init_color_image_metadata(cmd_buffer, image,
4312                                                src_layout, dst_layout,
4313                                                src_queue_mask, dst_queue_mask);
4314                 return;
4315         }
4316
4317         if (radv_image_has_dcc(image)) {
4318                 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4319                         radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4320                 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4321                            !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4322                         radv_decompress_dcc(cmd_buffer, image, range);
4323                 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4324                            !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4325                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4326                 }
4327         } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4328                 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4329                     !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4330                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4331                 }
4332         }
4333 }
4334
4335 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4336                                          struct radv_image *image,
4337                                          VkImageLayout src_layout,
4338                                          VkImageLayout dst_layout,
4339                                          uint32_t src_family,
4340                                          uint32_t dst_family,
4341                                          const VkImageSubresourceRange *range,
4342                                          VkImageAspectFlags pending_clears)
4343 {
4344         if (image->exclusive && src_family != dst_family) {
4345                 /* This is an acquire or a release operation and there will be
4346                  * a corresponding release/acquire. Do the transition in the
4347                  * most flexible queue. */
4348
4349                 assert(src_family == cmd_buffer->queue_family_index ||
4350                        dst_family == cmd_buffer->queue_family_index);
4351
4352                 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4353                         return;
4354
4355                 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4356                     (src_family == RADV_QUEUE_GENERAL ||
4357                      dst_family == RADV_QUEUE_GENERAL))
4358                         return;
4359         }
4360
4361         unsigned src_queue_mask =
4362                 radv_image_queue_family_mask(image, src_family,
4363                                              cmd_buffer->queue_family_index);
4364         unsigned dst_queue_mask =
4365                 radv_image_queue_family_mask(image, dst_family,
4366                                              cmd_buffer->queue_family_index);
4367
4368         if (vk_format_is_depth(image->vk_format)) {
4369                 radv_handle_depth_image_transition(cmd_buffer, image,
4370                                                    src_layout, dst_layout,
4371                                                    src_queue_mask, dst_queue_mask,
4372                                                    range, pending_clears);
4373         } else {
4374                 radv_handle_color_image_transition(cmd_buffer, image,
4375                                                    src_layout, dst_layout,
4376                                                    src_queue_mask, dst_queue_mask,
4377                                                    range);
4378         }
4379 }
4380
4381 struct radv_barrier_info {
4382         uint32_t eventCount;
4383         const VkEvent *pEvents;
4384         VkPipelineStageFlags srcStageMask;
4385 };
4386
4387 static void
4388 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4389              uint32_t memoryBarrierCount,
4390              const VkMemoryBarrier *pMemoryBarriers,
4391              uint32_t bufferMemoryBarrierCount,
4392              const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4393              uint32_t imageMemoryBarrierCount,
4394              const VkImageMemoryBarrier *pImageMemoryBarriers,
4395              const struct radv_barrier_info *info)
4396 {
4397         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4398         enum radv_cmd_flush_bits src_flush_bits = 0;
4399         enum radv_cmd_flush_bits dst_flush_bits = 0;
4400
4401         for (unsigned i = 0; i < info->eventCount; ++i) {
4402                 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4403                 uint64_t va = radv_buffer_get_va(event->bo);
4404
4405                 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4406
4407                 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4408
4409                 si_emit_wait_fence(cs, va, 1, 0xffffffff);
4410                 assert(cmd_buffer->cs->cdw <= cdw_max);
4411         }
4412
4413         for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4414                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4415                                                         NULL);
4416                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4417                                                         NULL);
4418         }
4419
4420         for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4421                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4422                                                         NULL);
4423                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4424                                                         NULL);
4425         }
4426
4427         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4428                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4429
4430                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4431                                                         image);
4432                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4433                                                         image);
4434         }
4435
4436         radv_stage_flush(cmd_buffer, info->srcStageMask);
4437         cmd_buffer->state.flush_bits |= src_flush_bits;
4438
4439         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4440                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4441                 radv_handle_image_transition(cmd_buffer, image,
4442                                              pImageMemoryBarriers[i].oldLayout,
4443                                              pImageMemoryBarriers[i].newLayout,
4444                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
4445                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
4446                                              &pImageMemoryBarriers[i].subresourceRange,
4447                                              0);
4448         }
4449
4450         /* Make sure CP DMA is idle because the driver might have performed a
4451          * DMA operation for copying or filling buffers/images.
4452          */
4453         si_cp_dma_wait_for_idle(cmd_buffer);
4454
4455         cmd_buffer->state.flush_bits |= dst_flush_bits;
4456 }
4457
4458 void radv_CmdPipelineBarrier(
4459         VkCommandBuffer                             commandBuffer,
4460         VkPipelineStageFlags                        srcStageMask,
4461         VkPipelineStageFlags                        destStageMask,
4462         VkBool32                                    byRegion,
4463         uint32_t                                    memoryBarrierCount,
4464         const VkMemoryBarrier*                      pMemoryBarriers,
4465         uint32_t                                    bufferMemoryBarrierCount,
4466         const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
4467         uint32_t                                    imageMemoryBarrierCount,
4468         const VkImageMemoryBarrier*                 pImageMemoryBarriers)
4469 {
4470         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4471         struct radv_barrier_info info;
4472
4473         info.eventCount = 0;
4474         info.pEvents = NULL;
4475         info.srcStageMask = srcStageMask;
4476
4477         radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4478                      bufferMemoryBarrierCount, pBufferMemoryBarriers,
4479                      imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4480 }
4481
4482
4483 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4484                         struct radv_event *event,
4485                         VkPipelineStageFlags stageMask,
4486                         unsigned value)
4487 {
4488         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4489         uint64_t va = radv_buffer_get_va(event->bo);
4490
4491         si_emit_cache_flush(cmd_buffer);
4492
4493         radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4494
4495         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4496
4497         /* Flags that only require a top-of-pipe event. */
4498         VkPipelineStageFlags top_of_pipe_flags =
4499                 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4500
4501         /* Flags that only require a post-index-fetch event. */
4502         VkPipelineStageFlags post_index_fetch_flags =
4503                 top_of_pipe_flags |
4504                 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4505                 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4506
4507         /* Make sure CP DMA is idle because the driver might have performed a
4508          * DMA operation for copying or filling buffers/images.
4509          */
4510         si_cp_dma_wait_for_idle(cmd_buffer);
4511
4512         /* TODO: Emit EOS events for syncing PS/CS stages. */
4513
4514         if (!(stageMask & ~top_of_pipe_flags)) {
4515                 /* Just need to sync the PFP engine. */
4516                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4517                 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4518                                 S_370_WR_CONFIRM(1) |
4519                                 S_370_ENGINE_SEL(V_370_PFP));
4520                 radeon_emit(cs, va);
4521                 radeon_emit(cs, va >> 32);
4522                 radeon_emit(cs, value);
4523         } else if (!(stageMask & ~post_index_fetch_flags)) {
4524                 /* Sync ME because PFP reads index and indirect buffers. */
4525                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4526                 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4527                                 S_370_WR_CONFIRM(1) |
4528                                 S_370_ENGINE_SEL(V_370_ME));
4529                 radeon_emit(cs, va);
4530                 radeon_emit(cs, va >> 32);
4531                 radeon_emit(cs, value);
4532         } else {
4533                 /* Otherwise, sync all prior GPU work using an EOP event. */
4534                 si_cs_emit_write_event_eop(cs,
4535                                            cmd_buffer->device->physical_device->rad_info.chip_class,
4536                                            radv_cmd_buffer_uses_mec(cmd_buffer),
4537                                            V_028A90_BOTTOM_OF_PIPE_TS, 0,
4538                                            EOP_DATA_SEL_VALUE_32BIT, va, 2, value,
4539                                            cmd_buffer->gfx9_eop_bug_va);
4540         }
4541
4542         assert(cmd_buffer->cs->cdw <= cdw_max);
4543 }
4544
4545 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4546                       VkEvent _event,
4547                       VkPipelineStageFlags stageMask)
4548 {
4549         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4550         RADV_FROM_HANDLE(radv_event, event, _event);
4551
4552         write_event(cmd_buffer, event, stageMask, 1);
4553 }
4554
4555 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4556                         VkEvent _event,
4557                         VkPipelineStageFlags stageMask)
4558 {
4559         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4560         RADV_FROM_HANDLE(radv_event, event, _event);
4561
4562         write_event(cmd_buffer, event, stageMask, 0);
4563 }
4564
4565 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4566                         uint32_t eventCount,
4567                         const VkEvent* pEvents,
4568                         VkPipelineStageFlags srcStageMask,
4569                         VkPipelineStageFlags dstStageMask,
4570                         uint32_t memoryBarrierCount,
4571                         const VkMemoryBarrier* pMemoryBarriers,
4572                         uint32_t bufferMemoryBarrierCount,
4573                         const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4574                         uint32_t imageMemoryBarrierCount,
4575                         const VkImageMemoryBarrier* pImageMemoryBarriers)
4576 {
4577         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4578         struct radv_barrier_info info;
4579
4580         info.eventCount = eventCount;
4581         info.pEvents = pEvents;
4582         info.srcStageMask = 0;
4583
4584         radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4585                      bufferMemoryBarrierCount, pBufferMemoryBarriers,
4586                      imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4587 }
4588
4589
4590 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4591                            uint32_t deviceMask)
4592 {
4593    /* No-op */
4594 }
4595
4596 /* VK_EXT_conditional_rendering */
4597 void radv_CmdBeginConditionalRenderingEXT(
4598         VkCommandBuffer                             commandBuffer,
4599         const VkConditionalRenderingBeginInfoEXT*   pConditionalRenderingBegin)
4600 {
4601         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4602         RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4603         bool draw_visible = true;
4604         uint64_t va;
4605
4606         va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4607
4608         /* By default, if the 32-bit value at offset in buffer memory is zero,
4609          * then the rendering commands are discarded, otherwise they are
4610          * executed as normal. If the inverted flag is set, all commands are
4611          * discarded if the value is non zero.
4612          */
4613         if (pConditionalRenderingBegin->flags &
4614             VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4615                 draw_visible = false;
4616         }
4617
4618         /* Enable predication for this command buffer. */
4619         si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4620         cmd_buffer->state.predicating = true;
4621
4622         /* Store conditional rendering user info. */
4623         cmd_buffer->state.predication_type = draw_visible;
4624         cmd_buffer->state.predication_va = va;
4625 }
4626
4627 void radv_CmdEndConditionalRenderingEXT(
4628         VkCommandBuffer                             commandBuffer)
4629 {
4630         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4631
4632         /* Disable predication for this command buffer. */
4633         si_emit_set_predication_state(cmd_buffer, false, 0);
4634         cmd_buffer->state.predicating = false;
4635
4636         /* Reset conditional rendering user info. */
4637         cmd_buffer->state.predication_type = -1;
4638         cmd_buffer->state.predication_va = 0;
4639 }
4640
4641 /* VK_EXT_transform_feedback */
4642 void radv_CmdBindTransformFeedbackBuffersEXT(
4643     VkCommandBuffer                             commandBuffer,
4644     uint32_t                                    firstBinding,
4645     uint32_t                                    bindingCount,
4646     const VkBuffer*                             pBuffers,
4647     const VkDeviceSize*                         pOffsets,
4648     const VkDeviceSize*                         pSizes)
4649 {
4650         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4651         struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4652         uint8_t enabled_mask = 0;
4653
4654         assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4655         for (uint32_t i = 0; i < bindingCount; i++) {
4656                 uint32_t idx = firstBinding + i;
4657
4658                 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4659                 sb[idx].offset = pOffsets[i];
4660                 sb[idx].size = pSizes[i];
4661
4662                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4663                                    sb[idx].buffer->bo);
4664
4665                 enabled_mask |= 1 << idx;
4666         }
4667
4668         cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4669
4670         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4671 }
4672
4673 static void
4674 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4675 {
4676         struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4677         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4678
4679         radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
4680         radeon_emit(cs,
4681                     S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
4682                     S_028B94_RAST_STREAM(0) |
4683                     S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
4684                     S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
4685                     S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
4686         radeon_emit(cs, so->hw_enabled_mask &
4687                         so->enabled_stream_buffers_mask);
4688 }
4689
4690 static void
4691 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
4692 {
4693         struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4694         bool old_streamout_enabled = so->streamout_enabled;
4695         uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
4696
4697         so->streamout_enabled = enable;
4698
4699         so->hw_enabled_mask = so->enabled_mask |
4700                               (so->enabled_mask << 4) |
4701                               (so->enabled_mask << 8) |
4702                               (so->enabled_mask << 12);
4703
4704         if ((old_streamout_enabled != so->streamout_enabled) ||
4705             (old_hw_enabled_mask != so->hw_enabled_mask))
4706                 radv_emit_streamout_enable(cmd_buffer);
4707 }
4708
4709 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
4710 {
4711         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4712         unsigned reg_strmout_cntl;
4713
4714         /* The register is at different places on different ASICs. */
4715         if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
4716                 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
4717                 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
4718         } else {
4719                 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
4720                 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
4721         }
4722
4723         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4724         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
4725
4726         radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
4727         radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
4728         radeon_emit(cs, reg_strmout_cntl >> 2);  /* register */
4729         radeon_emit(cs, 0);
4730         radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4731         radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4732         radeon_emit(cs, 4); /* poll interval */
4733 }
4734
4735 void radv_CmdBeginTransformFeedbackEXT(
4736     VkCommandBuffer                             commandBuffer,
4737     uint32_t                                    firstCounterBuffer,
4738     uint32_t                                    counterBufferCount,
4739     const VkBuffer*                             pCounterBuffers,
4740     const VkDeviceSize*                         pCounterBufferOffsets)
4741 {
4742         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4743         struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4744         struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4745         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4746
4747         radv_flush_vgt_streamout(cmd_buffer);
4748
4749         assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4750         for (uint32_t i = firstCounterBuffer; i < counterBufferCount; i++) {
4751                 if (!(so->enabled_mask & (1 << i)))
4752                         continue;
4753
4754                 /* SI binds streamout buffers as shader resources.
4755                  * VGT only counts primitives and tells the shader through
4756                  * SGPRs what to do.
4757                  */
4758                 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
4759                 radeon_emit(cs, sb[i].size >> 2);       /* BUFFER_SIZE (in DW) */
4760                 radeon_emit(cs, so->stride_in_dw[i]);                   /* VTX_STRIDE (in DW) */
4761
4762                 if (pCounterBuffers && pCounterBuffers[i]) {
4763                         /* The array of counter buffers is optional. */
4764                         RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[i]);
4765                         uint64_t va = radv_buffer_get_va(buffer->bo);
4766
4767                         va += buffer->offset + pCounterBufferOffsets[i];
4768
4769                         /* Append */
4770                         radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4771                         radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4772                                         STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4773                                         STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
4774                         radeon_emit(cs, 0); /* unused */
4775                         radeon_emit(cs, 0); /* unused */
4776                         radeon_emit(cs, va); /* src address lo */
4777                         radeon_emit(cs, va >> 32); /* src address hi */
4778
4779                         radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4780                 } else {
4781                         /* Start from the beginning. */
4782                         radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4783                         radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4784                                         STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4785                                         STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
4786                         radeon_emit(cs, 0); /* unused */
4787                         radeon_emit(cs, 0); /* unused */
4788                         radeon_emit(cs, 0); /* unused */
4789                         radeon_emit(cs, 0); /* unused */
4790                 }
4791         }
4792
4793         radv_set_streamout_enable(cmd_buffer, true);
4794 }
4795
4796 void radv_CmdEndTransformFeedbackEXT(
4797     VkCommandBuffer                             commandBuffer,
4798     uint32_t                                    firstCounterBuffer,
4799     uint32_t                                    counterBufferCount,
4800     const VkBuffer*                             pCounterBuffers,
4801     const VkDeviceSize*                         pCounterBufferOffsets)
4802 {
4803         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4804         struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4805         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4806
4807         radv_flush_vgt_streamout(cmd_buffer);
4808
4809         assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
4810         for (uint32_t i = firstCounterBuffer; i < counterBufferCount; i++) {
4811                 if (!(so->enabled_mask & (1 << i)))
4812                         continue;
4813
4814                 if (pCounterBuffers && pCounterBuffers[i]) {
4815                         /* The array of counters buffer is optional. */
4816                         RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[i]);
4817                         uint64_t va = radv_buffer_get_va(buffer->bo);
4818
4819                         va += buffer->offset + pCounterBufferOffsets[i];
4820
4821                         radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
4822                         radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
4823                                         STRMOUT_DATA_TYPE(1) | /* offset in bytes */
4824                                         STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
4825                                         STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
4826                         radeon_emit(cs, va);            /* dst address lo */
4827                         radeon_emit(cs, va >> 32);      /* dst address hi */
4828                         radeon_emit(cs, 0);             /* unused */
4829                         radeon_emit(cs, 0);             /* unused */
4830
4831                         radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
4832                 }
4833
4834                 /* Deactivate transform feedback by zeroing the buffer size.
4835                  * The counters (primitives generated, primitives emitted) may
4836                  * be enabled even if there is not buffer bound. This ensures
4837                  * that the primitives-emitted query won't increment.
4838                  */
4839                 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
4840         }
4841
4842         radv_set_streamout_enable(cmd_buffer, false);
4843 }
4844
4845 void radv_CmdDrawIndirectByteCountEXT(
4846     VkCommandBuffer                             commandBuffer,
4847     uint32_t                                    instanceCount,
4848     uint32_t                                    firstInstance,
4849     VkBuffer                                    _counterBuffer,
4850     VkDeviceSize                                counterBufferOffset,
4851     uint32_t                                    counterOffset,
4852     uint32_t                                    vertexStride)
4853 {
4854         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4855         RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
4856         struct radv_draw_info info = {};
4857
4858         info.instance_count = instanceCount;
4859         info.first_instance = firstInstance;
4860         info.strmout_buffer = counterBuffer;
4861         info.strmout_buffer_offset = counterBufferOffset;
4862         info.stride = vertexStride;
4863
4864         radv_draw(cmd_buffer, &info);
4865 }