src/amd/vulkan/radv_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "radv_private.h"
  29 #include "radv_radeon_winsys.h"
  30 #include "radv_shader.h"
  31 #include "radv_cs.h"
  32 #include "sid.h"
  33 #include "gfx9d.h"
  34 #include "vk_format.h"
  35 #include "radv_debug.h"
  36 #include "radv_meta.h"
  37
  38 #include "ac_debug.h"
  39
  40 enum {
  41         RADV_PREFETCH_VBO_DESCRIPTORS   = (1 << 0),
  42         RADV_PREFETCH_VS                = (1 << 1),
  43         RADV_PREFETCH_TCS               = (1 << 2),
  44         RADV_PREFETCH_TES               = (1 << 3),
  45         RADV_PREFETCH_GS                = (1 << 4),
  46         RADV_PREFETCH_PS                = (1 << 5),
  47         RADV_PREFETCH_SHADERS           = (RADV_PREFETCH_VS  |
  48                                            RADV_PREFETCH_TCS |
  49                                            RADV_PREFETCH_TES |
  50                                            RADV_PREFETCH_GS  |
  51                                            RADV_PREFETCH_PS)
  52 };
  53
  54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
  55                                          struct radv_image *image,
  56                                          VkImageLayout src_layout,
  57                                          VkImageLayout dst_layout,
  58                                          uint32_t src_family,
  59                                          uint32_t dst_family,
  60                                          const VkImageSubresourceRange *range);
  61
  62 const struct radv_dynamic_state default_dynamic_state = {
  63         .viewport = {
  64                 .count = 0,
  65         },
  66         .scissor = {
  67                 .count = 0,
  68         },
  69         .line_width = 1.0f,
  70         .depth_bias = {
  71                 .bias = 0.0f,
  72                 .clamp = 0.0f,
  73                 .slope = 0.0f,
  74         },
  75         .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
  76         .depth_bounds = {
  77                 .min = 0.0f,
  78                 .max = 1.0f,
  79         },
  80         .stencil_compare_mask = {
  81                 .front = ~0u,
  82                 .back = ~0u,
  83         },
  84         .stencil_write_mask = {
  85                 .front = ~0u,
  86                 .back = ~0u,
  87         },
  88         .stencil_reference = {
  89                 .front = 0u,
  90                 .back = 0u,
  91         },
  92 };
  93
  94 static void
  95 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
  96                         const struct radv_dynamic_state *src)
  97 {
  98         struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
  99         uint32_t copy_mask = src->mask;
 100         uint32_t dest_mask = 0;
 101
 102         /* Make sure to copy the number of viewports/scissors because they can
 103          * only be specified at pipeline creation time.
 104          */
 105         dest->viewport.count = src->viewport.count;
 106         dest->scissor.count = src->scissor.count;
 107         dest->discard_rectangle.count = src->discard_rectangle.count;
 108
 109         if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
 110                 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
 111                            src->viewport.count * sizeof(VkViewport))) {
 112                         typed_memcpy(dest->viewport.viewports,
 113                                      src->viewport.viewports,
 114                                      src->viewport.count);
 115                         dest_mask |= RADV_DYNAMIC_VIEWPORT;
 116                 }
 117         }
 118
 119         if (copy_mask & RADV_DYNAMIC_SCISSOR) {
 120                 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
 121                            src->scissor.count * sizeof(VkRect2D))) {
 122                         typed_memcpy(dest->scissor.scissors,
 123                                      src->scissor.scissors, src->scissor.count);
 124                         dest_mask |= RADV_DYNAMIC_SCISSOR;
 125                 }
 126         }
 127
 128         if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
 129                 if (dest->line_width != src->line_width) {
 130                         dest->line_width = src->line_width;
 131                         dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
 132                 }
 133         }
 134
 135         if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
 136                 if (memcmp(&dest->depth_bias, &src->depth_bias,
 137                            sizeof(src->depth_bias))) {
 138                         dest->depth_bias = src->depth_bias;
 139                         dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
 140                 }
 141         }
 142
 143         if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
 144                 if (memcmp(&dest->blend_constants, &src->blend_constants,
 145                            sizeof(src->blend_constants))) {
 146                         typed_memcpy(dest->blend_constants,
 147                                      src->blend_constants, 4);
 148                         dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
 149                 }
 150         }
 151
 152         if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
 153                 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
 154                            sizeof(src->depth_bounds))) {
 155                         dest->depth_bounds = src->depth_bounds;
 156                         dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
 157                 }
 158         }
 159
 160         if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
 161                 if (memcmp(&dest->stencil_compare_mask,
 162                            &src->stencil_compare_mask,
 163                            sizeof(src->stencil_compare_mask))) {
 164                         dest->stencil_compare_mask = src->stencil_compare_mask;
 165                         dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
 166                 }
 167         }
 168
 169         if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
 170                 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
 171                            sizeof(src->stencil_write_mask))) {
 172                         dest->stencil_write_mask = src->stencil_write_mask;
 173                         dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
 174                 }
 175         }
 176
 177         if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
 178                 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
 179                            sizeof(src->stencil_reference))) {
 180                         dest->stencil_reference = src->stencil_reference;
 181                         dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
 182                 }
 183         }
 184
 185         if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
 186                 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
 187                            src->discard_rectangle.count * sizeof(VkRect2D))) {
 188                         typed_memcpy(dest->discard_rectangle.rectangles,
 189                                      src->discard_rectangle.rectangles,
 190                                      src->discard_rectangle.count);
 191                         dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
 192                 }
 193         }
 194
 195         cmd_buffer->state.dirty |= dest_mask;
 196 }
 197
 198 static void
 199 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
 200                           struct radv_pipeline *pipeline)
 201 {
 202         struct radv_streamout_state *so = &cmd_buffer->state.streamout;
 203         struct radv_shader_info *info;
 204
 205         if (!pipeline->streamout_shader)
 206                 return;
 207
 208         info = &pipeline->streamout_shader->info.info;
 209         for (int i = 0; i < MAX_SO_BUFFERS; i++)
 210                 so->stride_in_dw[i] = info->so.strides[i];
 211
 212         so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
 213 }
 214
 215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
 216 {
 217         return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
 218                cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
 219 }
 220
 221 enum ring_type radv_queue_family_to_ring(int f) {
 222         switch (f) {
 223         case RADV_QUEUE_GENERAL:
 224                 return RING_GFX;
 225         case RADV_QUEUE_COMPUTE:
 226                 return RING_COMPUTE;
 227         case RADV_QUEUE_TRANSFER:
 228                 return RING_DMA;
 229         default:
 230                 unreachable("Unknown queue family");
 231         }
 232 }
 233
 234 static VkResult radv_create_cmd_buffer(
 235         struct radv_device *                         device,
 236         struct radv_cmd_pool *                       pool,
 237         VkCommandBufferLevel                        level,
 238         VkCommandBuffer*                            pCommandBuffer)
 239 {
 240         struct radv_cmd_buffer *cmd_buffer;
 241         unsigned ring;
 242         cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
 243                                VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 244         if (cmd_buffer == NULL)
 245                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 246
 247         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
 248         cmd_buffer->device = device;
 249         cmd_buffer->pool = pool;
 250         cmd_buffer->level = level;
 251
 252         if (pool) {
 253                 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
 254                 cmd_buffer->queue_family_index = pool->queue_family_index;
 255
 256         } else {
 257                 /* Init the pool_link so we can safely call list_del when we destroy
 258                  * the command buffer
 259                  */
 260                 list_inithead(&cmd_buffer->pool_link);
 261                 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
 262         }
 263
 264         ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
 265
 266         cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
 267         if (!cmd_buffer->cs) {
 268                 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 269                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 270         }
 271
 272         *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
 273
 274         list_inithead(&cmd_buffer->upload.list);
 275
 276         return VK_SUCCESS;
 277 }
 278
 279 static void
 280 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
 281 {
 282         list_del(&cmd_buffer->pool_link);
 283
 284         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 285                                  &cmd_buffer->upload.list, list) {
 286                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 287                 list_del(&up->list);
 288                 free(up);
 289         }
 290
 291         if (cmd_buffer->upload.upload_bo)
 292                 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
 293         cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
 294
 295         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
 296                 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
 297
 298         vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 299 }
 300
 301 static VkResult
 302 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 303 {
 304
 305         cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
 306
 307         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 308                                  &cmd_buffer->upload.list, list) {
 309                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 310                 list_del(&up->list);
 311                 free(up);
 312         }
 313
 314         cmd_buffer->push_constant_stages = 0;
 315         cmd_buffer->scratch_size_needed = 0;
 316         cmd_buffer->compute_scratch_size_needed = 0;
 317         cmd_buffer->esgs_ring_size_needed = 0;
 318         cmd_buffer->gsvs_ring_size_needed = 0;
 319         cmd_buffer->tess_rings_needed = false;
 320         cmd_buffer->sample_positions_needed = false;
 321
 322         if (cmd_buffer->upload.upload_bo)
 323                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 324                                    cmd_buffer->upload.upload_bo);
 325         cmd_buffer->upload.offset = 0;
 326
 327         cmd_buffer->record_result = VK_SUCCESS;
 328
 329         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
 330                 cmd_buffer->descriptors[i].dirty = 0;
 331                 cmd_buffer->descriptors[i].valid = 0;
 332                 cmd_buffer->descriptors[i].push_dirty = false;
 333         }
 334
 335         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
 336             cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
 337                 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
 338                 unsigned fence_offset, eop_bug_offset;
 339                 void *fence_ptr;
 340
 341                 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0, &fence_offset,
 342                                              &fence_ptr);
 343                 cmd_buffer->gfx9_fence_va =
 344                         radv_buffer_get_va(cmd_buffer->upload.upload_bo);
 345                 cmd_buffer->gfx9_fence_va += fence_offset;
 346
 347                 /* Allocate a buffer for the EOP bug on GFX9. */
 348                 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
 349                                              &eop_bug_offset, &fence_ptr);
 350                 cmd_buffer->gfx9_eop_bug_va =
 351                         radv_buffer_get_va(cmd_buffer->upload.upload_bo);
 352                 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
 353         }
 354
 355         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
 356
 357         return cmd_buffer->record_result;
 358 }
 359
 360 static bool
 361 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
 362                                   uint64_t min_needed)
 363 {
 364         uint64_t new_size;
 365         struct radeon_winsys_bo *bo;
 366         struct radv_cmd_buffer_upload *upload;
 367         struct radv_device *device = cmd_buffer->device;
 368
 369         new_size = MAX2(min_needed, 16 * 1024);
 370         new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
 371
 372         bo = device->ws->buffer_create(device->ws,
 373                                        new_size, 4096,
 374                                        RADEON_DOMAIN_GTT,
 375                                        RADEON_FLAG_CPU_ACCESS|
 376                                        RADEON_FLAG_NO_INTERPROCESS_SHARING |
 377                                        RADEON_FLAG_32BIT,
 378                                        RADV_BO_PRIORITY_UPLOAD_BUFFER);
 379
 380         if (!bo) {
 381                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 382                 return false;
 383         }
 384
 385         radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
 386         if (cmd_buffer->upload.upload_bo) {
 387                 upload = malloc(sizeof(*upload));
 388
 389                 if (!upload) {
 390                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
 391                         device->ws->buffer_destroy(bo);
 392                         return false;
 393                 }
 394
 395                 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
 396                 list_add(&upload->list, &cmd_buffer->upload.list);
 397         }
 398
 399         cmd_buffer->upload.upload_bo = bo;
 400         cmd_buffer->upload.size = new_size;
 401         cmd_buffer->upload.offset = 0;
 402         cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
 403
 404         if (!cmd_buffer->upload.map) {
 405                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 406                 return false;
 407         }
 408
 409         return true;
 410 }
 411
 412 bool
 413 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
 414                              unsigned size,
 415                              unsigned alignment,
 416                              unsigned *out_offset,
 417                              void **ptr)
 418 {
 419         uint64_t offset = align(cmd_buffer->upload.offset, alignment);
 420         if (offset + size > cmd_buffer->upload.size) {
 421                 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
 422                         return false;
 423                 offset = 0;
 424         }
 425
 426         *out_offset = offset;
 427         *ptr = cmd_buffer->upload.map + offset;
 428
 429         cmd_buffer->upload.offset = offset + size;
 430         return true;
 431 }
 432
 433 bool
 434 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
 435                             unsigned size, unsigned alignment,
 436                             const void *data, unsigned *out_offset)
 437 {
 438         uint8_t *ptr;
 439
 440         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
 441                                           out_offset, (void **)&ptr))
 442                 return false;
 443
 444         if (ptr)
 445                 memcpy(ptr, data, size);
 446
 447         return true;
 448 }
 449
 450 static void
 451 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
 452                             unsigned count, const uint32_t *data)
 453 {
 454         struct radeon_cmdbuf *cs = cmd_buffer->cs;
 455
 456         radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
 457
 458         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
 459         radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
 460                     S_370_WR_CONFIRM(1) |
 461                     S_370_ENGINE_SEL(V_370_ME));
 462         radeon_emit(cs, va);
 463         radeon_emit(cs, va >> 32);
 464         radeon_emit_array(cs, data, count);
 465 }
 466
 467 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
 468 {
 469         struct radv_device *device = cmd_buffer->device;
 470         struct radeon_cmdbuf *cs = cmd_buffer->cs;
 471         uint64_t va;
 472
 473         va = radv_buffer_get_va(device->trace_bo);
 474         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
 475                 va += 4;
 476
 477         ++cmd_buffer->state.trace_id;
 478         radv_emit_write_data_packet(cmd_buffer, va, 1,
 479                                     &cmd_buffer->state.trace_id);
 480
 481         radeon_check_space(cmd_buffer->device->ws, cs, 2);
 482
 483         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
 484         radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
 485 }
 486
 487 static void
 488 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
 489                            enum radv_cmd_flush_bits flags)
 490 {
 491         if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
 492                 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
 493                                 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
 494
 495                 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
 496
 497                 /* Force wait for graphics or compute engines to be idle. */
 498                 si_cs_emit_cache_flush(cmd_buffer->cs,
 499                                        cmd_buffer->device->physical_device->rad_info.chip_class,
 500                                        &cmd_buffer->gfx9_fence_idx,
 501                                        cmd_buffer->gfx9_fence_va,
 502                                        radv_cmd_buffer_uses_mec(cmd_buffer),
 503                                        flags, cmd_buffer->gfx9_eop_bug_va);
 504         }
 505
 506         if (unlikely(cmd_buffer->device->trace_bo))
 507                 radv_cmd_buffer_trace_emit(cmd_buffer);
 508 }
 509
 510 static void
 511 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
 512                    struct radv_pipeline *pipeline, enum ring_type ring)
 513 {
 514         struct radv_device *device = cmd_buffer->device;
 515         uint32_t data[2];
 516         uint64_t va;
 517
 518         va = radv_buffer_get_va(device->trace_bo);
 519
 520         switch (ring) {
 521         case RING_GFX:
 522                 va += 8;
 523                 break;
 524         case RING_COMPUTE:
 525                 va += 16;
 526                 break;
 527         default:
 528                 assert(!"invalid ring type");
 529         }
 530
 531         data[0] = (uintptr_t)pipeline;
 532         data[1] = (uintptr_t)pipeline >> 32;
 533
 534         radv_emit_write_data_packet(cmd_buffer, va, 2, data);
 535 }
 536
 537 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 538                              VkPipelineBindPoint bind_point,
 539                              struct radv_descriptor_set *set,
 540                              unsigned idx)
 541 {
 542         struct radv_descriptor_state *descriptors_state =
 543                 radv_get_descriptors_state(cmd_buffer, bind_point);
 544
 545         descriptors_state->sets[idx] = set;
 546
 547         descriptors_state->valid |= (1u << idx); /* active descriptors */
 548         descriptors_state->dirty |= (1u << idx);
 549 }
 550
 551 static void
 552 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
 553                       VkPipelineBindPoint bind_point)
 554 {
 555         struct radv_descriptor_state *descriptors_state =
 556                 radv_get_descriptors_state(cmd_buffer, bind_point);
 557         struct radv_device *device = cmd_buffer->device;
 558         uint32_t data[MAX_SETS * 2] = {};
 559         uint64_t va;
 560         unsigned i;
 561         va = radv_buffer_get_va(device->trace_bo) + 24;
 562
 563         for_each_bit(i, descriptors_state->valid) {
 564                 struct radv_descriptor_set *set = descriptors_state->sets[i];
 565                 data[i * 2] = (uintptr_t)set;
 566                 data[i * 2 + 1] = (uintptr_t)set >> 32;
 567         }
 568
 569         radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
 570 }
 571
 572 struct radv_userdata_info *
 573 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
 574                       gl_shader_stage stage,
 575                       int idx)
 576 {
 577         struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
 578         return &shader->info.user_sgprs_locs.shader_data[idx];
 579 }
 580
 581 static void
 582 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
 583                            struct radv_pipeline *pipeline,
 584                            gl_shader_stage stage,
 585                            int idx, uint64_t va)
 586 {
 587         struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
 588         uint32_t base_reg = pipeline->user_data_0[stage];
 589         if (loc->sgpr_idx == -1)
 590                 return;
 591
 592         assert(loc->num_sgprs == 1);
 593
 594         radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
 595                                  base_reg + loc->sgpr_idx * 4, va, false);
 596 }
 597
 598 static void
 599 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
 600                               struct radv_pipeline *pipeline,
 601                               struct radv_descriptor_state *descriptors_state,
 602                               gl_shader_stage stage)
 603 {
 604         struct radv_device *device = cmd_buffer->device;
 605         struct radeon_cmdbuf *cs = cmd_buffer->cs;
 606         uint32_t sh_base = pipeline->user_data_0[stage];
 607         struct radv_userdata_locations *locs =
 608                 &pipeline->shaders[stage]->info.user_sgprs_locs;
 609         unsigned mask = locs->descriptor_sets_enabled;
 610
 611         mask &= descriptors_state->dirty & descriptors_state->valid;
 612
 613         while (mask) {
 614                 int start, count;
 615
 616                 u_bit_scan_consecutive_range(&mask, &start, &count);
 617
 618                 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
 619                 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
 620
 621                 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
 622                 for (int i = 0; i < count; i++) {
 623                         struct radv_descriptor_set *set =
 624                                 descriptors_state->sets[start + i];
 625
 626                         radv_emit_shader_pointer_body(device, cs, set->va, true);
 627                 }
 628         }
 629 }
 630
 631 static void
 632 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer,
 633                              struct radv_pipeline *pipeline,
 634                              gl_shader_stage stage,
 635                              int idx, int count, uint32_t *values)
 636 {
 637         struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
 638         uint32_t base_reg = pipeline->user_data_0[stage];
 639         if (loc->sgpr_idx == -1)
 640                 return;
 641
 642         assert(loc->num_sgprs == count);
 643
 644         radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
 645         radeon_emit_array(cmd_buffer->cs, values, count);
 646 }
 647
 648 static void
 649 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
 650                               struct radv_pipeline *pipeline)
 651 {
 652         int num_samples = pipeline->graphics.ms.num_samples;
 653         struct radv_multisample_state *ms = &pipeline->graphics.ms;
 654         struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
 655
 656         if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
 657                 cmd_buffer->sample_positions_needed = true;
 658
 659         if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
 660                 return;
 661
 662         radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
 663         radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
 664         radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
 665
 666         radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
 667
 668         radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
 669
 670         /* GFX9: Flush DFSM when the AA mode changes. */
 671         if (cmd_buffer->device->dfsm_allowed) {
 672                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 673                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
 674         }
 675
 676         cmd_buffer->state.context_roll_without_scissor_emitted = true;
 677 }
 678
 679 static void
 680 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
 681                           struct radv_shader_variant *shader)
 682 {
 683         uint64_t va;
 684
 685         if (!shader)
 686                 return;
 687
 688         va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 689
 690         si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
 691 }
 692
 693 static void
 694 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
 695                       struct radv_pipeline *pipeline,
 696                       bool vertex_stage_only)
 697 {
 698         struct radv_cmd_state *state = &cmd_buffer->state;
 699         uint32_t mask = state->prefetch_L2_mask;
 700
 701         if (vertex_stage_only) {
 702                 /* Fast prefetch path for starting draws as soon as possible.
 703                  */
 704                 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
 705                                                   RADV_PREFETCH_VBO_DESCRIPTORS);
 706         }
 707
 708         if (mask & RADV_PREFETCH_VS)
 709                 radv_emit_shader_prefetch(cmd_buffer,
 710                                           pipeline->shaders[MESA_SHADER_VERTEX]);
 711
 712         if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
 713                 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
 714
 715         if (mask & RADV_PREFETCH_TCS)
 716                 radv_emit_shader_prefetch(cmd_buffer,
 717                                           pipeline->shaders[MESA_SHADER_TESS_CTRL]);
 718
 719         if (mask & RADV_PREFETCH_TES)
 720                 radv_emit_shader_prefetch(cmd_buffer,
 721                                           pipeline->shaders[MESA_SHADER_TESS_EVAL]);
 722
 723         if (mask & RADV_PREFETCH_GS) {
 724                 radv_emit_shader_prefetch(cmd_buffer,
 725                                           pipeline->shaders[MESA_SHADER_GEOMETRY]);
 726                 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
 727         }
 728
 729         if (mask & RADV_PREFETCH_PS)
 730                 radv_emit_shader_prefetch(cmd_buffer,
 731                                           pipeline->shaders[MESA_SHADER_FRAGMENT]);
 732
 733         state->prefetch_L2_mask &= ~mask;
 734 }
 735
 736 static void
 737 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
 738 {
 739         if (!cmd_buffer->device->physical_device->rbplus_allowed)
 740                 return;
 741
 742         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 743         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
 744         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 745
 746         unsigned sx_ps_downconvert = 0;
 747         unsigned sx_blend_opt_epsilon = 0;
 748         unsigned sx_blend_opt_control = 0;
 749
 750         for (unsigned i = 0; i < subpass->color_count; ++i) {
 751                 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
 752                         sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 753                         sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 754                         continue;
 755                 }
 756
 757                 int idx = subpass->color_attachments[i].attachment;
 758                 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
 759
 760                 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
 761                 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
 762                 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
 763                 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
 764
 765                 bool has_alpha, has_rgb;
 766
 767                 /* Set if RGB and A are present. */
 768                 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
 769
 770                 if (format == V_028C70_COLOR_8 ||
 771                     format == V_028C70_COLOR_16 ||
 772                     format == V_028C70_COLOR_32)
 773                         has_rgb = !has_alpha;
 774                 else
 775                         has_rgb = true;
 776
 777                 /* Check the colormask and export format. */
 778                 if (!(colormask & 0x7))
 779                         has_rgb = false;
 780                 if (!(colormask & 0x8))
 781                         has_alpha = false;
 782
 783                 if (spi_format == V_028714_SPI_SHADER_ZERO) {
 784                         has_rgb = false;
 785                         has_alpha = false;
 786                 }
 787
 788                 /* Disable value checking for disabled channels. */
 789                 if (!has_rgb)
 790                         sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 791                 if (!has_alpha)
 792                         sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 793
 794                 /* Enable down-conversion for 32bpp and smaller formats. */
 795                 switch (format) {
 796                 case V_028C70_COLOR_8:
 797                 case V_028C70_COLOR_8_8:
 798                 case V_028C70_COLOR_8_8_8_8:
 799                         /* For 1 and 2-channel formats, use the superset thereof. */
 800                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
 801                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 802                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 803                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
 804                                 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
 805                         }
 806                         break;
 807
 808                 case V_028C70_COLOR_5_6_5:
 809                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 810                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
 811                                 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
 812                         }
 813                         break;
 814
 815                 case V_028C70_COLOR_1_5_5_5:
 816                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 817                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
 818                                 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
 819                         }
 820                         break;
 821
 822                 case V_028C70_COLOR_4_4_4_4:
 823                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 824                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
 825                                 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
 826                         }
 827                         break;
 828
 829                 case V_028C70_COLOR_32:
 830                         if (swap == V_028C70_SWAP_STD &&
 831                             spi_format == V_028714_SPI_SHADER_32_R)
 832                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
 833                         else if (swap == V_028C70_SWAP_ALT_REV &&
 834                                  spi_format == V_028714_SPI_SHADER_32_AR)
 835                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
 836                         break;
 837
 838                 case V_028C70_COLOR_16:
 839                 case V_028C70_COLOR_16_16:
 840                         /* For 1-channel formats, use the superset thereof. */
 841                         if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
 842                             spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
 843                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 844                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 845                                 if (swap == V_028C70_SWAP_STD ||
 846                                     swap == V_028C70_SWAP_STD_REV)
 847                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
 848                                 else
 849                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
 850                         }
 851                         break;
 852
 853                 case V_028C70_COLOR_10_11_11:
 854                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 855                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
 856                                 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
 857                         }
 858                         break;
 859
 860                 case V_028C70_COLOR_2_10_10_10:
 861                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 862                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
 863                                 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
 864                         }
 865                         break;
 866                 }
 867         }
 868
 869         for (unsigned i = subpass->color_count; i < 8; ++i) {
 870                 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 871                 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 872         }
 873         /* TODO: avoid redundantly setting context registers */
 874         radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
 875         radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
 876         radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
 877         radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
 878
 879         cmd_buffer->state.context_roll_without_scissor_emitted = true;
 880 }
 881
 882 static void
 883 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
 884 {
 885         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 886
 887         if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
 888                 return;
 889
 890         radv_update_multisample_state(cmd_buffer, pipeline);
 891
 892         cmd_buffer->scratch_size_needed =
 893                                   MAX2(cmd_buffer->scratch_size_needed,
 894                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
 895
 896         if (!cmd_buffer->state.emitted_pipeline ||
 897             cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
 898              pipeline->graphics.can_use_guardband)
 899                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
 900
 901         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
 902
 903         if (!cmd_buffer->state.emitted_pipeline ||
 904             cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
 905             cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
 906             memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
 907                    pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
 908                 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
 909                 cmd_buffer->state.context_roll_without_scissor_emitted = true;
 910         }
 911
 912         for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
 913                 if (!pipeline->shaders[i])
 914                         continue;
 915
 916                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 917                                    pipeline->shaders[i]->bo);
 918         }
 919
 920         if (radv_pipeline_has_gs(pipeline))
 921                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 922                                    pipeline->gs_copy_shader->bo);
 923
 924         if (unlikely(cmd_buffer->device->trace_bo))
 925                 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
 926
 927         cmd_buffer->state.emitted_pipeline = pipeline;
 928
 929         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
 930 }
 931
 932 static void
 933 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
 934 {
 935         si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
 936                           cmd_buffer->state.dynamic.viewport.viewports);
 937 }
 938
 939 static void
 940 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
 941 {
 942         uint32_t count = cmd_buffer->state.dynamic.scissor.count;
 943
 944         si_write_scissors(cmd_buffer->cs, 0, count,
 945                           cmd_buffer->state.dynamic.scissor.scissors,
 946                           cmd_buffer->state.dynamic.viewport.viewports,
 947                           cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
 948
 949         cmd_buffer->state.context_roll_without_scissor_emitted = false;
 950 }
 951
 952 static void
 953 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
 954 {
 955         if (!cmd_buffer->state.dynamic.discard_rectangle.count)
 956                 return;
 957
 958         radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
 959                                    cmd_buffer->state.dynamic.discard_rectangle.count * 2);
 960         for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
 961                 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
 962                 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
 963                 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
 964                                             S_028214_BR_Y(rect.offset.y + rect.extent.height));
 965         }
 966 }
 967
 968 static void
 969 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
 970 {
 971         unsigned width = cmd_buffer->state.dynamic.line_width * 8;
 972
 973         radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
 974                                S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
 975 }
 976
 977 static void
 978 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
 979 {
 980         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 981
 982         radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
 983         radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
 984 }
 985
 986 static void
 987 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
 988 {
 989         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 990
 991         radeon_set_context_reg_seq(cmd_buffer->cs,
 992                                    R_028430_DB_STENCILREFMASK, 2);
 993         radeon_emit(cmd_buffer->cs,
 994                     S_028430_STENCILTESTVAL(d->stencil_reference.front) |
 995                     S_028430_STENCILMASK(d->stencil_compare_mask.front) |
 996                     S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
 997                     S_028430_STENCILOPVAL(1));
 998         radeon_emit(cmd_buffer->cs,
 999                     S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1000                     S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1001                     S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1002                     S_028434_STENCILOPVAL_BF(1));
1003 }
1004
1005 static void
1006 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1007 {
1008         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1009
1010         radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1011                                fui(d->depth_bounds.min));
1012         radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1013                                fui(d->depth_bounds.max));
1014 }
1015
1016 static void
1017 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1018 {
1019         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1020         unsigned slope = fui(d->depth_bias.slope * 16.0f);
1021         unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1022
1023
1024         radeon_set_context_reg_seq(cmd_buffer->cs,
1025                                    R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1026         radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1027         radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1028         radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1029         radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1030         radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1031 }
1032
1033 static void
1034 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1035                          int index,
1036                          struct radv_attachment_info *att,
1037                          struct radv_image *image,
1038                          VkImageLayout layout)
1039 {
1040         bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1041         struct radv_color_buffer_info *cb = &att->cb;
1042         uint32_t cb_color_info = cb->cb_color_info;
1043
1044         if (!radv_layout_dcc_compressed(image, layout,
1045                                         radv_image_queue_family_mask(image,
1046                                                                      cmd_buffer->queue_family_index,
1047                                                                      cmd_buffer->queue_family_index))) {
1048                 cb_color_info &= C_028C70_DCC_ENABLE;
1049         }
1050
1051         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1052                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1053                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1054                 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1055                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1056                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1057                 radeon_emit(cmd_buffer->cs, cb_color_info);
1058                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1059                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1060                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1061                 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1062                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1063                 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1064
1065                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1066                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1067                 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1068
1069                 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1070                                        S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1071         } else {
1072                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1073                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1074                 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1075                 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1076                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1077                 radeon_emit(cmd_buffer->cs, cb_color_info);
1078                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1079                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1080                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1081                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1082                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1083                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1084
1085                 if (is_vi) { /* DCC BASE */
1086                         radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1087                 }
1088         }
1089
1090         if (radv_image_has_dcc(image)) {
1091                 /* Drawing with DCC enabled also compresses colorbuffers. */
1092                 radv_update_dcc_metadata(cmd_buffer, image, true);
1093         }
1094 }
1095
1096 static void
1097 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1098                              struct radv_ds_buffer_info *ds,
1099                              struct radv_image *image, VkImageLayout layout,
1100                              bool requires_cond_exec)
1101 {
1102         uint32_t db_z_info = ds->db_z_info;
1103         uint32_t db_z_info_reg;
1104
1105         if (!radv_image_is_tc_compat_htile(image))
1106                 return;
1107
1108         if (!radv_layout_has_htile(image, layout,
1109                                    radv_image_queue_family_mask(image,
1110                                                                 cmd_buffer->queue_family_index,
1111                                                                 cmd_buffer->queue_family_index))) {
1112                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1113         }
1114
1115         db_z_info &= C_028040_ZRANGE_PRECISION;
1116
1117         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1118                 db_z_info_reg = R_028038_DB_Z_INFO;
1119         } else {
1120                 db_z_info_reg = R_028040_DB_Z_INFO;
1121         }
1122
1123         /* When we don't know the last fast clear value we need to emit a
1124          * conditional packet that will eventually skip the following
1125          * SET_CONTEXT_REG packet.
1126          */
1127         if (requires_cond_exec) {
1128                 uint64_t va = radv_buffer_get_va(image->bo);
1129                 va += image->offset + image->tc_compat_zrange_offset;
1130
1131                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1132                 radeon_emit(cmd_buffer->cs, va);
1133                 radeon_emit(cmd_buffer->cs, va >> 32);
1134                 radeon_emit(cmd_buffer->cs, 0);
1135                 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1136         }
1137
1138         radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1139 }
1140
1141 static void
1142 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1143                       struct radv_ds_buffer_info *ds,
1144                       struct radv_image *image,
1145                       VkImageLayout layout)
1146 {
1147         uint32_t db_z_info = ds->db_z_info;
1148         uint32_t db_stencil_info = ds->db_stencil_info;
1149
1150         if (!radv_layout_has_htile(image, layout,
1151                                    radv_image_queue_family_mask(image,
1152                                                                 cmd_buffer->queue_family_index,
1153                                                                 cmd_buffer->queue_family_index))) {
1154                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1155                 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1156         }
1157
1158         radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1159         radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1160
1161
1162         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1163                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1164                 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1165                 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1166                 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1167
1168                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1169                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* DB_Z_INFO */
1170                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* DB_STENCIL_INFO */
1171                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* DB_Z_READ_BASE */
1172                 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32));        /* DB_Z_READ_BASE_HI */
1173                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* DB_STENCIL_READ_BASE */
1174                 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1175                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* DB_Z_WRITE_BASE */
1176                 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32));       /* DB_Z_WRITE_BASE_HI */
1177                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1178                 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1179
1180                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1181                 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1182                 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1183         } else {
1184                 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1185
1186                 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1187                 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1188                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* R_028040_DB_Z_INFO */
1189                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* R_028044_DB_STENCIL_INFO */
1190                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* R_028048_DB_Z_READ_BASE */
1191                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* R_02804C_DB_STENCIL_READ_BASE */
1192                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* R_028050_DB_Z_WRITE_BASE */
1193                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1194                 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1195                 radeon_emit(cmd_buffer->cs, ds->db_depth_slice);        /* R_02805C_DB_DEPTH_SLICE */
1196
1197         }
1198
1199         /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1200         radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1201
1202         radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1203                                ds->pa_su_poly_offset_db_fmt_cntl);
1204 }
1205
1206 /**
1207  * Update the fast clear depth/stencil values if the image is bound as a
1208  * depth/stencil buffer.
1209  */
1210 static void
1211 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1212                                 struct radv_image *image,
1213                                 VkClearDepthStencilValue ds_clear_value,
1214                                 VkImageAspectFlags aspects)
1215 {
1216         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1217         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1218         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1219         struct radv_attachment_info *att;
1220         uint32_t att_idx;
1221
1222         if (!framebuffer || !subpass)
1223                 return;
1224
1225         if (!subpass->depth_stencil_attachment)
1226                 return;
1227
1228         att_idx = subpass->depth_stencil_attachment->attachment;
1229         att = &framebuffer->attachments[att_idx];
1230         if (att->attachment->image != image)
1231                 return;
1232
1233         radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1234         radeon_emit(cs, ds_clear_value.stencil);
1235         radeon_emit(cs, fui(ds_clear_value.depth));
1236
1237         /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1238          * only needed when clearing Z to 0.0.
1239          */
1240         if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1241             ds_clear_value.depth == 0.0) {
1242                 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1243
1244                 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1245                                              layout, false);
1246         }
1247
1248         cmd_buffer->state.context_roll_without_scissor_emitted = true;
1249 }
1250
1251 /**
1252  * Set the clear depth/stencil values to the image's metadata.
1253  */
1254 static void
1255 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1256                            struct radv_image *image,
1257                            VkClearDepthStencilValue ds_clear_value,
1258                            VkImageAspectFlags aspects)
1259 {
1260         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1261         uint64_t va = radv_buffer_get_va(image->bo);
1262         unsigned reg_offset = 0, reg_count = 0;
1263
1264         va += image->offset + image->clear_value_offset;
1265
1266         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1267                 ++reg_count;
1268         } else {
1269                 ++reg_offset;
1270                 va += 4;
1271         }
1272         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1273                 ++reg_count;
1274
1275         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1276         radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1277                         S_370_WR_CONFIRM(1) |
1278                         S_370_ENGINE_SEL(V_370_PFP));
1279         radeon_emit(cs, va);
1280         radeon_emit(cs, va >> 32);
1281         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1282                 radeon_emit(cs, ds_clear_value.stencil);
1283         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1284                 radeon_emit(cs, fui(ds_clear_value.depth));
1285 }
1286
1287 /**
1288  * Update the TC-compat metadata value for this image.
1289  */
1290 static void
1291 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1292                                    struct radv_image *image,
1293                                    uint32_t value)
1294 {
1295         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1296         uint64_t va = radv_buffer_get_va(image->bo);
1297         va += image->offset + image->tc_compat_zrange_offset;
1298
1299         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1300         radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1301                         S_370_WR_CONFIRM(1) |
1302                         S_370_ENGINE_SEL(V_370_PFP));
1303         radeon_emit(cs, va);
1304         radeon_emit(cs, va >> 32);
1305         radeon_emit(cs, value);
1306 }
1307
1308 static void
1309 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1310                                       struct radv_image *image,
1311                                       VkClearDepthStencilValue ds_clear_value)
1312 {
1313         uint64_t va = radv_buffer_get_va(image->bo);
1314         va += image->offset + image->tc_compat_zrange_offset;
1315         uint32_t cond_val;
1316
1317         /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1318          * depth clear value is 0.0f.
1319          */
1320         cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1321
1322         radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1323 }
1324
1325 /**
1326  * Update the clear depth/stencil values for this image.
1327  */
1328 void
1329 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1330                               struct radv_image *image,
1331                               VkClearDepthStencilValue ds_clear_value,
1332                               VkImageAspectFlags aspects)
1333 {
1334         assert(radv_image_has_htile(image));
1335
1336         radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1337
1338         if (radv_image_is_tc_compat_htile(image) &&
1339             (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1340                 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1341                                                       ds_clear_value);
1342         }
1343
1344         radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1345                                         aspects);
1346 }
1347
1348 /**
1349  * Load the clear depth/stencil values from the image's metadata.
1350  */
1351 static void
1352 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1353                             struct radv_image *image)
1354 {
1355         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1356         VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1357         uint64_t va = radv_buffer_get_va(image->bo);
1358         unsigned reg_offset = 0, reg_count = 0;
1359
1360         va += image->offset + image->clear_value_offset;
1361
1362         if (!radv_image_has_htile(image))
1363                 return;
1364
1365         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1366                 ++reg_count;
1367         } else {
1368                 ++reg_offset;
1369                 va += 4;
1370         }
1371         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1372                 ++reg_count;
1373
1374         uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1375
1376         if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1377                 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1378                 radeon_emit(cs, va);
1379                 radeon_emit(cs, va >> 32);
1380                 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1381                 radeon_emit(cs, reg_count);
1382         } else {
1383                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1384                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1385                                 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1386                                 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1387                 radeon_emit(cs, va);
1388                 radeon_emit(cs, va >> 32);
1389                 radeon_emit(cs, reg >> 2);
1390                 radeon_emit(cs, 0);
1391
1392                 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1393                 radeon_emit(cs, 0);
1394         }
1395 }
1396
1397 /*
1398  * With DCC some colors don't require CMASK elimination before being
1399  * used as a texture. This sets a predicate value to determine if the
1400  * cmask eliminate is required.
1401  */
1402 void
1403 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1404                          struct radv_image *image, bool value)
1405 {
1406         uint64_t pred_val = value;
1407         uint64_t va = radv_buffer_get_va(image->bo);
1408         va += image->offset + image->fce_pred_offset;
1409
1410         assert(radv_image_has_dcc(image));
1411
1412         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1413         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1414                                     S_370_WR_CONFIRM(1) |
1415                                     S_370_ENGINE_SEL(V_370_PFP));
1416         radeon_emit(cmd_buffer->cs, va);
1417         radeon_emit(cmd_buffer->cs, va >> 32);
1418         radeon_emit(cmd_buffer->cs, pred_val);
1419         radeon_emit(cmd_buffer->cs, pred_val >> 32);
1420 }
1421
1422 /**
1423  * Update the DCC predicate to reflect the compression state.
1424  */
1425 void
1426 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1427                          struct radv_image *image, bool value)
1428 {
1429         uint64_t pred_val = value;
1430         uint64_t va = radv_buffer_get_va(image->bo);
1431         va += image->offset + image->dcc_pred_offset;
1432
1433         assert(radv_image_has_dcc(image));
1434
1435         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1436         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1437                                     S_370_WR_CONFIRM(1) |
1438                                     S_370_ENGINE_SEL(V_370_PFP));
1439         radeon_emit(cmd_buffer->cs, va);
1440         radeon_emit(cmd_buffer->cs, va >> 32);
1441         radeon_emit(cmd_buffer->cs, pred_val);
1442         radeon_emit(cmd_buffer->cs, pred_val >> 32);
1443 }
1444
1445 /**
1446  * Update the fast clear color values if the image is bound as a color buffer.
1447  */
1448 static void
1449 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1450                                    struct radv_image *image,
1451                                    int cb_idx,
1452                                    uint32_t color_values[2])
1453 {
1454         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1455         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1456         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1457         struct radv_attachment_info *att;
1458         uint32_t att_idx;
1459
1460         if (!framebuffer || !subpass)
1461                 return;
1462
1463         att_idx = subpass->color_attachments[cb_idx].attachment;
1464         if (att_idx == VK_ATTACHMENT_UNUSED)
1465                 return;
1466
1467         att = &framebuffer->attachments[att_idx];
1468         if (att->attachment->image != image)
1469                 return;
1470
1471         radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1472         radeon_emit(cs, color_values[0]);
1473         radeon_emit(cs, color_values[1]);
1474
1475         cmd_buffer->state.context_roll_without_scissor_emitted = true;
1476 }
1477
1478 /**
1479  * Set the clear color values to the image's metadata.
1480  */
1481 static void
1482 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1483                               struct radv_image *image,
1484                               uint32_t color_values[2])
1485 {
1486         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1487         uint64_t va = radv_buffer_get_va(image->bo);
1488
1489         va += image->offset + image->clear_value_offset;
1490
1491         assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1492
1493         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1494         radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1495                         S_370_WR_CONFIRM(1) |
1496                         S_370_ENGINE_SEL(V_370_PFP));
1497         radeon_emit(cs, va);
1498         radeon_emit(cs, va >> 32);
1499         radeon_emit(cs, color_values[0]);
1500         radeon_emit(cs, color_values[1]);
1501 }
1502
1503 /**
1504  * Update the clear color values for this image.
1505  */
1506 void
1507 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1508                                  struct radv_image *image,
1509                                  int cb_idx,
1510                                  uint32_t color_values[2])
1511 {
1512         assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1513
1514         radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1515
1516         radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1517                                            color_values);
1518 }
1519
1520 /**
1521  * Load the clear color values from the image's metadata.
1522  */
1523 static void
1524 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1525                                struct radv_image *image,
1526                                int cb_idx)
1527 {
1528         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1529         uint64_t va = radv_buffer_get_va(image->bo);
1530
1531         va += image->offset + image->clear_value_offset;
1532
1533         if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1534                 return;
1535
1536         uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1537
1538         if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
1539                 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1540                 radeon_emit(cs, va);
1541                 radeon_emit(cs, va >> 32);
1542                 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1543                 radeon_emit(cs, 2);
1544         } else {
1545                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1546                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1547                                 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1548                                 COPY_DATA_COUNT_SEL);
1549                 radeon_emit(cs, va);
1550                 radeon_emit(cs, va >> 32);
1551                 radeon_emit(cs, reg >> 2);
1552                 radeon_emit(cs, 0);
1553
1554                 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1555                 radeon_emit(cs, 0);
1556         }
1557 }
1558
1559 static void
1560 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1561 {
1562         int i;
1563         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1564         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1565         unsigned num_bpp64_colorbufs = 0;
1566
1567         /* this may happen for inherited secondary recording */
1568         if (!framebuffer)
1569                 return;
1570
1571         for (i = 0; i < 8; ++i) {
1572                 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1573                         radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1574                                        S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1575                         continue;
1576                 }
1577
1578                 int idx = subpass->color_attachments[i].attachment;
1579                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1580                 struct radv_image *image = att->attachment->image;
1581                 VkImageLayout layout = subpass->color_attachments[i].layout;
1582
1583                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1584
1585                 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1586                 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1587
1588                 radv_load_color_clear_metadata(cmd_buffer, image, i);
1589
1590                 if (image->surface.bpe >= 8)
1591                         num_bpp64_colorbufs++;
1592         }
1593
1594         if (subpass->depth_stencil_attachment) {
1595                 int idx = subpass->depth_stencil_attachment->attachment;
1596                 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1597                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1598                 struct radv_image *image = att->attachment->image;
1599                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1600                 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1601                                                                                 cmd_buffer->queue_family_index,
1602                                                                                 cmd_buffer->queue_family_index);
1603                 /* We currently don't support writing decompressed HTILE */
1604                 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1605                        radv_layout_is_htile_compressed(image, layout, queue_mask));
1606
1607                 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1608
1609                 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1610                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1611                         cmd_buffer->state.offset_scale = att->ds.offset_scale;
1612                 }
1613                 radv_load_ds_clear_metadata(cmd_buffer, image);
1614         } else {
1615                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1616                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1617                 else
1618                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1619
1620                 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1621                 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1622         }
1623         radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1624                                S_028208_BR_X(framebuffer->width) |
1625                                S_028208_BR_Y(framebuffer->height));
1626
1627         if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1628                 uint8_t watermark = 4; /* Default value for VI. */
1629
1630                 /* For optimal DCC performance. */
1631                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1632                         if (num_bpp64_colorbufs >= 5) {
1633                                 watermark = 8;
1634                         } else {
1635                                 watermark = 6;
1636                         }
1637                 }
1638
1639                 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1640                                        S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1641                                        S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1642         }
1643
1644         if (cmd_buffer->device->dfsm_allowed) {
1645                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1646                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1647         }
1648
1649         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1650 }
1651
1652 static void
1653 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1654 {
1655         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1656         struct radv_cmd_state *state = &cmd_buffer->state;
1657
1658         if (state->index_type != state->last_index_type) {
1659                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1660                         radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1661                                                    2, state->index_type);
1662                 } else {
1663                         radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1664                         radeon_emit(cs, state->index_type);
1665                 }
1666
1667                 state->last_index_type = state->index_type;
1668         }
1669
1670         radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1671         radeon_emit(cs, state->index_va);
1672         radeon_emit(cs, state->index_va >> 32);
1673
1674         radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1675         radeon_emit(cs, state->max_index_count);
1676
1677         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1678 }
1679
1680 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1681 {
1682         bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1683         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1684         uint32_t pa_sc_mode_cntl_1 =
1685                 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1686         uint32_t db_count_control;
1687
1688         if(!cmd_buffer->state.active_occlusion_queries) {
1689                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1690                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1691                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1692                             has_perfect_queries) {
1693                                 /* Re-enable out-of-order rasterization if the
1694                                  * bound pipeline supports it and if it's has
1695                                  * been disabled before starting any perfect
1696                                  * occlusion queries.
1697                                  */
1698                                 radeon_set_context_reg(cmd_buffer->cs,
1699                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1700                                                        pa_sc_mode_cntl_1);
1701                         }
1702                 }
1703                 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1704         } else {
1705                 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1706                 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1707
1708                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1709                         db_count_control =
1710                                 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1711                                 S_028004_SAMPLE_RATE(sample_rate) |
1712                                 S_028004_ZPASS_ENABLE(1) |
1713                                 S_028004_SLICE_EVEN_ENABLE(1) |
1714                                 S_028004_SLICE_ODD_ENABLE(1);
1715
1716                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1717                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1718                             has_perfect_queries) {
1719                                 /* If the bound pipeline has enabled
1720                                  * out-of-order rasterization, we should
1721                                  * disable it before starting any perfect
1722                                  * occlusion queries.
1723                                  */
1724                                 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1725
1726                                 radeon_set_context_reg(cmd_buffer->cs,
1727                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1728                                                        pa_sc_mode_cntl_1);
1729                         }
1730                 } else {
1731                         db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1732                                 S_028004_SAMPLE_RATE(sample_rate);
1733                 }
1734         }
1735
1736         radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1737
1738         cmd_buffer->state.context_roll_without_scissor_emitted = true;
1739 }
1740
1741 static void
1742 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1743 {
1744         uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1745
1746         if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1747                 radv_emit_viewport(cmd_buffer);
1748
1749         if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1750             !cmd_buffer->device->physical_device->has_scissor_bug)
1751                 radv_emit_scissor(cmd_buffer);
1752
1753         if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1754                 radv_emit_line_width(cmd_buffer);
1755
1756         if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1757                 radv_emit_blend_constants(cmd_buffer);
1758
1759         if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1760                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1761                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1762                 radv_emit_stencil(cmd_buffer);
1763
1764         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1765                 radv_emit_depth_bounds(cmd_buffer);
1766
1767         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1768                 radv_emit_depth_bias(cmd_buffer);
1769
1770         if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1771                 radv_emit_discard_rectangle(cmd_buffer);
1772
1773         cmd_buffer->state.dirty &= ~states;
1774 }
1775
1776 static void
1777 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1778                             VkPipelineBindPoint bind_point)
1779 {
1780         struct radv_descriptor_state *descriptors_state =
1781                 radv_get_descriptors_state(cmd_buffer, bind_point);
1782         struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1783         unsigned bo_offset;
1784
1785         if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1786                                          set->mapped_ptr,
1787                                          &bo_offset))
1788                 return;
1789
1790         set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1791         set->va += bo_offset;
1792 }
1793
1794 static void
1795 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1796                                     VkPipelineBindPoint bind_point)
1797 {
1798         struct radv_descriptor_state *descriptors_state =
1799                 radv_get_descriptors_state(cmd_buffer, bind_point);
1800         uint32_t size = MAX_SETS * 4;
1801         uint32_t offset;
1802         void *ptr;
1803
1804         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1805                                           256, &offset, &ptr))
1806                 return;
1807
1808         for (unsigned i = 0; i < MAX_SETS; i++) {
1809                 uint32_t *uptr = ((uint32_t *)ptr) + i;
1810                 uint64_t set_va = 0;
1811                 struct radv_descriptor_set *set = descriptors_state->sets[i];
1812                 if (descriptors_state->valid & (1u << i))
1813                         set_va = set->va;
1814                 uptr[0] = set_va & 0xffffffff;
1815         }
1816
1817         uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1818         va += offset;
1819
1820         if (cmd_buffer->state.pipeline) {
1821                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1822                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1823                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1824
1825                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1826                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1827                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1828
1829                 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1830                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1831                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1832
1833                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1834                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1835                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1836
1837                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1838                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1839                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1840         }
1841
1842         if (cmd_buffer->state.compute_pipeline)
1843                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1844                                            AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1845 }
1846
1847 static void
1848 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1849                        VkShaderStageFlags stages)
1850 {
1851         VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1852                                          VK_PIPELINE_BIND_POINT_COMPUTE :
1853                                          VK_PIPELINE_BIND_POINT_GRAPHICS;
1854         struct radv_descriptor_state *descriptors_state =
1855                 radv_get_descriptors_state(cmd_buffer, bind_point);
1856         struct radv_cmd_state *state = &cmd_buffer->state;
1857         bool flush_indirect_descriptors;
1858
1859         if (!descriptors_state->dirty)
1860                 return;
1861
1862         if (descriptors_state->push_dirty)
1863                 radv_flush_push_descriptors(cmd_buffer, bind_point);
1864
1865         flush_indirect_descriptors =
1866                 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1867                  state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1868                 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1869                  state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1870
1871         if (flush_indirect_descriptors)
1872                 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1873
1874         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1875                                                            cmd_buffer->cs,
1876                                                            MAX_SETS * MESA_SHADER_STAGES * 4);
1877
1878         if (cmd_buffer->state.pipeline) {
1879                 radv_foreach_stage(stage, stages) {
1880                         if (!cmd_buffer->state.pipeline->shaders[stage])
1881                                 continue;
1882
1883                         radv_emit_descriptor_pointers(cmd_buffer,
1884                                                       cmd_buffer->state.pipeline,
1885                                                       descriptors_state, stage);
1886                 }
1887         }
1888
1889         if (cmd_buffer->state.compute_pipeline &&
1890             (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1891                 radv_emit_descriptor_pointers(cmd_buffer,
1892                                               cmd_buffer->state.compute_pipeline,
1893                                               descriptors_state,
1894                                               MESA_SHADER_COMPUTE);
1895         }
1896
1897         descriptors_state->dirty = 0;
1898         descriptors_state->push_dirty = false;
1899
1900         assert(cmd_buffer->cs->cdw <= cdw_max);
1901
1902         if (unlikely(cmd_buffer->device->trace_bo))
1903                 radv_save_descriptors(cmd_buffer, bind_point);
1904 }
1905
1906 static void
1907 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1908                      VkShaderStageFlags stages)
1909 {
1910         struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1911                                          ? cmd_buffer->state.compute_pipeline
1912                                          : cmd_buffer->state.pipeline;
1913         VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1914                                          VK_PIPELINE_BIND_POINT_COMPUTE :
1915                                          VK_PIPELINE_BIND_POINT_GRAPHICS;
1916         struct radv_descriptor_state *descriptors_state =
1917                 radv_get_descriptors_state(cmd_buffer, bind_point);
1918         struct radv_pipeline_layout *layout = pipeline->layout;
1919         struct radv_shader_variant *shader, *prev_shader;
1920         bool need_push_constants = false;
1921         unsigned offset;
1922         void *ptr;
1923         uint64_t va;
1924
1925         stages &= cmd_buffer->push_constant_stages;
1926         if (!stages ||
1927             (!layout->push_constant_size && !layout->dynamic_offset_count))
1928                 return;
1929
1930         radv_foreach_stage(stage, stages) {
1931                 if (!pipeline->shaders[stage])
1932                         continue;
1933
1934                 need_push_constants |= pipeline->shaders[stage]->info.info.loads_push_constants;
1935                 need_push_constants |= pipeline->shaders[stage]->info.info.loads_dynamic_offsets;
1936
1937                 uint8_t base = pipeline->shaders[stage]->info.info.base_inline_push_consts;
1938                 uint8_t count = pipeline->shaders[stage]->info.info.num_inline_push_consts;
1939
1940                 radv_emit_inline_push_consts(cmd_buffer, pipeline, stage,
1941                                              AC_UD_INLINE_PUSH_CONSTANTS,
1942                                              count,
1943                                              (uint32_t *)&cmd_buffer->push_constants[base * 4]);
1944         }
1945
1946         if (need_push_constants) {
1947                 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1948                                                   16 * layout->dynamic_offset_count,
1949                                                   256, &offset, &ptr))
1950                         return;
1951
1952                 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1953                 memcpy((char*)ptr + layout->push_constant_size,
1954                        descriptors_state->dynamic_buffers,
1955                        16 * layout->dynamic_offset_count);
1956
1957                 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1958                 va += offset;
1959
1960                 MAYBE_UNUSED unsigned cdw_max =
1961                         radeon_check_space(cmd_buffer->device->ws,
1962                                            cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1963
1964                 prev_shader = NULL;
1965                 radv_foreach_stage(stage, stages) {
1966                         shader = radv_get_shader(pipeline, stage);
1967
1968                         /* Avoid redundantly emitting the address for merged stages. */
1969                         if (shader && shader != prev_shader) {
1970                                 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1971                                                            AC_UD_PUSH_CONSTANTS, va);
1972
1973                                 prev_shader = shader;
1974                         }
1975                 }
1976                 assert(cmd_buffer->cs->cdw <= cdw_max);
1977         }
1978
1979         cmd_buffer->push_constant_stages &= ~stages;
1980 }
1981
1982 static void
1983 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1984                               bool pipeline_is_dirty)
1985 {
1986         if ((pipeline_is_dirty ||
1987             (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1988             cmd_buffer->state.pipeline->vertex_elements.count &&
1989             radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1990                 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1991                 unsigned vb_offset;
1992                 void *vb_ptr;
1993                 uint32_t i = 0;
1994                 uint32_t count = velems->count;
1995                 uint64_t va;
1996
1997                 /* allocate some descriptor state for vertex buffers */
1998                 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1999                                                   &vb_offset, &vb_ptr))
2000                         return;
2001
2002                 for (i = 0; i < count; i++) {
2003                         uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
2004                         uint32_t offset;
2005                         int vb = velems->binding[i];
2006                         struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
2007                         uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
2008
2009                         va = radv_buffer_get_va(buffer->bo);
2010
2011                         offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
2012                         va += offset + buffer->offset;
2013                         desc[0] = va;
2014                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
2015                         if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
2016                                 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
2017                         else
2018                                 desc[2] = buffer->size - offset;
2019                         desc[3] = velems->rsrc_word3[i];
2020                 }
2021
2022                 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2023                 va += vb_offset;
2024
2025                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
2026                                            AC_UD_VS_VERTEX_BUFFERS, va);
2027
2028                 cmd_buffer->state.vb_va = va;
2029                 cmd_buffer->state.vb_size = count * 16;
2030                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
2031         }
2032         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
2033 }
2034
2035 static void
2036 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2037 {
2038         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2039         struct radv_userdata_info *loc;
2040         uint32_t base_reg;
2041
2042         for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2043                 if (!radv_get_shader(pipeline, stage))
2044                         continue;
2045
2046                 loc = radv_lookup_user_sgpr(pipeline, stage,
2047                                             AC_UD_STREAMOUT_BUFFERS);
2048                 if (loc->sgpr_idx == -1)
2049                         continue;
2050
2051                 base_reg = pipeline->user_data_0[stage];
2052
2053                 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2054                                          base_reg + loc->sgpr_idx * 4, va, false);
2055         }
2056
2057         if (pipeline->gs_copy_shader) {
2058                 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2059                 if (loc->sgpr_idx != -1) {
2060                         base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2061
2062                         radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2063                                                  base_reg + loc->sgpr_idx * 4, va, false);
2064                 }
2065         }
2066 }
2067
2068 static void
2069 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2070 {
2071         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2072                 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2073                 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2074                 unsigned so_offset;
2075                 void *so_ptr;
2076                 uint64_t va;
2077
2078                 /* Allocate some descriptor state for streamout buffers. */
2079                 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2080                                                   MAX_SO_BUFFERS * 16, 256,
2081                                                   &so_offset, &so_ptr))
2082                         return;
2083
2084                 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2085                         struct radv_buffer *buffer = sb[i].buffer;
2086                         uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2087
2088                         if (!(so->enabled_mask & (1 << i)))
2089                                 continue;
2090
2091                         va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2092
2093                         va += sb[i].offset;
2094
2095                         /* Set the descriptor.
2096                          *
2097                          * On VI, the format must be non-INVALID, otherwise
2098                          * the buffer will be considered not bound and store
2099                          * instructions will be no-ops.
2100                          */
2101                         desc[0] = va;
2102                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2103                         desc[2] = 0xffffffff;
2104                         desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2105                                   S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2106                                   S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2107                                   S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2108                                   S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2109                 }
2110
2111                 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2112                 va += so_offset;
2113
2114                 radv_emit_streamout_buffers(cmd_buffer, va);
2115         }
2116
2117         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2118 }
2119
2120 static void
2121 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2122 {
2123         radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2124         radv_flush_streamout_descriptors(cmd_buffer);
2125         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2126         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2127 }
2128
2129 struct radv_draw_info {
2130         /**
2131          * Number of vertices.
2132          */
2133         uint32_t count;
2134
2135         /**
2136          * Index of the first vertex.
2137          */
2138         int32_t vertex_offset;
2139
2140         /**
2141          * First instance id.
2142          */
2143         uint32_t first_instance;
2144
2145         /**
2146          * Number of instances.
2147          */
2148         uint32_t instance_count;
2149
2150         /**
2151          * First index (indexed draws only).
2152          */
2153         uint32_t first_index;
2154
2155         /**
2156          * Whether it's an indexed draw.
2157          */
2158         bool indexed;
2159
2160         /**
2161          * Indirect draw parameters resource.
2162          */
2163         struct radv_buffer *indirect;
2164         uint64_t indirect_offset;
2165         uint32_t stride;
2166
2167         /**
2168          * Draw count parameters resource.
2169          */
2170         struct radv_buffer *count_buffer;
2171         uint64_t count_buffer_offset;
2172
2173         /**
2174          * Stream output parameters resource.
2175          */
2176         struct radv_buffer *strmout_buffer;
2177         uint64_t strmout_buffer_offset;
2178 };
2179
2180 static void
2181 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2182                          const struct radv_draw_info *draw_info)
2183 {
2184         struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2185         struct radv_cmd_state *state = &cmd_buffer->state;
2186         struct radeon_cmdbuf *cs = cmd_buffer->cs;
2187         uint32_t ia_multi_vgt_param;
2188         int32_t primitive_reset_en;
2189
2190         /* Draw state. */
2191         ia_multi_vgt_param =
2192                 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2193                                           draw_info->indirect,
2194                                           draw_info->indirect ? 0 : draw_info->count);
2195
2196         if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2197                 if (info->chip_class >= GFX9) {
2198                         radeon_set_uconfig_reg_idx(cs,
2199                                                    R_030960_IA_MULTI_VGT_PARAM,
2200                                                    4, ia_multi_vgt_param);
2201                 } else if (info->chip_class >= CIK) {
2202                         radeon_set_context_reg_idx(cs,
2203                                                    R_028AA8_IA_MULTI_VGT_PARAM,
2204                                                    1, ia_multi_vgt_param);
2205                 } else {
2206                         radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2207                                                ia_multi_vgt_param);
2208                 }
2209                 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2210         }
2211
2212         /* Primitive restart. */
2213         primitive_reset_en =
2214                 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2215
2216         if (primitive_reset_en != state->last_primitive_reset_en) {
2217                 state->last_primitive_reset_en = primitive_reset_en;
2218                 if (info->chip_class >= GFX9) {
2219                         radeon_set_uconfig_reg(cs,
2220                                                R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2221                                                primitive_reset_en);
2222                 } else {
2223                         radeon_set_context_reg(cs,
2224                                                R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2225                                                primitive_reset_en);
2226                 }
2227         }
2228
2229         if (primitive_reset_en) {
2230                 uint32_t primitive_reset_index =
2231                         state->index_type ? 0xffffffffu : 0xffffu;
2232
2233                 if (primitive_reset_index != state->last_primitive_reset_index) {
2234                         radeon_set_context_reg(cs,
2235                                                R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2236                                                primitive_reset_index);
2237                         state->last_primitive_reset_index = primitive_reset_index;
2238                 }
2239         }
2240
2241         if (draw_info->strmout_buffer) {
2242                 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2243
2244                 va += draw_info->strmout_buffer->offset +
2245                       draw_info->strmout_buffer_offset;
2246
2247                 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2248                                        draw_info->stride);
2249
2250                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2251                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2252                                 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2253                                 COPY_DATA_WR_CONFIRM);
2254                 radeon_emit(cs, va);
2255                 radeon_emit(cs, va >> 32);
2256                 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2257                 radeon_emit(cs, 0); /* unused */
2258
2259                 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2260         }
2261 }
2262
2263 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2264                              VkPipelineStageFlags src_stage_mask)
2265 {
2266         if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2267                               VK_PIPELINE_STAGE_TRANSFER_BIT |
2268                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2269                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2270                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2271         }
2272
2273         if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2274                               VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2275                               VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2276                               VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2277                               VK_PIPELINE_STAGE_TRANSFER_BIT |
2278                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2279                               VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2280                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2281                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2282         } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2283                                      VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2284                                      VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2285                                      VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2286                                      VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2287                                      VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2288                                      VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2289                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2290         }
2291 }
2292
2293 static enum radv_cmd_flush_bits
2294 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2295                       VkAccessFlags src_flags,
2296                       struct radv_image *image)
2297 {
2298         bool flush_CB_meta = true, flush_DB_meta = true;
2299         enum radv_cmd_flush_bits flush_bits = 0;
2300         uint32_t b;
2301
2302         if (image) {
2303                 if (!radv_image_has_CB_metadata(image))
2304                         flush_CB_meta = false;
2305                 if (!radv_image_has_htile(image))
2306                         flush_DB_meta = false;
2307         }
2308
2309         for_each_bit(b, src_flags) {
2310                 switch ((VkAccessFlagBits)(1 << b)) {
2311                 case VK_ACCESS_SHADER_WRITE_BIT:
2312                 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2313                 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2314                         flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2315                         break;
2316                 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2317                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2318                         if (flush_CB_meta)
2319                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2320                         break;
2321                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2322                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2323                         if (flush_DB_meta)
2324                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2325                         break;
2326                 case VK_ACCESS_TRANSFER_WRITE_BIT:
2327                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2328                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2329                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
2330
2331                         if (flush_CB_meta)
2332                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2333                         if (flush_DB_meta)
2334                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2335                         break;
2336                 default:
2337                         break;
2338                 }
2339         }
2340         return flush_bits;
2341 }
2342
2343 static enum radv_cmd_flush_bits
2344 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2345                       VkAccessFlags dst_flags,
2346                       struct radv_image *image)
2347 {
2348         bool flush_CB_meta = true, flush_DB_meta = true;
2349         enum radv_cmd_flush_bits flush_bits = 0;
2350         bool flush_CB = true, flush_DB = true;
2351         bool image_is_coherent = false;
2352         uint32_t b;
2353
2354         if (image) {
2355                 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2356                         flush_CB = false;
2357                         flush_DB = false;
2358                 }
2359
2360                 if (!radv_image_has_CB_metadata(image))
2361                         flush_CB_meta = false;
2362                 if (!radv_image_has_htile(image))
2363                         flush_DB_meta = false;
2364
2365                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2366                         if (image->info.samples == 1 &&
2367                             (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2368                                              VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2369                             !vk_format_is_stencil(image->vk_format)) {
2370                                 /* Single-sample color and single-sample depth
2371                                  * (not stencil) are coherent with shaders on
2372                                  * GFX9.
2373                                  */
2374                                 image_is_coherent = true;
2375                         }
2376                 }
2377         }
2378
2379         for_each_bit(b, dst_flags) {
2380                 switch ((VkAccessFlagBits)(1 << b)) {
2381                 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2382                 case VK_ACCESS_INDEX_READ_BIT:
2383                 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2384                         break;
2385                 case VK_ACCESS_UNIFORM_READ_BIT:
2386                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2387                         break;
2388                 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2389                 case VK_ACCESS_TRANSFER_READ_BIT:
2390                 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2391                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2392                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
2393                         break;
2394                 case VK_ACCESS_SHADER_READ_BIT:
2395                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2396
2397                         if (!image_is_coherent)
2398                                 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2399                         break;
2400                 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2401                         if (flush_CB)
2402                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2403                         if (flush_CB_meta)
2404                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2405                         break;
2406                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2407                         if (flush_DB)
2408                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2409                         if (flush_DB_meta)
2410                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2411                         break;
2412                 default:
2413                         break;
2414                 }
2415         }
2416         return flush_bits;
2417 }
2418
2419 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2420                           const struct radv_subpass_barrier *barrier)
2421 {
2422         cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2423                                                               NULL);
2424         radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2425         cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2426                                                               NULL);
2427 }
2428
2429 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2430                                                  struct radv_subpass_attachment att)
2431 {
2432         unsigned idx = att.attachment;
2433         struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2434         VkImageSubresourceRange range;
2435         range.aspectMask = 0;
2436         range.baseMipLevel = view->base_mip;
2437         range.levelCount = 1;
2438         range.baseArrayLayer = view->base_layer;
2439         range.layerCount = cmd_buffer->state.framebuffer->layers;
2440
2441         if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
2442                 /* If the current subpass uses multiview, the driver might have
2443                  * performed a fast color/depth clear to the whole image
2444                  * (including all layers). To make sure the driver will
2445                  * decompress the image correctly (if needed), we have to
2446                  * account for the "real" number of layers. If the view mask is
2447                  * sparse, this will decompress more layers than needed.
2448                  */
2449                 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2450         }
2451
2452         radv_handle_image_transition(cmd_buffer,
2453                                      view->image,
2454                                      cmd_buffer->state.attachments[idx].current_layout,
2455                                      att.layout, 0, 0, &range);
2456
2457         cmd_buffer->state.attachments[idx].current_layout = att.layout;
2458
2459
2460 }
2461
2462 void
2463 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2464                             const struct radv_subpass *subpass)
2465 {
2466         cmd_buffer->state.subpass = subpass;
2467
2468         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2469 }
2470
2471 static VkResult
2472 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2473                                  struct radv_render_pass *pass,
2474                                  const VkRenderPassBeginInfo *info)
2475 {
2476         struct radv_cmd_state *state = &cmd_buffer->state;
2477
2478         if (pass->attachment_count == 0) {
2479                 state->attachments = NULL;
2480                 return VK_SUCCESS;
2481         }
2482
2483         state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2484                                         pass->attachment_count *
2485                                         sizeof(state->attachments[0]),
2486                                         8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2487         if (state->attachments == NULL) {
2488                 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2489                 return cmd_buffer->record_result;
2490         }
2491
2492         for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2493                 struct radv_render_pass_attachment *att = &pass->attachments[i];
2494                 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2495                 VkImageAspectFlags clear_aspects = 0;
2496
2497                 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2498                         /* color attachment */
2499                         if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2500                                 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2501                         }
2502                 } else {
2503                         /* depthstencil attachment */
2504                         if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2505                             att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2506                                 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2507                                 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2508                                     att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2509                                         clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2510                         }
2511                         if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2512                             att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2513                                 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2514                         }
2515                 }
2516
2517                 state->attachments[i].pending_clear_aspects = clear_aspects;
2518                 state->attachments[i].cleared_views = 0;
2519                 if (clear_aspects && info) {
2520                         assert(info->clearValueCount > i);
2521                         state->attachments[i].clear_value = info->pClearValues[i];
2522                 }
2523
2524                 state->attachments[i].current_layout = att->initial_layout;
2525         }
2526
2527         return VK_SUCCESS;
2528 }
2529
2530 VkResult radv_AllocateCommandBuffers(
2531         VkDevice _device,
2532         const VkCommandBufferAllocateInfo *pAllocateInfo,
2533         VkCommandBuffer *pCommandBuffers)
2534 {
2535         RADV_FROM_HANDLE(radv_device, device, _device);
2536         RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2537
2538         VkResult result = VK_SUCCESS;
2539         uint32_t i;
2540
2541         for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2542
2543                 if (!list_empty(&pool->free_cmd_buffers)) {
2544                         struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2545
2546                         list_del(&cmd_buffer->pool_link);
2547                         list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2548
2549                         result = radv_reset_cmd_buffer(cmd_buffer);
2550                         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2551                         cmd_buffer->level = pAllocateInfo->level;
2552
2553                         pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2554                 } else {
2555                         result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2556                                                         &pCommandBuffers[i]);
2557                 }
2558                 if (result != VK_SUCCESS)
2559                         break;
2560         }
2561
2562         if (result != VK_SUCCESS) {
2563                 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2564                                         i, pCommandBuffers);
2565
2566                 /* From the Vulkan 1.0.66 spec:
2567                  *
2568                  * "vkAllocateCommandBuffers can be used to create multiple
2569                  *  command buffers. If the creation of any of those command
2570                  *  buffers fails, the implementation must destroy all
2571                  *  successfully created command buffer objects from this
2572                  *  command, set all entries of the pCommandBuffers array to
2573                  *  NULL and return the error."
2574                  */
2575                 memset(pCommandBuffers, 0,
2576                        sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2577         }
2578
2579         return result;
2580 }
2581
2582 void radv_FreeCommandBuffers(
2583         VkDevice device,
2584         VkCommandPool commandPool,
2585         uint32_t commandBufferCount,
2586         const VkCommandBuffer *pCommandBuffers)
2587 {
2588         for (uint32_t i = 0; i < commandBufferCount; i++) {
2589                 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2590
2591                 if (cmd_buffer) {
2592                         if (cmd_buffer->pool) {
2593                                 list_del(&cmd_buffer->pool_link);
2594                                 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2595                         } else
2596                                 radv_cmd_buffer_destroy(cmd_buffer);
2597
2598                 }
2599         }
2600 }
2601
2602 VkResult radv_ResetCommandBuffer(
2603         VkCommandBuffer commandBuffer,
2604         VkCommandBufferResetFlags flags)
2605 {
2606         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2607         return radv_reset_cmd_buffer(cmd_buffer);
2608 }
2609
2610 VkResult radv_BeginCommandBuffer(
2611         VkCommandBuffer commandBuffer,
2612         const VkCommandBufferBeginInfo *pBeginInfo)
2613 {
2614         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2615         VkResult result = VK_SUCCESS;
2616
2617         if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2618                 /* If the command buffer has already been resetted with
2619                  * vkResetCommandBuffer, no need to do it again.
2620                  */
2621                 result = radv_reset_cmd_buffer(cmd_buffer);
2622                 if (result != VK_SUCCESS)
2623                         return result;
2624         }
2625
2626         memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2627         cmd_buffer->state.last_primitive_reset_en = -1;
2628         cmd_buffer->state.last_index_type = -1;
2629         cmd_buffer->state.last_num_instances = -1;
2630         cmd_buffer->state.last_vertex_offset = -1;
2631         cmd_buffer->state.last_first_instance = -1;
2632         cmd_buffer->state.predication_type = -1;
2633         cmd_buffer->usage_flags = pBeginInfo->flags;
2634
2635         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2636             (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2637                 assert(pBeginInfo->pInheritanceInfo);
2638                 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2639                 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2640
2641                 struct radv_subpass *subpass =
2642                         &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2643
2644                 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2645                 if (result != VK_SUCCESS)
2646                         return result;
2647
2648                 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
2649         }
2650
2651         if (unlikely(cmd_buffer->device->trace_bo)) {
2652                 struct radv_device *device = cmd_buffer->device;
2653
2654                 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2655                                    device->trace_bo);
2656
2657                 radv_cmd_buffer_trace_emit(cmd_buffer);
2658         }
2659
2660         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2661
2662         return result;
2663 }
2664
2665 void radv_CmdBindVertexBuffers(
2666         VkCommandBuffer                             commandBuffer,
2667         uint32_t                                    firstBinding,
2668         uint32_t                                    bindingCount,
2669         const VkBuffer*                             pBuffers,
2670         const VkDeviceSize*                         pOffsets)
2671 {
2672         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2673         struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2674         bool changed = false;
2675
2676         /* We have to defer setting up vertex buffer since we need the buffer
2677          * stride from the pipeline. */
2678
2679         assert(firstBinding + bindingCount <= MAX_VBS);
2680         for (uint32_t i = 0; i < bindingCount; i++) {
2681                 uint32_t idx = firstBinding + i;
2682
2683                 if (!changed &&
2684                     (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2685                      vb[idx].offset != pOffsets[i])) {
2686                         changed = true;
2687                 }
2688
2689                 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2690                 vb[idx].offset = pOffsets[i];
2691
2692                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2693                                    vb[idx].buffer->bo);
2694         }
2695
2696         if (!changed) {
2697                 /* No state changes. */
2698                 return;
2699         }
2700
2701         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2702 }
2703
2704 void radv_CmdBindIndexBuffer(
2705         VkCommandBuffer                             commandBuffer,
2706         VkBuffer buffer,
2707         VkDeviceSize offset,
2708         VkIndexType indexType)
2709 {
2710         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2711         RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2712
2713         if (cmd_buffer->state.index_buffer == index_buffer &&
2714             cmd_buffer->state.index_offset == offset &&
2715             cmd_buffer->state.index_type == indexType) {
2716                 /* No state changes. */
2717                 return;
2718         }
2719
2720         cmd_buffer->state.index_buffer = index_buffer;
2721         cmd_buffer->state.index_offset = offset;
2722         cmd_buffer->state.index_type = indexType; /* vk matches hw */
2723         cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2724         cmd_buffer->state.index_va += index_buffer->offset + offset;
2725
2726         int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2727         cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2728         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2729         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2730 }
2731
2732
2733 static void
2734 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2735                          VkPipelineBindPoint bind_point,
2736                          struct radv_descriptor_set *set, unsigned idx)
2737 {
2738         struct radeon_winsys *ws = cmd_buffer->device->ws;
2739
2740         radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2741
2742         assert(set);
2743         assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2744
2745         if (!cmd_buffer->device->use_global_bo_list) {
2746                 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2747                         if (set->descriptors[j])
2748                                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2749         }
2750
2751         if(set->bo)
2752                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2753 }
2754
2755 void radv_CmdBindDescriptorSets(
2756         VkCommandBuffer                             commandBuffer,
2757         VkPipelineBindPoint                         pipelineBindPoint,
2758         VkPipelineLayout                            _layout,
2759         uint32_t                                    firstSet,
2760         uint32_t                                    descriptorSetCount,
2761         const VkDescriptorSet*                      pDescriptorSets,
2762         uint32_t                                    dynamicOffsetCount,
2763         const uint32_t*                             pDynamicOffsets)
2764 {
2765         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2766         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2767         unsigned dyn_idx = 0;
2768
2769         const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2770         struct radv_descriptor_state *descriptors_state =
2771                 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2772
2773         for (unsigned i = 0; i < descriptorSetCount; ++i) {
2774                 unsigned idx = i + firstSet;
2775                 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2776                 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2777
2778                 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2779                         unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2780                         uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2781                         assert(dyn_idx < dynamicOffsetCount);
2782
2783                         struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2784                         uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2785                         dst[0] = va;
2786                         dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2787                         dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2788                         dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2789                                  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2790                                  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2791                                  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2792                                  S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2793                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2794                         cmd_buffer->push_constant_stages |=
2795                                              set->layout->dynamic_shader_stages;
2796                 }
2797         }
2798 }
2799
2800 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2801                                           struct radv_descriptor_set *set,
2802                                           struct radv_descriptor_set_layout *layout,
2803                                           VkPipelineBindPoint bind_point)
2804 {
2805         struct radv_descriptor_state *descriptors_state =
2806                 radv_get_descriptors_state(cmd_buffer, bind_point);
2807         set->size = layout->size;
2808         set->layout = layout;
2809
2810         if (descriptors_state->push_set.capacity < set->size) {
2811                 size_t new_size = MAX2(set->size, 1024);
2812                 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2813                 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2814
2815                 free(set->mapped_ptr);
2816                 set->mapped_ptr = malloc(new_size);
2817
2818                 if (!set->mapped_ptr) {
2819                         descriptors_state->push_set.capacity = 0;
2820                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2821                         return false;
2822                 }
2823
2824                 descriptors_state->push_set.capacity = new_size;
2825         }
2826
2827         return true;
2828 }
2829
2830 void radv_meta_push_descriptor_set(
2831         struct radv_cmd_buffer*              cmd_buffer,
2832         VkPipelineBindPoint                  pipelineBindPoint,
2833         VkPipelineLayout                     _layout,
2834         uint32_t                             set,
2835         uint32_t                             descriptorWriteCount,
2836         const VkWriteDescriptorSet*          pDescriptorWrites)
2837 {
2838         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2839         struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2840         unsigned bo_offset;
2841
2842         assert(set == 0);
2843         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2844
2845         push_set->size = layout->set[set].layout->size;
2846         push_set->layout = layout->set[set].layout;
2847
2848         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2849                                           &bo_offset,
2850                                           (void**) &push_set->mapped_ptr))
2851                 return;
2852
2853         push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2854         push_set->va += bo_offset;
2855
2856         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2857                                     radv_descriptor_set_to_handle(push_set),
2858                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2859
2860         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2861 }
2862
2863 void radv_CmdPushDescriptorSetKHR(
2864         VkCommandBuffer                             commandBuffer,
2865         VkPipelineBindPoint                         pipelineBindPoint,
2866         VkPipelineLayout                            _layout,
2867         uint32_t                                    set,
2868         uint32_t                                    descriptorWriteCount,
2869         const VkWriteDescriptorSet*                 pDescriptorWrites)
2870 {
2871         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2872         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2873         struct radv_descriptor_state *descriptors_state =
2874                 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2875         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2876
2877         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2878
2879         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2880                                            layout->set[set].layout,
2881                                            pipelineBindPoint))
2882                 return;
2883
2884         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2885                                     radv_descriptor_set_to_handle(push_set),
2886                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2887
2888         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2889         descriptors_state->push_dirty = true;
2890 }
2891
2892 void radv_CmdPushDescriptorSetWithTemplateKHR(
2893         VkCommandBuffer                             commandBuffer,
2894         VkDescriptorUpdateTemplate                  descriptorUpdateTemplate,
2895         VkPipelineLayout                            _layout,
2896         uint32_t                                    set,
2897         const void*                                 pData)
2898 {
2899         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2900         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2901         RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2902         struct radv_descriptor_state *descriptors_state =
2903                 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2904         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2905
2906         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2907
2908         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2909                                            layout->set[set].layout,
2910                                            templ->bind_point))
2911                 return;
2912
2913         radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2914                                                  descriptorUpdateTemplate, pData);
2915
2916         radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2917         descriptors_state->push_dirty = true;
2918 }
2919
2920 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2921                            VkPipelineLayout layout,
2922                            VkShaderStageFlags stageFlags,
2923                            uint32_t offset,
2924                            uint32_t size,
2925                            const void* pValues)
2926 {
2927         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2928         memcpy(cmd_buffer->push_constants + offset, pValues, size);
2929         cmd_buffer->push_constant_stages |= stageFlags;
2930 }
2931
2932 VkResult radv_EndCommandBuffer(
2933         VkCommandBuffer                             commandBuffer)
2934 {
2935         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2936
2937         if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2938                 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2939                         cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2940                 si_emit_cache_flush(cmd_buffer);
2941         }
2942
2943         /* Make sure CP DMA is idle at the end of IBs because the kernel
2944          * doesn't wait for it.
2945          */
2946         si_cp_dma_wait_for_idle(cmd_buffer);
2947
2948         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2949
2950         if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2951                 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2952
2953         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2954
2955         return cmd_buffer->record_result;
2956 }
2957
2958 static void
2959 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2960 {
2961         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2962
2963         if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2964                 return;
2965
2966         assert(!pipeline->ctx_cs.cdw);
2967
2968         cmd_buffer->state.emitted_compute_pipeline = pipeline;
2969
2970         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2971         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2972
2973         cmd_buffer->compute_scratch_size_needed =
2974                                   MAX2(cmd_buffer->compute_scratch_size_needed,
2975                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2976
2977         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2978                            pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2979
2980         if (unlikely(cmd_buffer->device->trace_bo))
2981                 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2982 }
2983
2984 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2985                                             VkPipelineBindPoint bind_point)
2986 {
2987         struct radv_descriptor_state *descriptors_state =
2988                 radv_get_descriptors_state(cmd_buffer, bind_point);
2989
2990         descriptors_state->dirty |= descriptors_state->valid;
2991 }
2992
2993 void radv_CmdBindPipeline(
2994         VkCommandBuffer                             commandBuffer,
2995         VkPipelineBindPoint                         pipelineBindPoint,
2996         VkPipeline                                  _pipeline)
2997 {
2998         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2999         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
3000
3001         switch (pipelineBindPoint) {
3002         case VK_PIPELINE_BIND_POINT_COMPUTE:
3003                 if (cmd_buffer->state.compute_pipeline == pipeline)
3004                         return;
3005                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3006
3007                 cmd_buffer->state.compute_pipeline = pipeline;
3008                 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
3009                 break;
3010         case VK_PIPELINE_BIND_POINT_GRAPHICS:
3011                 if (cmd_buffer->state.pipeline == pipeline)
3012                         return;
3013                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
3014
3015                 cmd_buffer->state.pipeline = pipeline;
3016                 if (!pipeline)
3017                         break;
3018
3019                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
3020                 cmd_buffer->push_constant_stages |= pipeline->active_stages;
3021
3022                 /* the new vertex shader might not have the same user regs */
3023                 cmd_buffer->state.last_first_instance = -1;
3024                 cmd_buffer->state.last_vertex_offset = -1;
3025
3026                 /* Prefetch all pipeline shaders at first draw time. */
3027                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
3028
3029                 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
3030                 radv_bind_streamout_state(cmd_buffer, pipeline);
3031
3032                 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
3033                         cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
3034                 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
3035                         cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3036
3037                 if (radv_pipeline_has_tess(pipeline))
3038                         cmd_buffer->tess_rings_needed = true;
3039                 break;
3040         default:
3041                 assert(!"invalid bind point");
3042                 break;
3043         }
3044 }
3045
3046 void radv_CmdSetViewport(
3047         VkCommandBuffer                             commandBuffer,
3048         uint32_t                                    firstViewport,
3049         uint32_t                                    viewportCount,
3050         const VkViewport*                           pViewports)
3051 {
3052         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3053         struct radv_cmd_state *state = &cmd_buffer->state;
3054         MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3055
3056         assert(firstViewport < MAX_VIEWPORTS);
3057         assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3058
3059         if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3060                     pViewports, viewportCount * sizeof(*pViewports))) {
3061                 return;
3062         }
3063
3064         memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3065                viewportCount * sizeof(*pViewports));
3066
3067         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3068 }
3069
3070 void radv_CmdSetScissor(
3071         VkCommandBuffer                             commandBuffer,
3072         uint32_t                                    firstScissor,
3073         uint32_t                                    scissorCount,
3074         const VkRect2D*                             pScissors)
3075 {
3076         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3077         struct radv_cmd_state *state = &cmd_buffer->state;
3078         MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3079
3080         assert(firstScissor < MAX_SCISSORS);
3081         assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3082
3083         if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3084                     scissorCount * sizeof(*pScissors))) {
3085                 return;
3086         }
3087
3088         memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3089                scissorCount * sizeof(*pScissors));
3090
3091         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3092 }
3093
3094 void radv_CmdSetLineWidth(
3095         VkCommandBuffer                             commandBuffer,
3096         float                                       lineWidth)
3097 {
3098         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3099
3100         if (cmd_buffer->state.dynamic.line_width == lineWidth)
3101                 return;
3102
3103         cmd_buffer->state.dynamic.line_width = lineWidth;
3104         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3105 }
3106
3107 void radv_CmdSetDepthBias(
3108         VkCommandBuffer                             commandBuffer,
3109         float                                       depthBiasConstantFactor,
3110         float                                       depthBiasClamp,
3111         float                                       depthBiasSlopeFactor)
3112 {
3113         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3114         struct radv_cmd_state *state = &cmd_buffer->state;
3115
3116         if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3117             state->dynamic.depth_bias.clamp == depthBiasClamp &&
3118             state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3119                 return;
3120         }
3121
3122         state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3123         state->dynamic.depth_bias.clamp = depthBiasClamp;
3124         state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3125
3126         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3127 }
3128
3129 void radv_CmdSetBlendConstants(
3130         VkCommandBuffer                             commandBuffer,
3131         const float                                 blendConstants[4])
3132 {
3133         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3134         struct radv_cmd_state *state = &cmd_buffer->state;
3135
3136         if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3137                 return;
3138
3139         memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3140
3141         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3142 }
3143
3144 void radv_CmdSetDepthBounds(
3145         VkCommandBuffer                             commandBuffer,
3146         float                                       minDepthBounds,
3147         float                                       maxDepthBounds)
3148 {
3149         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3150         struct radv_cmd_state *state = &cmd_buffer->state;
3151
3152         if (state->dynamic.depth_bounds.min == minDepthBounds &&
3153             state->dynamic.depth_bounds.max == maxDepthBounds) {
3154                 return;
3155         }
3156
3157         state->dynamic.depth_bounds.min = minDepthBounds;
3158         state->dynamic.depth_bounds.max = maxDepthBounds;
3159
3160         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3161 }
3162
3163 void radv_CmdSetStencilCompareMask(
3164         VkCommandBuffer                             commandBuffer,
3165         VkStencilFaceFlags                          faceMask,
3166         uint32_t                                    compareMask)
3167 {
3168         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3169         struct radv_cmd_state *state = &cmd_buffer->state;
3170         bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3171         bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3172
3173         if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3174             (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3175                 return;
3176         }
3177
3178         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3179                 state->dynamic.stencil_compare_mask.front = compareMask;
3180         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3181                 state->dynamic.stencil_compare_mask.back = compareMask;
3182
3183         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3184 }
3185
3186 void radv_CmdSetStencilWriteMask(
3187         VkCommandBuffer                             commandBuffer,
3188         VkStencilFaceFlags                          faceMask,
3189         uint32_t                                    writeMask)
3190 {
3191         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3192         struct radv_cmd_state *state = &cmd_buffer->state;
3193         bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3194         bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3195
3196         if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3197             (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3198                 return;
3199         }
3200
3201         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3202                 state->dynamic.stencil_write_mask.front = writeMask;
3203         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3204                 state->dynamic.stencil_write_mask.back = writeMask;
3205
3206         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3207 }
3208
3209 void radv_CmdSetStencilReference(
3210         VkCommandBuffer                             commandBuffer,
3211         VkStencilFaceFlags                          faceMask,
3212         uint32_t                                    reference)
3213 {
3214         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3215         struct radv_cmd_state *state = &cmd_buffer->state;
3216         bool front_same = state->dynamic.stencil_reference.front == reference;
3217         bool back_same = state->dynamic.stencil_reference.back == reference;
3218
3219         if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3220             (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3221                 return;
3222         }
3223
3224         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3225                 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3226         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3227                 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3228
3229         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3230 }
3231
3232 void radv_CmdSetDiscardRectangleEXT(
3233         VkCommandBuffer                             commandBuffer,
3234         uint32_t                                    firstDiscardRectangle,
3235         uint32_t                                    discardRectangleCount,
3236         const VkRect2D*                             pDiscardRectangles)
3237 {
3238         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3239         struct radv_cmd_state *state = &cmd_buffer->state;
3240         MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3241
3242         assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3243         assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3244
3245         if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3246                     pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3247                 return;
3248         }
3249
3250         typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3251                      pDiscardRectangles, discardRectangleCount);
3252
3253         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3254 }
3255
3256 void radv_CmdExecuteCommands(
3257         VkCommandBuffer                             commandBuffer,
3258         uint32_t                                    commandBufferCount,
3259         const VkCommandBuffer*                      pCmdBuffers)
3260 {
3261         RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3262
3263         assert(commandBufferCount > 0);
3264
3265         /* Emit pending flushes on primary prior to executing secondary */
3266         si_emit_cache_flush(primary);
3267
3268         for (uint32_t i = 0; i < commandBufferCount; i++) {
3269                 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3270
3271                 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3272                                                     secondary->scratch_size_needed);
3273                 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3274                                                             secondary->compute_scratch_size_needed);
3275
3276                 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3277                         primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3278                 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3279                         primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3280                 if (secondary->tess_rings_needed)
3281                         primary->tess_rings_needed = true;
3282                 if (secondary->sample_positions_needed)
3283                         primary->sample_positions_needed = true;
3284
3285                 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3286
3287
3288                 /* When the secondary command buffer is compute only we don't
3289                  * need to re-emit the current graphics pipeline.
3290                  */
3291                 if (secondary->state.emitted_pipeline) {
3292                         primary->state.emitted_pipeline =
3293                                 secondary->state.emitted_pipeline;
3294                 }
3295
3296                 /* When the secondary command buffer is graphics only we don't
3297                  * need to re-emit the current compute pipeline.
3298                  */
3299                 if (secondary->state.emitted_compute_pipeline) {
3300                         primary->state.emitted_compute_pipeline =
3301                                 secondary->state.emitted_compute_pipeline;
3302                 }
3303
3304                 /* Only re-emit the draw packets when needed. */
3305                 if (secondary->state.last_primitive_reset_en != -1) {
3306                         primary->state.last_primitive_reset_en =
3307                                 secondary->state.last_primitive_reset_en;
3308                 }
3309
3310                 if (secondary->state.last_primitive_reset_index) {
3311                         primary->state.last_primitive_reset_index =
3312                                 secondary->state.last_primitive_reset_index;
3313                 }
3314
3315                 if (secondary->state.last_ia_multi_vgt_param) {
3316                         primary->state.last_ia_multi_vgt_param =
3317                                 secondary->state.last_ia_multi_vgt_param;
3318                 }
3319
3320                 primary->state.last_first_instance = secondary->state.last_first_instance;
3321                 primary->state.last_num_instances = secondary->state.last_num_instances;
3322                 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3323
3324                 if (secondary->state.last_index_type != -1) {
3325                         primary->state.last_index_type =
3326                                 secondary->state.last_index_type;
3327                 }
3328         }
3329
3330         /* After executing commands from secondary buffers we have to dirty
3331          * some states.
3332          */
3333         primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3334                                 RADV_CMD_DIRTY_INDEX_BUFFER |
3335                                 RADV_CMD_DIRTY_DYNAMIC_ALL;
3336         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3337         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3338 }
3339
3340 VkResult radv_CreateCommandPool(
3341         VkDevice                                    _device,
3342         const VkCommandPoolCreateInfo*              pCreateInfo,
3343         const VkAllocationCallbacks*                pAllocator,
3344         VkCommandPool*                              pCmdPool)
3345 {
3346         RADV_FROM_HANDLE(radv_device, device, _device);
3347         struct radv_cmd_pool *pool;
3348
3349         pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3350                            VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3351         if (pool == NULL)
3352                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3353
3354         if (pAllocator)
3355                 pool->alloc = *pAllocator;
3356         else
3357                 pool->alloc = device->alloc;
3358
3359         list_inithead(&pool->cmd_buffers);
3360         list_inithead(&pool->free_cmd_buffers);
3361
3362         pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3363
3364         *pCmdPool = radv_cmd_pool_to_handle(pool);
3365
3366         return VK_SUCCESS;
3367
3368 }
3369
3370 void radv_DestroyCommandPool(
3371         VkDevice                                    _device,
3372         VkCommandPool                               commandPool,
3373         const VkAllocationCallbacks*                pAllocator)
3374 {
3375         RADV_FROM_HANDLE(radv_device, device, _device);
3376         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3377
3378         if (!pool)
3379                 return;
3380
3381         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3382                                  &pool->cmd_buffers, pool_link) {
3383                 radv_cmd_buffer_destroy(cmd_buffer);
3384         }
3385
3386         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3387                                  &pool->free_cmd_buffers, pool_link) {
3388                 radv_cmd_buffer_destroy(cmd_buffer);
3389         }
3390
3391         vk_free2(&device->alloc, pAllocator, pool);
3392 }
3393
3394 VkResult radv_ResetCommandPool(
3395         VkDevice                                    device,
3396         VkCommandPool                               commandPool,
3397         VkCommandPoolResetFlags                     flags)
3398 {
3399         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3400         VkResult result;
3401
3402         list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3403                             &pool->cmd_buffers, pool_link) {
3404                 result = radv_reset_cmd_buffer(cmd_buffer);
3405                 if (result != VK_SUCCESS)
3406                         return result;
3407         }
3408
3409         return VK_SUCCESS;
3410 }
3411
3412 void radv_TrimCommandPool(
3413     VkDevice                                    device,
3414     VkCommandPool                               commandPool,
3415     VkCommandPoolTrimFlags                      flags)
3416 {
3417         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3418
3419         if (!pool)
3420                 return;
3421
3422         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3423                                  &pool->free_cmd_buffers, pool_link) {
3424                 radv_cmd_buffer_destroy(cmd_buffer);
3425         }
3426 }
3427
3428 static uint32_t
3429 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3430 {
3431         struct radv_cmd_state *state = &cmd_buffer->state;
3432         uint32_t subpass_id = state->subpass - state->pass->subpasses;
3433
3434         /* The id of this subpass shouldn't exceed the number of subpasses in
3435          * this render pass minus 1.
3436          */
3437         assert(subpass_id < state->pass->subpass_count);
3438         return subpass_id;
3439 }
3440
3441 static void
3442 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3443                               uint32_t subpass_id)
3444 {
3445         struct radv_cmd_state *state = &cmd_buffer->state;
3446         struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3447
3448         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3449                                                            cmd_buffer->cs, 4096);
3450
3451         radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3452
3453         for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3454                 const uint32_t a = subpass->attachments[i].attachment;
3455                 if (a == VK_ATTACHMENT_UNUSED)
3456                         continue;
3457
3458                 radv_handle_subpass_image_transition(cmd_buffer,
3459                                                      subpass->attachments[i]);
3460         }
3461
3462         radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3463         radv_cmd_buffer_clear_subpass(cmd_buffer);
3464
3465         assert(cmd_buffer->cs->cdw <= cdw_max);
3466 }
3467
3468 static void
3469 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)
3470 {
3471         struct radv_cmd_state *state = &cmd_buffer->state;
3472         const struct radv_subpass *subpass = state->subpass;
3473         uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);
3474
3475         radv_cmd_buffer_resolve_subpass(cmd_buffer);
3476
3477         for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3478                 const uint32_t a = subpass->attachments[i].attachment;
3479                 if (a == VK_ATTACHMENT_UNUSED)
3480                         continue;
3481
3482                 if (state->pass->attachments[a].last_subpass_idx != subpass_id)
3483                         continue;
3484
3485                 VkImageLayout layout = state->pass->attachments[a].final_layout;
3486                 radv_handle_subpass_image_transition(cmd_buffer,
3487                                       (struct radv_subpass_attachment){a, layout});
3488         }
3489 }
3490
3491 void radv_CmdBeginRenderPass(
3492         VkCommandBuffer                             commandBuffer,
3493         const VkRenderPassBeginInfo*                pRenderPassBegin,
3494         VkSubpassContents                           contents)
3495 {
3496         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3497         RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3498         RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3499         VkResult result;
3500
3501         cmd_buffer->state.framebuffer = framebuffer;
3502         cmd_buffer->state.pass = pass;
3503         cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3504
3505         result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3506         if (result != VK_SUCCESS)
3507                 return;
3508
3509         radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
3510 }
3511
3512 void radv_CmdBeginRenderPass2KHR(
3513     VkCommandBuffer                             commandBuffer,
3514     const VkRenderPassBeginInfo*                pRenderPassBeginInfo,
3515     const VkSubpassBeginInfoKHR*                pSubpassBeginInfo)
3516 {
3517         radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3518                                 pSubpassBeginInfo->contents);
3519 }
3520
3521 void radv_CmdNextSubpass(
3522     VkCommandBuffer                             commandBuffer,
3523     VkSubpassContents                           contents)
3524 {
3525         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3526
3527         uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
3528         radv_cmd_buffer_end_subpass(cmd_buffer);
3529         radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
3530 }
3531
3532 void radv_CmdNextSubpass2KHR(
3533     VkCommandBuffer                             commandBuffer,
3534     const VkSubpassBeginInfoKHR*                pSubpassBeginInfo,
3535     const VkSubpassEndInfoKHR*                  pSubpassEndInfo)
3536 {
3537         radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3538 }
3539
3540 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3541 {
3542         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3543         for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3544                 if (!radv_get_shader(pipeline, stage))
3545                         continue;
3546
3547                 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3548                 if (loc->sgpr_idx == -1)
3549                         continue;
3550                 uint32_t base_reg = pipeline->user_data_0[stage];
3551                 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3552
3553         }
3554         if (pipeline->gs_copy_shader) {
3555                 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3556                 if (loc->sgpr_idx != -1) {
3557                         uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3558                         radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3559                 }
3560         }
3561 }
3562
3563 static void
3564 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3565                          uint32_t vertex_count,
3566                          bool use_opaque)
3567 {
3568         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3569         radeon_emit(cmd_buffer->cs, vertex_count);
3570         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3571                                     S_0287F0_USE_OPAQUE(use_opaque));
3572 }
3573
3574 static void
3575 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3576                                  uint64_t index_va,
3577                                  uint32_t index_count)
3578 {
3579         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3580         radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3581         radeon_emit(cmd_buffer->cs, index_va);
3582         radeon_emit(cmd_buffer->cs, index_va >> 32);
3583         radeon_emit(cmd_buffer->cs, index_count);
3584         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3585 }
3586
3587 static void
3588 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3589                                   bool indexed,
3590                                   uint32_t draw_count,
3591                                   uint64_t count_va,
3592                                   uint32_t stride)
3593 {
3594         struct radeon_cmdbuf *cs = cmd_buffer->cs;
3595         unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3596                                       : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3597         bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3598         uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3599         bool predicating = cmd_buffer->state.predicating;
3600         assert(base_reg);
3601
3602         /* just reset draw state for vertex data */
3603         cmd_buffer->state.last_first_instance = -1;
3604         cmd_buffer->state.last_num_instances = -1;
3605         cmd_buffer->state.last_vertex_offset = -1;
3606
3607         if (draw_count == 1 && !count_va && !draw_id_enable) {
3608                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3609                                      PKT3_DRAW_INDIRECT, 3, predicating));
3610                 radeon_emit(cs, 0);
3611                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3612                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3613                 radeon_emit(cs, di_src_sel);
3614         } else {
3615                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3616                                      PKT3_DRAW_INDIRECT_MULTI,
3617                                      8, predicating));
3618                 radeon_emit(cs, 0);
3619                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3620                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3621                 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3622                             S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3623                             S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3624                 radeon_emit(cs, draw_count); /* count */
3625                 radeon_emit(cs, count_va); /* count_addr */
3626                 radeon_emit(cs, count_va >> 32);
3627                 radeon_emit(cs, stride); /* stride */
3628                 radeon_emit(cs, di_src_sel);
3629         }
3630 }
3631
3632 static void
3633 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3634                        const struct radv_draw_info *info)
3635 {
3636         struct radv_cmd_state *state = &cmd_buffer->state;
3637         struct radeon_winsys *ws = cmd_buffer->device->ws;
3638         struct radeon_cmdbuf *cs = cmd_buffer->cs;
3639
3640         if (info->indirect) {
3641                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3642                 uint64_t count_va = 0;
3643
3644                 va += info->indirect->offset + info->indirect_offset;
3645
3646                 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3647
3648                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3649                 radeon_emit(cs, 1);
3650                 radeon_emit(cs, va);
3651                 radeon_emit(cs, va >> 32);
3652
3653                 if (info->count_buffer) {
3654                         count_va = radv_buffer_get_va(info->count_buffer->bo);
3655                         count_va += info->count_buffer->offset +
3656                                     info->count_buffer_offset;
3657
3658                         radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3659                 }
3660
3661                 if (!state->subpass->view_mask) {
3662                         radv_cs_emit_indirect_draw_packet(cmd_buffer,
3663                                                           info->indexed,
3664                                                           info->count,
3665                                                           count_va,
3666                                                           info->stride);
3667                 } else {
3668                         unsigned i;
3669                         for_each_bit(i, state->subpass->view_mask) {
3670                                 radv_emit_view_index(cmd_buffer, i);
3671
3672                                 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3673                                                                   info->indexed,
3674                                                                   info->count,
3675                                                                   count_va,
3676                                                                   info->stride);
3677                         }
3678                 }
3679         } else {
3680                 assert(state->pipeline->graphics.vtx_base_sgpr);
3681
3682                 if (info->vertex_offset != state->last_vertex_offset ||
3683                     info->first_instance != state->last_first_instance) {
3684                         radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3685                                               state->pipeline->graphics.vtx_emit_num);
3686
3687                         radeon_emit(cs, info->vertex_offset);
3688                         radeon_emit(cs, info->first_instance);
3689                         if (state->pipeline->graphics.vtx_emit_num == 3)
3690                                 radeon_emit(cs, 0);
3691                         state->last_first_instance = info->first_instance;
3692                         state->last_vertex_offset = info->vertex_offset;
3693                 }
3694
3695                 if (state->last_num_instances != info->instance_count) {
3696                         radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3697                         radeon_emit(cs, info->instance_count);
3698                         state->last_num_instances = info->instance_count;
3699                 }
3700
3701                 if (info->indexed) {
3702                         int index_size = state->index_type ? 4 : 2;
3703                         uint64_t index_va;
3704
3705                         index_va = state->index_va;
3706                         index_va += info->first_index * index_size;
3707
3708                         if (!state->subpass->view_mask) {
3709                                 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3710                                                                  index_va,
3711                                                                  info->count);
3712                         } else {
3713                                 unsigned i;
3714                                 for_each_bit(i, state->subpass->view_mask) {
3715                                         radv_emit_view_index(cmd_buffer, i);
3716
3717                                         radv_cs_emit_draw_indexed_packet(cmd_buffer,
3718                                                                          index_va,
3719                                                                          info->count);
3720                                 }
3721                         }
3722                 } else {
3723                         if (!state->subpass->view_mask) {
3724                                 radv_cs_emit_draw_packet(cmd_buffer,
3725                                                          info->count,
3726                                                          !!info->strmout_buffer);
3727                         } else {
3728                                 unsigned i;
3729                                 for_each_bit(i, state->subpass->view_mask) {
3730                                         radv_emit_view_index(cmd_buffer, i);
3731
3732                                         radv_cs_emit_draw_packet(cmd_buffer,
3733                                                                  info->count,
3734                                                                  !!info->strmout_buffer);
3735                                 }
3736                         }
3737                 }
3738         }
3739 }
3740
3741 /*
3742  * Vega and raven have a bug which triggers if there are multiple context
3743  * register contexts active at the same time with different scissor values.
3744  *
3745  * There are two possible workarounds:
3746  * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3747  *    there is only ever 1 active set of scissor values at the same time.
3748  *
3749  * 2) Whenever the hardware switches contexts we have to set the scissor
3750  *    registers again even if it is a noop. That way the new context gets
3751  *    the correct scissor values.
3752  *
3753  * This implements option 2. radv_need_late_scissor_emission needs to
3754  * return true on affected HW if radv_emit_all_graphics_states sets
3755  * any context registers.
3756  */
3757 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3758                                             const struct radv_draw_info *info)
3759 {
3760         struct radv_cmd_state *state = &cmd_buffer->state;
3761
3762         if (!cmd_buffer->device->physical_device->has_scissor_bug)
3763                 return false;
3764
3765         if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
3766                 return true;
3767
3768         uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3769
3770         /* Index, vertex and streamout buffers don't change context regs, and
3771          * pipeline is already handled.
3772          */
3773         used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3774                          RADV_CMD_DIRTY_VERTEX_BUFFER |
3775                          RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3776                          RADV_CMD_DIRTY_PIPELINE);
3777
3778         if (cmd_buffer->state.dirty & used_states)
3779                 return true;
3780
3781         if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
3782             (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3783                 return true;
3784
3785         return false;
3786 }
3787
3788 static void
3789 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3790                               const struct radv_draw_info *info)
3791 {
3792         bool late_scissor_emission;
3793
3794         if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3795             cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3796                 radv_emit_rbplus_state(cmd_buffer);
3797
3798         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3799                 radv_emit_graphics_pipeline(cmd_buffer);
3800
3801         /* This should be before the cmd_buffer->state.dirty is cleared
3802          * (excluding RADV_CMD_DIRTY_PIPELINE) and after
3803          * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
3804         late_scissor_emission =
3805                 radv_need_late_scissor_emission(cmd_buffer, info);
3806
3807         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3808                 radv_emit_framebuffer_state(cmd_buffer);
3809
3810         if (info->indexed) {
3811                 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3812                         radv_emit_index_buffer(cmd_buffer);
3813         } else {
3814                 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3815                  * so the state must be re-emitted before the next indexed
3816                  * draw.
3817                  */
3818                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3819                         cmd_buffer->state.last_index_type = -1;
3820                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3821                 }
3822         }
3823
3824         radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3825
3826         radv_emit_draw_registers(cmd_buffer, info);
3827
3828         if (late_scissor_emission)
3829                 radv_emit_scissor(cmd_buffer);
3830 }
3831
3832 static void
3833 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3834           const struct radv_draw_info *info)
3835 {
3836         struct radeon_info *rad_info =
3837                 &cmd_buffer->device->physical_device->rad_info;
3838         bool has_prefetch =
3839                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3840         bool pipeline_is_dirty =
3841                 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3842                 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3843
3844         MAYBE_UNUSED unsigned cdw_max =
3845                 radeon_check_space(cmd_buffer->device->ws,
3846                                    cmd_buffer->cs, 4096);
3847
3848         if (likely(!info->indirect)) {
3849                 /* SI-CI treat instance_count==0 as instance_count==1. There is
3850                  * no workaround for indirect draws, but we can at least skip
3851                  * direct draws.
3852                  */
3853                 if (unlikely(!info->instance_count))
3854                         return;
3855
3856                 /* Handle count == 0. */
3857                 if (unlikely(!info->count && !info->strmout_buffer))
3858                         return;
3859         }
3860
3861         /* Use optimal packet order based on whether we need to sync the
3862          * pipeline.
3863          */
3864         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3865                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3866                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3867                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3868                 /* If we have to wait for idle, set all states first, so that
3869                  * all SET packets are processed in parallel with previous draw
3870                  * calls. Then upload descriptors, set shader pointers, and
3871                  * draw, and prefetch at the end. This ensures that the time
3872                  * the CUs are idle is very short. (there are only SET_SH
3873                  * packets between the wait and the draw)
3874                  */
3875                 radv_emit_all_graphics_states(cmd_buffer, info);
3876                 si_emit_cache_flush(cmd_buffer);
3877                 /* <-- CUs are idle here --> */
3878
3879                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3880
3881                 radv_emit_draw_packets(cmd_buffer, info);
3882                 /* <-- CUs are busy here --> */
3883
3884                 /* Start prefetches after the draw has been started. Both will
3885                  * run in parallel, but starting the draw first is more
3886                  * important.
3887                  */
3888                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3889                         radv_emit_prefetch_L2(cmd_buffer,
3890                                               cmd_buffer->state.pipeline, false);
3891                 }
3892         } else {
3893                 /* If we don't wait for idle, start prefetches first, then set
3894                  * states, and draw at the end.
3895                  */
3896                 si_emit_cache_flush(cmd_buffer);
3897
3898                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3899                         /* Only prefetch the vertex shader and VBO descriptors
3900                          * in order to start the draw as soon as possible.
3901                          */
3902                         radv_emit_prefetch_L2(cmd_buffer,
3903                                               cmd_buffer->state.pipeline, true);
3904                 }
3905
3906                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3907
3908                 radv_emit_all_graphics_states(cmd_buffer, info);
3909                 radv_emit_draw_packets(cmd_buffer, info);
3910
3911                 /* Prefetch the remaining shaders after the draw has been
3912                  * started.
3913                  */
3914                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3915                         radv_emit_prefetch_L2(cmd_buffer,
3916                                               cmd_buffer->state.pipeline, false);
3917                 }
3918         }
3919
3920         /* Workaround for a VGT hang when streamout is enabled.
3921          * It must be done after drawing.
3922          */
3923         if (cmd_buffer->state.streamout.streamout_enabled &&
3924             (rad_info->family == CHIP_HAWAII ||
3925              rad_info->family == CHIP_TONGA ||
3926              rad_info->family == CHIP_FIJI)) {
3927                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3928         }
3929
3930         assert(cmd_buffer->cs->cdw <= cdw_max);
3931         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3932 }
3933
3934 void radv_CmdDraw(
3935         VkCommandBuffer                             commandBuffer,
3936         uint32_t                                    vertexCount,
3937         uint32_t                                    instanceCount,
3938         uint32_t                                    firstVertex,
3939         uint32_t                                    firstInstance)
3940 {
3941         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3942         struct radv_draw_info info = {};
3943
3944         info.count = vertexCount;
3945         info.instance_count = instanceCount;
3946         info.first_instance = firstInstance;
3947         info.vertex_offset = firstVertex;
3948
3949         radv_draw(cmd_buffer, &info);
3950 }
3951
3952 void radv_CmdDrawIndexed(
3953         VkCommandBuffer                             commandBuffer,
3954         uint32_t                                    indexCount,
3955         uint32_t                                    instanceCount,
3956         uint32_t                                    firstIndex,
3957         int32_t                                     vertexOffset,
3958         uint32_t                                    firstInstance)
3959 {
3960         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3961         struct radv_draw_info info = {};
3962
3963         info.indexed = true;
3964         info.count = indexCount;
3965         info.instance_count = instanceCount;
3966         info.first_index = firstIndex;
3967         info.vertex_offset = vertexOffset;
3968         info.first_instance = firstInstance;
3969
3970         radv_draw(cmd_buffer, &info);
3971 }
3972
3973 void radv_CmdDrawIndirect(
3974         VkCommandBuffer                             commandBuffer,
3975         VkBuffer                                    _buffer,
3976         VkDeviceSize                                offset,
3977         uint32_t                                    drawCount,
3978         uint32_t                                    stride)
3979 {
3980         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3981         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3982         struct radv_draw_info info = {};
3983
3984         info.count = drawCount;
3985         info.indirect = buffer;
3986         info.indirect_offset = offset;
3987         info.stride = stride;
3988
3989         radv_draw(cmd_buffer, &info);
3990 }
3991
3992 void radv_CmdDrawIndexedIndirect(
3993         VkCommandBuffer                             commandBuffer,
3994         VkBuffer                                    _buffer,
3995         VkDeviceSize                                offset,
3996         uint32_t                                    drawCount,
3997         uint32_t                                    stride)
3998 {
3999         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4000         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4001         struct radv_draw_info info = {};
4002
4003         info.indexed = true;
4004         info.count = drawCount;
4005         info.indirect = buffer;
4006         info.indirect_offset = offset;
4007         info.stride = stride;
4008
4009         radv_draw(cmd_buffer, &info);
4010 }
4011
4012 void radv_CmdDrawIndirectCountAMD(
4013         VkCommandBuffer                             commandBuffer,
4014         VkBuffer                                    _buffer,
4015         VkDeviceSize                                offset,
4016         VkBuffer                                    _countBuffer,
4017         VkDeviceSize                                countBufferOffset,
4018         uint32_t                                    maxDrawCount,
4019         uint32_t                                    stride)
4020 {
4021         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4022         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4023         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4024         struct radv_draw_info info = {};
4025
4026         info.count = maxDrawCount;
4027         info.indirect = buffer;
4028         info.indirect_offset = offset;
4029         info.count_buffer = count_buffer;
4030         info.count_buffer_offset = countBufferOffset;
4031         info.stride = stride;
4032
4033         radv_draw(cmd_buffer, &info);
4034 }
4035
4036 void radv_CmdDrawIndexedIndirectCountAMD(
4037         VkCommandBuffer                             commandBuffer,
4038         VkBuffer                                    _buffer,
4039         VkDeviceSize                                offset,
4040         VkBuffer                                    _countBuffer,
4041         VkDeviceSize                                countBufferOffset,
4042         uint32_t                                    maxDrawCount,
4043         uint32_t                                    stride)
4044 {
4045         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4046         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4047         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4048         struct radv_draw_info info = {};
4049
4050         info.indexed = true;
4051         info.count = maxDrawCount;
4052         info.indirect = buffer;
4053         info.indirect_offset = offset;
4054         info.count_buffer = count_buffer;
4055         info.count_buffer_offset = countBufferOffset;
4056         info.stride = stride;
4057
4058         radv_draw(cmd_buffer, &info);
4059 }
4060
4061 void radv_CmdDrawIndirectCountKHR(
4062         VkCommandBuffer                             commandBuffer,
4063         VkBuffer                                    _buffer,
4064         VkDeviceSize                                offset,
4065         VkBuffer                                    _countBuffer,
4066         VkDeviceSize                                countBufferOffset,
4067         uint32_t                                    maxDrawCount,
4068         uint32_t                                    stride)
4069 {
4070         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4071         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4072         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4073         struct radv_draw_info info = {};
4074
4075         info.count = maxDrawCount;
4076         info.indirect = buffer;
4077         info.indirect_offset = offset;
4078         info.count_buffer = count_buffer;
4079         info.count_buffer_offset = countBufferOffset;
4080         info.stride = stride;
4081
4082         radv_draw(cmd_buffer, &info);
4083 }
4084
4085 void radv_CmdDrawIndexedIndirectCountKHR(
4086         VkCommandBuffer                             commandBuffer,
4087         VkBuffer                                    _buffer,
4088         VkDeviceSize                                offset,
4089         VkBuffer                                    _countBuffer,
4090         VkDeviceSize                                countBufferOffset,
4091         uint32_t                                    maxDrawCount,
4092         uint32_t                                    stride)
4093 {
4094         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4095         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4096         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4097         struct radv_draw_info info = {};
4098
4099         info.indexed = true;
4100         info.count = maxDrawCount;
4101         info.indirect = buffer;
4102         info.indirect_offset = offset;
4103         info.count_buffer = count_buffer;
4104         info.count_buffer_offset = countBufferOffset;
4105         info.stride = stride;
4106
4107         radv_draw(cmd_buffer, &info);
4108 }
4109
4110 struct radv_dispatch_info {
4111         /**
4112          * Determine the layout of the grid (in block units) to be used.
4113          */
4114         uint32_t blocks[3];
4115
4116         /**
4117          * A starting offset for the grid. If unaligned is set, the offset
4118          * must still be aligned.
4119          */
4120         uint32_t offsets[3];
4121         /**
4122          * Whether it's an unaligned compute dispatch.
4123          */
4124         bool unaligned;
4125
4126         /**
4127          * Indirect compute parameters resource.
4128          */
4129         struct radv_buffer *indirect;
4130         uint64_t indirect_offset;
4131 };
4132
4133 static void
4134 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4135                            const struct radv_dispatch_info *info)
4136 {
4137         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4138         struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4139         unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4140         struct radeon_winsys *ws = cmd_buffer->device->ws;
4141         bool predicating = cmd_buffer->state.predicating;
4142         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4143         struct radv_userdata_info *loc;
4144
4145         loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4146                                     AC_UD_CS_GRID_SIZE);
4147
4148         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4149
4150         if (info->indirect) {
4151                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4152
4153                 va += info->indirect->offset + info->indirect_offset;
4154
4155                 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4156
4157                 if (loc->sgpr_idx != -1) {
4158                         for (unsigned i = 0; i < 3; ++i) {
4159                                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4160                                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4161                                                 COPY_DATA_DST_SEL(COPY_DATA_REG));
4162                                 radeon_emit(cs, (va +  4 * i));
4163                                 radeon_emit(cs, (va + 4 * i) >> 32);
4164                                 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4165                                                  + loc->sgpr_idx * 4) >> 2) + i);
4166                                 radeon_emit(cs, 0);
4167                         }
4168                 }
4169
4170                 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4171                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4172                                         PKT3_SHADER_TYPE_S(1));
4173                         radeon_emit(cs, va);
4174                         radeon_emit(cs, va >> 32);
4175                         radeon_emit(cs, dispatch_initiator);
4176                 } else {
4177                         radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4178                                         PKT3_SHADER_TYPE_S(1));
4179                         radeon_emit(cs, 1);
4180                         radeon_emit(cs, va);
4181                         radeon_emit(cs, va >> 32);
4182
4183                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4184                                         PKT3_SHADER_TYPE_S(1));
4185                         radeon_emit(cs, 0);
4186                         radeon_emit(cs, dispatch_initiator);
4187                 }
4188         } else {
4189                 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4190                 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4191
4192                 if (info->unaligned) {
4193                         unsigned *cs_block_size = compute_shader->info.cs.block_size;
4194                         unsigned remainder[3];
4195
4196                         /* If aligned, these should be an entire block size,
4197                          * not 0.
4198                          */
4199                         remainder[0] = blocks[0] + cs_block_size[0] -
4200                                        align_u32_npot(blocks[0], cs_block_size[0]);
4201                         remainder[1] = blocks[1] + cs_block_size[1] -
4202                                        align_u32_npot(blocks[1], cs_block_size[1]);
4203                         remainder[2] = blocks[2] + cs_block_size[2] -
4204                                        align_u32_npot(blocks[2], cs_block_size[2]);
4205
4206                         blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4207                         blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4208                         blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4209
4210                         for(unsigned i = 0; i < 3; ++i) {
4211                                 assert(offsets[i] % cs_block_size[i] == 0);
4212                                 offsets[i] /= cs_block_size[i];
4213                         }
4214
4215                         radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4216                         radeon_emit(cs,
4217                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4218                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4219                         radeon_emit(cs,
4220                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4221                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4222                         radeon_emit(cs,
4223                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4224                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4225
4226                         dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4227                 }
4228
4229                 if (loc->sgpr_idx != -1) {
4230                         assert(loc->num_sgprs == 3);
4231
4232                         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4233                                                   loc->sgpr_idx * 4, 3);
4234                         radeon_emit(cs, blocks[0]);
4235                         radeon_emit(cs, blocks[1]);
4236                         radeon_emit(cs, blocks[2]);
4237                 }
4238
4239                 if (offsets[0] || offsets[1] || offsets[2]) {
4240                         radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4241                         radeon_emit(cs, offsets[0]);
4242                         radeon_emit(cs, offsets[1]);
4243                         radeon_emit(cs, offsets[2]);
4244
4245                         /* The blocks in the packet are not counts but end values. */
4246                         for (unsigned i = 0; i < 3; ++i)
4247                                 blocks[i] += offsets[i];
4248                 } else {
4249                         dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4250                 }
4251
4252                 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4253                                 PKT3_SHADER_TYPE_S(1));
4254                 radeon_emit(cs, blocks[0]);
4255                 radeon_emit(cs, blocks[1]);
4256                 radeon_emit(cs, blocks[2]);
4257                 radeon_emit(cs, dispatch_initiator);
4258         }
4259
4260         assert(cmd_buffer->cs->cdw <= cdw_max);
4261 }
4262
4263 static void
4264 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4265 {
4266         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4267         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4268 }
4269
4270 static void
4271 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4272               const struct radv_dispatch_info *info)
4273 {
4274         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4275         bool has_prefetch =
4276                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4277         bool pipeline_is_dirty = pipeline &&
4278                                  pipeline != cmd_buffer->state.emitted_compute_pipeline;
4279
4280         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4281                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4282                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4283                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4284                 /* If we have to wait for idle, set all states first, so that
4285                  * all SET packets are processed in parallel with previous draw
4286                  * calls. Then upload descriptors, set shader pointers, and
4287                  * dispatch, and prefetch at the end. This ensures that the
4288                  * time the CUs are idle is very short. (there are only SET_SH
4289                  * packets between the wait and the draw)
4290                  */
4291                 radv_emit_compute_pipeline(cmd_buffer);
4292                 si_emit_cache_flush(cmd_buffer);
4293                 /* <-- CUs are idle here --> */
4294
4295                 radv_upload_compute_shader_descriptors(cmd_buffer);
4296
4297                 radv_emit_dispatch_packets(cmd_buffer, info);
4298                 /* <-- CUs are busy here --> */
4299
4300                 /* Start prefetches after the dispatch has been started. Both
4301                  * will run in parallel, but starting the dispatch first is
4302                  * more important.
4303                  */
4304                 if (has_prefetch && pipeline_is_dirty) {
4305                         radv_emit_shader_prefetch(cmd_buffer,
4306                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
4307                 }
4308         } else {
4309                 /* If we don't wait for idle, start prefetches first, then set
4310                  * states, and dispatch at the end.
4311                  */
4312                 si_emit_cache_flush(cmd_buffer);
4313
4314                 if (has_prefetch && pipeline_is_dirty) {
4315                         radv_emit_shader_prefetch(cmd_buffer,
4316                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
4317                 }
4318
4319                 radv_upload_compute_shader_descriptors(cmd_buffer);
4320
4321                 radv_emit_compute_pipeline(cmd_buffer);
4322                 radv_emit_dispatch_packets(cmd_buffer, info);
4323         }
4324
4325         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4326 }
4327
4328 void radv_CmdDispatchBase(
4329         VkCommandBuffer                             commandBuffer,
4330         uint32_t                                    base_x,
4331         uint32_t                                    base_y,
4332         uint32_t                                    base_z,
4333         uint32_t                                    x,
4334         uint32_t                                    y,
4335         uint32_t                                    z)
4336 {
4337         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4338         struct radv_dispatch_info info = {};
4339
4340         info.blocks[0] = x;
4341         info.blocks[1] = y;
4342         info.blocks[2] = z;
4343
4344         info.offsets[0] = base_x;
4345         info.offsets[1] = base_y;
4346         info.offsets[2] = base_z;
4347         radv_dispatch(cmd_buffer, &info);
4348 }
4349
4350 void radv_CmdDispatch(
4351         VkCommandBuffer                             commandBuffer,
4352         uint32_t                                    x,
4353         uint32_t                                    y,
4354         uint32_t                                    z)
4355 {
4356         radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4357 }
4358
4359 void radv_CmdDispatchIndirect(
4360         VkCommandBuffer                             commandBuffer,
4361         VkBuffer                                    _buffer,
4362         VkDeviceSize                                offset)
4363 {
4364         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4365         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4366         struct radv_dispatch_info info = {};
4367
4368         info.indirect = buffer;
4369         info.indirect_offset = offset;
4370
4371         radv_dispatch(cmd_buffer, &info);
4372 }
4373
4374 void radv_unaligned_dispatch(
4375         struct radv_cmd_buffer                      *cmd_buffer,
4376         uint32_t                                    x,
4377         uint32_t                                    y,
4378         uint32_t                                    z)
4379 {
4380         struct radv_dispatch_info info = {};
4381
4382         info.blocks[0] = x;
4383         info.blocks[1] = y;
4384         info.blocks[2] = z;
4385         info.unaligned = 1;
4386
4387         radv_dispatch(cmd_buffer, &info);
4388 }
4389
4390 void radv_CmdEndRenderPass(
4391         VkCommandBuffer                             commandBuffer)
4392 {
4393         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4394
4395         radv_cmd_buffer_end_subpass(cmd_buffer);
4396
4397         radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4398
4399         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4400
4401         cmd_buffer->state.pass = NULL;
4402         cmd_buffer->state.subpass = NULL;
4403         cmd_buffer->state.attachments = NULL;
4404         cmd_buffer->state.framebuffer = NULL;
4405 }
4406
4407 void radv_CmdEndRenderPass2KHR(
4408     VkCommandBuffer                             commandBuffer,
4409     const VkSubpassEndInfoKHR*                  pSubpassEndInfo)
4410 {
4411         radv_CmdEndRenderPass(commandBuffer);
4412 }
4413
4414 /*
4415  * For HTILE we have the following interesting clear words:
4416  *   0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4417  *   0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4418  *   0xfffffff0: Clear depth to 1.0
4419  *   0x00000000: Clear depth to 0.0
4420  */
4421 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4422                                   struct radv_image *image,
4423                                   const VkImageSubresourceRange *range,
4424                                   uint32_t clear_word)
4425 {
4426         assert(range->baseMipLevel == 0);
4427         assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4428         unsigned layer_count = radv_get_layerCount(image, range);
4429         uint64_t size = image->surface.htile_slice_size * layer_count;
4430         VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4431         uint64_t offset = image->offset + image->htile_offset +
4432                           image->surface.htile_slice_size * range->baseArrayLayer;
4433         struct radv_cmd_state *state = &cmd_buffer->state;
4434         VkClearDepthStencilValue value = {};
4435
4436         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4437                              RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4438
4439         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4440                                               size, clear_word);
4441
4442         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4443
4444         if (vk_format_is_stencil(image->vk_format))
4445                 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4446
4447         radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4448
4449         if (radv_image_is_tc_compat_htile(image)) {
4450                 /* Initialize the TC-compat metada value to 0 because by
4451                  * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4452                  * need have to conditionally update its value when performing
4453                  * a fast depth clear.
4454                  */
4455                 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4456         }
4457 }
4458
4459 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4460                                                struct radv_image *image,
4461                                                VkImageLayout src_layout,
4462                                                VkImageLayout dst_layout,
4463                                                unsigned src_queue_mask,
4464                                                unsigned dst_queue_mask,
4465                                                const VkImageSubresourceRange *range)
4466 {
4467         if (!radv_image_has_htile(image))
4468                 return;
4469
4470         if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4471                    radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4472                 /* TODO: merge with the clear if applicable */
4473                 radv_initialize_htile(cmd_buffer, image, range, 0);
4474         } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4475                    radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4476                 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4477                 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4478         } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4479                    !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4480                 VkImageSubresourceRange local_range = *range;
4481                 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4482                 local_range.baseMipLevel = 0;
4483                 local_range.levelCount = 1;
4484
4485                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4486                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4487
4488                 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4489
4490                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4491                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4492         }
4493 }
4494
4495 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4496                                   struct radv_image *image, uint32_t value)
4497 {
4498         struct radv_cmd_state *state = &cmd_buffer->state;
4499
4500         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4501                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4502
4503         state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4504
4505         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4506 }
4507
4508 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4509                            struct radv_image *image)
4510 {
4511         struct radv_cmd_state *state = &cmd_buffer->state;
4512         static const uint32_t fmask_clear_values[4] = {
4513                 0x00000000,
4514                 0x02020202,
4515                 0xE4E4E4E4,
4516                 0x76543210
4517         };
4518         uint32_t log2_samples = util_logbase2(image->info.samples);
4519         uint32_t value = fmask_clear_values[log2_samples];
4520
4521         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4522                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4523
4524         state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4525
4526         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4527 }
4528
4529 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4530                          struct radv_image *image, uint32_t value)
4531 {
4532         struct radv_cmd_state *state = &cmd_buffer->state;
4533
4534         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4535                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4536
4537         state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4538
4539         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4540                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4541 }
4542
4543 /**
4544  * Initialize DCC/FMASK/CMASK metadata for a color image.
4545  */
4546 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4547                                            struct radv_image *image,
4548                                            VkImageLayout src_layout,
4549                                            VkImageLayout dst_layout,
4550                                            unsigned src_queue_mask,
4551                                            unsigned dst_queue_mask)
4552 {
4553         if (radv_image_has_cmask(image)) {
4554                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4555
4556                 /*  TODO: clarify this. */
4557                 if (radv_image_has_fmask(image)) {
4558                         value = 0xccccccccu;
4559                 }
4560
4561                 radv_initialise_cmask(cmd_buffer, image, value);
4562         }
4563
4564         if (radv_image_has_fmask(image)) {
4565                 radv_initialize_fmask(cmd_buffer, image);
4566         }
4567
4568         if (radv_image_has_dcc(image)) {
4569                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4570                 bool need_decompress_pass = false;
4571
4572                 if (radv_layout_dcc_compressed(image, dst_layout,
4573                                                dst_queue_mask)) {
4574                         value = 0x20202020u;
4575                         need_decompress_pass = true;
4576                 }
4577
4578                 radv_initialize_dcc(cmd_buffer, image, value);
4579
4580                 radv_update_fce_metadata(cmd_buffer, image,
4581                                          need_decompress_pass);
4582         }
4583
4584         if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4585                 uint32_t color_values[2] = {};
4586                 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4587         }
4588 }
4589
4590 /**
4591  * Handle color image transitions for DCC/FMASK/CMASK.
4592  */
4593 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4594                                                struct radv_image *image,
4595                                                VkImageLayout src_layout,
4596                                                VkImageLayout dst_layout,
4597                                                unsigned src_queue_mask,
4598                                                unsigned dst_queue_mask,
4599                                                const VkImageSubresourceRange *range)
4600 {
4601         if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4602                 radv_init_color_image_metadata(cmd_buffer, image,
4603                                                src_layout, dst_layout,
4604                                                src_queue_mask, dst_queue_mask);
4605                 return;
4606         }
4607
4608         if (radv_image_has_dcc(image)) {
4609                 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4610                         radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4611                 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4612                            !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4613                         radv_decompress_dcc(cmd_buffer, image, range);
4614                 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4615                            !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4616                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4617                 }
4618         } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4619                 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4620                     !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4621                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4622                 }
4623
4624                 if (radv_image_has_fmask(image)) {
4625                         if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
4626                             dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
4627                                 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
4628                         }
4629                 }
4630         }
4631 }
4632
4633 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4634                                          struct radv_image *image,
4635                                          VkImageLayout src_layout,
4636                                          VkImageLayout dst_layout,
4637                                          uint32_t src_family,
4638                                          uint32_t dst_family,
4639                                          const VkImageSubresourceRange *range)
4640 {
4641         if (image->exclusive && src_family != dst_family) {
4642                 /* This is an acquire or a release operation and there will be
4643                  * a corresponding release/acquire. Do the transition in the
4644                  * most flexible queue. */
4645
4646                 assert(src_family == cmd_buffer->queue_family_index ||
4647                        dst_family == cmd_buffer->queue_family_index);
4648
4649                 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4650                         return;
4651
4652                 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4653                     (src_family == RADV_QUEUE_GENERAL ||
4654                      dst_family == RADV_QUEUE_GENERAL))
4655                         return;
4656         }
4657
4658         if (src_layout == dst_layout)
4659                 return;
4660
4661         unsigned src_queue_mask =
4662                 radv_image_queue_family_mask(image, src_family,
4663                                              cmd_buffer->queue_family_index);
4664         unsigned dst_queue_mask =
4665                 radv_image_queue_family_mask(image, dst_family,
4666                                              cmd_buffer->queue_family_index);
4667
4668         if (vk_format_is_depth(image->vk_format)) {
4669                 radv_handle_depth_image_transition(cmd_buffer, image,
4670                                                    src_layout, dst_layout,
4671                                                    src_queue_mask, dst_queue_mask,
4672                                                    range);
4673         } else {
4674                 radv_handle_color_image_transition(cmd_buffer, image,
4675                                                    src_layout, dst_layout,
4676                                                    src_queue_mask, dst_queue_mask,
4677                                                    range);
4678         }
4679 }
4680
4681 struct radv_barrier_info {
4682         uint32_t eventCount;
4683         const VkEvent *pEvents;
4684         VkPipelineStageFlags srcStageMask;
4685         VkPipelineStageFlags dstStageMask;
4686 };
4687
4688 static void
4689 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4690              uint32_t memoryBarrierCount,
4691              const VkMemoryBarrier *pMemoryBarriers,
4692              uint32_t bufferMemoryBarrierCount,
4693              const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4694              uint32_t imageMemoryBarrierCount,
4695              const VkImageMemoryBarrier *pImageMemoryBarriers,
4696              const struct radv_barrier_info *info)
4697 {
4698         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4699         enum radv_cmd_flush_bits src_flush_bits = 0;
4700         enum radv_cmd_flush_bits dst_flush_bits = 0;
4701
4702         for (unsigned i = 0; i < info->eventCount; ++i) {
4703                 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4704                 uint64_t va = radv_buffer_get_va(event->bo);
4705
4706                 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4707
4708                 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4709
4710                 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4711                 assert(cmd_buffer->cs->cdw <= cdw_max);
4712         }
4713
4714         for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4715                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4716                                                         NULL);
4717                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4718                                                         NULL);
4719         }
4720
4721         for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4722                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4723                                                         NULL);
4724                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4725                                                         NULL);
4726         }
4727
4728         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4729                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4730
4731                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4732                                                         image);
4733                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4734                                                         image);
4735         }
4736
4737         /* The Vulkan spec 1.1.98 says:
4738          *
4739          * "An execution dependency with only
4740          *  VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT in the destination stage mask
4741          *  will only prevent that stage from executing in subsequently
4742          *  submitted commands. As this stage does not perform any actual
4743          *  execution, this is not observable - in effect, it does not delay
4744          *  processing of subsequent commands. Similarly an execution dependency
4745          *  with only VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT in the source stage mask
4746          *  will effectively not wait for any prior commands to complete."
4747          */
4748         if (info->dstStageMask != VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT)
4749                 radv_stage_flush(cmd_buffer, info->srcStageMask);
4750         cmd_buffer->state.flush_bits |= src_flush_bits;
4751
4752         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4753                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4754                 radv_handle_image_transition(cmd_buffer, image,
4755                                              pImageMemoryBarriers[i].oldLayout,
4756                                              pImageMemoryBarriers[i].newLayout,
4757                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
4758                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
4759                                              &pImageMemoryBarriers[i].subresourceRange);
4760         }
4761
4762         /* Make sure CP DMA is idle because the driver might have performed a
4763          * DMA operation for copying or filling buffers/images.
4764          */
4765         if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4766                                   VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4767                 si_cp_dma_wait_for_idle(cmd_buffer);
4768
4769         cmd_buffer->state.flush_bits |= dst_flush_bits;
4770 }
4771
4772 void radv_CmdPipelineBarrier(
4773         VkCommandBuffer                             commandBuffer,
4774         VkPipelineStageFlags                        srcStageMask,
4775         VkPipelineStageFlags                        destStageMask,
4776         VkBool32                                    byRegion,
4777         uint32_t                                    memoryBarrierCount,
4778         const VkMemoryBarrier*                      pMemoryBarriers,
4779         uint32_t                                    bufferMemoryBarrierCount,
4780         const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
4781         uint32_t                                    imageMemoryBarrierCount,
4782         const VkImageMemoryBarrier*                 pImageMemoryBarriers)
4783 {
4784         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4785         struct radv_barrier_info info;
4786
4787         info.eventCount = 0;
4788         info.pEvents = NULL;
4789         info.srcStageMask = srcStageMask;
4790         info.dstStageMask = destStageMask;
4791
4792         radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4793                      bufferMemoryBarrierCount, pBufferMemoryBarriers,
4794                      imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4795 }
4796
4797
4798 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4799                         struct radv_event *event,
4800                         VkPipelineStageFlags stageMask,
4801                         unsigned value)
4802 {
4803         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4804         uint64_t va = radv_buffer_get_va(event->bo);
4805
4806         si_emit_cache_flush(cmd_buffer);
4807
4808         radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4809
4810         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4811
4812         /* Flags that only require a top-of-pipe event. */
4813         VkPipelineStageFlags top_of_pipe_flags =
4814                 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4815
4816         /* Flags that only require a post-index-fetch event. */
4817         VkPipelineStageFlags post_index_fetch_flags =
4818                 top_of_pipe_flags |
4819                 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4820                 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4821
4822         /* Make sure CP DMA is idle because the driver might have performed a
4823          * DMA operation for copying or filling buffers/images.
4824          */
4825         if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4826                          VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4827                 si_cp_dma_wait_for_idle(cmd_buffer);
4828
4829         /* TODO: Emit EOS events for syncing PS/CS stages. */
4830
4831         if (!(stageMask & ~top_of_pipe_flags)) {
4832                 /* Just need to sync the PFP engine. */
4833                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4834                 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4835                                 S_370_WR_CONFIRM(1) |
4836                                 S_370_ENGINE_SEL(V_370_PFP));
4837                 radeon_emit(cs, va);
4838                 radeon_emit(cs, va >> 32);
4839                 radeon_emit(cs, value);
4840         } else if (!(stageMask & ~post_index_fetch_flags)) {
4841                 /* Sync ME because PFP reads index and indirect buffers. */
4842                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4843                 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4844                                 S_370_WR_CONFIRM(1) |
4845                                 S_370_ENGINE_SEL(V_370_ME));
4846                 radeon_emit(cs, va);
4847                 radeon_emit(cs, va >> 32);
4848                 radeon_emit(cs, value);
4849         } else {
4850                 /* Otherwise, sync all prior GPU work using an EOP event. */
4851                 si_cs_emit_write_event_eop(cs,
4852                                            cmd_buffer->device->physical_device->rad_info.chip_class,
4853                                            radv_cmd_buffer_uses_mec(cmd_buffer),
4854                                            V_028A90_BOTTOM_OF_PIPE_TS, 0,
4855                                            EOP_DATA_SEL_VALUE_32BIT, va, value,
4856                                            cmd_buffer->gfx9_eop_bug_va);
4857         }
4858
4859         assert(cmd_buffer->cs->cdw <= cdw_max);
4860 }
4861
4862 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4863                       VkEvent _event,
4864                       VkPipelineStageFlags stageMask)
4865 {
4866         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4867         RADV_FROM_HANDLE(radv_event, event, _event);
4868
4869         write_event(cmd_buffer, event, stageMask, 1);
4870 }
4871
4872 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4873                         VkEvent _event,
4874                         VkPipelineStageFlags stageMask)
4875 {
4876         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4877         RADV_FROM_HANDLE(radv_event, event, _event);
4878
4879         write_event(cmd_buffer, event, stageMask, 0);
4880 }
4881
4882 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4883                         uint32_t eventCount,
4884                         const VkEvent* pEvents,
4885                         VkPipelineStageFlags srcStageMask,
4886                         VkPipelineStageFlags dstStageMask,
4887                         uint32_t memoryBarrierCount,
4888                         const VkMemoryBarrier* pMemoryBarriers,
4889                         uint32_t bufferMemoryBarrierCount,
4890                         const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4891                         uint32_t imageMemoryBarrierCount,
4892                         const VkImageMemoryBarrier* pImageMemoryBarriers)
4893 {
4894         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4895         struct radv_barrier_info info;
4896
4897         info.eventCount = eventCount;
4898         info.pEvents = pEvents;
4899         info.srcStageMask = 0;
4900
4901         radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4902                      bufferMemoryBarrierCount, pBufferMemoryBarriers,
4903                      imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4904 }
4905
4906
4907 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4908                            uint32_t deviceMask)
4909 {
4910    /* No-op */
4911 }
4912
4913 /* VK_EXT_conditional_rendering */
4914 void radv_CmdBeginConditionalRenderingEXT(
4915         VkCommandBuffer                             commandBuffer,
4916         const VkConditionalRenderingBeginInfoEXT*   pConditionalRenderingBegin)
4917 {
4918         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4919         RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4920         bool draw_visible = true;
4921         uint64_t va;
4922
4923         va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4924
4925         /* By default, if the 32-bit value at offset in buffer memory is zero,
4926          * then the rendering commands are discarded, otherwise they are
4927          * executed as normal. If the inverted flag is set, all commands are
4928          * discarded if the value is non zero.
4929          */
4930         if (pConditionalRenderingBegin->flags &
4931             VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4932                 draw_visible = false;
4933         }
4934
4935         si_emit_cache_flush(cmd_buffer);
4936
4937         /* Enable predication for this command buffer. */
4938         si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4939         cmd_buffer->state.predicating = true;
4940
4941         /* Store conditional rendering user info. */
4942         cmd_buffer->state.predication_type = draw_visible;
4943         cmd_buffer->state.predication_va = va;
4944 }
4945
4946 void radv_CmdEndConditionalRenderingEXT(
4947         VkCommandBuffer                             commandBuffer)
4948 {
4949         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4950
4951         /* Disable predication for this command buffer. */
4952         si_emit_set_predication_state(cmd_buffer, false, 0);
4953         cmd_buffer->state.predicating = false;
4954
4955         /* Reset conditional rendering user info. */
4956         cmd_buffer->state.predication_type = -1;
4957         cmd_buffer->state.predication_va = 0;
4958 }
4959
4960 /* VK_EXT_transform_feedback */
4961 void radv_CmdBindTransformFeedbackBuffersEXT(
4962     VkCommandBuffer                             commandBuffer,
4963     uint32_t                                    firstBinding,
4964     uint32_t                                    bindingCount,
4965     const VkBuffer*                             pBuffers,
4966     const VkDeviceSize*                         pOffsets,
4967     const VkDeviceSize*                         pSizes)
4968 {
4969         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4970         struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4971         uint8_t enabled_mask = 0;
4972
4973         assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4974         for (uint32_t i = 0; i < bindingCount; i++) {
4975                 uint32_t idx = firstBinding + i;
4976
4977                 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4978                 sb[idx].offset = pOffsets[i];
4979                 sb[idx].size = pSizes[i];
4980
4981                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4982                                    sb[idx].buffer->bo);
4983
4984                 enabled_mask |= 1 << idx;
4985         }
4986
4987         cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4988
4989         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4990 }
4991
4992 static void
4993 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4994 {
4995         struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4996         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4997
4998         radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
4999         radeon_emit(cs,
5000                     S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
5001                     S_028B94_RAST_STREAM(0) |
5002                     S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
5003                     S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
5004                     S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
5005         radeon_emit(cs, so->hw_enabled_mask &
5006                         so->enabled_stream_buffers_mask);
5007
5008         cmd_buffer->state.context_roll_without_scissor_emitted = true;
5009 }
5010
5011 static void
5012 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
5013 {
5014         struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5015         bool old_streamout_enabled = so->streamout_enabled;
5016         uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
5017
5018         so->streamout_enabled = enable;
5019
5020         so->hw_enabled_mask = so->enabled_mask |
5021                               (so->enabled_mask << 4) |
5022                               (so->enabled_mask << 8) |
5023                               (so->enabled_mask << 12);
5024
5025         if ((old_streamout_enabled != so->streamout_enabled) ||
5026             (old_hw_enabled_mask != so->hw_enabled_mask))
5027                 radv_emit_streamout_enable(cmd_buffer);
5028 }
5029
5030 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
5031 {
5032         struct radeon_cmdbuf *cs = cmd_buffer->cs;
5033         unsigned reg_strmout_cntl;
5034
5035         /* The register is at different places on different ASICs. */
5036         if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
5037                 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
5038                 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
5039         } else {
5040                 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
5041                 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
5042         }
5043
5044         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
5045         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
5046
5047         radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
5048         radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
5049         radeon_emit(cs, reg_strmout_cntl >> 2);  /* register */
5050         radeon_emit(cs, 0);
5051         radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
5052         radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
5053         radeon_emit(cs, 4); /* poll interval */
5054 }
5055
5056 void radv_CmdBeginTransformFeedbackEXT(
5057     VkCommandBuffer                             commandBuffer,
5058     uint32_t                                    firstCounterBuffer,
5059     uint32_t                                    counterBufferCount,
5060     const VkBuffer*                             pCounterBuffers,
5061     const VkDeviceSize*                         pCounterBufferOffsets)
5062 {
5063         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5064         struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
5065         struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5066         struct radeon_cmdbuf *cs = cmd_buffer->cs;
5067         uint32_t i;
5068
5069         radv_flush_vgt_streamout(cmd_buffer);
5070
5071         assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5072         for_each_bit(i, so->enabled_mask) {
5073                 int32_t counter_buffer_idx = i - firstCounterBuffer;
5074                 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5075                         counter_buffer_idx = -1;
5076
5077                 /* SI binds streamout buffers as shader resources.
5078                  * VGT only counts primitives and tells the shader through
5079                  * SGPRs what to do.
5080                  */
5081                 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5082                 radeon_emit(cs, sb[i].size >> 2);       /* BUFFER_SIZE (in DW) */
5083                 radeon_emit(cs, so->stride_in_dw[i]);                   /* VTX_STRIDE (in DW) */
5084
5085                 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5086
5087                 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5088                         /* The array of counter buffers is optional. */
5089                         RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5090                         uint64_t va = radv_buffer_get_va(buffer->bo);
5091
5092                         va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5093
5094                         /* Append */
5095                         radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5096                         radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5097                                         STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5098                                         STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5099                         radeon_emit(cs, 0); /* unused */
5100                         radeon_emit(cs, 0); /* unused */
5101                         radeon_emit(cs, va); /* src address lo */
5102                         radeon_emit(cs, va >> 32); /* src address hi */
5103
5104                         radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5105                 } else {
5106                         /* Start from the beginning. */
5107                         radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5108                         radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5109                                         STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5110                                         STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5111                         radeon_emit(cs, 0); /* unused */
5112                         radeon_emit(cs, 0); /* unused */
5113                         radeon_emit(cs, 0); /* unused */
5114                         radeon_emit(cs, 0); /* unused */
5115                 }
5116         }
5117
5118         radv_set_streamout_enable(cmd_buffer, true);
5119 }
5120
5121 void radv_CmdEndTransformFeedbackEXT(
5122     VkCommandBuffer                             commandBuffer,
5123     uint32_t                                    firstCounterBuffer,
5124     uint32_t                                    counterBufferCount,
5125     const VkBuffer*                             pCounterBuffers,
5126     const VkDeviceSize*                         pCounterBufferOffsets)
5127 {
5128         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5129         struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5130         struct radeon_cmdbuf *cs = cmd_buffer->cs;
5131         uint32_t i;
5132
5133         radv_flush_vgt_streamout(cmd_buffer);
5134
5135         assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5136         for_each_bit(i, so->enabled_mask) {
5137                 int32_t counter_buffer_idx = i - firstCounterBuffer;
5138                 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5139                         counter_buffer_idx = -1;
5140
5141                 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5142                         /* The array of counters buffer is optional. */
5143                         RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5144                         uint64_t va = radv_buffer_get_va(buffer->bo);
5145
5146                         va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5147
5148                         radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5149                         radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5150                                         STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5151                                         STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5152                                         STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5153                         radeon_emit(cs, va);            /* dst address lo */
5154                         radeon_emit(cs, va >> 32);      /* dst address hi */
5155                         radeon_emit(cs, 0);             /* unused */
5156                         radeon_emit(cs, 0);             /* unused */
5157
5158                         radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5159                 }
5160
5161                 /* Deactivate transform feedback by zeroing the buffer size.
5162                  * The counters (primitives generated, primitives emitted) may
5163                  * be enabled even if there is not buffer bound. This ensures
5164                  * that the primitives-emitted query won't increment.
5165                  */
5166                 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5167
5168                 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5169         }
5170
5171         radv_set_streamout_enable(cmd_buffer, false);
5172 }
5173
5174 void radv_CmdDrawIndirectByteCountEXT(
5175     VkCommandBuffer                             commandBuffer,
5176     uint32_t                                    instanceCount,
5177     uint32_t                                    firstInstance,
5178     VkBuffer                                    _counterBuffer,
5179     VkDeviceSize                                counterBufferOffset,
5180     uint32_t                                    counterOffset,
5181     uint32_t                                    vertexStride)
5182 {
5183         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5184         RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5185         struct radv_draw_info info = {};
5186
5187         info.instance_count = instanceCount;
5188         info.first_instance = firstInstance;
5189         info.strmout_buffer = counterBuffer;
5190         info.strmout_buffer_offset = counterBufferOffset;
5191         info.stride = vertexStride;
5192
5193         radv_draw(cmd_buffer, &info);
5194 }