src/amd/vulkan/radv_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "radv_private.h"
  29 #include "radv_radeon_winsys.h"
  30 #include "radv_shader.h"
  31 #include "radv_cs.h"
  32 #include "sid.h"
  33 #include "gfx9d.h"
  34 #include "vk_format.h"
  35 #include "radv_debug.h"
  36 #include "radv_meta.h"
  37
  38 #include "ac_debug.h"
  39
  40 enum {
  41         RADV_PREFETCH_VBO_DESCRIPTORS   = (1 << 0),
  42         RADV_PREFETCH_VS                = (1 << 1),
  43         RADV_PREFETCH_TCS               = (1 << 2),
  44         RADV_PREFETCH_TES               = (1 << 3),
  45         RADV_PREFETCH_GS                = (1 << 4),
  46         RADV_PREFETCH_PS                = (1 << 5),
  47         RADV_PREFETCH_SHADERS           = (RADV_PREFETCH_VS  |
  48                                            RADV_PREFETCH_TCS |
  49                                            RADV_PREFETCH_TES |
  50                                            RADV_PREFETCH_GS  |
  51                                            RADV_PREFETCH_PS)
  52 };
  53
  54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
  55                                          struct radv_image *image,
  56                                          VkImageLayout src_layout,
  57                                          VkImageLayout dst_layout,
  58                                          uint32_t src_family,
  59                                          uint32_t dst_family,
  60                                          const VkImageSubresourceRange *range,
  61                                          VkImageAspectFlags pending_clears);
  62
  63 const struct radv_dynamic_state default_dynamic_state = {
  64         .viewport = {
  65                 .count = 0,
  66         },
  67         .scissor = {
  68                 .count = 0,
  69         },
  70         .line_width = 1.0f,
  71         .depth_bias = {
  72                 .bias = 0.0f,
  73                 .clamp = 0.0f,
  74                 .slope = 0.0f,
  75         },
  76         .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
  77         .depth_bounds = {
  78                 .min = 0.0f,
  79                 .max = 1.0f,
  80         },
  81         .stencil_compare_mask = {
  82                 .front = ~0u,
  83                 .back = ~0u,
  84         },
  85         .stencil_write_mask = {
  86                 .front = ~0u,
  87                 .back = ~0u,
  88         },
  89         .stencil_reference = {
  90                 .front = 0u,
  91                 .back = 0u,
  92         },
  93 };
  94
  95 static void
  96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
  97                         const struct radv_dynamic_state *src)
  98 {
  99         struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
 100         uint32_t copy_mask = src->mask;
 101         uint32_t dest_mask = 0;
 102
 103         /* Make sure to copy the number of viewports/scissors because they can
 104          * only be specified at pipeline creation time.
 105          */
 106         dest->viewport.count = src->viewport.count;
 107         dest->scissor.count = src->scissor.count;
 108         dest->discard_rectangle.count = src->discard_rectangle.count;
 109
 110         if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
 111                 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
 112                            src->viewport.count * sizeof(VkViewport))) {
 113                         typed_memcpy(dest->viewport.viewports,
 114                                      src->viewport.viewports,
 115                                      src->viewport.count);
 116                         dest_mask |= RADV_DYNAMIC_VIEWPORT;
 117                 }
 118         }
 119
 120         if (copy_mask & RADV_DYNAMIC_SCISSOR) {
 121                 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
 122                            src->scissor.count * sizeof(VkRect2D))) {
 123                         typed_memcpy(dest->scissor.scissors,
 124                                      src->scissor.scissors, src->scissor.count);
 125                         dest_mask |= RADV_DYNAMIC_SCISSOR;
 126                 }
 127         }
 128
 129         if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
 130                 if (dest->line_width != src->line_width) {
 131                         dest->line_width = src->line_width;
 132                         dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
 133                 }
 134         }
 135
 136         if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
 137                 if (memcmp(&dest->depth_bias, &src->depth_bias,
 138                            sizeof(src->depth_bias))) {
 139                         dest->depth_bias = src->depth_bias;
 140                         dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
 141                 }
 142         }
 143
 144         if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
 145                 if (memcmp(&dest->blend_constants, &src->blend_constants,
 146                            sizeof(src->blend_constants))) {
 147                         typed_memcpy(dest->blend_constants,
 148                                      src->blend_constants, 4);
 149                         dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
 150                 }
 151         }
 152
 153         if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
 154                 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
 155                            sizeof(src->depth_bounds))) {
 156                         dest->depth_bounds = src->depth_bounds;
 157                         dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
 158                 }
 159         }
 160
 161         if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
 162                 if (memcmp(&dest->stencil_compare_mask,
 163                            &src->stencil_compare_mask,
 164                            sizeof(src->stencil_compare_mask))) {
 165                         dest->stencil_compare_mask = src->stencil_compare_mask;
 166                         dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
 167                 }
 168         }
 169
 170         if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
 171                 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
 172                            sizeof(src->stencil_write_mask))) {
 173                         dest->stencil_write_mask = src->stencil_write_mask;
 174                         dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
 175                 }
 176         }
 177
 178         if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
 179                 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
 180                            sizeof(src->stencil_reference))) {
 181                         dest->stencil_reference = src->stencil_reference;
 182                         dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
 183                 }
 184         }
 185
 186         if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
 187                 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
 188                            src->discard_rectangle.count * sizeof(VkRect2D))) {
 189                         typed_memcpy(dest->discard_rectangle.rectangles,
 190                                      src->discard_rectangle.rectangles,
 191                                      src->discard_rectangle.count);
 192                         dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
 193                 }
 194         }
 195
 196         cmd_buffer->state.dirty |= dest_mask;
 197 }
 198
 199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
 200 {
 201         return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
 202                cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
 203 }
 204
 205 enum ring_type radv_queue_family_to_ring(int f) {
 206         switch (f) {
 207         case RADV_QUEUE_GENERAL:
 208                 return RING_GFX;
 209         case RADV_QUEUE_COMPUTE:
 210                 return RING_COMPUTE;
 211         case RADV_QUEUE_TRANSFER:
 212                 return RING_DMA;
 213         default:
 214                 unreachable("Unknown queue family");
 215         }
 216 }
 217
 218 static VkResult radv_create_cmd_buffer(
 219         struct radv_device *                         device,
 220         struct radv_cmd_pool *                       pool,
 221         VkCommandBufferLevel                        level,
 222         VkCommandBuffer*                            pCommandBuffer)
 223 {
 224         struct radv_cmd_buffer *cmd_buffer;
 225         unsigned ring;
 226         cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
 227                                VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 228         if (cmd_buffer == NULL)
 229                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 230
 231         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
 232         cmd_buffer->device = device;
 233         cmd_buffer->pool = pool;
 234         cmd_buffer->level = level;
 235
 236         if (pool) {
 237                 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
 238                 cmd_buffer->queue_family_index = pool->queue_family_index;
 239
 240         } else {
 241                 /* Init the pool_link so we can safely call list_del when we destroy
 242                  * the command buffer
 243                  */
 244                 list_inithead(&cmd_buffer->pool_link);
 245                 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
 246         }
 247
 248         ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
 249
 250         cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
 251         if (!cmd_buffer->cs) {
 252                 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 253                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 254         }
 255
 256         *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
 257
 258         list_inithead(&cmd_buffer->upload.list);
 259
 260         return VK_SUCCESS;
 261 }
 262
 263 static void
 264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
 265 {
 266         list_del(&cmd_buffer->pool_link);
 267
 268         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 269                                  &cmd_buffer->upload.list, list) {
 270                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 271                 list_del(&up->list);
 272                 free(up);
 273         }
 274
 275         if (cmd_buffer->upload.upload_bo)
 276                 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
 277         cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
 278
 279         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
 280                 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
 281
 282         vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 283 }
 284
 285 static VkResult
 286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 287 {
 288
 289         cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
 290
 291         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 292                                  &cmd_buffer->upload.list, list) {
 293                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 294                 list_del(&up->list);
 295                 free(up);
 296         }
 297
 298         cmd_buffer->push_constant_stages = 0;
 299         cmd_buffer->scratch_size_needed = 0;
 300         cmd_buffer->compute_scratch_size_needed = 0;
 301         cmd_buffer->esgs_ring_size_needed = 0;
 302         cmd_buffer->gsvs_ring_size_needed = 0;
 303         cmd_buffer->tess_rings_needed = false;
 304         cmd_buffer->sample_positions_needed = false;
 305
 306         if (cmd_buffer->upload.upload_bo)
 307                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 308                                    cmd_buffer->upload.upload_bo, 8);
 309         cmd_buffer->upload.offset = 0;
 310
 311         cmd_buffer->record_result = VK_SUCCESS;
 312
 313         cmd_buffer->ring_offsets_idx = -1;
 314
 315         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
 316                 cmd_buffer->descriptors[i].dirty = 0;
 317                 cmd_buffer->descriptors[i].valid = 0;
 318                 cmd_buffer->descriptors[i].push_dirty = false;
 319         }
 320
 321         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 322                 void *fence_ptr;
 323                 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
 324                                              &cmd_buffer->gfx9_fence_offset,
 325                                              &fence_ptr);
 326                 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
 327         }
 328
 329         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
 330
 331         return cmd_buffer->record_result;
 332 }
 333
 334 static bool
 335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
 336                                   uint64_t min_needed)
 337 {
 338         uint64_t new_size;
 339         struct radeon_winsys_bo *bo;
 340         struct radv_cmd_buffer_upload *upload;
 341         struct radv_device *device = cmd_buffer->device;
 342
 343         new_size = MAX2(min_needed, 16 * 1024);
 344         new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
 345
 346         bo = device->ws->buffer_create(device->ws,
 347                                        new_size, 4096,
 348                                        RADEON_DOMAIN_GTT,
 349                                        RADEON_FLAG_CPU_ACCESS|
 350                                        RADEON_FLAG_NO_INTERPROCESS_SHARING |
 351                                        RADEON_FLAG_32BIT);
 352
 353         if (!bo) {
 354                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 355                 return false;
 356         }
 357
 358         radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
 359         if (cmd_buffer->upload.upload_bo) {
 360                 upload = malloc(sizeof(*upload));
 361
 362                 if (!upload) {
 363                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
 364                         device->ws->buffer_destroy(bo);
 365                         return false;
 366                 }
 367
 368                 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
 369                 list_add(&upload->list, &cmd_buffer->upload.list);
 370         }
 371
 372         cmd_buffer->upload.upload_bo = bo;
 373         cmd_buffer->upload.size = new_size;
 374         cmd_buffer->upload.offset = 0;
 375         cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
 376
 377         if (!cmd_buffer->upload.map) {
 378                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 379                 return false;
 380         }
 381
 382         return true;
 383 }
 384
 385 bool
 386 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
 387                              unsigned size,
 388                              unsigned alignment,
 389                              unsigned *out_offset,
 390                              void **ptr)
 391 {
 392         uint64_t offset = align(cmd_buffer->upload.offset, alignment);
 393         if (offset + size > cmd_buffer->upload.size) {
 394                 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
 395                         return false;
 396                 offset = 0;
 397         }
 398
 399         *out_offset = offset;
 400         *ptr = cmd_buffer->upload.map + offset;
 401
 402         cmd_buffer->upload.offset = offset + size;
 403         return true;
 404 }
 405
 406 bool
 407 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
 408                             unsigned size, unsigned alignment,
 409                             const void *data, unsigned *out_offset)
 410 {
 411         uint8_t *ptr;
 412
 413         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
 414                                           out_offset, (void **)&ptr))
 415                 return false;
 416
 417         if (ptr)
 418                 memcpy(ptr, data, size);
 419
 420         return true;
 421 }
 422
 423 static void
 424 radv_emit_write_data_packet(struct radeon_cmdbuf *cs, uint64_t va,
 425                             unsigned count, const uint32_t *data)
 426 {
 427         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
 428         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
 429                     S_370_WR_CONFIRM(1) |
 430                     S_370_ENGINE_SEL(V_370_ME));
 431         radeon_emit(cs, va);
 432         radeon_emit(cs, va >> 32);
 433         radeon_emit_array(cs, data, count);
 434 }
 435
 436 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
 437 {
 438         struct radv_device *device = cmd_buffer->device;
 439         struct radeon_cmdbuf *cs = cmd_buffer->cs;
 440         uint64_t va;
 441
 442         va = radv_buffer_get_va(device->trace_bo);
 443         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
 444                 va += 4;
 445
 446         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
 447
 448         ++cmd_buffer->state.trace_id;
 449         radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
 450         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
 451         radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
 452 }
 453
 454 static void
 455 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
 456                            enum radv_cmd_flush_bits flags)
 457 {
 458         if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
 459                 uint32_t *ptr = NULL;
 460                 uint64_t va = 0;
 461
 462                 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
 463                                 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
 464
 465                 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
 466                         va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
 467                              cmd_buffer->gfx9_fence_offset;
 468                         ptr = &cmd_buffer->gfx9_fence_idx;
 469                 }
 470
 471                 /* Force wait for graphics or compute engines to be idle. */
 472                 si_cs_emit_cache_flush(cmd_buffer->cs,
 473                                        cmd_buffer->device->physical_device->rad_info.chip_class,
 474                                        ptr, va,
 475                                        radv_cmd_buffer_uses_mec(cmd_buffer),
 476                                        flags);
 477         }
 478
 479         if (unlikely(cmd_buffer->device->trace_bo))
 480                 radv_cmd_buffer_trace_emit(cmd_buffer);
 481 }
 482
 483 static void
 484 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
 485                    struct radv_pipeline *pipeline, enum ring_type ring)
 486 {
 487         struct radv_device *device = cmd_buffer->device;
 488         struct radeon_cmdbuf *cs = cmd_buffer->cs;
 489         uint32_t data[2];
 490         uint64_t va;
 491
 492         va = radv_buffer_get_va(device->trace_bo);
 493
 494         switch (ring) {
 495         case RING_GFX:
 496                 va += 8;
 497                 break;
 498         case RING_COMPUTE:
 499                 va += 16;
 500                 break;
 501         default:
 502                 assert(!"invalid ring type");
 503         }
 504
 505         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 506                                                            cmd_buffer->cs, 6);
 507
 508         data[0] = (uintptr_t)pipeline;
 509         data[1] = (uintptr_t)pipeline >> 32;
 510
 511         radv_emit_write_data_packet(cs, va, 2, data);
 512 }
 513
 514 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 515                              VkPipelineBindPoint bind_point,
 516                              struct radv_descriptor_set *set,
 517                              unsigned idx)
 518 {
 519         struct radv_descriptor_state *descriptors_state =
 520                 radv_get_descriptors_state(cmd_buffer, bind_point);
 521
 522         descriptors_state->sets[idx] = set;
 523         if (set)
 524                 descriptors_state->valid |= (1u << idx);
 525         else
 526                 descriptors_state->valid &= ~(1u << idx);
 527         descriptors_state->dirty |= (1u << idx);
 528 }
 529
 530 static void
 531 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
 532                       VkPipelineBindPoint bind_point)
 533 {
 534         struct radv_descriptor_state *descriptors_state =
 535                 radv_get_descriptors_state(cmd_buffer, bind_point);
 536         struct radv_device *device = cmd_buffer->device;
 537         struct radeon_cmdbuf *cs = cmd_buffer->cs;
 538         uint32_t data[MAX_SETS * 2] = {};
 539         uint64_t va;
 540         unsigned i;
 541         va = radv_buffer_get_va(device->trace_bo) + 24;
 542
 543         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 544                                                            cmd_buffer->cs, 4 + MAX_SETS * 2);
 545
 546         for_each_bit(i, descriptors_state->valid) {
 547                 struct radv_descriptor_set *set = descriptors_state->sets[i];
 548                 data[i * 2] = (uintptr_t)set;
 549                 data[i * 2 + 1] = (uintptr_t)set >> 32;
 550         }
 551
 552         radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
 553 }
 554
 555 struct radv_userdata_info *
 556 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
 557                       gl_shader_stage stage,
 558                       int idx)
 559 {
 560         struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
 561         return &shader->info.user_sgprs_locs.shader_data[idx];
 562 }
 563
 564 static void
 565 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
 566                            struct radv_pipeline *pipeline,
 567                            gl_shader_stage stage,
 568                            int idx, uint64_t va)
 569 {
 570         struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
 571         uint32_t base_reg = pipeline->user_data_0[stage];
 572         if (loc->sgpr_idx == -1)
 573                 return;
 574
 575         assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
 576         assert(!loc->indirect);
 577
 578         radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
 579                                  base_reg + loc->sgpr_idx * 4, va, false);
 580 }
 581
 582 static void
 583 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
 584                               struct radv_pipeline *pipeline,
 585                               struct radv_descriptor_state *descriptors_state,
 586                               gl_shader_stage stage)
 587 {
 588         struct radv_device *device = cmd_buffer->device;
 589         struct radeon_cmdbuf *cs = cmd_buffer->cs;
 590         uint32_t sh_base = pipeline->user_data_0[stage];
 591         struct radv_userdata_locations *locs =
 592                 &pipeline->shaders[stage]->info.user_sgprs_locs;
 593         unsigned mask = locs->descriptor_sets_enabled;
 594
 595         mask &= descriptors_state->dirty & descriptors_state->valid;
 596
 597         while (mask) {
 598                 int start, count;
 599
 600                 u_bit_scan_consecutive_range(&mask, &start, &count);
 601
 602                 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
 603                 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
 604
 605                 radv_emit_shader_pointer_head(cs, sh_offset, count,
 606                                               HAVE_32BIT_POINTERS);
 607                 for (int i = 0; i < count; i++) {
 608                         struct radv_descriptor_set *set =
 609                                 descriptors_state->sets[start + i];
 610
 611                         radv_emit_shader_pointer_body(device, cs, set->va,
 612                                                       HAVE_32BIT_POINTERS);
 613                 }
 614         }
 615 }
 616
 617 static void
 618 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
 619                               struct radv_pipeline *pipeline)
 620 {
 621         int num_samples = pipeline->graphics.ms.num_samples;
 622         struct radv_multisample_state *ms = &pipeline->graphics.ms;
 623         struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
 624
 625         if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
 626                 cmd_buffer->sample_positions_needed = true;
 627
 628         if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
 629                 return;
 630
 631         radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
 632         radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
 633         radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
 634
 635         radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
 636
 637         radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
 638
 639         /* GFX9: Flush DFSM when the AA mode changes. */
 640         if (cmd_buffer->device->dfsm_allowed) {
 641                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 642                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
 643         }
 644 }
 645
 646 static void
 647 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
 648                           struct radv_shader_variant *shader)
 649 {
 650         uint64_t va;
 651
 652         if (!shader)
 653                 return;
 654
 655         va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 656
 657         si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
 658 }
 659
 660 static void
 661 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
 662                       struct radv_pipeline *pipeline,
 663                       bool vertex_stage_only)
 664 {
 665         struct radv_cmd_state *state = &cmd_buffer->state;
 666         uint32_t mask = state->prefetch_L2_mask;
 667
 668         if (vertex_stage_only) {
 669                 /* Fast prefetch path for starting draws as soon as possible.
 670                  */
 671                 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
 672                                                   RADV_PREFETCH_VBO_DESCRIPTORS);
 673         }
 674
 675         if (mask & RADV_PREFETCH_VS)
 676                 radv_emit_shader_prefetch(cmd_buffer,
 677                                           pipeline->shaders[MESA_SHADER_VERTEX]);
 678
 679         if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
 680                 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
 681
 682         if (mask & RADV_PREFETCH_TCS)
 683                 radv_emit_shader_prefetch(cmd_buffer,
 684                                           pipeline->shaders[MESA_SHADER_TESS_CTRL]);
 685
 686         if (mask & RADV_PREFETCH_TES)
 687                 radv_emit_shader_prefetch(cmd_buffer,
 688                                           pipeline->shaders[MESA_SHADER_TESS_EVAL]);
 689
 690         if (mask & RADV_PREFETCH_GS) {
 691                 radv_emit_shader_prefetch(cmd_buffer,
 692                                           pipeline->shaders[MESA_SHADER_GEOMETRY]);
 693                 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
 694         }
 695
 696         if (mask & RADV_PREFETCH_PS)
 697                 radv_emit_shader_prefetch(cmd_buffer,
 698                                           pipeline->shaders[MESA_SHADER_FRAGMENT]);
 699
 700         state->prefetch_L2_mask &= ~mask;
 701 }
 702
 703 static void
 704 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
 705 {
 706         if (!cmd_buffer->device->physical_device->rbplus_allowed)
 707                 return;
 708
 709         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 710         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
 711         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 712
 713         unsigned sx_ps_downconvert = 0;
 714         unsigned sx_blend_opt_epsilon = 0;
 715         unsigned sx_blend_opt_control = 0;
 716
 717         for (unsigned i = 0; i < subpass->color_count; ++i) {
 718                 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
 719                         continue;
 720
 721                 int idx = subpass->color_attachments[i].attachment;
 722                 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
 723
 724                 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
 725                 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
 726                 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
 727                 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
 728
 729                 bool has_alpha, has_rgb;
 730
 731                 /* Set if RGB and A are present. */
 732                 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
 733
 734                 if (format == V_028C70_COLOR_8 ||
 735                     format == V_028C70_COLOR_16 ||
 736                     format == V_028C70_COLOR_32)
 737                         has_rgb = !has_alpha;
 738                 else
 739                         has_rgb = true;
 740
 741                 /* Check the colormask and export format. */
 742                 if (!(colormask & 0x7))
 743                         has_rgb = false;
 744                 if (!(colormask & 0x8))
 745                         has_alpha = false;
 746
 747                 if (spi_format == V_028714_SPI_SHADER_ZERO) {
 748                         has_rgb = false;
 749                         has_alpha = false;
 750                 }
 751
 752                 /* Disable value checking for disabled channels. */
 753                 if (!has_rgb)
 754                         sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 755                 if (!has_alpha)
 756                         sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 757
 758                 /* Enable down-conversion for 32bpp and smaller formats. */
 759                 switch (format) {
 760                 case V_028C70_COLOR_8:
 761                 case V_028C70_COLOR_8_8:
 762                 case V_028C70_COLOR_8_8_8_8:
 763                         /* For 1 and 2-channel formats, use the superset thereof. */
 764                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
 765                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 766                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 767                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
 768                                 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
 769                         }
 770                         break;
 771
 772                 case V_028C70_COLOR_5_6_5:
 773                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 774                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
 775                                 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
 776                         }
 777                         break;
 778
 779                 case V_028C70_COLOR_1_5_5_5:
 780                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 781                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
 782                                 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
 783                         }
 784                         break;
 785
 786                 case V_028C70_COLOR_4_4_4_4:
 787                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 788                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
 789                                 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
 790                         }
 791                         break;
 792
 793                 case V_028C70_COLOR_32:
 794                         if (swap == V_028C70_SWAP_STD &&
 795                             spi_format == V_028714_SPI_SHADER_32_R)
 796                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
 797                         else if (swap == V_028C70_SWAP_ALT_REV &&
 798                                  spi_format == V_028714_SPI_SHADER_32_AR)
 799                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
 800                         break;
 801
 802                 case V_028C70_COLOR_16:
 803                 case V_028C70_COLOR_16_16:
 804                         /* For 1-channel formats, use the superset thereof. */
 805                         if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
 806                             spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
 807                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 808                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 809                                 if (swap == V_028C70_SWAP_STD ||
 810                                     swap == V_028C70_SWAP_STD_REV)
 811                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
 812                                 else
 813                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
 814                         }
 815                         break;
 816
 817                 case V_028C70_COLOR_10_11_11:
 818                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 819                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
 820                                 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
 821                         }
 822                         break;
 823
 824                 case V_028C70_COLOR_2_10_10_10:
 825                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 826                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
 827                                 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
 828                         }
 829                         break;
 830                 }
 831         }
 832
 833         radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
 834         radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
 835         radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
 836         radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
 837 }
 838
 839 static void
 840 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
 841 {
 842         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 843
 844         if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
 845                 return;
 846
 847         radv_update_multisample_state(cmd_buffer, pipeline);
 848
 849         cmd_buffer->scratch_size_needed =
 850                                   MAX2(cmd_buffer->scratch_size_needed,
 851                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
 852
 853         if (!cmd_buffer->state.emitted_pipeline ||
 854             cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
 855              pipeline->graphics.can_use_guardband)
 856                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
 857
 858         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
 859
 860         for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
 861                 if (!pipeline->shaders[i])
 862                         continue;
 863
 864                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 865                                    pipeline->shaders[i]->bo, 8);
 866         }
 867
 868         if (radv_pipeline_has_gs(pipeline))
 869                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 870                                    pipeline->gs_copy_shader->bo, 8);
 871
 872         if (unlikely(cmd_buffer->device->trace_bo))
 873                 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
 874
 875         cmd_buffer->state.emitted_pipeline = pipeline;
 876
 877         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
 878 }
 879
 880 static void
 881 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
 882 {
 883         si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
 884                           cmd_buffer->state.dynamic.viewport.viewports);
 885 }
 886
 887 static void
 888 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
 889 {
 890         uint32_t count = cmd_buffer->state.dynamic.scissor.count;
 891
 892         si_write_scissors(cmd_buffer->cs, 0, count,
 893                           cmd_buffer->state.dynamic.scissor.scissors,
 894                           cmd_buffer->state.dynamic.viewport.viewports,
 895                           cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
 896 }
 897
 898 static void
 899 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
 900 {
 901         if (!cmd_buffer->state.dynamic.discard_rectangle.count)
 902                 return;
 903
 904         radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
 905                                    cmd_buffer->state.dynamic.discard_rectangle.count * 2);
 906         for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
 907                 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
 908                 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
 909                 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
 910                                             S_028214_BR_Y(rect.offset.y + rect.extent.height));
 911         }
 912 }
 913
 914 static void
 915 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
 916 {
 917         unsigned width = cmd_buffer->state.dynamic.line_width * 8;
 918
 919         radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
 920                                S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
 921 }
 922
 923 static void
 924 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
 925 {
 926         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 927
 928         radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
 929         radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
 930 }
 931
 932 static void
 933 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
 934 {
 935         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 936
 937         radeon_set_context_reg_seq(cmd_buffer->cs,
 938                                    R_028430_DB_STENCILREFMASK, 2);
 939         radeon_emit(cmd_buffer->cs,
 940                     S_028430_STENCILTESTVAL(d->stencil_reference.front) |
 941                     S_028430_STENCILMASK(d->stencil_compare_mask.front) |
 942                     S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
 943                     S_028430_STENCILOPVAL(1));
 944         radeon_emit(cmd_buffer->cs,
 945                     S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
 946                     S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
 947                     S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
 948                     S_028434_STENCILOPVAL_BF(1));
 949 }
 950
 951 static void
 952 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
 953 {
 954         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 955
 956         radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
 957                                fui(d->depth_bounds.min));
 958         radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
 959                                fui(d->depth_bounds.max));
 960 }
 961
 962 static void
 963 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
 964 {
 965         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 966         unsigned slope = fui(d->depth_bias.slope * 16.0f);
 967         unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
 968
 969
 970         radeon_set_context_reg_seq(cmd_buffer->cs,
 971                                    R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
 972         radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
 973         radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
 974         radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
 975         radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
 976         radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
 977 }
 978
 979 static void
 980 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
 981                          int index,
 982                          struct radv_attachment_info *att,
 983                          struct radv_image *image,
 984                          VkImageLayout layout)
 985 {
 986         bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
 987         struct radv_color_buffer_info *cb = &att->cb;
 988         uint32_t cb_color_info = cb->cb_color_info;
 989
 990         if (!radv_layout_dcc_compressed(image, layout,
 991                                         radv_image_queue_family_mask(image,
 992                                                                      cmd_buffer->queue_family_index,
 993                                                                      cmd_buffer->queue_family_index))) {
 994                 cb_color_info &= C_028C70_DCC_ENABLE;
 995         }
 996
 997         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 998                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
 999                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1000                 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1001                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1002                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1003                 radeon_emit(cmd_buffer->cs, cb_color_info);
1004                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1005                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1006                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1007                 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1008                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1009                 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1010
1011                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1012                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1013                 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1014
1015                 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1016                                        S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1017         } else {
1018                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1019                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1020                 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1021                 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1022                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1023                 radeon_emit(cmd_buffer->cs, cb_color_info);
1024                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1025                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1026                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1027                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1028                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1029                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1030
1031                 if (is_vi) { /* DCC BASE */
1032                         radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1033                 }
1034         }
1035 }
1036
1037 static void
1038 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1039                              struct radv_ds_buffer_info *ds,
1040                              struct radv_image *image, VkImageLayout layout,
1041                              bool requires_cond_write)
1042 {
1043         uint32_t db_z_info = ds->db_z_info;
1044         uint32_t db_z_info_reg;
1045
1046         if (!radv_image_is_tc_compat_htile(image))
1047                 return;
1048
1049         if (!radv_layout_has_htile(image, layout,
1050                                    radv_image_queue_family_mask(image,
1051                                                                 cmd_buffer->queue_family_index,
1052                                                                 cmd_buffer->queue_family_index))) {
1053                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1054         }
1055
1056         db_z_info &= C_028040_ZRANGE_PRECISION;
1057
1058         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1059                 db_z_info_reg = R_028038_DB_Z_INFO;
1060         } else {
1061                 db_z_info_reg = R_028040_DB_Z_INFO;
1062         }
1063
1064         /* When we don't know the last fast clear value we need to emit a
1065          * conditional packet, otherwise we can update DB_Z_INFO directly.
1066          */
1067         if (requires_cond_write) {
1068                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1069
1070                 const uint32_t write_space = 0 << 8;    /* register */
1071                 const uint32_t poll_space = 1 << 4;     /* memory */
1072                 const uint32_t function = 3 << 0;       /* equal to the reference */
1073                 const uint32_t options = write_space | poll_space | function;
1074                 radeon_emit(cmd_buffer->cs, options);
1075
1076                 /* poll address - location of the depth clear value */
1077                 uint64_t va = radv_buffer_get_va(image->bo);
1078                 va += image->offset + image->clear_value_offset;
1079
1080                 /* In presence of stencil format, we have to adjust the base
1081                  * address because the first value is the stencil clear value.
1082                  */
1083                 if (vk_format_is_stencil(image->vk_format))
1084                         va += 4;
1085
1086                 radeon_emit(cmd_buffer->cs, va);
1087                 radeon_emit(cmd_buffer->cs, va >> 32);
1088
1089                 radeon_emit(cmd_buffer->cs, fui(0.0f));          /* reference value */
1090                 radeon_emit(cmd_buffer->cs, (uint32_t)-1);       /* comparison mask */
1091                 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1092                 radeon_emit(cmd_buffer->cs, 0u);                 /* write address high */
1093                 radeon_emit(cmd_buffer->cs, db_z_info);
1094         } else {
1095                 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1096         }
1097 }
1098
1099 static void
1100 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1101                       struct radv_ds_buffer_info *ds,
1102                       struct radv_image *image,
1103                       VkImageLayout layout)
1104 {
1105         uint32_t db_z_info = ds->db_z_info;
1106         uint32_t db_stencil_info = ds->db_stencil_info;
1107
1108         if (!radv_layout_has_htile(image, layout,
1109                                    radv_image_queue_family_mask(image,
1110                                                                 cmd_buffer->queue_family_index,
1111                                                                 cmd_buffer->queue_family_index))) {
1112                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1113                 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1114         }
1115
1116         radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1117         radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1118
1119
1120         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1121                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1122                 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1123                 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1124                 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1125
1126                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1127                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* DB_Z_INFO */
1128                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* DB_STENCIL_INFO */
1129                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* DB_Z_READ_BASE */
1130                 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32));        /* DB_Z_READ_BASE_HI */
1131                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* DB_STENCIL_READ_BASE */
1132                 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1133                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* DB_Z_WRITE_BASE */
1134                 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32));       /* DB_Z_WRITE_BASE_HI */
1135                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1136                 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1137
1138                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1139                 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1140                 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1141         } else {
1142                 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1143
1144                 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1145                 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1146                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* R_028040_DB_Z_INFO */
1147                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* R_028044_DB_STENCIL_INFO */
1148                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* R_028048_DB_Z_READ_BASE */
1149                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* R_02804C_DB_STENCIL_READ_BASE */
1150                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* R_028050_DB_Z_WRITE_BASE */
1151                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1152                 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1153                 radeon_emit(cmd_buffer->cs, ds->db_depth_slice);        /* R_02805C_DB_DEPTH_SLICE */
1154
1155         }
1156
1157         /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1158         radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1159
1160         radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1161                                ds->pa_su_poly_offset_db_fmt_cntl);
1162 }
1163
1164 /**
1165  * Update the fast clear depth/stencil values if the image is bound as a
1166  * depth/stencil buffer.
1167  */
1168 static void
1169 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1170                                 struct radv_image *image,
1171                                 VkClearDepthStencilValue ds_clear_value,
1172                                 VkImageAspectFlags aspects)
1173 {
1174         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1175         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1176         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1177         struct radv_attachment_info *att;
1178         uint32_t att_idx;
1179
1180         if (!framebuffer || !subpass)
1181                 return;
1182
1183         att_idx = subpass->depth_stencil_attachment.attachment;
1184         if (att_idx == VK_ATTACHMENT_UNUSED)
1185                 return;
1186
1187         att = &framebuffer->attachments[att_idx];
1188         if (att->attachment->image != image)
1189                 return;
1190
1191         radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1192         radeon_emit(cs, ds_clear_value.stencil);
1193         radeon_emit(cs, fui(ds_clear_value.depth));
1194
1195         /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1196          * only needed when clearing Z to 0.0.
1197          */
1198         if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1199             ds_clear_value.depth == 0.0) {
1200                 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1201
1202                 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1203                                              layout, false);
1204         }
1205 }
1206
1207 /**
1208  * Set the clear depth/stencil values to the image's metadata.
1209  */
1210 static void
1211 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1212                            struct radv_image *image,
1213                            VkClearDepthStencilValue ds_clear_value,
1214                            VkImageAspectFlags aspects)
1215 {
1216         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1217         uint64_t va = radv_buffer_get_va(image->bo);
1218         unsigned reg_offset = 0, reg_count = 0;
1219
1220         va += image->offset + image->clear_value_offset;
1221
1222         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1223                 ++reg_count;
1224         } else {
1225                 ++reg_offset;
1226                 va += 4;
1227         }
1228         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1229                 ++reg_count;
1230
1231         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1232         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1233                         S_370_WR_CONFIRM(1) |
1234                         S_370_ENGINE_SEL(V_370_PFP));
1235         radeon_emit(cs, va);
1236         radeon_emit(cs, va >> 32);
1237         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1238                 radeon_emit(cs, ds_clear_value.stencil);
1239         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1240                 radeon_emit(cs, fui(ds_clear_value.depth));
1241 }
1242
1243 /**
1244  * Update the clear depth/stencil values for this image.
1245  */
1246 void
1247 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1248                               struct radv_image *image,
1249                               VkClearDepthStencilValue ds_clear_value,
1250                               VkImageAspectFlags aspects)
1251 {
1252         assert(radv_image_has_htile(image));
1253
1254         radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1255
1256         radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1257                                         aspects);
1258 }
1259
1260 /**
1261  * Load the clear depth/stencil values from the image's metadata.
1262  */
1263 static void
1264 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1265                             struct radv_image *image)
1266 {
1267         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1268         VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1269         uint64_t va = radv_buffer_get_va(image->bo);
1270         unsigned reg_offset = 0, reg_count = 0;
1271
1272         va += image->offset + image->clear_value_offset;
1273
1274         if (!radv_image_has_htile(image))
1275                 return;
1276
1277         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1278                 ++reg_count;
1279         } else {
1280                 ++reg_offset;
1281                 va += 4;
1282         }
1283         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1284                 ++reg_count;
1285
1286         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1287         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1288                         COPY_DATA_DST_SEL(COPY_DATA_REG) |
1289                         (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1290         radeon_emit(cs, va);
1291         radeon_emit(cs, va >> 32);
1292         radeon_emit(cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1293         radeon_emit(cs, 0);
1294
1295         radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1296         radeon_emit(cs, 0);
1297 }
1298
1299 /*
1300  * With DCC some colors don't require CMASK elimination before being
1301  * used as a texture. This sets a predicate value to determine if the
1302  * cmask eliminate is required.
1303  */
1304 void
1305 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1306                                   struct radv_image *image,
1307                                   bool value)
1308 {
1309         uint64_t pred_val = value;
1310         uint64_t va = radv_buffer_get_va(image->bo);
1311         va += image->offset + image->dcc_pred_offset;
1312
1313         assert(radv_image_has_dcc(image));
1314
1315         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1316         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1317                                     S_370_WR_CONFIRM(1) |
1318                                     S_370_ENGINE_SEL(V_370_PFP));
1319         radeon_emit(cmd_buffer->cs, va);
1320         radeon_emit(cmd_buffer->cs, va >> 32);
1321         radeon_emit(cmd_buffer->cs, pred_val);
1322         radeon_emit(cmd_buffer->cs, pred_val >> 32);
1323 }
1324
1325 /**
1326  * Update the fast clear color values if the image is bound as a color buffer.
1327  */
1328 static void
1329 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1330                                    struct radv_image *image,
1331                                    int cb_idx,
1332                                    uint32_t color_values[2])
1333 {
1334         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1335         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1336         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1337         struct radv_attachment_info *att;
1338         uint32_t att_idx;
1339
1340         if (!framebuffer || !subpass)
1341                 return;
1342
1343         att_idx = subpass->color_attachments[cb_idx].attachment;
1344         if (att_idx == VK_ATTACHMENT_UNUSED)
1345                 return;
1346
1347         att = &framebuffer->attachments[att_idx];
1348         if (att->attachment->image != image)
1349                 return;
1350
1351         radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1352         radeon_emit(cs, color_values[0]);
1353         radeon_emit(cs, color_values[1]);
1354 }
1355
1356 /**
1357  * Set the clear color values to the image's metadata.
1358  */
1359 static void
1360 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1361                               struct radv_image *image,
1362                               uint32_t color_values[2])
1363 {
1364         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1365         uint64_t va = radv_buffer_get_va(image->bo);
1366
1367         va += image->offset + image->clear_value_offset;
1368
1369         assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1370
1371         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1372         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1373                         S_370_WR_CONFIRM(1) |
1374                         S_370_ENGINE_SEL(V_370_PFP));
1375         radeon_emit(cs, va);
1376         radeon_emit(cs, va >> 32);
1377         radeon_emit(cs, color_values[0]);
1378         radeon_emit(cs, color_values[1]);
1379 }
1380
1381 /**
1382  * Update the clear color values for this image.
1383  */
1384 void
1385 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1386                                  struct radv_image *image,
1387                                  int cb_idx,
1388                                  uint32_t color_values[2])
1389 {
1390         assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1391
1392         radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1393
1394         radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1395                                            color_values);
1396 }
1397
1398 /**
1399  * Load the clear color values from the image's metadata.
1400  */
1401 static void
1402 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1403                                struct radv_image *image,
1404                                int cb_idx)
1405 {
1406         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1407         uint64_t va = radv_buffer_get_va(image->bo);
1408
1409         va += image->offset + image->clear_value_offset;
1410
1411         if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1412                 return;
1413
1414         uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1415
1416         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1417         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1418                         COPY_DATA_DST_SEL(COPY_DATA_REG) |
1419                         COPY_DATA_COUNT_SEL);
1420         radeon_emit(cs, va);
1421         radeon_emit(cs, va >> 32);
1422         radeon_emit(cs, reg >> 2);
1423         radeon_emit(cs, 0);
1424
1425         radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1426         radeon_emit(cs, 0);
1427 }
1428
1429 static void
1430 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1431 {
1432         int i;
1433         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1434         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1435
1436         /* this may happen for inherited secondary recording */
1437         if (!framebuffer)
1438                 return;
1439
1440         for (i = 0; i < 8; ++i) {
1441                 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1442                         radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1443                                        S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1444                         continue;
1445                 }
1446
1447                 int idx = subpass->color_attachments[i].attachment;
1448                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1449                 struct radv_image *image = att->attachment->image;
1450                 VkImageLayout layout = subpass->color_attachments[i].layout;
1451
1452                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1453
1454                 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1455                 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1456
1457                 radv_load_color_clear_metadata(cmd_buffer, image, i);
1458         }
1459
1460         if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1461                 int idx = subpass->depth_stencil_attachment.attachment;
1462                 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1463                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1464                 struct radv_image *image = att->attachment->image;
1465                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1466                 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1467                                                                                 cmd_buffer->queue_family_index,
1468                                                                                 cmd_buffer->queue_family_index);
1469                 /* We currently don't support writing decompressed HTILE */
1470                 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1471                        radv_layout_is_htile_compressed(image, layout, queue_mask));
1472
1473                 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1474
1475                 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1476                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1477                         cmd_buffer->state.offset_scale = att->ds.offset_scale;
1478                 }
1479                 radv_load_ds_clear_metadata(cmd_buffer, image);
1480         } else {
1481                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1482                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1483                 else
1484                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1485
1486                 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1487                 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1488         }
1489         radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1490                                S_028208_BR_X(framebuffer->width) |
1491                                S_028208_BR_Y(framebuffer->height));
1492
1493         if (cmd_buffer->device->dfsm_allowed) {
1494                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1495                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1496         }
1497
1498         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1499 }
1500
1501 static void
1502 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1503 {
1504         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1505         struct radv_cmd_state *state = &cmd_buffer->state;
1506
1507         if (state->index_type != state->last_index_type) {
1508                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1509                         radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1510                                                    2, state->index_type);
1511                 } else {
1512                         radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1513                         radeon_emit(cs, state->index_type);
1514                 }
1515
1516                 state->last_index_type = state->index_type;
1517         }
1518
1519         radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1520         radeon_emit(cs, state->index_va);
1521         radeon_emit(cs, state->index_va >> 32);
1522
1523         radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1524         radeon_emit(cs, state->max_index_count);
1525
1526         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1527 }
1528
1529 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1530 {
1531         bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1532         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1533         uint32_t pa_sc_mode_cntl_1 =
1534                 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1535         uint32_t db_count_control;
1536
1537         if(!cmd_buffer->state.active_occlusion_queries) {
1538                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1539                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1540                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1541                             has_perfect_queries) {
1542                                 /* Re-enable out-of-order rasterization if the
1543                                  * bound pipeline supports it and if it's has
1544                                  * been disabled before starting any perfect
1545                                  * occlusion queries.
1546                                  */
1547                                 radeon_set_context_reg(cmd_buffer->cs,
1548                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1549                                                        pa_sc_mode_cntl_1);
1550                         }
1551                         db_count_control = 0;
1552                 } else {
1553                         db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1554                 }
1555         } else {
1556                 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1557                 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1558
1559                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1560                         db_count_control =
1561                                 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1562                                 S_028004_SAMPLE_RATE(sample_rate) |
1563                                 S_028004_ZPASS_ENABLE(1) |
1564                                 S_028004_SLICE_EVEN_ENABLE(1) |
1565                                 S_028004_SLICE_ODD_ENABLE(1);
1566
1567                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1568                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1569                             has_perfect_queries) {
1570                                 /* If the bound pipeline has enabled
1571                                  * out-of-order rasterization, we should
1572                                  * disable it before starting any perfect
1573                                  * occlusion queries.
1574                                  */
1575                                 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1576
1577                                 radeon_set_context_reg(cmd_buffer->cs,
1578                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1579                                                        pa_sc_mode_cntl_1);
1580                         }
1581                 } else {
1582                         db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1583                                 S_028004_SAMPLE_RATE(sample_rate);
1584                 }
1585         }
1586
1587         radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1588 }
1589
1590 static void
1591 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1592 {
1593         uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1594
1595         if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1596                 radv_emit_viewport(cmd_buffer);
1597
1598         if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1599             !cmd_buffer->device->physical_device->has_scissor_bug)
1600                 radv_emit_scissor(cmd_buffer);
1601
1602         if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1603                 radv_emit_line_width(cmd_buffer);
1604
1605         if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1606                 radv_emit_blend_constants(cmd_buffer);
1607
1608         if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1609                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1610                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1611                 radv_emit_stencil(cmd_buffer);
1612
1613         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1614                 radv_emit_depth_bounds(cmd_buffer);
1615
1616         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1617                 radv_emit_depth_bias(cmd_buffer);
1618
1619         if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1620                 radv_emit_discard_rectangle(cmd_buffer);
1621
1622         cmd_buffer->state.dirty &= ~states;
1623 }
1624
1625 static void
1626 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1627                             VkPipelineBindPoint bind_point)
1628 {
1629         struct radv_descriptor_state *descriptors_state =
1630                 radv_get_descriptors_state(cmd_buffer, bind_point);
1631         struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1632         unsigned bo_offset;
1633
1634         if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1635                                          set->mapped_ptr,
1636                                          &bo_offset))
1637                 return;
1638
1639         set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1640         set->va += bo_offset;
1641 }
1642
1643 static void
1644 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1645                                     VkPipelineBindPoint bind_point)
1646 {
1647         struct radv_descriptor_state *descriptors_state =
1648                 radv_get_descriptors_state(cmd_buffer, bind_point);
1649         uint32_t size = MAX_SETS * 2 * 4;
1650         uint32_t offset;
1651         void *ptr;
1652
1653         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1654                                           256, &offset, &ptr))
1655                 return;
1656
1657         for (unsigned i = 0; i < MAX_SETS; i++) {
1658                 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1659                 uint64_t set_va = 0;
1660                 struct radv_descriptor_set *set = descriptors_state->sets[i];
1661                 if (descriptors_state->valid & (1u << i))
1662                         set_va = set->va;
1663                 uptr[0] = set_va & 0xffffffff;
1664                 uptr[1] = set_va >> 32;
1665         }
1666
1667         uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1668         va += offset;
1669
1670         if (cmd_buffer->state.pipeline) {
1671                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1672                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1673                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1674
1675                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1676                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1677                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1678
1679                 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1680                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1681                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1682
1683                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1684                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1685                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1686
1687                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1688                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1689                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1690         }
1691
1692         if (cmd_buffer->state.compute_pipeline)
1693                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1694                                            AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1695 }
1696
1697 static void
1698 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1699                        VkShaderStageFlags stages)
1700 {
1701         VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1702                                          VK_PIPELINE_BIND_POINT_COMPUTE :
1703                                          VK_PIPELINE_BIND_POINT_GRAPHICS;
1704         struct radv_descriptor_state *descriptors_state =
1705                 radv_get_descriptors_state(cmd_buffer, bind_point);
1706
1707         if (!descriptors_state->dirty)
1708                 return;
1709
1710         if (descriptors_state->push_dirty)
1711                 radv_flush_push_descriptors(cmd_buffer, bind_point);
1712
1713         if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1714             (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1715                 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1716         }
1717
1718         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1719                                                            cmd_buffer->cs,
1720                                                            MAX_SETS * MESA_SHADER_STAGES * 4);
1721
1722         if (cmd_buffer->state.pipeline) {
1723                 radv_foreach_stage(stage, stages) {
1724                         if (!cmd_buffer->state.pipeline->shaders[stage])
1725                                 continue;
1726
1727                         radv_emit_descriptor_pointers(cmd_buffer,
1728                                                       cmd_buffer->state.pipeline,
1729                                                       descriptors_state, stage);
1730                 }
1731         }
1732
1733         if (cmd_buffer->state.compute_pipeline &&
1734             (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1735                 radv_emit_descriptor_pointers(cmd_buffer,
1736                                               cmd_buffer->state.compute_pipeline,
1737                                               descriptors_state,
1738                                               MESA_SHADER_COMPUTE);
1739         }
1740
1741         descriptors_state->dirty = 0;
1742         descriptors_state->push_dirty = false;
1743
1744         if (unlikely(cmd_buffer->device->trace_bo))
1745                 radv_save_descriptors(cmd_buffer, bind_point);
1746
1747         assert(cmd_buffer->cs->cdw <= cdw_max);
1748 }
1749
1750 static void
1751 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1752                      VkShaderStageFlags stages)
1753 {
1754         struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1755                                          ? cmd_buffer->state.compute_pipeline
1756                                          : cmd_buffer->state.pipeline;
1757         VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1758                                          VK_PIPELINE_BIND_POINT_COMPUTE :
1759                                          VK_PIPELINE_BIND_POINT_GRAPHICS;
1760         struct radv_descriptor_state *descriptors_state =
1761                 radv_get_descriptors_state(cmd_buffer, bind_point);
1762         struct radv_pipeline_layout *layout = pipeline->layout;
1763         struct radv_shader_variant *shader, *prev_shader;
1764         unsigned offset;
1765         void *ptr;
1766         uint64_t va;
1767
1768         stages &= cmd_buffer->push_constant_stages;
1769         if (!stages ||
1770             (!layout->push_constant_size && !layout->dynamic_offset_count))
1771                 return;
1772
1773         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1774                                           16 * layout->dynamic_offset_count,
1775                                           256, &offset, &ptr))
1776                 return;
1777
1778         memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1779         memcpy((char*)ptr + layout->push_constant_size,
1780                descriptors_state->dynamic_buffers,
1781                16 * layout->dynamic_offset_count);
1782
1783         va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1784         va += offset;
1785
1786         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1787                                                            cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1788
1789         prev_shader = NULL;
1790         radv_foreach_stage(stage, stages) {
1791                 shader = radv_get_shader(pipeline, stage);
1792
1793                 /* Avoid redundantly emitting the address for merged stages. */
1794                 if (shader && shader != prev_shader) {
1795                         radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1796                                                    AC_UD_PUSH_CONSTANTS, va);
1797
1798                         prev_shader = shader;
1799                 }
1800         }
1801
1802         cmd_buffer->push_constant_stages &= ~stages;
1803         assert(cmd_buffer->cs->cdw <= cdw_max);
1804 }
1805
1806 static void
1807 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1808                               bool pipeline_is_dirty)
1809 {
1810         if ((pipeline_is_dirty ||
1811             (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1812             cmd_buffer->state.pipeline->vertex_elements.count &&
1813             radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1814                 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1815                 unsigned vb_offset;
1816                 void *vb_ptr;
1817                 uint32_t i = 0;
1818                 uint32_t count = velems->count;
1819                 uint64_t va;
1820
1821                 /* allocate some descriptor state for vertex buffers */
1822                 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1823                                                   &vb_offset, &vb_ptr))
1824                         return;
1825
1826                 for (i = 0; i < count; i++) {
1827                         uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1828                         uint32_t offset;
1829                         int vb = velems->binding[i];
1830                         struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1831                         uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1832
1833                         va = radv_buffer_get_va(buffer->bo);
1834
1835                         offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1836                         va += offset + buffer->offset;
1837                         desc[0] = va;
1838                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1839                         if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1840                                 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1841                         else
1842                                 desc[2] = buffer->size - offset;
1843                         desc[3] = velems->rsrc_word3[i];
1844                 }
1845
1846                 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1847                 va += vb_offset;
1848
1849                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1850                                            AC_UD_VS_VERTEX_BUFFERS, va);
1851
1852                 cmd_buffer->state.vb_va = va;
1853                 cmd_buffer->state.vb_size = count * 16;
1854                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1855         }
1856         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1857 }
1858
1859 static void
1860 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1861 {
1862         radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1863         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1864         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1865 }
1866
1867 static void
1868 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1869                          bool instanced_draw, bool indirect_draw,
1870                          uint32_t draw_vertex_count)
1871 {
1872         struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1873         struct radv_cmd_state *state = &cmd_buffer->state;
1874         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1875         uint32_t ia_multi_vgt_param;
1876         int32_t primitive_reset_en;
1877
1878         /* Draw state. */
1879         ia_multi_vgt_param =
1880                 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1881                                           indirect_draw, draw_vertex_count);
1882
1883         if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1884                 if (info->chip_class >= GFX9) {
1885                         radeon_set_uconfig_reg_idx(cs,
1886                                                    R_030960_IA_MULTI_VGT_PARAM,
1887                                                    4, ia_multi_vgt_param);
1888                 } else if (info->chip_class >= CIK) {
1889                         radeon_set_context_reg_idx(cs,
1890                                                    R_028AA8_IA_MULTI_VGT_PARAM,
1891                                                    1, ia_multi_vgt_param);
1892                 } else {
1893                         radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1894                                                ia_multi_vgt_param);
1895                 }
1896                 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1897         }
1898
1899         /* Primitive restart. */
1900         primitive_reset_en =
1901                 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1902
1903         if (primitive_reset_en != state->last_primitive_reset_en) {
1904                 state->last_primitive_reset_en = primitive_reset_en;
1905                 if (info->chip_class >= GFX9) {
1906                         radeon_set_uconfig_reg(cs,
1907                                                R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1908                                                primitive_reset_en);
1909                 } else {
1910                         radeon_set_context_reg(cs,
1911                                                R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1912                                                primitive_reset_en);
1913                 }
1914         }
1915
1916         if (primitive_reset_en) {
1917                 uint32_t primitive_reset_index =
1918                         state->index_type ? 0xffffffffu : 0xffffu;
1919
1920                 if (primitive_reset_index != state->last_primitive_reset_index) {
1921                         radeon_set_context_reg(cs,
1922                                                R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1923                                                primitive_reset_index);
1924                         state->last_primitive_reset_index = primitive_reset_index;
1925                 }
1926         }
1927 }
1928
1929 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1930                              VkPipelineStageFlags src_stage_mask)
1931 {
1932         if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1933                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1934                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1935                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1936                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1937         }
1938
1939         if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1940                               VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1941                               VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1942                               VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1943                               VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1944                               VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1945                               VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1946                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1947                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1948                               VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1949                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1950                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1951         } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1952                                      VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1953                                      VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1954                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1955         }
1956 }
1957
1958 static enum radv_cmd_flush_bits
1959 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1960                       VkAccessFlags src_flags,
1961                       struct radv_image *image)
1962 {
1963         enum radv_cmd_flush_bits flush_bits = 0;
1964         uint32_t b;
1965         for_each_bit(b, src_flags) {
1966                 switch ((VkAccessFlagBits)(1 << b)) {
1967                 case VK_ACCESS_SHADER_WRITE_BIT:
1968                         flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1969                         break;
1970                 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1971                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
1972                         if (!image || (image && radv_image_has_CB_metadata(image))) {
1973                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1974                         }
1975                         break;
1976                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1977                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
1978                         if (!image || (image && radv_image_has_htile(image))) {
1979                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1980                         }
1981                         break;
1982                 case VK_ACCESS_TRANSFER_WRITE_BIT:
1983                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1984                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1985                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1986                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1987                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
1988                         break;
1989                 default:
1990                         break;
1991                 }
1992         }
1993         return flush_bits;
1994 }
1995
1996 static enum radv_cmd_flush_bits
1997 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1998                       VkAccessFlags dst_flags,
1999                       struct radv_image *image)
2000 {
2001         enum radv_cmd_flush_bits flush_bits = 0;
2002         uint32_t b;
2003         for_each_bit(b, dst_flags) {
2004                 switch ((VkAccessFlagBits)(1 << b)) {
2005                 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2006                 case VK_ACCESS_INDEX_READ_BIT:
2007                         break;
2008                 case VK_ACCESS_UNIFORM_READ_BIT:
2009                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2010                         break;
2011                 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2012                 case VK_ACCESS_SHADER_READ_BIT:
2013                 case VK_ACCESS_TRANSFER_READ_BIT:
2014                 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2015                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2016                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
2017                         break;
2018                 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2019                         /* TODO: change to image && when the image gets passed
2020                          * through from the subpass. */
2021                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2022                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2023                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2024                         break;
2025                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2026                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2027                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2028                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2029                         break;
2030                 default:
2031                         break;
2032                 }
2033         }
2034         return flush_bits;
2035 }
2036
2037 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2038 {
2039         cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2040                                                               NULL);
2041         radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2042         cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2043                                                               NULL);
2044 }
2045
2046 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2047                                                  struct radv_subpass_attachment att)
2048 {
2049         unsigned idx = att.attachment;
2050         struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2051         VkImageSubresourceRange range;
2052         range.aspectMask = 0;
2053         range.baseMipLevel = view->base_mip;
2054         range.levelCount = 1;
2055         range.baseArrayLayer = view->base_layer;
2056         range.layerCount = cmd_buffer->state.framebuffer->layers;
2057
2058         radv_handle_image_transition(cmd_buffer,
2059                                      view->image,
2060                                      cmd_buffer->state.attachments[idx].current_layout,
2061                                      att.layout, 0, 0, &range,
2062                                      cmd_buffer->state.attachments[idx].pending_clear_aspects);
2063
2064         cmd_buffer->state.attachments[idx].current_layout = att.layout;
2065
2066
2067 }
2068
2069 void
2070 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2071                             const struct radv_subpass *subpass, bool transitions)
2072 {
2073         if (transitions) {
2074                 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2075
2076                 for (unsigned i = 0; i < subpass->color_count; ++i) {
2077                         if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2078                                 radv_handle_subpass_image_transition(cmd_buffer,
2079                                                                      subpass->color_attachments[i]);
2080                 }
2081
2082                 for (unsigned i = 0; i < subpass->input_count; ++i) {
2083                         radv_handle_subpass_image_transition(cmd_buffer,
2084                                                         subpass->input_attachments[i]);
2085                 }
2086
2087                 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2088                         radv_handle_subpass_image_transition(cmd_buffer,
2089                                                         subpass->depth_stencil_attachment);
2090                 }
2091         }
2092
2093         cmd_buffer->state.subpass = subpass;
2094
2095         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2096 }
2097
2098 static VkResult
2099 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2100                                  struct radv_render_pass *pass,
2101                                  const VkRenderPassBeginInfo *info)
2102 {
2103         struct radv_cmd_state *state = &cmd_buffer->state;
2104
2105         if (pass->attachment_count == 0) {
2106                 state->attachments = NULL;
2107                 return VK_SUCCESS;
2108         }
2109
2110         state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2111                                         pass->attachment_count *
2112                                         sizeof(state->attachments[0]),
2113                                         8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2114         if (state->attachments == NULL) {
2115                 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2116                 return cmd_buffer->record_result;
2117         }
2118
2119         for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2120                 struct radv_render_pass_attachment *att = &pass->attachments[i];
2121                 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2122                 VkImageAspectFlags clear_aspects = 0;
2123
2124                 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2125                         /* color attachment */
2126                         if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2127                                 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2128                         }
2129                 } else {
2130                         /* depthstencil attachment */
2131                         if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2132                             att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2133                                 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2134                                 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2135                                     att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2136                                         clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2137                         }
2138                         if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2139                             att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2140                                 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2141                         }
2142                 }
2143
2144                 state->attachments[i].pending_clear_aspects = clear_aspects;
2145                 state->attachments[i].cleared_views = 0;
2146                 if (clear_aspects && info) {
2147                         assert(info->clearValueCount > i);
2148                         state->attachments[i].clear_value = info->pClearValues[i];
2149                 }
2150
2151                 state->attachments[i].current_layout = att->initial_layout;
2152         }
2153
2154         return VK_SUCCESS;
2155 }
2156
2157 VkResult radv_AllocateCommandBuffers(
2158         VkDevice _device,
2159         const VkCommandBufferAllocateInfo *pAllocateInfo,
2160         VkCommandBuffer *pCommandBuffers)
2161 {
2162         RADV_FROM_HANDLE(radv_device, device, _device);
2163         RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2164
2165         VkResult result = VK_SUCCESS;
2166         uint32_t i;
2167
2168         for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2169
2170                 if (!list_empty(&pool->free_cmd_buffers)) {
2171                         struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2172
2173                         list_del(&cmd_buffer->pool_link);
2174                         list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2175
2176                         result = radv_reset_cmd_buffer(cmd_buffer);
2177                         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2178                         cmd_buffer->level = pAllocateInfo->level;
2179
2180                         pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2181                 } else {
2182                         result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2183                                                         &pCommandBuffers[i]);
2184                 }
2185                 if (result != VK_SUCCESS)
2186                         break;
2187         }
2188
2189         if (result != VK_SUCCESS) {
2190                 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2191                                         i, pCommandBuffers);
2192
2193                 /* From the Vulkan 1.0.66 spec:
2194                  *
2195                  * "vkAllocateCommandBuffers can be used to create multiple
2196                  *  command buffers. If the creation of any of those command
2197                  *  buffers fails, the implementation must destroy all
2198                  *  successfully created command buffer objects from this
2199                  *  command, set all entries of the pCommandBuffers array to
2200                  *  NULL and return the error."
2201                  */
2202                 memset(pCommandBuffers, 0,
2203                        sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2204         }
2205
2206         return result;
2207 }
2208
2209 void radv_FreeCommandBuffers(
2210         VkDevice device,
2211         VkCommandPool commandPool,
2212         uint32_t commandBufferCount,
2213         const VkCommandBuffer *pCommandBuffers)
2214 {
2215         for (uint32_t i = 0; i < commandBufferCount; i++) {
2216                 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2217
2218                 if (cmd_buffer) {
2219                         if (cmd_buffer->pool) {
2220                                 list_del(&cmd_buffer->pool_link);
2221                                 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2222                         } else
2223                                 radv_cmd_buffer_destroy(cmd_buffer);
2224
2225                 }
2226         }
2227 }
2228
2229 VkResult radv_ResetCommandBuffer(
2230         VkCommandBuffer commandBuffer,
2231         VkCommandBufferResetFlags flags)
2232 {
2233         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2234         return radv_reset_cmd_buffer(cmd_buffer);
2235 }
2236
2237 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2238 {
2239         struct radv_device *device = cmd_buffer->device;
2240         if (device->gfx_init) {
2241                 uint64_t va = radv_buffer_get_va(device->gfx_init);
2242                 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2243                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2244                 radeon_emit(cmd_buffer->cs, va);
2245                 radeon_emit(cmd_buffer->cs, va >> 32);
2246                 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2247         } else
2248                 si_init_config(cmd_buffer);
2249 }
2250
2251 VkResult radv_BeginCommandBuffer(
2252         VkCommandBuffer commandBuffer,
2253         const VkCommandBufferBeginInfo *pBeginInfo)
2254 {
2255         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2256         VkResult result = VK_SUCCESS;
2257
2258         if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2259                 /* If the command buffer has already been resetted with
2260                  * vkResetCommandBuffer, no need to do it again.
2261                  */
2262                 result = radv_reset_cmd_buffer(cmd_buffer);
2263                 if (result != VK_SUCCESS)
2264                         return result;
2265         }
2266
2267         memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2268         cmd_buffer->state.last_primitive_reset_en = -1;
2269         cmd_buffer->state.last_index_type = -1;
2270         cmd_buffer->state.last_num_instances = -1;
2271         cmd_buffer->state.last_vertex_offset = -1;
2272         cmd_buffer->state.last_first_instance = -1;
2273         cmd_buffer->usage_flags = pBeginInfo->flags;
2274
2275         /* setup initial configuration into command buffer */
2276         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2277                 switch (cmd_buffer->queue_family_index) {
2278                 case RADV_QUEUE_GENERAL:
2279                         emit_gfx_buffer_state(cmd_buffer);
2280                         break;
2281                 case RADV_QUEUE_COMPUTE:
2282                         si_init_compute(cmd_buffer);
2283                         break;
2284                 case RADV_QUEUE_TRANSFER:
2285                 default:
2286                         break;
2287                 }
2288         }
2289
2290         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2291             (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2292                 assert(pBeginInfo->pInheritanceInfo);
2293                 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2294                 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2295
2296                 struct radv_subpass *subpass =
2297                         &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2298
2299                 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2300                 if (result != VK_SUCCESS)
2301                         return result;
2302
2303                 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2304         }
2305
2306         if (unlikely(cmd_buffer->device->trace_bo)) {
2307                 struct radv_device *device = cmd_buffer->device;
2308
2309                 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2310                                    device->trace_bo, 8);
2311
2312                 radv_cmd_buffer_trace_emit(cmd_buffer);
2313         }
2314
2315         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2316
2317         return result;
2318 }
2319
2320 void radv_CmdBindVertexBuffers(
2321         VkCommandBuffer                             commandBuffer,
2322         uint32_t                                    firstBinding,
2323         uint32_t                                    bindingCount,
2324         const VkBuffer*                             pBuffers,
2325         const VkDeviceSize*                         pOffsets)
2326 {
2327         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2328         struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2329         bool changed = false;
2330
2331         /* We have to defer setting up vertex buffer since we need the buffer
2332          * stride from the pipeline. */
2333
2334         assert(firstBinding + bindingCount <= MAX_VBS);
2335         for (uint32_t i = 0; i < bindingCount; i++) {
2336                 uint32_t idx = firstBinding + i;
2337
2338                 if (!changed &&
2339                     (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2340                      vb[idx].offset != pOffsets[i])) {
2341                         changed = true;
2342                 }
2343
2344                 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2345                 vb[idx].offset = pOffsets[i];
2346
2347                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2348                                    vb[idx].buffer->bo, 8);
2349         }
2350
2351         if (!changed) {
2352                 /* No state changes. */
2353                 return;
2354         }
2355
2356         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2357 }
2358
2359 void radv_CmdBindIndexBuffer(
2360         VkCommandBuffer                             commandBuffer,
2361         VkBuffer buffer,
2362         VkDeviceSize offset,
2363         VkIndexType indexType)
2364 {
2365         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2366         RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2367
2368         if (cmd_buffer->state.index_buffer == index_buffer &&
2369             cmd_buffer->state.index_offset == offset &&
2370             cmd_buffer->state.index_type == indexType) {
2371                 /* No state changes. */
2372                 return;
2373         }
2374
2375         cmd_buffer->state.index_buffer = index_buffer;
2376         cmd_buffer->state.index_offset = offset;
2377         cmd_buffer->state.index_type = indexType; /* vk matches hw */
2378         cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2379         cmd_buffer->state.index_va += index_buffer->offset + offset;
2380
2381         int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2382         cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2383         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2384         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2385 }
2386
2387
2388 static void
2389 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2390                          VkPipelineBindPoint bind_point,
2391                          struct radv_descriptor_set *set, unsigned idx)
2392 {
2393         struct radeon_winsys *ws = cmd_buffer->device->ws;
2394
2395         radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2396         if (!set)
2397                 return;
2398
2399         assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2400
2401         if (!cmd_buffer->device->use_global_bo_list) {
2402                 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2403                         if (set->descriptors[j])
2404                                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2405         }
2406
2407         if(set->bo)
2408                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2409 }
2410
2411 void radv_CmdBindDescriptorSets(
2412         VkCommandBuffer                             commandBuffer,
2413         VkPipelineBindPoint                         pipelineBindPoint,
2414         VkPipelineLayout                            _layout,
2415         uint32_t                                    firstSet,
2416         uint32_t                                    descriptorSetCount,
2417         const VkDescriptorSet*                      pDescriptorSets,
2418         uint32_t                                    dynamicOffsetCount,
2419         const uint32_t*                             pDynamicOffsets)
2420 {
2421         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2422         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2423         unsigned dyn_idx = 0;
2424
2425         const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2426         struct radv_descriptor_state *descriptors_state =
2427                 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2428
2429         for (unsigned i = 0; i < descriptorSetCount; ++i) {
2430                 unsigned idx = i + firstSet;
2431                 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2432                 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2433
2434                 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2435                         unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2436                         uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2437                         assert(dyn_idx < dynamicOffsetCount);
2438
2439                         struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2440                         uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2441                         dst[0] = va;
2442                         dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2443                         dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2444                         dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2445                                  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2446                                  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2447                                  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2448                                  S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2449                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2450                         cmd_buffer->push_constant_stages |=
2451                                              set->layout->dynamic_shader_stages;
2452                 }
2453         }
2454 }
2455
2456 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2457                                           struct radv_descriptor_set *set,
2458                                           struct radv_descriptor_set_layout *layout,
2459                                           VkPipelineBindPoint bind_point)
2460 {
2461         struct radv_descriptor_state *descriptors_state =
2462                 radv_get_descriptors_state(cmd_buffer, bind_point);
2463         set->size = layout->size;
2464         set->layout = layout;
2465
2466         if (descriptors_state->push_set.capacity < set->size) {
2467                 size_t new_size = MAX2(set->size, 1024);
2468                 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2469                 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2470
2471                 free(set->mapped_ptr);
2472                 set->mapped_ptr = malloc(new_size);
2473
2474                 if (!set->mapped_ptr) {
2475                         descriptors_state->push_set.capacity = 0;
2476                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2477                         return false;
2478                 }
2479
2480                 descriptors_state->push_set.capacity = new_size;
2481         }
2482
2483         return true;
2484 }
2485
2486 void radv_meta_push_descriptor_set(
2487         struct radv_cmd_buffer*              cmd_buffer,
2488         VkPipelineBindPoint                  pipelineBindPoint,
2489         VkPipelineLayout                     _layout,
2490         uint32_t                             set,
2491         uint32_t                             descriptorWriteCount,
2492         const VkWriteDescriptorSet*          pDescriptorWrites)
2493 {
2494         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2495         struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2496         unsigned bo_offset;
2497
2498         assert(set == 0);
2499         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2500
2501         push_set->size = layout->set[set].layout->size;
2502         push_set->layout = layout->set[set].layout;
2503
2504         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2505                                           &bo_offset,
2506                                           (void**) &push_set->mapped_ptr))
2507                 return;
2508
2509         push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2510         push_set->va += bo_offset;
2511
2512         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2513                                     radv_descriptor_set_to_handle(push_set),
2514                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2515
2516         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2517 }
2518
2519 void radv_CmdPushDescriptorSetKHR(
2520         VkCommandBuffer                             commandBuffer,
2521         VkPipelineBindPoint                         pipelineBindPoint,
2522         VkPipelineLayout                            _layout,
2523         uint32_t                                    set,
2524         uint32_t                                    descriptorWriteCount,
2525         const VkWriteDescriptorSet*                 pDescriptorWrites)
2526 {
2527         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2528         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2529         struct radv_descriptor_state *descriptors_state =
2530                 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2531         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2532
2533         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2534
2535         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2536                                            layout->set[set].layout,
2537                                            pipelineBindPoint))
2538                 return;
2539
2540         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2541                                     radv_descriptor_set_to_handle(push_set),
2542                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2543
2544         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2545         descriptors_state->push_dirty = true;
2546 }
2547
2548 void radv_CmdPushDescriptorSetWithTemplateKHR(
2549         VkCommandBuffer                             commandBuffer,
2550         VkDescriptorUpdateTemplateKHR               descriptorUpdateTemplate,
2551         VkPipelineLayout                            _layout,
2552         uint32_t                                    set,
2553         const void*                                 pData)
2554 {
2555         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2556         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2557         RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2558         struct radv_descriptor_state *descriptors_state =
2559                 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2560         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2561
2562         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2563
2564         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2565                                            layout->set[set].layout,
2566                                            templ->bind_point))
2567                 return;
2568
2569         radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2570                                                  descriptorUpdateTemplate, pData);
2571
2572         radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2573         descriptors_state->push_dirty = true;
2574 }
2575
2576 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2577                            VkPipelineLayout layout,
2578                            VkShaderStageFlags stageFlags,
2579                            uint32_t offset,
2580                            uint32_t size,
2581                            const void* pValues)
2582 {
2583         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2584         memcpy(cmd_buffer->push_constants + offset, pValues, size);
2585         cmd_buffer->push_constant_stages |= stageFlags;
2586 }
2587
2588 VkResult radv_EndCommandBuffer(
2589         VkCommandBuffer                             commandBuffer)
2590 {
2591         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2592
2593         if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2594                 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2595                         cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2596                 si_emit_cache_flush(cmd_buffer);
2597         }
2598
2599         /* Make sure CP DMA is idle at the end of IBs because the kernel
2600          * doesn't wait for it.
2601          */
2602         si_cp_dma_wait_for_idle(cmd_buffer);
2603
2604         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2605
2606         if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2607                 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2608
2609         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2610
2611         return cmd_buffer->record_result;
2612 }
2613
2614 static void
2615 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2616 {
2617         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2618
2619         if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2620                 return;
2621
2622         cmd_buffer->state.emitted_compute_pipeline = pipeline;
2623
2624         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2625         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2626
2627         cmd_buffer->compute_scratch_size_needed =
2628                                   MAX2(cmd_buffer->compute_scratch_size_needed,
2629                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2630
2631         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2632                            pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
2633
2634         if (unlikely(cmd_buffer->device->trace_bo))
2635                 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2636 }
2637
2638 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2639                                             VkPipelineBindPoint bind_point)
2640 {
2641         struct radv_descriptor_state *descriptors_state =
2642                 radv_get_descriptors_state(cmd_buffer, bind_point);
2643
2644         descriptors_state->dirty |= descriptors_state->valid;
2645 }
2646
2647 void radv_CmdBindPipeline(
2648         VkCommandBuffer                             commandBuffer,
2649         VkPipelineBindPoint                         pipelineBindPoint,
2650         VkPipeline                                  _pipeline)
2651 {
2652         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2653         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2654
2655         switch (pipelineBindPoint) {
2656         case VK_PIPELINE_BIND_POINT_COMPUTE:
2657                 if (cmd_buffer->state.compute_pipeline == pipeline)
2658                         return;
2659                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2660
2661                 cmd_buffer->state.compute_pipeline = pipeline;
2662                 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2663                 break;
2664         case VK_PIPELINE_BIND_POINT_GRAPHICS:
2665                 if (cmd_buffer->state.pipeline == pipeline)
2666                         return;
2667                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2668
2669                 cmd_buffer->state.pipeline = pipeline;
2670                 if (!pipeline)
2671                         break;
2672
2673                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2674                 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2675
2676                 /* the new vertex shader might not have the same user regs */
2677                 cmd_buffer->state.last_first_instance = -1;
2678                 cmd_buffer->state.last_vertex_offset = -1;
2679
2680                 /* Prefetch all pipeline shaders at first draw time. */
2681                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2682
2683                 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2684
2685                 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2686                         cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2687                 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2688                         cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2689
2690                 if (radv_pipeline_has_tess(pipeline))
2691                         cmd_buffer->tess_rings_needed = true;
2692
2693                 if (radv_pipeline_has_gs(pipeline)) {
2694                         struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2695                                                                              AC_UD_SCRATCH_RING_OFFSETS);
2696                         if (cmd_buffer->ring_offsets_idx == -1)
2697                                 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2698                         else if (loc->sgpr_idx != -1)
2699                                 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2700                 }
2701                 break;
2702         default:
2703                 assert(!"invalid bind point");
2704                 break;
2705         }
2706 }
2707
2708 void radv_CmdSetViewport(
2709         VkCommandBuffer                             commandBuffer,
2710         uint32_t                                    firstViewport,
2711         uint32_t                                    viewportCount,
2712         const VkViewport*                           pViewports)
2713 {
2714         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2715         struct radv_cmd_state *state = &cmd_buffer->state;
2716         MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2717
2718         assert(firstViewport < MAX_VIEWPORTS);
2719         assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2720
2721         memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2722                viewportCount * sizeof(*pViewports));
2723
2724         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2725 }
2726
2727 void radv_CmdSetScissor(
2728         VkCommandBuffer                             commandBuffer,
2729         uint32_t                                    firstScissor,
2730         uint32_t                                    scissorCount,
2731         const VkRect2D*                             pScissors)
2732 {
2733         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2734         struct radv_cmd_state *state = &cmd_buffer->state;
2735         MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2736
2737         assert(firstScissor < MAX_SCISSORS);
2738         assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2739
2740         memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2741                scissorCount * sizeof(*pScissors));
2742
2743         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2744 }
2745
2746 void radv_CmdSetLineWidth(
2747         VkCommandBuffer                             commandBuffer,
2748         float                                       lineWidth)
2749 {
2750         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2751         cmd_buffer->state.dynamic.line_width = lineWidth;
2752         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2753 }
2754
2755 void radv_CmdSetDepthBias(
2756         VkCommandBuffer                             commandBuffer,
2757         float                                       depthBiasConstantFactor,
2758         float                                       depthBiasClamp,
2759         float                                       depthBiasSlopeFactor)
2760 {
2761         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2762
2763         cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2764         cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2765         cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2766
2767         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2768 }
2769
2770 void radv_CmdSetBlendConstants(
2771         VkCommandBuffer                             commandBuffer,
2772         const float                                 blendConstants[4])
2773 {
2774         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2775
2776         memcpy(cmd_buffer->state.dynamic.blend_constants,
2777                blendConstants, sizeof(float) * 4);
2778
2779         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2780 }
2781
2782 void radv_CmdSetDepthBounds(
2783         VkCommandBuffer                             commandBuffer,
2784         float                                       minDepthBounds,
2785         float                                       maxDepthBounds)
2786 {
2787         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2788
2789         cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2790         cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2791
2792         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2793 }
2794
2795 void radv_CmdSetStencilCompareMask(
2796         VkCommandBuffer                             commandBuffer,
2797         VkStencilFaceFlags                          faceMask,
2798         uint32_t                                    compareMask)
2799 {
2800         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2801
2802         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2803                 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2804         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2805                 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2806
2807         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2808 }
2809
2810 void radv_CmdSetStencilWriteMask(
2811         VkCommandBuffer                             commandBuffer,
2812         VkStencilFaceFlags                          faceMask,
2813         uint32_t                                    writeMask)
2814 {
2815         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2816
2817         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2818                 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2819         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2820                 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2821
2822         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2823 }
2824
2825 void radv_CmdSetStencilReference(
2826         VkCommandBuffer                             commandBuffer,
2827         VkStencilFaceFlags                          faceMask,
2828         uint32_t                                    reference)
2829 {
2830         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2831
2832         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2833                 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2834         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2835                 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2836
2837         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2838 }
2839
2840 void radv_CmdSetDiscardRectangleEXT(
2841         VkCommandBuffer                             commandBuffer,
2842         uint32_t                                    firstDiscardRectangle,
2843         uint32_t                                    discardRectangleCount,
2844         const VkRect2D*                             pDiscardRectangles)
2845 {
2846         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2847         struct radv_cmd_state *state = &cmd_buffer->state;
2848         MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2849
2850         assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2851         assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2852
2853         typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2854                      pDiscardRectangles, discardRectangleCount);
2855
2856         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2857 }
2858
2859 void radv_CmdExecuteCommands(
2860         VkCommandBuffer                             commandBuffer,
2861         uint32_t                                    commandBufferCount,
2862         const VkCommandBuffer*                      pCmdBuffers)
2863 {
2864         RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2865
2866         assert(commandBufferCount > 0);
2867
2868         /* Emit pending flushes on primary prior to executing secondary */
2869         si_emit_cache_flush(primary);
2870
2871         for (uint32_t i = 0; i < commandBufferCount; i++) {
2872                 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2873
2874                 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2875                                                     secondary->scratch_size_needed);
2876                 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2877                                                             secondary->compute_scratch_size_needed);
2878
2879                 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2880                         primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2881                 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2882                         primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2883                 if (secondary->tess_rings_needed)
2884                         primary->tess_rings_needed = true;
2885                 if (secondary->sample_positions_needed)
2886                         primary->sample_positions_needed = true;
2887
2888                 if (secondary->ring_offsets_idx != -1) {
2889                         if (primary->ring_offsets_idx == -1)
2890                                 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2891                         else
2892                                 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2893                 }
2894                 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2895
2896
2897                 /* When the secondary command buffer is compute only we don't
2898                  * need to re-emit the current graphics pipeline.
2899                  */
2900                 if (secondary->state.emitted_pipeline) {
2901                         primary->state.emitted_pipeline =
2902                                 secondary->state.emitted_pipeline;
2903                 }
2904
2905                 /* When the secondary command buffer is graphics only we don't
2906                  * need to re-emit the current compute pipeline.
2907                  */
2908                 if (secondary->state.emitted_compute_pipeline) {
2909                         primary->state.emitted_compute_pipeline =
2910                                 secondary->state.emitted_compute_pipeline;
2911                 }
2912
2913                 /* Only re-emit the draw packets when needed. */
2914                 if (secondary->state.last_primitive_reset_en != -1) {
2915                         primary->state.last_primitive_reset_en =
2916                                 secondary->state.last_primitive_reset_en;
2917                 }
2918
2919                 if (secondary->state.last_primitive_reset_index) {
2920                         primary->state.last_primitive_reset_index =
2921                                 secondary->state.last_primitive_reset_index;
2922                 }
2923
2924                 if (secondary->state.last_ia_multi_vgt_param) {
2925                         primary->state.last_ia_multi_vgt_param =
2926                                 secondary->state.last_ia_multi_vgt_param;
2927                 }
2928
2929                 primary->state.last_first_instance = secondary->state.last_first_instance;
2930                 primary->state.last_num_instances = secondary->state.last_num_instances;
2931                 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2932
2933                 if (secondary->state.last_index_type != -1) {
2934                         primary->state.last_index_type =
2935                                 secondary->state.last_index_type;
2936                 }
2937         }
2938
2939         /* After executing commands from secondary buffers we have to dirty
2940          * some states.
2941          */
2942         primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2943                                 RADV_CMD_DIRTY_INDEX_BUFFER |
2944                                 RADV_CMD_DIRTY_DYNAMIC_ALL;
2945         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2946         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2947 }
2948
2949 VkResult radv_CreateCommandPool(
2950         VkDevice                                    _device,
2951         const VkCommandPoolCreateInfo*              pCreateInfo,
2952         const VkAllocationCallbacks*                pAllocator,
2953         VkCommandPool*                              pCmdPool)
2954 {
2955         RADV_FROM_HANDLE(radv_device, device, _device);
2956         struct radv_cmd_pool *pool;
2957
2958         pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2959                            VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2960         if (pool == NULL)
2961                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2962
2963         if (pAllocator)
2964                 pool->alloc = *pAllocator;
2965         else
2966                 pool->alloc = device->alloc;
2967
2968         list_inithead(&pool->cmd_buffers);
2969         list_inithead(&pool->free_cmd_buffers);
2970
2971         pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2972
2973         *pCmdPool = radv_cmd_pool_to_handle(pool);
2974
2975         return VK_SUCCESS;
2976
2977 }
2978
2979 void radv_DestroyCommandPool(
2980         VkDevice                                    _device,
2981         VkCommandPool                               commandPool,
2982         const VkAllocationCallbacks*                pAllocator)
2983 {
2984         RADV_FROM_HANDLE(radv_device, device, _device);
2985         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2986
2987         if (!pool)
2988                 return;
2989
2990         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2991                                  &pool->cmd_buffers, pool_link) {
2992                 radv_cmd_buffer_destroy(cmd_buffer);
2993         }
2994
2995         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2996                                  &pool->free_cmd_buffers, pool_link) {
2997                 radv_cmd_buffer_destroy(cmd_buffer);
2998         }
2999
3000         vk_free2(&device->alloc, pAllocator, pool);
3001 }
3002
3003 VkResult radv_ResetCommandPool(
3004         VkDevice                                    device,
3005         VkCommandPool                               commandPool,
3006         VkCommandPoolResetFlags                     flags)
3007 {
3008         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3009         VkResult result;
3010
3011         list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3012                             &pool->cmd_buffers, pool_link) {
3013                 result = radv_reset_cmd_buffer(cmd_buffer);
3014                 if (result != VK_SUCCESS)
3015                         return result;
3016         }
3017
3018         return VK_SUCCESS;
3019 }
3020
3021 void radv_TrimCommandPool(
3022     VkDevice                                    device,
3023     VkCommandPool                               commandPool,
3024     VkCommandPoolTrimFlagsKHR                   flags)
3025 {
3026         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3027
3028         if (!pool)
3029                 return;
3030
3031         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3032                                  &pool->free_cmd_buffers, pool_link) {
3033                 radv_cmd_buffer_destroy(cmd_buffer);
3034         }
3035 }
3036
3037 void radv_CmdBeginRenderPass(
3038         VkCommandBuffer                             commandBuffer,
3039         const VkRenderPassBeginInfo*                pRenderPassBegin,
3040         VkSubpassContents                           contents)
3041 {
3042         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3043         RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3044         RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3045
3046         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3047                                                            cmd_buffer->cs, 2048);
3048         MAYBE_UNUSED VkResult result;
3049
3050         cmd_buffer->state.framebuffer = framebuffer;
3051         cmd_buffer->state.pass = pass;
3052         cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3053
3054         result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3055         if (result != VK_SUCCESS)
3056                 return;
3057
3058         radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3059         assert(cmd_buffer->cs->cdw <= cdw_max);
3060
3061         radv_cmd_buffer_clear_subpass(cmd_buffer);
3062 }
3063
3064 void radv_CmdNextSubpass(
3065     VkCommandBuffer                             commandBuffer,
3066     VkSubpassContents                           contents)
3067 {
3068         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3069
3070         radv_cmd_buffer_resolve_subpass(cmd_buffer);
3071
3072         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3073                                               2048);
3074
3075         radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3076         radv_cmd_buffer_clear_subpass(cmd_buffer);
3077 }
3078
3079 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3080 {
3081         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3082         for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3083                 if (!radv_get_shader(pipeline, stage))
3084                         continue;
3085
3086                 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3087                 if (loc->sgpr_idx == -1)
3088                         continue;
3089                 uint32_t base_reg = pipeline->user_data_0[stage];
3090                 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3091
3092         }
3093         if (pipeline->gs_copy_shader) {
3094                 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3095                 if (loc->sgpr_idx != -1) {
3096                         uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3097                         radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3098                 }
3099         }
3100 }
3101
3102 static void
3103 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3104                          uint32_t vertex_count)
3105 {
3106         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3107         radeon_emit(cmd_buffer->cs, vertex_count);
3108         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3109                                     S_0287F0_USE_OPAQUE(0));
3110 }
3111
3112 static void
3113 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3114                                  uint64_t index_va,
3115                                  uint32_t index_count)
3116 {
3117         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3118         radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3119         radeon_emit(cmd_buffer->cs, index_va);
3120         radeon_emit(cmd_buffer->cs, index_va >> 32);
3121         radeon_emit(cmd_buffer->cs, index_count);
3122         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3123 }
3124
3125 static void
3126 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3127                                   bool indexed,
3128                                   uint32_t draw_count,
3129                                   uint64_t count_va,
3130                                   uint32_t stride)
3131 {
3132         struct radeon_cmdbuf *cs = cmd_buffer->cs;
3133         unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3134                                       : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3135         bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3136         uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3137         assert(base_reg);
3138
3139         /* just reset draw state for vertex data */
3140         cmd_buffer->state.last_first_instance = -1;
3141         cmd_buffer->state.last_num_instances = -1;
3142         cmd_buffer->state.last_vertex_offset = -1;
3143
3144         if (draw_count == 1 && !count_va && !draw_id_enable) {
3145                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3146                                      PKT3_DRAW_INDIRECT, 3, false));
3147                 radeon_emit(cs, 0);
3148                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3149                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3150                 radeon_emit(cs, di_src_sel);
3151         } else {
3152                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3153                                      PKT3_DRAW_INDIRECT_MULTI,
3154                                      8, false));
3155                 radeon_emit(cs, 0);
3156                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3157                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3158                 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3159                             S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3160                             S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3161                 radeon_emit(cs, draw_count); /* count */
3162                 radeon_emit(cs, count_va); /* count_addr */
3163                 radeon_emit(cs, count_va >> 32);
3164                 radeon_emit(cs, stride); /* stride */
3165                 radeon_emit(cs, di_src_sel);
3166         }
3167 }
3168
3169 struct radv_draw_info {
3170         /**
3171          * Number of vertices.
3172          */
3173         uint32_t count;
3174
3175         /**
3176          * Index of the first vertex.
3177          */
3178         int32_t vertex_offset;
3179
3180         /**
3181          * First instance id.
3182          */
3183         uint32_t first_instance;
3184
3185         /**
3186          * Number of instances.
3187          */
3188         uint32_t instance_count;
3189
3190         /**
3191          * First index (indexed draws only).
3192          */
3193         uint32_t first_index;
3194
3195         /**
3196          * Whether it's an indexed draw.
3197          */
3198         bool indexed;
3199
3200         /**
3201          * Indirect draw parameters resource.
3202          */
3203         struct radv_buffer *indirect;
3204         uint64_t indirect_offset;
3205         uint32_t stride;
3206
3207         /**
3208          * Draw count parameters resource.
3209          */
3210         struct radv_buffer *count_buffer;
3211         uint64_t count_buffer_offset;
3212 };
3213
3214 static void
3215 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3216                        const struct radv_draw_info *info)
3217 {
3218         struct radv_cmd_state *state = &cmd_buffer->state;
3219         struct radeon_winsys *ws = cmd_buffer->device->ws;
3220         struct radeon_cmdbuf *cs = cmd_buffer->cs;
3221
3222         if (info->indirect) {
3223                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3224                 uint64_t count_va = 0;
3225
3226                 va += info->indirect->offset + info->indirect_offset;
3227
3228                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3229
3230                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3231                 radeon_emit(cs, 1);
3232                 radeon_emit(cs, va);
3233                 radeon_emit(cs, va >> 32);
3234
3235                 if (info->count_buffer) {
3236                         count_va = radv_buffer_get_va(info->count_buffer->bo);
3237                         count_va += info->count_buffer->offset +
3238                                     info->count_buffer_offset;
3239
3240                         radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3241                 }
3242
3243                 if (!state->subpass->view_mask) {
3244                         radv_cs_emit_indirect_draw_packet(cmd_buffer,
3245                                                           info->indexed,
3246                                                           info->count,
3247                                                           count_va,
3248                                                           info->stride);
3249                 } else {
3250                         unsigned i;
3251                         for_each_bit(i, state->subpass->view_mask) {
3252                                 radv_emit_view_index(cmd_buffer, i);
3253
3254                                 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3255                                                                   info->indexed,
3256                                                                   info->count,
3257                                                                   count_va,
3258                                                                   info->stride);
3259                         }
3260                 }
3261         } else {
3262                 assert(state->pipeline->graphics.vtx_base_sgpr);
3263
3264                 if (info->vertex_offset != state->last_vertex_offset ||
3265                     info->first_instance != state->last_first_instance) {
3266                         radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3267                                               state->pipeline->graphics.vtx_emit_num);
3268
3269                         radeon_emit(cs, info->vertex_offset);
3270                         radeon_emit(cs, info->first_instance);
3271                         if (state->pipeline->graphics.vtx_emit_num == 3)
3272                                 radeon_emit(cs, 0);
3273                         state->last_first_instance = info->first_instance;
3274                         state->last_vertex_offset = info->vertex_offset;
3275                 }
3276
3277                 if (state->last_num_instances != info->instance_count) {
3278                         radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3279                         radeon_emit(cs, info->instance_count);
3280                         state->last_num_instances = info->instance_count;
3281                 }
3282
3283                 if (info->indexed) {
3284                         int index_size = state->index_type ? 4 : 2;
3285                         uint64_t index_va;
3286
3287                         index_va = state->index_va;
3288                         index_va += info->first_index * index_size;
3289
3290                         if (!state->subpass->view_mask) {
3291                                 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3292                                                                  index_va,
3293                                                                  info->count);
3294                         } else {
3295                                 unsigned i;
3296                                 for_each_bit(i, state->subpass->view_mask) {
3297                                         radv_emit_view_index(cmd_buffer, i);
3298
3299                                         radv_cs_emit_draw_indexed_packet(cmd_buffer,
3300                                                                          index_va,
3301                                                                          info->count);
3302                                 }
3303                         }
3304                 } else {
3305                         if (!state->subpass->view_mask) {
3306                                 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3307                         } else {
3308                                 unsigned i;
3309                                 for_each_bit(i, state->subpass->view_mask) {
3310                                         radv_emit_view_index(cmd_buffer, i);
3311
3312                                         radv_cs_emit_draw_packet(cmd_buffer,
3313                                                                  info->count);
3314                                 }
3315                         }
3316                 }
3317         }
3318 }
3319
3320 /*
3321  * Vega and raven have a bug which triggers if there are multiple context
3322  * register contexts active at the same time with different scissor values.
3323  *
3324  * There are two possible workarounds:
3325  * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3326  *    there is only ever 1 active set of scissor values at the same time.
3327  *
3328  * 2) Whenever the hardware switches contexts we have to set the scissor
3329  *    registers again even if it is a noop. That way the new context gets
3330  *    the correct scissor values.
3331  *
3332  * This implements option 2. radv_need_late_scissor_emission needs to
3333  * return true on affected HW if radv_emit_all_graphics_states sets
3334  * any context registers.
3335  */
3336 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3337                                             bool indexed_draw)
3338 {
3339         struct radv_cmd_state *state = &cmd_buffer->state;
3340
3341         if (!cmd_buffer->device->physical_device->has_scissor_bug)
3342                 return false;
3343
3344         uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3345
3346         /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
3347         used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER | RADV_CMD_DIRTY_VERTEX_BUFFER | RADV_CMD_DIRTY_PIPELINE);
3348
3349         /* Assume all state changes except  these two can imply context rolls. */
3350         if (cmd_buffer->state.dirty & used_states)
3351                 return true;
3352
3353         if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3354                 return true;
3355
3356         if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3357             (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3358                 return true;
3359
3360         return false;
3361 }
3362
3363 static void
3364 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3365                               const struct radv_draw_info *info)
3366 {
3367         bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3368
3369         if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3370             cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3371                 radv_emit_rbplus_state(cmd_buffer);
3372
3373         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3374                 radv_emit_graphics_pipeline(cmd_buffer);
3375
3376         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3377                 radv_emit_framebuffer_state(cmd_buffer);
3378
3379         if (info->indexed) {
3380                 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3381                         radv_emit_index_buffer(cmd_buffer);
3382         } else {
3383                 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3384                  * so the state must be re-emitted before the next indexed
3385                  * draw.
3386                  */
3387                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3388                         cmd_buffer->state.last_index_type = -1;
3389                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3390                 }
3391         }
3392
3393         radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3394
3395         radv_emit_draw_registers(cmd_buffer, info->indexed,
3396                                  info->instance_count > 1, info->indirect,
3397                                  info->indirect ? 0 : info->count);
3398
3399         if (late_scissor_emission)
3400                 radv_emit_scissor(cmd_buffer);
3401 }
3402
3403 static void
3404 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3405           const struct radv_draw_info *info)
3406 {
3407         bool has_prefetch =
3408                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3409         bool pipeline_is_dirty =
3410                 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3411                 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3412
3413         MAYBE_UNUSED unsigned cdw_max =
3414                 radeon_check_space(cmd_buffer->device->ws,
3415                                    cmd_buffer->cs, 4096);
3416
3417         /* Use optimal packet order based on whether we need to sync the
3418          * pipeline.
3419          */
3420         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3421                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3422                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3423                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3424                 /* If we have to wait for idle, set all states first, so that
3425                  * all SET packets are processed in parallel with previous draw
3426                  * calls. Then upload descriptors, set shader pointers, and
3427                  * draw, and prefetch at the end. This ensures that the time
3428                  * the CUs are idle is very short. (there are only SET_SH
3429                  * packets between the wait and the draw)
3430                  */
3431                 radv_emit_all_graphics_states(cmd_buffer, info);
3432                 si_emit_cache_flush(cmd_buffer);
3433                 /* <-- CUs are idle here --> */
3434
3435                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3436
3437                 radv_emit_draw_packets(cmd_buffer, info);
3438                 /* <-- CUs are busy here --> */
3439
3440                 /* Start prefetches after the draw has been started. Both will
3441                  * run in parallel, but starting the draw first is more
3442                  * important.
3443                  */
3444                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3445                         radv_emit_prefetch_L2(cmd_buffer,
3446                                               cmd_buffer->state.pipeline, false);
3447                 }
3448         } else {
3449                 /* If we don't wait for idle, start prefetches first, then set
3450                  * states, and draw at the end.
3451                  */
3452                 si_emit_cache_flush(cmd_buffer);
3453
3454                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3455                         /* Only prefetch the vertex shader and VBO descriptors
3456                          * in order to start the draw as soon as possible.
3457                          */
3458                         radv_emit_prefetch_L2(cmd_buffer,
3459                                               cmd_buffer->state.pipeline, true);
3460                 }
3461
3462                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3463
3464                 radv_emit_all_graphics_states(cmd_buffer, info);
3465                 radv_emit_draw_packets(cmd_buffer, info);
3466
3467                 /* Prefetch the remaining shaders after the draw has been
3468                  * started.
3469                  */
3470                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3471                         radv_emit_prefetch_L2(cmd_buffer,
3472                                               cmd_buffer->state.pipeline, false);
3473                 }
3474         }
3475
3476         assert(cmd_buffer->cs->cdw <= cdw_max);
3477         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3478 }
3479
3480 void radv_CmdDraw(
3481         VkCommandBuffer                             commandBuffer,
3482         uint32_t                                    vertexCount,
3483         uint32_t                                    instanceCount,
3484         uint32_t                                    firstVertex,
3485         uint32_t                                    firstInstance)
3486 {
3487         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3488         struct radv_draw_info info = {};
3489
3490         info.count = vertexCount;
3491         info.instance_count = instanceCount;
3492         info.first_instance = firstInstance;
3493         info.vertex_offset = firstVertex;
3494
3495         radv_draw(cmd_buffer, &info);
3496 }
3497
3498 void radv_CmdDrawIndexed(
3499         VkCommandBuffer                             commandBuffer,
3500         uint32_t                                    indexCount,
3501         uint32_t                                    instanceCount,
3502         uint32_t                                    firstIndex,
3503         int32_t                                     vertexOffset,
3504         uint32_t                                    firstInstance)
3505 {
3506         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3507         struct radv_draw_info info = {};
3508
3509         info.indexed = true;
3510         info.count = indexCount;
3511         info.instance_count = instanceCount;
3512         info.first_index = firstIndex;
3513         info.vertex_offset = vertexOffset;
3514         info.first_instance = firstInstance;
3515
3516         radv_draw(cmd_buffer, &info);
3517 }
3518
3519 void radv_CmdDrawIndirect(
3520         VkCommandBuffer                             commandBuffer,
3521         VkBuffer                                    _buffer,
3522         VkDeviceSize                                offset,
3523         uint32_t                                    drawCount,
3524         uint32_t                                    stride)
3525 {
3526         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3527         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3528         struct radv_draw_info info = {};
3529
3530         info.count = drawCount;
3531         info.indirect = buffer;
3532         info.indirect_offset = offset;
3533         info.stride = stride;
3534
3535         radv_draw(cmd_buffer, &info);
3536 }
3537
3538 void radv_CmdDrawIndexedIndirect(
3539         VkCommandBuffer                             commandBuffer,
3540         VkBuffer                                    _buffer,
3541         VkDeviceSize                                offset,
3542         uint32_t                                    drawCount,
3543         uint32_t                                    stride)
3544 {
3545         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3546         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3547         struct radv_draw_info info = {};
3548
3549         info.indexed = true;
3550         info.count = drawCount;
3551         info.indirect = buffer;
3552         info.indirect_offset = offset;
3553         info.stride = stride;
3554
3555         radv_draw(cmd_buffer, &info);
3556 }
3557
3558 void radv_CmdDrawIndirectCountAMD(
3559         VkCommandBuffer                             commandBuffer,
3560         VkBuffer                                    _buffer,
3561         VkDeviceSize                                offset,
3562         VkBuffer                                    _countBuffer,
3563         VkDeviceSize                                countBufferOffset,
3564         uint32_t                                    maxDrawCount,
3565         uint32_t                                    stride)
3566 {
3567         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3568         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3569         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3570         struct radv_draw_info info = {};
3571
3572         info.count = maxDrawCount;
3573         info.indirect = buffer;
3574         info.indirect_offset = offset;
3575         info.count_buffer = count_buffer;
3576         info.count_buffer_offset = countBufferOffset;
3577         info.stride = stride;
3578
3579         radv_draw(cmd_buffer, &info);
3580 }
3581
3582 void radv_CmdDrawIndexedIndirectCountAMD(
3583         VkCommandBuffer                             commandBuffer,
3584         VkBuffer                                    _buffer,
3585         VkDeviceSize                                offset,
3586         VkBuffer                                    _countBuffer,
3587         VkDeviceSize                                countBufferOffset,
3588         uint32_t                                    maxDrawCount,
3589         uint32_t                                    stride)
3590 {
3591         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3592         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3593         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3594         struct radv_draw_info info = {};
3595
3596         info.indexed = true;
3597         info.count = maxDrawCount;
3598         info.indirect = buffer;
3599         info.indirect_offset = offset;
3600         info.count_buffer = count_buffer;
3601         info.count_buffer_offset = countBufferOffset;
3602         info.stride = stride;
3603
3604         radv_draw(cmd_buffer, &info);
3605 }
3606
3607 void radv_CmdDrawIndirectCountKHR(
3608         VkCommandBuffer                             commandBuffer,
3609         VkBuffer                                    _buffer,
3610         VkDeviceSize                                offset,
3611         VkBuffer                                    _countBuffer,
3612         VkDeviceSize                                countBufferOffset,
3613         uint32_t                                    maxDrawCount,
3614         uint32_t                                    stride)
3615 {
3616         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3617         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3618         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3619         struct radv_draw_info info = {};
3620
3621         info.count = maxDrawCount;
3622         info.indirect = buffer;
3623         info.indirect_offset = offset;
3624         info.count_buffer = count_buffer;
3625         info.count_buffer_offset = countBufferOffset;
3626         info.stride = stride;
3627
3628         radv_draw(cmd_buffer, &info);
3629 }
3630
3631 void radv_CmdDrawIndexedIndirectCountKHR(
3632         VkCommandBuffer                             commandBuffer,
3633         VkBuffer                                    _buffer,
3634         VkDeviceSize                                offset,
3635         VkBuffer                                    _countBuffer,
3636         VkDeviceSize                                countBufferOffset,
3637         uint32_t                                    maxDrawCount,
3638         uint32_t                                    stride)
3639 {
3640         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3641         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3642         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3643         struct radv_draw_info info = {};
3644
3645         info.indexed = true;
3646         info.count = maxDrawCount;
3647         info.indirect = buffer;
3648         info.indirect_offset = offset;
3649         info.count_buffer = count_buffer;
3650         info.count_buffer_offset = countBufferOffset;
3651         info.stride = stride;
3652
3653         radv_draw(cmd_buffer, &info);
3654 }
3655
3656 struct radv_dispatch_info {
3657         /**
3658          * Determine the layout of the grid (in block units) to be used.
3659          */
3660         uint32_t blocks[3];
3661
3662         /**
3663          * A starting offset for the grid. If unaligned is set, the offset
3664          * must still be aligned.
3665          */
3666         uint32_t offsets[3];
3667         /**
3668          * Whether it's an unaligned compute dispatch.
3669          */
3670         bool unaligned;
3671
3672         /**
3673          * Indirect compute parameters resource.
3674          */
3675         struct radv_buffer *indirect;
3676         uint64_t indirect_offset;
3677 };
3678
3679 static void
3680 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3681                            const struct radv_dispatch_info *info)
3682 {
3683         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3684         struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3685         unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3686         struct radeon_winsys *ws = cmd_buffer->device->ws;
3687         struct radeon_cmdbuf *cs = cmd_buffer->cs;
3688         struct radv_userdata_info *loc;
3689
3690         loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3691                                     AC_UD_CS_GRID_SIZE);
3692
3693         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3694
3695         if (info->indirect) {
3696                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3697
3698                 va += info->indirect->offset + info->indirect_offset;
3699
3700                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3701
3702                 if (loc->sgpr_idx != -1) {
3703                         for (unsigned i = 0; i < 3; ++i) {
3704                                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3705                                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3706                                                 COPY_DATA_DST_SEL(COPY_DATA_REG));
3707                                 radeon_emit(cs, (va +  4 * i));
3708                                 radeon_emit(cs, (va + 4 * i) >> 32);
3709                                 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3710                                                  + loc->sgpr_idx * 4) >> 2) + i);
3711                                 radeon_emit(cs, 0);
3712                         }
3713                 }
3714
3715                 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3716                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3717                                         PKT3_SHADER_TYPE_S(1));
3718                         radeon_emit(cs, va);
3719                         radeon_emit(cs, va >> 32);
3720                         radeon_emit(cs, dispatch_initiator);
3721                 } else {
3722                         radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3723                                         PKT3_SHADER_TYPE_S(1));
3724                         radeon_emit(cs, 1);
3725                         radeon_emit(cs, va);
3726                         radeon_emit(cs, va >> 32);
3727
3728                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3729                                         PKT3_SHADER_TYPE_S(1));
3730                         radeon_emit(cs, 0);
3731                         radeon_emit(cs, dispatch_initiator);
3732                 }
3733         } else {
3734                 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3735                 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3736
3737                 if (info->unaligned) {
3738                         unsigned *cs_block_size = compute_shader->info.cs.block_size;
3739                         unsigned remainder[3];
3740
3741                         /* If aligned, these should be an entire block size,
3742                          * not 0.
3743                          */
3744                         remainder[0] = blocks[0] + cs_block_size[0] -
3745                                        align_u32_npot(blocks[0], cs_block_size[0]);
3746                         remainder[1] = blocks[1] + cs_block_size[1] -
3747                                        align_u32_npot(blocks[1], cs_block_size[1]);
3748                         remainder[2] = blocks[2] + cs_block_size[2] -
3749                                        align_u32_npot(blocks[2], cs_block_size[2]);
3750
3751                         blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3752                         blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3753                         blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3754
3755                         for(unsigned i = 0; i < 3; ++i) {
3756                                 assert(offsets[i] % cs_block_size[i] == 0);
3757                                 offsets[i] /= cs_block_size[i];
3758                         }
3759
3760                         radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3761                         radeon_emit(cs,
3762                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3763                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3764                         radeon_emit(cs,
3765                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3766                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3767                         radeon_emit(cs,
3768                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3769                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3770
3771                         dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3772                 }
3773
3774                 if (loc->sgpr_idx != -1) {
3775                         assert(!loc->indirect);
3776                         assert(loc->num_sgprs == 3);
3777
3778                         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3779                                                   loc->sgpr_idx * 4, 3);
3780                         radeon_emit(cs, blocks[0]);
3781                         radeon_emit(cs, blocks[1]);
3782                         radeon_emit(cs, blocks[2]);
3783                 }
3784
3785                 if (offsets[0] || offsets[1] || offsets[2]) {
3786                         radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3787                         radeon_emit(cs, offsets[0]);
3788                         radeon_emit(cs, offsets[1]);
3789                         radeon_emit(cs, offsets[2]);
3790
3791                         /* The blocks in the packet are not counts but end values. */
3792                         for (unsigned i = 0; i < 3; ++i)
3793                                 blocks[i] += offsets[i];
3794                 } else {
3795                         dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3796                 }
3797
3798                 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3799                                 PKT3_SHADER_TYPE_S(1));
3800                 radeon_emit(cs, blocks[0]);
3801                 radeon_emit(cs, blocks[1]);
3802                 radeon_emit(cs, blocks[2]);
3803                 radeon_emit(cs, dispatch_initiator);
3804         }
3805
3806         assert(cmd_buffer->cs->cdw <= cdw_max);
3807 }
3808
3809 static void
3810 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3811 {
3812         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3813         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3814 }
3815
3816 static void
3817 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3818               const struct radv_dispatch_info *info)
3819 {
3820         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3821         bool has_prefetch =
3822                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3823         bool pipeline_is_dirty = pipeline &&
3824                                  pipeline != cmd_buffer->state.emitted_compute_pipeline;
3825
3826         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3827                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3828                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3829                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3830                 /* If we have to wait for idle, set all states first, so that
3831                  * all SET packets are processed in parallel with previous draw
3832                  * calls. Then upload descriptors, set shader pointers, and
3833                  * dispatch, and prefetch at the end. This ensures that the
3834                  * time the CUs are idle is very short. (there are only SET_SH
3835                  * packets between the wait and the draw)
3836                  */
3837                 radv_emit_compute_pipeline(cmd_buffer);
3838                 si_emit_cache_flush(cmd_buffer);
3839                 /* <-- CUs are idle here --> */
3840
3841                 radv_upload_compute_shader_descriptors(cmd_buffer);
3842
3843                 radv_emit_dispatch_packets(cmd_buffer, info);
3844                 /* <-- CUs are busy here --> */
3845
3846                 /* Start prefetches after the dispatch has been started. Both
3847                  * will run in parallel, but starting the dispatch first is
3848                  * more important.
3849                  */
3850                 if (has_prefetch && pipeline_is_dirty) {
3851                         radv_emit_shader_prefetch(cmd_buffer,
3852                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3853                 }
3854         } else {
3855                 /* If we don't wait for idle, start prefetches first, then set
3856                  * states, and dispatch at the end.
3857                  */
3858                 si_emit_cache_flush(cmd_buffer);
3859
3860                 if (has_prefetch && pipeline_is_dirty) {
3861                         radv_emit_shader_prefetch(cmd_buffer,
3862                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3863                 }
3864
3865                 radv_upload_compute_shader_descriptors(cmd_buffer);
3866
3867                 radv_emit_compute_pipeline(cmd_buffer);
3868                 radv_emit_dispatch_packets(cmd_buffer, info);
3869         }
3870
3871         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3872 }
3873
3874 void radv_CmdDispatchBase(
3875         VkCommandBuffer                             commandBuffer,
3876         uint32_t                                    base_x,
3877         uint32_t                                    base_y,
3878         uint32_t                                    base_z,
3879         uint32_t                                    x,
3880         uint32_t                                    y,
3881         uint32_t                                    z)
3882 {
3883         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3884         struct radv_dispatch_info info = {};
3885
3886         info.blocks[0] = x;
3887         info.blocks[1] = y;
3888         info.blocks[2] = z;
3889
3890         info.offsets[0] = base_x;
3891         info.offsets[1] = base_y;
3892         info.offsets[2] = base_z;
3893         radv_dispatch(cmd_buffer, &info);
3894 }
3895
3896 void radv_CmdDispatch(
3897         VkCommandBuffer                             commandBuffer,
3898         uint32_t                                    x,
3899         uint32_t                                    y,
3900         uint32_t                                    z)
3901 {
3902         radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3903 }
3904
3905 void radv_CmdDispatchIndirect(
3906         VkCommandBuffer                             commandBuffer,
3907         VkBuffer                                    _buffer,
3908         VkDeviceSize                                offset)
3909 {
3910         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3911         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3912         struct radv_dispatch_info info = {};
3913
3914         info.indirect = buffer;
3915         info.indirect_offset = offset;
3916
3917         radv_dispatch(cmd_buffer, &info);
3918 }
3919
3920 void radv_unaligned_dispatch(
3921         struct radv_cmd_buffer                      *cmd_buffer,
3922         uint32_t                                    x,
3923         uint32_t                                    y,
3924         uint32_t                                    z)
3925 {
3926         struct radv_dispatch_info info = {};
3927
3928         info.blocks[0] = x;
3929         info.blocks[1] = y;
3930         info.blocks[2] = z;
3931         info.unaligned = 1;
3932
3933         radv_dispatch(cmd_buffer, &info);
3934 }
3935
3936 void radv_CmdEndRenderPass(
3937         VkCommandBuffer                             commandBuffer)
3938 {
3939         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3940
3941         radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3942
3943         radv_cmd_buffer_resolve_subpass(cmd_buffer);
3944
3945         for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3946                 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3947                 radv_handle_subpass_image_transition(cmd_buffer,
3948                                       (struct radv_subpass_attachment){i, layout});
3949         }
3950
3951         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3952
3953         cmd_buffer->state.pass = NULL;
3954         cmd_buffer->state.subpass = NULL;
3955         cmd_buffer->state.attachments = NULL;
3956         cmd_buffer->state.framebuffer = NULL;
3957 }
3958
3959 /*
3960  * For HTILE we have the following interesting clear words:
3961  *   0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3962  *   0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3963  *   0xfffffff0: Clear depth to 1.0
3964  *   0x00000000: Clear depth to 0.0
3965  */
3966 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3967                                   struct radv_image *image,
3968                                   const VkImageSubresourceRange *range,
3969                                   uint32_t clear_word)
3970 {
3971         assert(range->baseMipLevel == 0);
3972         assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3973         unsigned layer_count = radv_get_layerCount(image, range);
3974         uint64_t size = image->surface.htile_slice_size * layer_count;
3975         VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
3976         uint64_t offset = image->offset + image->htile_offset +
3977                           image->surface.htile_slice_size * range->baseArrayLayer;
3978         struct radv_cmd_state *state = &cmd_buffer->state;
3979         VkClearDepthStencilValue value = {};
3980
3981         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3982                              RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3983
3984         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3985                                               size, clear_word);
3986
3987         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3988
3989         if (vk_format_is_stencil(image->vk_format))
3990                 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3991
3992         radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
3993 }
3994
3995 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3996                                                struct radv_image *image,
3997                                                VkImageLayout src_layout,
3998                                                VkImageLayout dst_layout,
3999                                                unsigned src_queue_mask,
4000                                                unsigned dst_queue_mask,
4001                                                const VkImageSubresourceRange *range,
4002                                                VkImageAspectFlags pending_clears)
4003 {
4004         if (!radv_image_has_htile(image))
4005                 return;
4006
4007         if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4008                    radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4009                 /* TODO: merge with the clear if applicable */
4010                 radv_initialize_htile(cmd_buffer, image, range, 0);
4011         } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4012                    radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4013                 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4014                 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4015         } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4016                    !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4017                 VkImageSubresourceRange local_range = *range;
4018                 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4019                 local_range.baseMipLevel = 0;
4020                 local_range.levelCount = 1;
4021
4022                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4023                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4024
4025                 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4026
4027                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4028                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4029         }
4030 }
4031
4032 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4033                                   struct radv_image *image, uint32_t value)
4034 {
4035         struct radv_cmd_state *state = &cmd_buffer->state;
4036
4037         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4038                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4039
4040         state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4041
4042         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4043 }
4044
4045 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4046                          struct radv_image *image, uint32_t value)
4047 {
4048         struct radv_cmd_state *state = &cmd_buffer->state;
4049
4050         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4051                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4052
4053         state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4054
4055         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4056                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4057 }
4058
4059 /**
4060  * Initialize DCC/FMASK/CMASK metadata for a color image.
4061  */
4062 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4063                                            struct radv_image *image,
4064                                            VkImageLayout src_layout,
4065                                            VkImageLayout dst_layout,
4066                                            unsigned src_queue_mask,
4067                                            unsigned dst_queue_mask)
4068 {
4069         if (radv_image_has_cmask(image)) {
4070                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4071
4072                 /*  TODO: clarify this. */
4073                 if (radv_image_has_fmask(image)) {
4074                         value = 0xccccccccu;
4075                 }
4076
4077                 radv_initialise_cmask(cmd_buffer, image, value);
4078         }
4079
4080         if (radv_image_has_dcc(image)) {
4081                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4082
4083                 if (radv_layout_dcc_compressed(image, dst_layout,
4084                                                dst_queue_mask)) {
4085                         value = 0x20202020u;
4086                 }
4087
4088                 radv_initialize_dcc(cmd_buffer, image, value);
4089
4090                 radv_set_dcc_need_cmask_elim_pred(cmd_buffer, image, false);
4091         }
4092
4093         if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4094                 uint32_t color_values[2] = {};
4095                 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4096         }
4097 }
4098
4099 /**
4100  * Handle color image transitions for DCC/FMASK/CMASK.
4101  */
4102 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4103                                                struct radv_image *image,
4104                                                VkImageLayout src_layout,
4105                                                VkImageLayout dst_layout,
4106                                                unsigned src_queue_mask,
4107                                                unsigned dst_queue_mask,
4108                                                const VkImageSubresourceRange *range)
4109 {
4110         if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4111                 radv_init_color_image_metadata(cmd_buffer, image,
4112                                                src_layout, dst_layout,
4113                                                src_queue_mask, dst_queue_mask);
4114                 return;
4115         }
4116
4117         if (radv_image_has_dcc(image)) {
4118                 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4119                         radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4120                 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4121                            !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4122                         radv_decompress_dcc(cmd_buffer, image, range);
4123                 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4124                            !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4125                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4126                 }
4127         } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4128                 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4129                     !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4130                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4131                 }
4132         }
4133 }
4134
4135 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4136                                          struct radv_image *image,
4137                                          VkImageLayout src_layout,
4138                                          VkImageLayout dst_layout,
4139                                          uint32_t src_family,
4140                                          uint32_t dst_family,
4141                                          const VkImageSubresourceRange *range,
4142                                          VkImageAspectFlags pending_clears)
4143 {
4144         if (image->exclusive && src_family != dst_family) {
4145                 /* This is an acquire or a release operation and there will be
4146                  * a corresponding release/acquire. Do the transition in the
4147                  * most flexible queue. */
4148
4149                 assert(src_family == cmd_buffer->queue_family_index ||
4150                        dst_family == cmd_buffer->queue_family_index);
4151
4152                 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4153                         return;
4154
4155                 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4156                     (src_family == RADV_QUEUE_GENERAL ||
4157                      dst_family == RADV_QUEUE_GENERAL))
4158                         return;
4159         }
4160
4161         unsigned src_queue_mask =
4162                 radv_image_queue_family_mask(image, src_family,
4163                                              cmd_buffer->queue_family_index);
4164         unsigned dst_queue_mask =
4165                 radv_image_queue_family_mask(image, dst_family,
4166                                              cmd_buffer->queue_family_index);
4167
4168         if (vk_format_is_depth(image->vk_format)) {
4169                 radv_handle_depth_image_transition(cmd_buffer, image,
4170                                                    src_layout, dst_layout,
4171                                                    src_queue_mask, dst_queue_mask,
4172                                                    range, pending_clears);
4173         } else {
4174                 radv_handle_color_image_transition(cmd_buffer, image,
4175                                                    src_layout, dst_layout,
4176                                                    src_queue_mask, dst_queue_mask,
4177                                                    range);
4178         }
4179 }
4180
4181 struct radv_barrier_info {
4182         uint32_t eventCount;
4183         const VkEvent *pEvents;
4184         VkPipelineStageFlags srcStageMask;
4185 };
4186
4187 static void
4188 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4189              uint32_t memoryBarrierCount,
4190              const VkMemoryBarrier *pMemoryBarriers,
4191              uint32_t bufferMemoryBarrierCount,
4192              const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4193              uint32_t imageMemoryBarrierCount,
4194              const VkImageMemoryBarrier *pImageMemoryBarriers,
4195              const struct radv_barrier_info *info)
4196 {
4197         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4198         enum radv_cmd_flush_bits src_flush_bits = 0;
4199         enum radv_cmd_flush_bits dst_flush_bits = 0;
4200
4201         for (unsigned i = 0; i < info->eventCount; ++i) {
4202                 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4203                 uint64_t va = radv_buffer_get_va(event->bo);
4204
4205                 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4206
4207                 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4208
4209                 si_emit_wait_fence(cs, va, 1, 0xffffffff);
4210                 assert(cmd_buffer->cs->cdw <= cdw_max);
4211         }
4212
4213         for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4214                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4215                                                         NULL);
4216                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4217                                                         NULL);
4218         }
4219
4220         for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4221                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4222                                                         NULL);
4223                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4224                                                         NULL);
4225         }
4226
4227         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4228                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4229
4230                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4231                                                         image);
4232                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4233                                                         image);
4234         }
4235
4236         radv_stage_flush(cmd_buffer, info->srcStageMask);
4237         cmd_buffer->state.flush_bits |= src_flush_bits;
4238
4239         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4240                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4241                 radv_handle_image_transition(cmd_buffer, image,
4242                                              pImageMemoryBarriers[i].oldLayout,
4243                                              pImageMemoryBarriers[i].newLayout,
4244                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
4245                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
4246                                              &pImageMemoryBarriers[i].subresourceRange,
4247                                              0);
4248         }
4249
4250         /* Make sure CP DMA is idle because the driver might have performed a
4251          * DMA operation for copying or filling buffers/images.
4252          */
4253         si_cp_dma_wait_for_idle(cmd_buffer);
4254
4255         cmd_buffer->state.flush_bits |= dst_flush_bits;
4256 }
4257
4258 void radv_CmdPipelineBarrier(
4259         VkCommandBuffer                             commandBuffer,
4260         VkPipelineStageFlags                        srcStageMask,
4261         VkPipelineStageFlags                        destStageMask,
4262         VkBool32                                    byRegion,
4263         uint32_t                                    memoryBarrierCount,
4264         const VkMemoryBarrier*                      pMemoryBarriers,
4265         uint32_t                                    bufferMemoryBarrierCount,
4266         const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
4267         uint32_t                                    imageMemoryBarrierCount,
4268         const VkImageMemoryBarrier*                 pImageMemoryBarriers)
4269 {
4270         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4271         struct radv_barrier_info info;
4272
4273         info.eventCount = 0;
4274         info.pEvents = NULL;
4275         info.srcStageMask = srcStageMask;
4276
4277         radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4278                      bufferMemoryBarrierCount, pBufferMemoryBarriers,
4279                      imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4280 }
4281
4282
4283 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4284                         struct radv_event *event,
4285                         VkPipelineStageFlags stageMask,
4286                         unsigned value)
4287 {
4288         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4289         uint64_t va = radv_buffer_get_va(event->bo);
4290
4291         radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4292
4293         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4294
4295         /* Flags that only require a top-of-pipe event. */
4296         VkPipelineStageFlags top_of_pipe_flags =
4297                 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4298
4299         /* Flags that only require a post-index-fetch event. */
4300         VkPipelineStageFlags post_index_fetch_flags =
4301                 top_of_pipe_flags |
4302                 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4303                 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4304
4305         /* Make sure CP DMA is idle because the driver might have performed a
4306          * DMA operation for copying or filling buffers/images.
4307          */
4308         si_cp_dma_wait_for_idle(cmd_buffer);
4309
4310         /* TODO: Emit EOS events for syncing PS/CS stages. */
4311
4312         if (!(stageMask & ~top_of_pipe_flags)) {
4313                 /* Just need to sync the PFP engine. */
4314                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4315                 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4316                                 S_370_WR_CONFIRM(1) |
4317                                 S_370_ENGINE_SEL(V_370_PFP));
4318                 radeon_emit(cs, va);
4319                 radeon_emit(cs, va >> 32);
4320                 radeon_emit(cs, value);
4321         } else if (!(stageMask & ~post_index_fetch_flags)) {
4322                 /* Sync ME because PFP reads index and indirect buffers. */
4323                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4324                 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
4325                                 S_370_WR_CONFIRM(1) |
4326                                 S_370_ENGINE_SEL(V_370_ME));
4327                 radeon_emit(cs, va);
4328                 radeon_emit(cs, va >> 32);
4329                 radeon_emit(cs, value);
4330         } else {
4331                 /* Otherwise, sync all prior GPU work using an EOP event. */
4332                 si_cs_emit_write_event_eop(cs,
4333                                            cmd_buffer->device->physical_device->rad_info.chip_class,
4334                                            radv_cmd_buffer_uses_mec(cmd_buffer),
4335                                            V_028A90_BOTTOM_OF_PIPE_TS, 0,
4336                                            EOP_DATA_SEL_VALUE_32BIT, va, 2, value);
4337         }
4338
4339         assert(cmd_buffer->cs->cdw <= cdw_max);
4340 }
4341
4342 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4343                       VkEvent _event,
4344                       VkPipelineStageFlags stageMask)
4345 {
4346         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4347         RADV_FROM_HANDLE(radv_event, event, _event);
4348
4349         write_event(cmd_buffer, event, stageMask, 1);
4350 }
4351
4352 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4353                         VkEvent _event,
4354                         VkPipelineStageFlags stageMask)
4355 {
4356         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4357         RADV_FROM_HANDLE(radv_event, event, _event);
4358
4359         write_event(cmd_buffer, event, stageMask, 0);
4360 }
4361
4362 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4363                         uint32_t eventCount,
4364                         const VkEvent* pEvents,
4365                         VkPipelineStageFlags srcStageMask,
4366                         VkPipelineStageFlags dstStageMask,
4367                         uint32_t memoryBarrierCount,
4368                         const VkMemoryBarrier* pMemoryBarriers,
4369                         uint32_t bufferMemoryBarrierCount,
4370                         const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4371                         uint32_t imageMemoryBarrierCount,
4372                         const VkImageMemoryBarrier* pImageMemoryBarriers)
4373 {
4374         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4375         struct radv_barrier_info info;
4376
4377         info.eventCount = eventCount;
4378         info.pEvents = pEvents;
4379         info.srcStageMask = 0;
4380
4381         radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4382                      bufferMemoryBarrierCount, pBufferMemoryBarriers,
4383                      imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4384 }
4385
4386
4387 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4388                            uint32_t deviceMask)
4389 {
4390    /* No-op */
4391 }