src/amd/vulkan/radv_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "radv_private.h"
  29 #include "radv_radeon_winsys.h"
  30 #include "radv_shader.h"
  31 #include "radv_cs.h"
  32 #include "sid.h"
  33 #include "gfx9d.h"
  34 #include "vk_format.h"
  35 #include "radv_debug.h"
  36 #include "radv_meta.h"
  37
  38 #include "ac_debug.h"
  39
  40 enum {
  41         RADV_PREFETCH_VBO_DESCRIPTORS   = (1 << 0),
  42         RADV_PREFETCH_VS                = (1 << 1),
  43         RADV_PREFETCH_TCS               = (1 << 2),
  44         RADV_PREFETCH_TES               = (1 << 3),
  45         RADV_PREFETCH_GS                = (1 << 4),
  46         RADV_PREFETCH_PS                = (1 << 5),
  47         RADV_PREFETCH_SHADERS           = (RADV_PREFETCH_VS  |
  48                                            RADV_PREFETCH_TCS |
  49                                            RADV_PREFETCH_TES |
  50                                            RADV_PREFETCH_GS  |
  51                                            RADV_PREFETCH_PS)
  52 };
  53
  54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
  55                                          struct radv_image *image,
  56                                          VkImageLayout src_layout,
  57                                          VkImageLayout dst_layout,
  58                                          uint32_t src_family,
  59                                          uint32_t dst_family,
  60                                          const VkImageSubresourceRange *range,
  61                                          VkImageAspectFlags pending_clears);
  62
  63 const struct radv_dynamic_state default_dynamic_state = {
  64         .viewport = {
  65                 .count = 0,
  66         },
  67         .scissor = {
  68                 .count = 0,
  69         },
  70         .line_width = 1.0f,
  71         .depth_bias = {
  72                 .bias = 0.0f,
  73                 .clamp = 0.0f,
  74                 .slope = 0.0f,
  75         },
  76         .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
  77         .depth_bounds = {
  78                 .min = 0.0f,
  79                 .max = 1.0f,
  80         },
  81         .stencil_compare_mask = {
  82                 .front = ~0u,
  83                 .back = ~0u,
  84         },
  85         .stencil_write_mask = {
  86                 .front = ~0u,
  87                 .back = ~0u,
  88         },
  89         .stencil_reference = {
  90                 .front = 0u,
  91                 .back = 0u,
  92         },
  93 };
  94
  95 static void
  96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
  97                         const struct radv_dynamic_state *src)
  98 {
  99         struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
 100         uint32_t copy_mask = src->mask;
 101         uint32_t dest_mask = 0;
 102
 103         /* Make sure to copy the number of viewports/scissors because they can
 104          * only be specified at pipeline creation time.
 105          */
 106         dest->viewport.count = src->viewport.count;
 107         dest->scissor.count = src->scissor.count;
 108         dest->discard_rectangle.count = src->discard_rectangle.count;
 109
 110         if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
 111                 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
 112                            src->viewport.count * sizeof(VkViewport))) {
 113                         typed_memcpy(dest->viewport.viewports,
 114                                      src->viewport.viewports,
 115                                      src->viewport.count);
 116                         dest_mask |= RADV_DYNAMIC_VIEWPORT;
 117                 }
 118         }
 119
 120         if (copy_mask & RADV_DYNAMIC_SCISSOR) {
 121                 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
 122                            src->scissor.count * sizeof(VkRect2D))) {
 123                         typed_memcpy(dest->scissor.scissors,
 124                                      src->scissor.scissors, src->scissor.count);
 125                         dest_mask |= RADV_DYNAMIC_SCISSOR;
 126                 }
 127         }
 128
 129         if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
 130                 if (dest->line_width != src->line_width) {
 131                         dest->line_width = src->line_width;
 132                         dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
 133                 }
 134         }
 135
 136         if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
 137                 if (memcmp(&dest->depth_bias, &src->depth_bias,
 138                            sizeof(src->depth_bias))) {
 139                         dest->depth_bias = src->depth_bias;
 140                         dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
 141                 }
 142         }
 143
 144         if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
 145                 if (memcmp(&dest->blend_constants, &src->blend_constants,
 146                            sizeof(src->blend_constants))) {
 147                         typed_memcpy(dest->blend_constants,
 148                                      src->blend_constants, 4);
 149                         dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
 150                 }
 151         }
 152
 153         if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
 154                 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
 155                            sizeof(src->depth_bounds))) {
 156                         dest->depth_bounds = src->depth_bounds;
 157                         dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
 158                 }
 159         }
 160
 161         if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
 162                 if (memcmp(&dest->stencil_compare_mask,
 163                            &src->stencil_compare_mask,
 164                            sizeof(src->stencil_compare_mask))) {
 165                         dest->stencil_compare_mask = src->stencil_compare_mask;
 166                         dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
 167                 }
 168         }
 169
 170         if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
 171                 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
 172                            sizeof(src->stencil_write_mask))) {
 173                         dest->stencil_write_mask = src->stencil_write_mask;
 174                         dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
 175                 }
 176         }
 177
 178         if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
 179                 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
 180                            sizeof(src->stencil_reference))) {
 181                         dest->stencil_reference = src->stencil_reference;
 182                         dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
 183                 }
 184         }
 185
 186         if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
 187                 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
 188                            src->discard_rectangle.count * sizeof(VkRect2D))) {
 189                         typed_memcpy(dest->discard_rectangle.rectangles,
 190                                      src->discard_rectangle.rectangles,
 191                                      src->discard_rectangle.count);
 192                         dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
 193                 }
 194         }
 195
 196         cmd_buffer->state.dirty |= dest_mask;
 197 }
 198
 199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
 200 {
 201         return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
 202                cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
 203 }
 204
 205 enum ring_type radv_queue_family_to_ring(int f) {
 206         switch (f) {
 207         case RADV_QUEUE_GENERAL:
 208                 return RING_GFX;
 209         case RADV_QUEUE_COMPUTE:
 210                 return RING_COMPUTE;
 211         case RADV_QUEUE_TRANSFER:
 212                 return RING_DMA;
 213         default:
 214                 unreachable("Unknown queue family");
 215         }
 216 }
 217
 218 static VkResult radv_create_cmd_buffer(
 219         struct radv_device *                         device,
 220         struct radv_cmd_pool *                       pool,
 221         VkCommandBufferLevel                        level,
 222         VkCommandBuffer*                            pCommandBuffer)
 223 {
 224         struct radv_cmd_buffer *cmd_buffer;
 225         unsigned ring;
 226         cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
 227                                VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 228         if (cmd_buffer == NULL)
 229                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 230
 231         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
 232         cmd_buffer->device = device;
 233         cmd_buffer->pool = pool;
 234         cmd_buffer->level = level;
 235
 236         if (pool) {
 237                 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
 238                 cmd_buffer->queue_family_index = pool->queue_family_index;
 239
 240         } else {
 241                 /* Init the pool_link so we can safefly call list_del when we destroy
 242                  * the command buffer
 243                  */
 244                 list_inithead(&cmd_buffer->pool_link);
 245                 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
 246         }
 247
 248         ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
 249
 250         cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
 251         if (!cmd_buffer->cs) {
 252                 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 253                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 254         }
 255
 256         *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
 257
 258         list_inithead(&cmd_buffer->upload.list);
 259
 260         return VK_SUCCESS;
 261 }
 262
 263 static void
 264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
 265 {
 266         list_del(&cmd_buffer->pool_link);
 267
 268         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 269                                  &cmd_buffer->upload.list, list) {
 270                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 271                 list_del(&up->list);
 272                 free(up);
 273         }
 274
 275         if (cmd_buffer->upload.upload_bo)
 276                 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
 277         cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
 278
 279         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
 280                 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
 281
 282         vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 283 }
 284
 285 static VkResult
 286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 287 {
 288
 289         cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
 290
 291         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 292                                  &cmd_buffer->upload.list, list) {
 293                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 294                 list_del(&up->list);
 295                 free(up);
 296         }
 297
 298         cmd_buffer->push_constant_stages = 0;
 299         cmd_buffer->scratch_size_needed = 0;
 300         cmd_buffer->compute_scratch_size_needed = 0;
 301         cmd_buffer->esgs_ring_size_needed = 0;
 302         cmd_buffer->gsvs_ring_size_needed = 0;
 303         cmd_buffer->tess_rings_needed = false;
 304         cmd_buffer->sample_positions_needed = false;
 305
 306         if (cmd_buffer->upload.upload_bo)
 307                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 308                                    cmd_buffer->upload.upload_bo, 8);
 309         cmd_buffer->upload.offset = 0;
 310
 311         cmd_buffer->record_result = VK_SUCCESS;
 312
 313         cmd_buffer->ring_offsets_idx = -1;
 314
 315         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
 316                 cmd_buffer->descriptors[i].dirty = 0;
 317                 cmd_buffer->descriptors[i].valid = 0;
 318                 cmd_buffer->descriptors[i].push_dirty = false;
 319         }
 320
 321         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 322                 void *fence_ptr;
 323                 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
 324                                              &cmd_buffer->gfx9_fence_offset,
 325                                              &fence_ptr);
 326                 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
 327         }
 328
 329         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
 330
 331         return cmd_buffer->record_result;
 332 }
 333
 334 static bool
 335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
 336                                   uint64_t min_needed)
 337 {
 338         uint64_t new_size;
 339         struct radeon_winsys_bo *bo;
 340         struct radv_cmd_buffer_upload *upload;
 341         struct radv_device *device = cmd_buffer->device;
 342
 343         new_size = MAX2(min_needed, 16 * 1024);
 344         new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
 345
 346         bo = device->ws->buffer_create(device->ws,
 347                                        new_size, 4096,
 348                                        RADEON_DOMAIN_GTT,
 349                                        RADEON_FLAG_CPU_ACCESS|
 350                                        RADEON_FLAG_NO_INTERPROCESS_SHARING);
 351
 352         if (!bo) {
 353                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 354                 return false;
 355         }
 356
 357         radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
 358         if (cmd_buffer->upload.upload_bo) {
 359                 upload = malloc(sizeof(*upload));
 360
 361                 if (!upload) {
 362                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
 363                         device->ws->buffer_destroy(bo);
 364                         return false;
 365                 }
 366
 367                 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
 368                 list_add(&upload->list, &cmd_buffer->upload.list);
 369         }
 370
 371         cmd_buffer->upload.upload_bo = bo;
 372         cmd_buffer->upload.size = new_size;
 373         cmd_buffer->upload.offset = 0;
 374         cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
 375
 376         if (!cmd_buffer->upload.map) {
 377                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 378                 return false;
 379         }
 380
 381         return true;
 382 }
 383
 384 bool
 385 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
 386                              unsigned size,
 387                              unsigned alignment,
 388                              unsigned *out_offset,
 389                              void **ptr)
 390 {
 391         uint64_t offset = align(cmd_buffer->upload.offset, alignment);
 392         if (offset + size > cmd_buffer->upload.size) {
 393                 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
 394                         return false;
 395                 offset = 0;
 396         }
 397
 398         *out_offset = offset;
 399         *ptr = cmd_buffer->upload.map + offset;
 400
 401         cmd_buffer->upload.offset = offset + size;
 402         return true;
 403 }
 404
 405 bool
 406 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
 407                             unsigned size, unsigned alignment,
 408                             const void *data, unsigned *out_offset)
 409 {
 410         uint8_t *ptr;
 411
 412         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
 413                                           out_offset, (void **)&ptr))
 414                 return false;
 415
 416         if (ptr)
 417                 memcpy(ptr, data, size);
 418
 419         return true;
 420 }
 421
 422 static void
 423 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
 424                             unsigned count, const uint32_t *data)
 425 {
 426         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
 427         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
 428                     S_370_WR_CONFIRM(1) |
 429                     S_370_ENGINE_SEL(V_370_ME));
 430         radeon_emit(cs, va);
 431         radeon_emit(cs, va >> 32);
 432         radeon_emit_array(cs, data, count);
 433 }
 434
 435 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
 436 {
 437         struct radv_device *device = cmd_buffer->device;
 438         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 439         uint64_t va;
 440
 441         va = radv_buffer_get_va(device->trace_bo);
 442         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
 443                 va += 4;
 444
 445         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
 446
 447         ++cmd_buffer->state.trace_id;
 448         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 449         radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
 450         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
 451         radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
 452 }
 453
 454 static void
 455 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
 456                            enum radv_cmd_flush_bits flags)
 457 {
 458         if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
 459                 uint32_t *ptr = NULL;
 460                 uint64_t va = 0;
 461
 462                 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
 463                                 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
 464
 465                 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
 466                         va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
 467                              cmd_buffer->gfx9_fence_offset;
 468                         ptr = &cmd_buffer->gfx9_fence_idx;
 469                 }
 470
 471                 /* Force wait for graphics or compute engines to be idle. */
 472                 si_cs_emit_cache_flush(cmd_buffer->cs,
 473                                        cmd_buffer->device->physical_device->rad_info.chip_class,
 474                                        ptr, va,
 475                                        radv_cmd_buffer_uses_mec(cmd_buffer),
 476                                        flags);
 477         }
 478
 479         if (unlikely(cmd_buffer->device->trace_bo))
 480                 radv_cmd_buffer_trace_emit(cmd_buffer);
 481 }
 482
 483 static void
 484 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
 485                    struct radv_pipeline *pipeline, enum ring_type ring)
 486 {
 487         struct radv_device *device = cmd_buffer->device;
 488         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 489         uint32_t data[2];
 490         uint64_t va;
 491
 492         va = radv_buffer_get_va(device->trace_bo);
 493
 494         switch (ring) {
 495         case RING_GFX:
 496                 va += 8;
 497                 break;
 498         case RING_COMPUTE:
 499                 va += 16;
 500                 break;
 501         default:
 502                 assert(!"invalid ring type");
 503         }
 504
 505         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 506                                                            cmd_buffer->cs, 6);
 507
 508         data[0] = (uintptr_t)pipeline;
 509         data[1] = (uintptr_t)pipeline >> 32;
 510
 511         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 512         radv_emit_write_data_packet(cs, va, 2, data);
 513 }
 514
 515 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 516                              VkPipelineBindPoint bind_point,
 517                              struct radv_descriptor_set *set,
 518                              unsigned idx)
 519 {
 520         struct radv_descriptor_state *descriptors_state =
 521                 radv_get_descriptors_state(cmd_buffer, bind_point);
 522
 523         descriptors_state->sets[idx] = set;
 524         if (set)
 525                 descriptors_state->valid |= (1u << idx);
 526         else
 527                 descriptors_state->valid &= ~(1u << idx);
 528         descriptors_state->dirty |= (1u << idx);
 529 }
 530
 531 static void
 532 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
 533                       VkPipelineBindPoint bind_point)
 534 {
 535         struct radv_descriptor_state *descriptors_state =
 536                 radv_get_descriptors_state(cmd_buffer, bind_point);
 537         struct radv_device *device = cmd_buffer->device;
 538         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 539         uint32_t data[MAX_SETS * 2] = {};
 540         uint64_t va;
 541         unsigned i;
 542         va = radv_buffer_get_va(device->trace_bo) + 24;
 543
 544         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 545                                                            cmd_buffer->cs, 4 + MAX_SETS * 2);
 546
 547         for_each_bit(i, descriptors_state->valid) {
 548                 struct radv_descriptor_set *set = descriptors_state->sets[i];
 549                 data[i * 2] = (uintptr_t)set;
 550                 data[i * 2 + 1] = (uintptr_t)set >> 32;
 551         }
 552
 553         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 554         radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
 555 }
 556
 557 struct radv_userdata_info *
 558 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
 559                       gl_shader_stage stage,
 560                       int idx)
 561 {
 562         if (stage == MESA_SHADER_VERTEX) {
 563                 if (pipeline->shaders[MESA_SHADER_VERTEX])
 564                         return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
 565                 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
 566                         return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
 567                 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
 568                         return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
 569         } else if (stage == MESA_SHADER_TESS_EVAL) {
 570                 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
 571                         return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
 572                 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
 573                         return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
 574         }
 575         return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
 576 }
 577
 578 static void
 579 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
 580                            struct radv_pipeline *pipeline,
 581                            gl_shader_stage stage,
 582                            int idx, uint64_t va)
 583 {
 584         struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
 585         uint32_t base_reg = pipeline->user_data_0[stage];
 586         if (loc->sgpr_idx == -1)
 587                 return;
 588         assert(loc->num_sgprs == 2);
 589         assert(!loc->indirect);
 590         radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
 591         radeon_emit(cmd_buffer->cs, va);
 592         radeon_emit(cmd_buffer->cs, va >> 32);
 593 }
 594
 595 static void
 596 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
 597                               struct radv_pipeline *pipeline)
 598 {
 599         int num_samples = pipeline->graphics.ms.num_samples;
 600         struct radv_multisample_state *ms = &pipeline->graphics.ms;
 601         struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
 602
 603         if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
 604                 cmd_buffer->sample_positions_needed = true;
 605
 606         if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
 607                 return;
 608
 609         radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
 610         radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
 611         radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
 612
 613         radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
 614
 615         radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
 616
 617         /* GFX9: Flush DFSM when the AA mode changes. */
 618         if (cmd_buffer->device->dfsm_allowed) {
 619                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 620                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
 621         }
 622 }
 623
 624 static void
 625 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
 626                           struct radv_shader_variant *shader)
 627 {
 628         uint64_t va;
 629
 630         if (!shader)
 631                 return;
 632
 633         va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 634
 635         si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
 636 }
 637
 638 static void
 639 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
 640                       struct radv_pipeline *pipeline,
 641                       bool vertex_stage_only)
 642 {
 643         struct radv_cmd_state *state = &cmd_buffer->state;
 644         uint32_t mask = state->prefetch_L2_mask;
 645
 646         if (vertex_stage_only) {
 647                 /* Fast prefetch path for starting draws as soon as possible.
 648                  */
 649                 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
 650                                                   RADV_PREFETCH_VBO_DESCRIPTORS);
 651         }
 652
 653         if (mask & RADV_PREFETCH_VS)
 654                 radv_emit_shader_prefetch(cmd_buffer,
 655                                           pipeline->shaders[MESA_SHADER_VERTEX]);
 656
 657         if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
 658                 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
 659
 660         if (mask & RADV_PREFETCH_TCS)
 661                 radv_emit_shader_prefetch(cmd_buffer,
 662                                           pipeline->shaders[MESA_SHADER_TESS_CTRL]);
 663
 664         if (mask & RADV_PREFETCH_TES)
 665                 radv_emit_shader_prefetch(cmd_buffer,
 666                                           pipeline->shaders[MESA_SHADER_TESS_EVAL]);
 667
 668         if (mask & RADV_PREFETCH_GS) {
 669                 radv_emit_shader_prefetch(cmd_buffer,
 670                                           pipeline->shaders[MESA_SHADER_GEOMETRY]);
 671                 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
 672         }
 673
 674         if (mask & RADV_PREFETCH_PS)
 675                 radv_emit_shader_prefetch(cmd_buffer,
 676                                           pipeline->shaders[MESA_SHADER_FRAGMENT]);
 677
 678         state->prefetch_L2_mask &= ~mask;
 679 }
 680
 681 static void
 682 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
 683 {
 684         if (!cmd_buffer->device->physical_device->rbplus_allowed)
 685                 return;
 686
 687         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 688         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
 689         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 690
 691         unsigned sx_ps_downconvert = 0;
 692         unsigned sx_blend_opt_epsilon = 0;
 693         unsigned sx_blend_opt_control = 0;
 694
 695         for (unsigned i = 0; i < subpass->color_count; ++i) {
 696                 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
 697                         continue;
 698
 699                 int idx = subpass->color_attachments[i].attachment;
 700                 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
 701
 702                 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
 703                 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
 704                 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
 705                 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
 706
 707                 bool has_alpha, has_rgb;
 708
 709                 /* Set if RGB and A are present. */
 710                 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
 711
 712                 if (format == V_028C70_COLOR_8 ||
 713                     format == V_028C70_COLOR_16 ||
 714                     format == V_028C70_COLOR_32)
 715                         has_rgb = !has_alpha;
 716                 else
 717                         has_rgb = true;
 718
 719                 /* Check the colormask and export format. */
 720                 if (!(colormask & 0x7))
 721                         has_rgb = false;
 722                 if (!(colormask & 0x8))
 723                         has_alpha = false;
 724
 725                 if (spi_format == V_028714_SPI_SHADER_ZERO) {
 726                         has_rgb = false;
 727                         has_alpha = false;
 728                 }
 729
 730                 /* Disable value checking for disabled channels. */
 731                 if (!has_rgb)
 732                         sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 733                 if (!has_alpha)
 734                         sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 735
 736                 /* Enable down-conversion for 32bpp and smaller formats. */
 737                 switch (format) {
 738                 case V_028C70_COLOR_8:
 739                 case V_028C70_COLOR_8_8:
 740                 case V_028C70_COLOR_8_8_8_8:
 741                         /* For 1 and 2-channel formats, use the superset thereof. */
 742                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
 743                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 744                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 745                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
 746                                 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
 747                         }
 748                         break;
 749
 750                 case V_028C70_COLOR_5_6_5:
 751                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 752                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
 753                                 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
 754                         }
 755                         break;
 756
 757                 case V_028C70_COLOR_1_5_5_5:
 758                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 759                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
 760                                 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
 761                         }
 762                         break;
 763
 764                 case V_028C70_COLOR_4_4_4_4:
 765                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 766                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
 767                                 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
 768                         }
 769                         break;
 770
 771                 case V_028C70_COLOR_32:
 772                         if (swap == V_028C70_SWAP_STD &&
 773                             spi_format == V_028714_SPI_SHADER_32_R)
 774                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
 775                         else if (swap == V_028C70_SWAP_ALT_REV &&
 776                                  spi_format == V_028714_SPI_SHADER_32_AR)
 777                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
 778                         break;
 779
 780                 case V_028C70_COLOR_16:
 781                 case V_028C70_COLOR_16_16:
 782                         /* For 1-channel formats, use the superset thereof. */
 783                         if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
 784                             spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
 785                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 786                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 787                                 if (swap == V_028C70_SWAP_STD ||
 788                                     swap == V_028C70_SWAP_STD_REV)
 789                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
 790                                 else
 791                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
 792                         }
 793                         break;
 794
 795                 case V_028C70_COLOR_10_11_11:
 796                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 797                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
 798                                 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
 799                         }
 800                         break;
 801
 802                 case V_028C70_COLOR_2_10_10_10:
 803                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 804                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
 805                                 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
 806                         }
 807                         break;
 808                 }
 809         }
 810
 811         radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
 812         radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
 813         radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
 814         radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
 815 }
 816
 817 static void
 818 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
 819 {
 820         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 821
 822         if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
 823                 return;
 824
 825         radv_update_multisample_state(cmd_buffer, pipeline);
 826
 827         cmd_buffer->scratch_size_needed =
 828                                   MAX2(cmd_buffer->scratch_size_needed,
 829                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
 830
 831         if (!cmd_buffer->state.emitted_pipeline ||
 832             cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
 833              pipeline->graphics.can_use_guardband)
 834                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
 835
 836         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
 837
 838         for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
 839                 if (!pipeline->shaders[i])
 840                         continue;
 841
 842                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 843                                    pipeline->shaders[i]->bo, 8);
 844         }
 845
 846         if (radv_pipeline_has_gs(pipeline))
 847                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 848                                    pipeline->gs_copy_shader->bo, 8);
 849
 850         if (unlikely(cmd_buffer->device->trace_bo))
 851                 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
 852
 853         cmd_buffer->state.emitted_pipeline = pipeline;
 854
 855         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
 856 }
 857
 858 static void
 859 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
 860 {
 861         si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
 862                           cmd_buffer->state.dynamic.viewport.viewports);
 863 }
 864
 865 static void
 866 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
 867 {
 868         uint32_t count = cmd_buffer->state.dynamic.scissor.count;
 869
 870         /* Vega10/Raven scissor bug workaround. This must be done before VPORT
 871          * scissor registers are changed. There is also a more efficient but
 872          * more involved alternative workaround.
 873          */
 874         if (cmd_buffer->device->physical_device->has_scissor_bug) {
 875                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
 876                 si_emit_cache_flush(cmd_buffer);
 877         }
 878         si_write_scissors(cmd_buffer->cs, 0, count,
 879                           cmd_buffer->state.dynamic.scissor.scissors,
 880                           cmd_buffer->state.dynamic.viewport.viewports,
 881                           cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
 882 }
 883
 884 static void
 885 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
 886 {
 887         if (!cmd_buffer->state.dynamic.discard_rectangle.count)
 888                 return;
 889
 890         radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
 891                                    cmd_buffer->state.dynamic.discard_rectangle.count * 2);
 892         for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
 893                 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
 894                 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
 895                 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
 896                                             S_028214_BR_Y(rect.offset.y + rect.extent.height));
 897         }
 898 }
 899
 900 static void
 901 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
 902 {
 903         unsigned width = cmd_buffer->state.dynamic.line_width * 8;
 904
 905         radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
 906                                S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
 907 }
 908
 909 static void
 910 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
 911 {
 912         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 913
 914         radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
 915         radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
 916 }
 917
 918 static void
 919 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
 920 {
 921         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 922
 923         radeon_set_context_reg_seq(cmd_buffer->cs,
 924                                    R_028430_DB_STENCILREFMASK, 2);
 925         radeon_emit(cmd_buffer->cs,
 926                     S_028430_STENCILTESTVAL(d->stencil_reference.front) |
 927                     S_028430_STENCILMASK(d->stencil_compare_mask.front) |
 928                     S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
 929                     S_028430_STENCILOPVAL(1));
 930         radeon_emit(cmd_buffer->cs,
 931                     S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
 932                     S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
 933                     S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
 934                     S_028434_STENCILOPVAL_BF(1));
 935 }
 936
 937 static void
 938 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
 939 {
 940         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 941
 942         radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
 943                                fui(d->depth_bounds.min));
 944         radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
 945                                fui(d->depth_bounds.max));
 946 }
 947
 948 static void
 949 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
 950 {
 951         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 952         unsigned slope = fui(d->depth_bias.slope * 16.0f);
 953         unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
 954
 955
 956         radeon_set_context_reg_seq(cmd_buffer->cs,
 957                                    R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
 958         radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
 959         radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
 960         radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
 961         radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
 962         radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
 963 }
 964
 965 static void
 966 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
 967                          int index,
 968                          struct radv_attachment_info *att,
 969                          struct radv_image *image,
 970                          VkImageLayout layout)
 971 {
 972         bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
 973         struct radv_color_buffer_info *cb = &att->cb;
 974         uint32_t cb_color_info = cb->cb_color_info;
 975
 976         if (!radv_layout_dcc_compressed(image, layout,
 977                                         radv_image_queue_family_mask(image,
 978                                                                      cmd_buffer->queue_family_index,
 979                                                                      cmd_buffer->queue_family_index))) {
 980                 cb_color_info &= C_028C70_DCC_ENABLE;
 981         }
 982
 983         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 984                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
 985                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
 986                 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
 987                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
 988                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
 989                 radeon_emit(cmd_buffer->cs, cb_color_info);
 990                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
 991                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
 992                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
 993                 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
 994                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
 995                 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
 996
 997                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
 998                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
 999                 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1000
1001                 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1002                                        S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1003         } else {
1004                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1005                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1006                 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1007                 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1008                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1009                 radeon_emit(cmd_buffer->cs, cb_color_info);
1010                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1011                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1012                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1013                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1014                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1015                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1016
1017                 if (is_vi) { /* DCC BASE */
1018                         radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1019                 }
1020         }
1021 }
1022
1023 static void
1024 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1025                       struct radv_ds_buffer_info *ds,
1026                       struct radv_image *image,
1027                       VkImageLayout layout)
1028 {
1029         uint32_t db_z_info = ds->db_z_info;
1030         uint32_t db_stencil_info = ds->db_stencil_info;
1031
1032         if (!radv_layout_has_htile(image, layout,
1033                                    radv_image_queue_family_mask(image,
1034                                                                 cmd_buffer->queue_family_index,
1035                                                                 cmd_buffer->queue_family_index))) {
1036                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1037                 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1038         }
1039
1040         radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1041         radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1042
1043
1044         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1045                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1046                 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1047                 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1048                 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1049
1050                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1051                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* DB_Z_INFO */
1052                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* DB_STENCIL_INFO */
1053                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* DB_Z_READ_BASE */
1054                 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32));        /* DB_Z_READ_BASE_HI */
1055                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* DB_STENCIL_READ_BASE */
1056                 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1057                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* DB_Z_WRITE_BASE */
1058                 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32));       /* DB_Z_WRITE_BASE_HI */
1059                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1060                 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1061
1062                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1063                 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1064                 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1065         } else {
1066                 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1067
1068                 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1069                 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1070                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* R_028040_DB_Z_INFO */
1071                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* R_028044_DB_STENCIL_INFO */
1072                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* R_028048_DB_Z_READ_BASE */
1073                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* R_02804C_DB_STENCIL_READ_BASE */
1074                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* R_028050_DB_Z_WRITE_BASE */
1075                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1076                 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1077                 radeon_emit(cmd_buffer->cs, ds->db_depth_slice);        /* R_02805C_DB_DEPTH_SLICE */
1078
1079         }
1080
1081         radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1082                                ds->pa_su_poly_offset_db_fmt_cntl);
1083 }
1084
1085 void
1086 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1087                           struct radv_image *image,
1088                           VkClearDepthStencilValue ds_clear_value,
1089                           VkImageAspectFlags aspects)
1090 {
1091         uint64_t va = radv_buffer_get_va(image->bo);
1092         va += image->offset + image->clear_value_offset;
1093         unsigned reg_offset = 0, reg_count = 0;
1094
1095         assert(radv_image_has_htile(image));
1096
1097         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1098                 ++reg_count;
1099         } else {
1100                 ++reg_offset;
1101                 va += 4;
1102         }
1103         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1104                 ++reg_count;
1105
1106         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1107         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1108                                     S_370_WR_CONFIRM(1) |
1109                                     S_370_ENGINE_SEL(V_370_PFP));
1110         radeon_emit(cmd_buffer->cs, va);
1111         radeon_emit(cmd_buffer->cs, va >> 32);
1112         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1113                 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1114         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1115                 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1116
1117         radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1118         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1119                 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1120         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1121                 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1122 }
1123
1124 static void
1125 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1126                            struct radv_image *image)
1127 {
1128         VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1129         uint64_t va = radv_buffer_get_va(image->bo);
1130         va += image->offset + image->clear_value_offset;
1131         unsigned reg_offset = 0, reg_count = 0;
1132
1133         if (!radv_image_has_htile(image))
1134                 return;
1135
1136         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1137                 ++reg_count;
1138         } else {
1139                 ++reg_offset;
1140                 va += 4;
1141         }
1142         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1143                 ++reg_count;
1144
1145         radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1146         radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1147                                     COPY_DATA_DST_SEL(COPY_DATA_REG) |
1148                                     (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1149         radeon_emit(cmd_buffer->cs, va);
1150         radeon_emit(cmd_buffer->cs, va >> 32);
1151         radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1152         radeon_emit(cmd_buffer->cs, 0);
1153
1154         radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1155         radeon_emit(cmd_buffer->cs, 0);
1156 }
1157
1158 /*
1159  *with DCC some colors don't require CMASK elimiation before being
1160  * used as a texture. This sets a predicate value to determine if the
1161  * cmask eliminate is required.
1162  */
1163 void
1164 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1165                                   struct radv_image *image,
1166                                   bool value)
1167 {
1168         uint64_t pred_val = value;
1169         uint64_t va = radv_buffer_get_va(image->bo);
1170         va += image->offset + image->dcc_pred_offset;
1171
1172         assert(radv_image_has_dcc(image));
1173
1174         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1175         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1176                                     S_370_WR_CONFIRM(1) |
1177                                     S_370_ENGINE_SEL(V_370_PFP));
1178         radeon_emit(cmd_buffer->cs, va);
1179         radeon_emit(cmd_buffer->cs, va >> 32);
1180         radeon_emit(cmd_buffer->cs, pred_val);
1181         radeon_emit(cmd_buffer->cs, pred_val >> 32);
1182 }
1183
1184 void
1185 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1186                           struct radv_image *image,
1187                           int idx,
1188                           uint32_t color_values[2])
1189 {
1190         uint64_t va = radv_buffer_get_va(image->bo);
1191         va += image->offset + image->clear_value_offset;
1192
1193         assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1194
1195         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1196         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1197                                     S_370_WR_CONFIRM(1) |
1198                                     S_370_ENGINE_SEL(V_370_PFP));
1199         radeon_emit(cmd_buffer->cs, va);
1200         radeon_emit(cmd_buffer->cs, va >> 32);
1201         radeon_emit(cmd_buffer->cs, color_values[0]);
1202         radeon_emit(cmd_buffer->cs, color_values[1]);
1203
1204         radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1205         radeon_emit(cmd_buffer->cs, color_values[0]);
1206         radeon_emit(cmd_buffer->cs, color_values[1]);
1207 }
1208
1209 static void
1210 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1211                            struct radv_image *image,
1212                            int idx)
1213 {
1214         uint64_t va = radv_buffer_get_va(image->bo);
1215         va += image->offset + image->clear_value_offset;
1216
1217         if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1218                 return;
1219
1220         uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1221
1222         radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1223         radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1224                                     COPY_DATA_DST_SEL(COPY_DATA_REG) |
1225                                     COPY_DATA_COUNT_SEL);
1226         radeon_emit(cmd_buffer->cs, va);
1227         radeon_emit(cmd_buffer->cs, va >> 32);
1228         radeon_emit(cmd_buffer->cs, reg >> 2);
1229         radeon_emit(cmd_buffer->cs, 0);
1230
1231         radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1232         radeon_emit(cmd_buffer->cs, 0);
1233 }
1234
1235 static void
1236 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1237 {
1238         int i;
1239         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1240         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1241
1242         /* this may happen for inherited secondary recording */
1243         if (!framebuffer)
1244                 return;
1245
1246         for (i = 0; i < 8; ++i) {
1247                 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1248                         radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1249                                        S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1250                         continue;
1251                 }
1252
1253                 int idx = subpass->color_attachments[i].attachment;
1254                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1255                 struct radv_image *image = att->attachment->image;
1256                 VkImageLayout layout = subpass->color_attachments[i].layout;
1257
1258                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1259
1260                 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1261                 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1262
1263                 radv_load_color_clear_regs(cmd_buffer, image, i);
1264         }
1265
1266         if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1267                 int idx = subpass->depth_stencil_attachment.attachment;
1268                 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1269                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1270                 struct radv_image *image = att->attachment->image;
1271                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1272                 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1273                                                                                 cmd_buffer->queue_family_index,
1274                                                                                 cmd_buffer->queue_family_index);
1275                 /* We currently don't support writing decompressed HTILE */
1276                 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1277                        radv_layout_is_htile_compressed(image, layout, queue_mask));
1278
1279                 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1280
1281                 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1282                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1283                         cmd_buffer->state.offset_scale = att->ds.offset_scale;
1284                 }
1285                 radv_load_depth_clear_regs(cmd_buffer, image);
1286         } else {
1287                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1288                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1289                 else
1290                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1291
1292                 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1293                 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1294         }
1295         radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1296                                S_028208_BR_X(framebuffer->width) |
1297                                S_028208_BR_Y(framebuffer->height));
1298
1299         if (cmd_buffer->device->dfsm_allowed) {
1300                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1301                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1302         }
1303
1304         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1305 }
1306
1307 static void
1308 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1309 {
1310         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1311         struct radv_cmd_state *state = &cmd_buffer->state;
1312
1313         if (state->index_type != state->last_index_type) {
1314                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1315                         radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1316                                                    2, state->index_type);
1317                 } else {
1318                         radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1319                         radeon_emit(cs, state->index_type);
1320                 }
1321
1322                 state->last_index_type = state->index_type;
1323         }
1324
1325         radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1326         radeon_emit(cs, state->index_va);
1327         radeon_emit(cs, state->index_va >> 32);
1328
1329         radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1330         radeon_emit(cs, state->max_index_count);
1331
1332         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1333 }
1334
1335 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1336 {
1337         bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1338         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1339         uint32_t pa_sc_mode_cntl_1 =
1340                 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1341         uint32_t db_count_control;
1342
1343         if(!cmd_buffer->state.active_occlusion_queries) {
1344                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1345                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1346                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1347                             has_perfect_queries) {
1348                                 /* Re-enable out-of-order rasterization if the
1349                                  * bound pipeline supports it and if it's has
1350                                  * been disabled before starting any perfect
1351                                  * occlusion queries.
1352                                  */
1353                                 radeon_set_context_reg(cmd_buffer->cs,
1354                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1355                                                        pa_sc_mode_cntl_1);
1356                         }
1357                         db_count_control = 0;
1358                 } else {
1359                         db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1360                 }
1361         } else {
1362                 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1363                 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1364
1365                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1366                         db_count_control =
1367                                 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1368                                 S_028004_SAMPLE_RATE(sample_rate) |
1369                                 S_028004_ZPASS_ENABLE(1) |
1370                                 S_028004_SLICE_EVEN_ENABLE(1) |
1371                                 S_028004_SLICE_ODD_ENABLE(1);
1372
1373                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1374                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1375                             has_perfect_queries) {
1376                                 /* If the bound pipeline has enabled
1377                                  * out-of-order rasterization, we should
1378                                  * disable it before starting any perfect
1379                                  * occlusion queries.
1380                                  */
1381                                 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1382
1383                                 radeon_set_context_reg(cmd_buffer->cs,
1384                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1385                                                        pa_sc_mode_cntl_1);
1386                         }
1387                 } else {
1388                         db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1389                                 S_028004_SAMPLE_RATE(sample_rate);
1390                 }
1391         }
1392
1393         radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1394 }
1395
1396 static void
1397 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1398 {
1399         uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1400
1401         if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1402                 radv_emit_viewport(cmd_buffer);
1403
1404         if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1405                 radv_emit_scissor(cmd_buffer);
1406
1407         if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1408                 radv_emit_line_width(cmd_buffer);
1409
1410         if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1411                 radv_emit_blend_constants(cmd_buffer);
1412
1413         if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1414                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1415                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1416                 radv_emit_stencil(cmd_buffer);
1417
1418         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1419                 radv_emit_depth_bounds(cmd_buffer);
1420
1421         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1422                 radv_emit_depth_bias(cmd_buffer);
1423
1424         if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1425                 radv_emit_discard_rectangle(cmd_buffer);
1426
1427         cmd_buffer->state.dirty &= ~states;
1428 }
1429
1430 static void
1431 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1432                                    struct radv_pipeline *pipeline,
1433                                    int idx,
1434                                    uint64_t va,
1435                                    gl_shader_stage stage)
1436 {
1437         struct radv_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1438         uint32_t base_reg = pipeline->user_data_0[stage];
1439
1440         if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1441                 return;
1442
1443         assert(!desc_set_loc->indirect);
1444         assert(desc_set_loc->num_sgprs == 2);
1445         radeon_set_sh_reg_seq(cmd_buffer->cs,
1446                               base_reg + desc_set_loc->sgpr_idx * 4, 2);
1447         radeon_emit(cmd_buffer->cs, va);
1448         radeon_emit(cmd_buffer->cs, va >> 32);
1449 }
1450
1451 static void
1452 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1453                                   VkShaderStageFlags stages,
1454                                   struct radv_descriptor_set *set,
1455                                   unsigned idx)
1456 {
1457         if (cmd_buffer->state.pipeline) {
1458                 radv_foreach_stage(stage, stages) {
1459                         if (cmd_buffer->state.pipeline->shaders[stage])
1460                                 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1461                                                                    idx, set->va,
1462                                                                    stage);
1463                 }
1464         }
1465
1466         if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1467                 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1468                                                    idx, set->va,
1469                                                    MESA_SHADER_COMPUTE);
1470 }
1471
1472 static void
1473 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1474                             VkPipelineBindPoint bind_point)
1475 {
1476         struct radv_descriptor_state *descriptors_state =
1477                 radv_get_descriptors_state(cmd_buffer, bind_point);
1478         struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1479         unsigned bo_offset;
1480
1481         if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1482                                          set->mapped_ptr,
1483                                          &bo_offset))
1484                 return;
1485
1486         set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1487         set->va += bo_offset;
1488 }
1489
1490 static void
1491 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1492                                     VkPipelineBindPoint bind_point)
1493 {
1494         struct radv_descriptor_state *descriptors_state =
1495                 radv_get_descriptors_state(cmd_buffer, bind_point);
1496         uint32_t size = MAX_SETS * 2 * 4;
1497         uint32_t offset;
1498         void *ptr;
1499
1500         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1501                                           256, &offset, &ptr))
1502                 return;
1503
1504         for (unsigned i = 0; i < MAX_SETS; i++) {
1505                 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1506                 uint64_t set_va = 0;
1507                 struct radv_descriptor_set *set = descriptors_state->sets[i];
1508                 if (descriptors_state->valid & (1u << i))
1509                         set_va = set->va;
1510                 uptr[0] = set_va & 0xffffffff;
1511                 uptr[1] = set_va >> 32;
1512         }
1513
1514         uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1515         va += offset;
1516
1517         if (cmd_buffer->state.pipeline) {
1518                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1519                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1520                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1521
1522                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1523                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1524                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1525
1526                 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1527                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1528                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1529
1530                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1531                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1532                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1533
1534                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1535                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1536                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1537         }
1538
1539         if (cmd_buffer->state.compute_pipeline)
1540                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1541                                            AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1542 }
1543
1544 static void
1545 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1546                        VkShaderStageFlags stages)
1547 {
1548         VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1549                                          VK_PIPELINE_BIND_POINT_COMPUTE :
1550                                          VK_PIPELINE_BIND_POINT_GRAPHICS;
1551         struct radv_descriptor_state *descriptors_state =
1552                 radv_get_descriptors_state(cmd_buffer, bind_point);
1553         unsigned i;
1554
1555         if (!descriptors_state->dirty)
1556                 return;
1557
1558         if (descriptors_state->push_dirty)
1559                 radv_flush_push_descriptors(cmd_buffer, bind_point);
1560
1561         if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1562             (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1563                 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1564         }
1565
1566         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1567                                                            cmd_buffer->cs,
1568                                                            MAX_SETS * MESA_SHADER_STAGES * 4);
1569
1570         for_each_bit(i, descriptors_state->dirty) {
1571                 struct radv_descriptor_set *set = descriptors_state->sets[i];
1572                 if (!(descriptors_state->valid & (1u << i)))
1573                         continue;
1574
1575                 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1576         }
1577         descriptors_state->dirty = 0;
1578         descriptors_state->push_dirty = false;
1579
1580         if (unlikely(cmd_buffer->device->trace_bo))
1581                 radv_save_descriptors(cmd_buffer, bind_point);
1582
1583         assert(cmd_buffer->cs->cdw <= cdw_max);
1584 }
1585
1586 static void
1587 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1588                      VkShaderStageFlags stages)
1589 {
1590         struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1591                                          ? cmd_buffer->state.compute_pipeline
1592                                          : cmd_buffer->state.pipeline;
1593         struct radv_pipeline_layout *layout = pipeline->layout;
1594         unsigned offset;
1595         void *ptr;
1596         uint64_t va;
1597
1598         stages &= cmd_buffer->push_constant_stages;
1599         if (!stages ||
1600             (!layout->push_constant_size && !layout->dynamic_offset_count))
1601                 return;
1602
1603         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1604                                           16 * layout->dynamic_offset_count,
1605                                           256, &offset, &ptr))
1606                 return;
1607
1608         memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1609         memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1610                16 * layout->dynamic_offset_count);
1611
1612         va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1613         va += offset;
1614
1615         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1616                                                            cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1617
1618         radv_foreach_stage(stage, stages) {
1619                 if (pipeline->shaders[stage]) {
1620                         radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1621                                                    AC_UD_PUSH_CONSTANTS, va);
1622                 }
1623         }
1624
1625         cmd_buffer->push_constant_stages &= ~stages;
1626         assert(cmd_buffer->cs->cdw <= cdw_max);
1627 }
1628
1629 static void
1630 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1631                               bool pipeline_is_dirty)
1632 {
1633         if ((pipeline_is_dirty ||
1634             (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1635             cmd_buffer->state.pipeline->vertex_elements.count &&
1636             radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1637                 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1638                 unsigned vb_offset;
1639                 void *vb_ptr;
1640                 uint32_t i = 0;
1641                 uint32_t count = velems->count;
1642                 uint64_t va;
1643
1644                 /* allocate some descriptor state for vertex buffers */
1645                 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1646                                                   &vb_offset, &vb_ptr))
1647                         return;
1648
1649                 for (i = 0; i < count; i++) {
1650                         uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1651                         uint32_t offset;
1652                         int vb = velems->binding[i];
1653                         struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1654                         uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1655
1656                         va = radv_buffer_get_va(buffer->bo);
1657
1658                         offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1659                         va += offset + buffer->offset;
1660                         desc[0] = va;
1661                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1662                         if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1663                                 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1664                         else
1665                                 desc[2] = buffer->size - offset;
1666                         desc[3] = velems->rsrc_word3[i];
1667                 }
1668
1669                 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1670                 va += vb_offset;
1671
1672                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1673                                            AC_UD_VS_VERTEX_BUFFERS, va);
1674
1675                 cmd_buffer->state.vb_va = va;
1676                 cmd_buffer->state.vb_size = count * 16;
1677                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1678         }
1679         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1680 }
1681
1682 static void
1683 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1684 {
1685         radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1686         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1687         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1688 }
1689
1690 static void
1691 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1692                          bool instanced_draw, bool indirect_draw,
1693                          uint32_t draw_vertex_count)
1694 {
1695         struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1696         struct radv_cmd_state *state = &cmd_buffer->state;
1697         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1698         uint32_t ia_multi_vgt_param;
1699         int32_t primitive_reset_en;
1700
1701         /* Draw state. */
1702         ia_multi_vgt_param =
1703                 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1704                                           indirect_draw, draw_vertex_count);
1705
1706         if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1707                 if (info->chip_class >= GFX9) {
1708                         radeon_set_uconfig_reg_idx(cs,
1709                                                    R_030960_IA_MULTI_VGT_PARAM,
1710                                                    4, ia_multi_vgt_param);
1711                 } else if (info->chip_class >= CIK) {
1712                         radeon_set_context_reg_idx(cs,
1713                                                    R_028AA8_IA_MULTI_VGT_PARAM,
1714                                                    1, ia_multi_vgt_param);
1715                 } else {
1716                         radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1717                                                ia_multi_vgt_param);
1718                 }
1719                 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1720         }
1721
1722         /* Primitive restart. */
1723         primitive_reset_en =
1724                 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1725
1726         if (primitive_reset_en != state->last_primitive_reset_en) {
1727                 state->last_primitive_reset_en = primitive_reset_en;
1728                 if (info->chip_class >= GFX9) {
1729                         radeon_set_uconfig_reg(cs,
1730                                                R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1731                                                primitive_reset_en);
1732                 } else {
1733                         radeon_set_context_reg(cs,
1734                                                R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1735                                                primitive_reset_en);
1736                 }
1737         }
1738
1739         if (primitive_reset_en) {
1740                 uint32_t primitive_reset_index =
1741                         state->index_type ? 0xffffffffu : 0xffffu;
1742
1743                 if (primitive_reset_index != state->last_primitive_reset_index) {
1744                         radeon_set_context_reg(cs,
1745                                                R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1746                                                primitive_reset_index);
1747                         state->last_primitive_reset_index = primitive_reset_index;
1748                 }
1749         }
1750 }
1751
1752 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1753                              VkPipelineStageFlags src_stage_mask)
1754 {
1755         if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1756                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1757                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1758                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1759                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1760         }
1761
1762         if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1763                               VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1764                               VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1765                               VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1766                               VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1767                               VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1768                               VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1769                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1770                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1771                               VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1772                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1773                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1774         } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1775                                      VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1776                                      VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1777                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1778         }
1779 }
1780
1781 static enum radv_cmd_flush_bits
1782 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1783                                   VkAccessFlags src_flags)
1784 {
1785         enum radv_cmd_flush_bits flush_bits = 0;
1786         uint32_t b;
1787         for_each_bit(b, src_flags) {
1788                 switch ((VkAccessFlagBits)(1 << b)) {
1789                 case VK_ACCESS_SHADER_WRITE_BIT:
1790                         flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1791                         break;
1792                 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1793                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1794                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1795                         break;
1796                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1797                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1798                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1799                         break;
1800                 case VK_ACCESS_TRANSFER_WRITE_BIT:
1801                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1802                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1803                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1804                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1805                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
1806                         break;
1807                 default:
1808                         break;
1809                 }
1810         }
1811         return flush_bits;
1812 }
1813
1814 static enum radv_cmd_flush_bits
1815 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1816                       VkAccessFlags dst_flags,
1817                       struct radv_image *image)
1818 {
1819         enum radv_cmd_flush_bits flush_bits = 0;
1820         uint32_t b;
1821         for_each_bit(b, dst_flags) {
1822                 switch ((VkAccessFlagBits)(1 << b)) {
1823                 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1824                 case VK_ACCESS_INDEX_READ_BIT:
1825                         break;
1826                 case VK_ACCESS_UNIFORM_READ_BIT:
1827                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1828                         break;
1829                 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1830                 case VK_ACCESS_SHADER_READ_BIT:
1831                 case VK_ACCESS_TRANSFER_READ_BIT:
1832                 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1833                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1834                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
1835                         break;
1836                 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1837                         /* TODO: change to image && when the image gets passed
1838                          * through from the subpass. */
1839                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1840                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1841                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1842                         break;
1843                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1844                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1845                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1846                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1847                         break;
1848                 default:
1849                         break;
1850                 }
1851         }
1852         return flush_bits;
1853 }
1854
1855 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1856 {
1857         cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1858         radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1859         cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1860                                                               NULL);
1861 }
1862
1863 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1864                                                  VkAttachmentReference att)
1865 {
1866         unsigned idx = att.attachment;
1867         struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1868         VkImageSubresourceRange range;
1869         range.aspectMask = 0;
1870         range.baseMipLevel = view->base_mip;
1871         range.levelCount = 1;
1872         range.baseArrayLayer = view->base_layer;
1873         range.layerCount = cmd_buffer->state.framebuffer->layers;
1874
1875         radv_handle_image_transition(cmd_buffer,
1876                                      view->image,
1877                                      cmd_buffer->state.attachments[idx].current_layout,
1878                                      att.layout, 0, 0, &range,
1879                                      cmd_buffer->state.attachments[idx].pending_clear_aspects);
1880
1881         cmd_buffer->state.attachments[idx].current_layout = att.layout;
1882
1883
1884 }
1885
1886 void
1887 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1888                             const struct radv_subpass *subpass, bool transitions)
1889 {
1890         if (transitions) {
1891                 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1892
1893                 for (unsigned i = 0; i < subpass->color_count; ++i) {
1894                         if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1895                                 radv_handle_subpass_image_transition(cmd_buffer,
1896                                                                      subpass->color_attachments[i]);
1897                 }
1898
1899                 for (unsigned i = 0; i < subpass->input_count; ++i) {
1900                         radv_handle_subpass_image_transition(cmd_buffer,
1901                                                         subpass->input_attachments[i]);
1902                 }
1903
1904                 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1905                         radv_handle_subpass_image_transition(cmd_buffer,
1906                                                         subpass->depth_stencil_attachment);
1907                 }
1908         }
1909
1910         cmd_buffer->state.subpass = subpass;
1911
1912         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
1913 }
1914
1915 static VkResult
1916 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1917                                  struct radv_render_pass *pass,
1918                                  const VkRenderPassBeginInfo *info)
1919 {
1920         struct radv_cmd_state *state = &cmd_buffer->state;
1921
1922         if (pass->attachment_count == 0) {
1923                 state->attachments = NULL;
1924                 return VK_SUCCESS;
1925         }
1926
1927         state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1928                                         pass->attachment_count *
1929                                         sizeof(state->attachments[0]),
1930                                         8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1931         if (state->attachments == NULL) {
1932                 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1933                 return cmd_buffer->record_result;
1934         }
1935
1936         for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1937                 struct radv_render_pass_attachment *att = &pass->attachments[i];
1938                 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1939                 VkImageAspectFlags clear_aspects = 0;
1940
1941                 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1942                         /* color attachment */
1943                         if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1944                                 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1945                         }
1946                 } else {
1947                         /* depthstencil attachment */
1948                         if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1949                             att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1950                                 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1951                                 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1952                                     att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1953                                         clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1954                         }
1955                         if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1956                             att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1957                                 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1958                         }
1959                 }
1960
1961                 state->attachments[i].pending_clear_aspects = clear_aspects;
1962                 state->attachments[i].cleared_views = 0;
1963                 if (clear_aspects && info) {
1964                         assert(info->clearValueCount > i);
1965                         state->attachments[i].clear_value = info->pClearValues[i];
1966                 }
1967
1968                 state->attachments[i].current_layout = att->initial_layout;
1969         }
1970
1971         return VK_SUCCESS;
1972 }
1973
1974 VkResult radv_AllocateCommandBuffers(
1975         VkDevice _device,
1976         const VkCommandBufferAllocateInfo *pAllocateInfo,
1977         VkCommandBuffer *pCommandBuffers)
1978 {
1979         RADV_FROM_HANDLE(radv_device, device, _device);
1980         RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1981
1982         VkResult result = VK_SUCCESS;
1983         uint32_t i;
1984
1985         for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1986
1987                 if (!list_empty(&pool->free_cmd_buffers)) {
1988                         struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1989
1990                         list_del(&cmd_buffer->pool_link);
1991                         list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1992
1993                         result = radv_reset_cmd_buffer(cmd_buffer);
1994                         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1995                         cmd_buffer->level = pAllocateInfo->level;
1996
1997                         pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1998                 } else {
1999                         result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2000                                                         &pCommandBuffers[i]);
2001                 }
2002                 if (result != VK_SUCCESS)
2003                         break;
2004         }
2005
2006         if (result != VK_SUCCESS) {
2007                 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2008                                         i, pCommandBuffers);
2009
2010                 /* From the Vulkan 1.0.66 spec:
2011                  *
2012                  * "vkAllocateCommandBuffers can be used to create multiple
2013                  *  command buffers. If the creation of any of those command
2014                  *  buffers fails, the implementation must destroy all
2015                  *  successfully created command buffer objects from this
2016                  *  command, set all entries of the pCommandBuffers array to
2017                  *  NULL and return the error."
2018                  */
2019                 memset(pCommandBuffers, 0,
2020                        sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2021         }
2022
2023         return result;
2024 }
2025
2026 void radv_FreeCommandBuffers(
2027         VkDevice device,
2028         VkCommandPool commandPool,
2029         uint32_t commandBufferCount,
2030         const VkCommandBuffer *pCommandBuffers)
2031 {
2032         for (uint32_t i = 0; i < commandBufferCount; i++) {
2033                 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2034
2035                 if (cmd_buffer) {
2036                         if (cmd_buffer->pool) {
2037                                 list_del(&cmd_buffer->pool_link);
2038                                 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2039                         } else
2040                                 radv_cmd_buffer_destroy(cmd_buffer);
2041
2042                 }
2043         }
2044 }
2045
2046 VkResult radv_ResetCommandBuffer(
2047         VkCommandBuffer commandBuffer,
2048         VkCommandBufferResetFlags flags)
2049 {
2050         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2051         return radv_reset_cmd_buffer(cmd_buffer);
2052 }
2053
2054 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2055 {
2056         struct radv_device *device = cmd_buffer->device;
2057         if (device->gfx_init) {
2058                 uint64_t va = radv_buffer_get_va(device->gfx_init);
2059                 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2060                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2061                 radeon_emit(cmd_buffer->cs, va);
2062                 radeon_emit(cmd_buffer->cs, va >> 32);
2063                 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2064         } else
2065                 si_init_config(cmd_buffer);
2066 }
2067
2068 VkResult radv_BeginCommandBuffer(
2069         VkCommandBuffer commandBuffer,
2070         const VkCommandBufferBeginInfo *pBeginInfo)
2071 {
2072         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2073         VkResult result = VK_SUCCESS;
2074
2075         if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2076                 /* If the command buffer has already been resetted with
2077                  * vkResetCommandBuffer, no need to do it again.
2078                  */
2079                 result = radv_reset_cmd_buffer(cmd_buffer);
2080                 if (result != VK_SUCCESS)
2081                         return result;
2082         }
2083
2084         memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2085         cmd_buffer->state.last_primitive_reset_en = -1;
2086         cmd_buffer->state.last_index_type = -1;
2087         cmd_buffer->state.last_num_instances = -1;
2088         cmd_buffer->state.last_vertex_offset = -1;
2089         cmd_buffer->state.last_first_instance = -1;
2090         cmd_buffer->usage_flags = pBeginInfo->flags;
2091
2092         /* setup initial configuration into command buffer */
2093         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2094                 switch (cmd_buffer->queue_family_index) {
2095                 case RADV_QUEUE_GENERAL:
2096                         emit_gfx_buffer_state(cmd_buffer);
2097                         break;
2098                 case RADV_QUEUE_COMPUTE:
2099                         si_init_compute(cmd_buffer);
2100                         break;
2101                 case RADV_QUEUE_TRANSFER:
2102                 default:
2103                         break;
2104                 }
2105         }
2106
2107         if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2108                 assert(pBeginInfo->pInheritanceInfo);
2109                 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2110                 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2111
2112                 struct radv_subpass *subpass =
2113                         &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2114
2115                 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2116                 if (result != VK_SUCCESS)
2117                         return result;
2118
2119                 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2120         }
2121
2122         if (unlikely(cmd_buffer->device->trace_bo))
2123                 radv_cmd_buffer_trace_emit(cmd_buffer);
2124
2125         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2126
2127         return result;
2128 }
2129
2130 void radv_CmdBindVertexBuffers(
2131         VkCommandBuffer                             commandBuffer,
2132         uint32_t                                    firstBinding,
2133         uint32_t                                    bindingCount,
2134         const VkBuffer*                             pBuffers,
2135         const VkDeviceSize*                         pOffsets)
2136 {
2137         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2138         struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2139         bool changed = false;
2140
2141         /* We have to defer setting up vertex buffer since we need the buffer
2142          * stride from the pipeline. */
2143
2144         assert(firstBinding + bindingCount <= MAX_VBS);
2145         for (uint32_t i = 0; i < bindingCount; i++) {
2146                 uint32_t idx = firstBinding + i;
2147
2148                 if (!changed &&
2149                     (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2150                      vb[idx].offset != pOffsets[i])) {
2151                         changed = true;
2152                 }
2153
2154                 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2155                 vb[idx].offset = pOffsets[i];
2156
2157                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2158                                    vb[idx].buffer->bo, 8);
2159         }
2160
2161         if (!changed) {
2162                 /* No state changes. */
2163                 return;
2164         }
2165
2166         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2167 }
2168
2169 void radv_CmdBindIndexBuffer(
2170         VkCommandBuffer                             commandBuffer,
2171         VkBuffer buffer,
2172         VkDeviceSize offset,
2173         VkIndexType indexType)
2174 {
2175         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2176         RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2177
2178         if (cmd_buffer->state.index_buffer == index_buffer &&
2179             cmd_buffer->state.index_offset == offset &&
2180             cmd_buffer->state.index_type == indexType) {
2181                 /* No state changes. */
2182                 return;
2183         }
2184
2185         cmd_buffer->state.index_buffer = index_buffer;
2186         cmd_buffer->state.index_offset = offset;
2187         cmd_buffer->state.index_type = indexType; /* vk matches hw */
2188         cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2189         cmd_buffer->state.index_va += index_buffer->offset + offset;
2190
2191         int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2192         cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2193         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2194         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2195 }
2196
2197
2198 static void
2199 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2200                          VkPipelineBindPoint bind_point,
2201                          struct radv_descriptor_set *set, unsigned idx)
2202 {
2203         struct radeon_winsys *ws = cmd_buffer->device->ws;
2204
2205         radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2206         if (!set)
2207                 return;
2208
2209         assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2210
2211         if (!cmd_buffer->device->use_global_bo_list) {
2212                 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2213                         if (set->descriptors[j])
2214                                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2215         }
2216
2217         if(set->bo)
2218                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2219 }
2220
2221 void radv_CmdBindDescriptorSets(
2222         VkCommandBuffer                             commandBuffer,
2223         VkPipelineBindPoint                         pipelineBindPoint,
2224         VkPipelineLayout                            _layout,
2225         uint32_t                                    firstSet,
2226         uint32_t                                    descriptorSetCount,
2227         const VkDescriptorSet*                      pDescriptorSets,
2228         uint32_t                                    dynamicOffsetCount,
2229         const uint32_t*                             pDynamicOffsets)
2230 {
2231         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2232         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2233         unsigned dyn_idx = 0;
2234
2235         const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2236
2237         for (unsigned i = 0; i < descriptorSetCount; ++i) {
2238                 unsigned idx = i + firstSet;
2239                 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2240                 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2241
2242                 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2243                         unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2244                         uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2245                         assert(dyn_idx < dynamicOffsetCount);
2246
2247                         struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2248                         uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2249                         dst[0] = va;
2250                         dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2251                         dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2252                         dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2253                                  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2254                                  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2255                                  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2256                                  S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2257                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2258                         cmd_buffer->push_constant_stages |=
2259                                              set->layout->dynamic_shader_stages;
2260                 }
2261         }
2262 }
2263
2264 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2265                                           struct radv_descriptor_set *set,
2266                                           struct radv_descriptor_set_layout *layout,
2267                                           VkPipelineBindPoint bind_point)
2268 {
2269         struct radv_descriptor_state *descriptors_state =
2270                 radv_get_descriptors_state(cmd_buffer, bind_point);
2271         set->size = layout->size;
2272         set->layout = layout;
2273
2274         if (descriptors_state->push_set.capacity < set->size) {
2275                 size_t new_size = MAX2(set->size, 1024);
2276                 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2277                 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2278
2279                 free(set->mapped_ptr);
2280                 set->mapped_ptr = malloc(new_size);
2281
2282                 if (!set->mapped_ptr) {
2283                         descriptors_state->push_set.capacity = 0;
2284                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2285                         return false;
2286                 }
2287
2288                 descriptors_state->push_set.capacity = new_size;
2289         }
2290
2291         return true;
2292 }
2293
2294 void radv_meta_push_descriptor_set(
2295         struct radv_cmd_buffer*              cmd_buffer,
2296         VkPipelineBindPoint                  pipelineBindPoint,
2297         VkPipelineLayout                     _layout,
2298         uint32_t                             set,
2299         uint32_t                             descriptorWriteCount,
2300         const VkWriteDescriptorSet*          pDescriptorWrites)
2301 {
2302         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2303         struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2304         unsigned bo_offset;
2305
2306         assert(set == 0);
2307         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2308
2309         push_set->size = layout->set[set].layout->size;
2310         push_set->layout = layout->set[set].layout;
2311
2312         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2313                                           &bo_offset,
2314                                           (void**) &push_set->mapped_ptr))
2315                 return;
2316
2317         push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2318         push_set->va += bo_offset;
2319
2320         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2321                                     radv_descriptor_set_to_handle(push_set),
2322                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2323
2324         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2325 }
2326
2327 void radv_CmdPushDescriptorSetKHR(
2328         VkCommandBuffer                             commandBuffer,
2329         VkPipelineBindPoint                         pipelineBindPoint,
2330         VkPipelineLayout                            _layout,
2331         uint32_t                                    set,
2332         uint32_t                                    descriptorWriteCount,
2333         const VkWriteDescriptorSet*                 pDescriptorWrites)
2334 {
2335         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2336         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2337         struct radv_descriptor_state *descriptors_state =
2338                 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2339         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2340
2341         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2342
2343         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2344                                            layout->set[set].layout,
2345                                            pipelineBindPoint))
2346                 return;
2347
2348         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2349                                     radv_descriptor_set_to_handle(push_set),
2350                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2351
2352         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2353         descriptors_state->push_dirty = true;
2354 }
2355
2356 void radv_CmdPushDescriptorSetWithTemplateKHR(
2357         VkCommandBuffer                             commandBuffer,
2358         VkDescriptorUpdateTemplateKHR               descriptorUpdateTemplate,
2359         VkPipelineLayout                            _layout,
2360         uint32_t                                    set,
2361         const void*                                 pData)
2362 {
2363         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2364         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2365         RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2366         struct radv_descriptor_state *descriptors_state =
2367                 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2368         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2369
2370         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2371
2372         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2373                                            layout->set[set].layout,
2374                                            templ->bind_point))
2375                 return;
2376
2377         radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2378                                                  descriptorUpdateTemplate, pData);
2379
2380         radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2381         descriptors_state->push_dirty = true;
2382 }
2383
2384 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2385                            VkPipelineLayout layout,
2386                            VkShaderStageFlags stageFlags,
2387                            uint32_t offset,
2388                            uint32_t size,
2389                            const void* pValues)
2390 {
2391         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2392         memcpy(cmd_buffer->push_constants + offset, pValues, size);
2393         cmd_buffer->push_constant_stages |= stageFlags;
2394 }
2395
2396 VkResult radv_EndCommandBuffer(
2397         VkCommandBuffer                             commandBuffer)
2398 {
2399         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2400
2401         if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2402                 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2403                         cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2404                 si_emit_cache_flush(cmd_buffer);
2405         }
2406
2407         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2408
2409         if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2410                 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2411
2412         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2413
2414         return cmd_buffer->record_result;
2415 }
2416
2417 static void
2418 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2419 {
2420         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2421
2422         if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2423                 return;
2424
2425         cmd_buffer->state.emitted_compute_pipeline = pipeline;
2426
2427         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2428         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2429
2430         cmd_buffer->compute_scratch_size_needed =
2431                                   MAX2(cmd_buffer->compute_scratch_size_needed,
2432                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2433
2434         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2435                            pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
2436
2437         if (unlikely(cmd_buffer->device->trace_bo))
2438                 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2439 }
2440
2441 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2442                                             VkPipelineBindPoint bind_point)
2443 {
2444         struct radv_descriptor_state *descriptors_state =
2445                 radv_get_descriptors_state(cmd_buffer, bind_point);
2446
2447         descriptors_state->dirty |= descriptors_state->valid;
2448 }
2449
2450 void radv_CmdBindPipeline(
2451         VkCommandBuffer                             commandBuffer,
2452         VkPipelineBindPoint                         pipelineBindPoint,
2453         VkPipeline                                  _pipeline)
2454 {
2455         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2456         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2457
2458         switch (pipelineBindPoint) {
2459         case VK_PIPELINE_BIND_POINT_COMPUTE:
2460                 if (cmd_buffer->state.compute_pipeline == pipeline)
2461                         return;
2462                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2463
2464                 cmd_buffer->state.compute_pipeline = pipeline;
2465                 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2466                 break;
2467         case VK_PIPELINE_BIND_POINT_GRAPHICS:
2468                 if (cmd_buffer->state.pipeline == pipeline)
2469                         return;
2470                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2471
2472                 cmd_buffer->state.pipeline = pipeline;
2473                 if (!pipeline)
2474                         break;
2475
2476                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2477                 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2478
2479                 /* the new vertex shader might not have the same user regs */
2480                 cmd_buffer->state.last_first_instance = -1;
2481                 cmd_buffer->state.last_vertex_offset = -1;
2482
2483                 /* Prefetch all pipeline shaders at first draw time. */
2484                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2485
2486                 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2487
2488                 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2489                         cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2490                 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2491                         cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2492
2493                 if (radv_pipeline_has_tess(pipeline))
2494                         cmd_buffer->tess_rings_needed = true;
2495
2496                 if (radv_pipeline_has_gs(pipeline)) {
2497                         struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2498                                                                              AC_UD_SCRATCH_RING_OFFSETS);
2499                         if (cmd_buffer->ring_offsets_idx == -1)
2500                                 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2501                         else if (loc->sgpr_idx != -1)
2502                                 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2503                 }
2504                 break;
2505         default:
2506                 assert(!"invalid bind point");
2507                 break;
2508         }
2509 }
2510
2511 void radv_CmdSetViewport(
2512         VkCommandBuffer                             commandBuffer,
2513         uint32_t                                    firstViewport,
2514         uint32_t                                    viewportCount,
2515         const VkViewport*                           pViewports)
2516 {
2517         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2518         struct radv_cmd_state *state = &cmd_buffer->state;
2519         MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2520
2521         assert(firstViewport < MAX_VIEWPORTS);
2522         assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2523
2524         if (cmd_buffer->device->physical_device->has_scissor_bug) {
2525                 /* Try to skip unnecessary PS partial flushes when the viewports
2526                  * don't change.
2527                  */
2528                 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2529                                       RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2530                     !memcmp(state->dynamic.viewport.viewports + firstViewport,
2531                             pViewports, viewportCount * sizeof(*pViewports))) {
2532                         return;
2533                 }
2534         }
2535
2536         memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2537                viewportCount * sizeof(*pViewports));
2538
2539         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2540 }
2541
2542 void radv_CmdSetScissor(
2543         VkCommandBuffer                             commandBuffer,
2544         uint32_t                                    firstScissor,
2545         uint32_t                                    scissorCount,
2546         const VkRect2D*                             pScissors)
2547 {
2548         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2549         struct radv_cmd_state *state = &cmd_buffer->state;
2550         MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2551
2552         assert(firstScissor < MAX_SCISSORS);
2553         assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2554
2555         if (cmd_buffer->device->physical_device->has_scissor_bug) {
2556                 /* Try to skip unnecessary PS partial flushes when the scissors
2557                  * don't change.
2558                  */
2559                 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2560                                       RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2561                     !memcmp(state->dynamic.scissor.scissors + firstScissor,
2562                             pScissors, scissorCount * sizeof(*pScissors))) {
2563                         return;
2564                 }
2565         }
2566
2567         memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2568                scissorCount * sizeof(*pScissors));
2569
2570         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2571 }
2572
2573 void radv_CmdSetLineWidth(
2574         VkCommandBuffer                             commandBuffer,
2575         float                                       lineWidth)
2576 {
2577         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2578         cmd_buffer->state.dynamic.line_width = lineWidth;
2579         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2580 }
2581
2582 void radv_CmdSetDepthBias(
2583         VkCommandBuffer                             commandBuffer,
2584         float                                       depthBiasConstantFactor,
2585         float                                       depthBiasClamp,
2586         float                                       depthBiasSlopeFactor)
2587 {
2588         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2589
2590         cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2591         cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2592         cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2593
2594         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2595 }
2596
2597 void radv_CmdSetBlendConstants(
2598         VkCommandBuffer                             commandBuffer,
2599         const float                                 blendConstants[4])
2600 {
2601         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2602
2603         memcpy(cmd_buffer->state.dynamic.blend_constants,
2604                blendConstants, sizeof(float) * 4);
2605
2606         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2607 }
2608
2609 void radv_CmdSetDepthBounds(
2610         VkCommandBuffer                             commandBuffer,
2611         float                                       minDepthBounds,
2612         float                                       maxDepthBounds)
2613 {
2614         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2615
2616         cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2617         cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2618
2619         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2620 }
2621
2622 void radv_CmdSetStencilCompareMask(
2623         VkCommandBuffer                             commandBuffer,
2624         VkStencilFaceFlags                          faceMask,
2625         uint32_t                                    compareMask)
2626 {
2627         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2628
2629         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2630                 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2631         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2632                 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2633
2634         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2635 }
2636
2637 void radv_CmdSetStencilWriteMask(
2638         VkCommandBuffer                             commandBuffer,
2639         VkStencilFaceFlags                          faceMask,
2640         uint32_t                                    writeMask)
2641 {
2642         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2643
2644         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2645                 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2646         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2647                 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2648
2649         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2650 }
2651
2652 void radv_CmdSetStencilReference(
2653         VkCommandBuffer                             commandBuffer,
2654         VkStencilFaceFlags                          faceMask,
2655         uint32_t                                    reference)
2656 {
2657         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2658
2659         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2660                 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2661         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2662                 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2663
2664         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2665 }
2666
2667 void radv_CmdSetDiscardRectangleEXT(
2668         VkCommandBuffer                             commandBuffer,
2669         uint32_t                                    firstDiscardRectangle,
2670         uint32_t                                    discardRectangleCount,
2671         const VkRect2D*                             pDiscardRectangles)
2672 {
2673         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2674         struct radv_cmd_state *state = &cmd_buffer->state;
2675         MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2676
2677         assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2678         assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2679
2680         typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2681                      pDiscardRectangles, discardRectangleCount);
2682
2683         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2684 }
2685
2686 void radv_CmdExecuteCommands(
2687         VkCommandBuffer                             commandBuffer,
2688         uint32_t                                    commandBufferCount,
2689         const VkCommandBuffer*                      pCmdBuffers)
2690 {
2691         RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2692
2693         assert(commandBufferCount > 0);
2694
2695         /* Emit pending flushes on primary prior to executing secondary */
2696         si_emit_cache_flush(primary);
2697
2698         for (uint32_t i = 0; i < commandBufferCount; i++) {
2699                 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2700
2701                 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2702                                                     secondary->scratch_size_needed);
2703                 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2704                                                             secondary->compute_scratch_size_needed);
2705
2706                 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2707                         primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2708                 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2709                         primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2710                 if (secondary->tess_rings_needed)
2711                         primary->tess_rings_needed = true;
2712                 if (secondary->sample_positions_needed)
2713                         primary->sample_positions_needed = true;
2714
2715                 if (secondary->ring_offsets_idx != -1) {
2716                         if (primary->ring_offsets_idx == -1)
2717                                 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2718                         else
2719                                 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2720                 }
2721                 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2722
2723
2724                 /* When the secondary command buffer is compute only we don't
2725                  * need to re-emit the current graphics pipeline.
2726                  */
2727                 if (secondary->state.emitted_pipeline) {
2728                         primary->state.emitted_pipeline =
2729                                 secondary->state.emitted_pipeline;
2730                 }
2731
2732                 /* When the secondary command buffer is graphics only we don't
2733                  * need to re-emit the current compute pipeline.
2734                  */
2735                 if (secondary->state.emitted_compute_pipeline) {
2736                         primary->state.emitted_compute_pipeline =
2737                                 secondary->state.emitted_compute_pipeline;
2738                 }
2739
2740                 /* Only re-emit the draw packets when needed. */
2741                 if (secondary->state.last_primitive_reset_en != -1) {
2742                         primary->state.last_primitive_reset_en =
2743                                 secondary->state.last_primitive_reset_en;
2744                 }
2745
2746                 if (secondary->state.last_primitive_reset_index) {
2747                         primary->state.last_primitive_reset_index =
2748                                 secondary->state.last_primitive_reset_index;
2749                 }
2750
2751                 if (secondary->state.last_ia_multi_vgt_param) {
2752                         primary->state.last_ia_multi_vgt_param =
2753                                 secondary->state.last_ia_multi_vgt_param;
2754                 }
2755
2756                 primary->state.last_first_instance = secondary->state.last_first_instance;
2757                 primary->state.last_num_instances = secondary->state.last_num_instances;
2758                 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2759
2760                 if (secondary->state.last_index_type != -1) {
2761                         primary->state.last_index_type =
2762                                 secondary->state.last_index_type;
2763                 }
2764         }
2765
2766         /* After executing commands from secondary buffers we have to dirty
2767          * some states.
2768          */
2769         primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2770                                 RADV_CMD_DIRTY_INDEX_BUFFER |
2771                                 RADV_CMD_DIRTY_DYNAMIC_ALL;
2772         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2773         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2774 }
2775
2776 VkResult radv_CreateCommandPool(
2777         VkDevice                                    _device,
2778         const VkCommandPoolCreateInfo*              pCreateInfo,
2779         const VkAllocationCallbacks*                pAllocator,
2780         VkCommandPool*                              pCmdPool)
2781 {
2782         RADV_FROM_HANDLE(radv_device, device, _device);
2783         struct radv_cmd_pool *pool;
2784
2785         pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2786                            VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2787         if (pool == NULL)
2788                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2789
2790         if (pAllocator)
2791                 pool->alloc = *pAllocator;
2792         else
2793                 pool->alloc = device->alloc;
2794
2795         list_inithead(&pool->cmd_buffers);
2796         list_inithead(&pool->free_cmd_buffers);
2797
2798         pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2799
2800         *pCmdPool = radv_cmd_pool_to_handle(pool);
2801
2802         return VK_SUCCESS;
2803
2804 }
2805
2806 void radv_DestroyCommandPool(
2807         VkDevice                                    _device,
2808         VkCommandPool                               commandPool,
2809         const VkAllocationCallbacks*                pAllocator)
2810 {
2811         RADV_FROM_HANDLE(radv_device, device, _device);
2812         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2813
2814         if (!pool)
2815                 return;
2816
2817         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2818                                  &pool->cmd_buffers, pool_link) {
2819                 radv_cmd_buffer_destroy(cmd_buffer);
2820         }
2821
2822         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2823                                  &pool->free_cmd_buffers, pool_link) {
2824                 radv_cmd_buffer_destroy(cmd_buffer);
2825         }
2826
2827         vk_free2(&device->alloc, pAllocator, pool);
2828 }
2829
2830 VkResult radv_ResetCommandPool(
2831         VkDevice                                    device,
2832         VkCommandPool                               commandPool,
2833         VkCommandPoolResetFlags                     flags)
2834 {
2835         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2836         VkResult result;
2837
2838         list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2839                             &pool->cmd_buffers, pool_link) {
2840                 result = radv_reset_cmd_buffer(cmd_buffer);
2841                 if (result != VK_SUCCESS)
2842                         return result;
2843         }
2844
2845         return VK_SUCCESS;
2846 }
2847
2848 void radv_TrimCommandPool(
2849     VkDevice                                    device,
2850     VkCommandPool                               commandPool,
2851     VkCommandPoolTrimFlagsKHR                   flags)
2852 {
2853         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2854
2855         if (!pool)
2856                 return;
2857
2858         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2859                                  &pool->free_cmd_buffers, pool_link) {
2860                 radv_cmd_buffer_destroy(cmd_buffer);
2861         }
2862 }
2863
2864 void radv_CmdBeginRenderPass(
2865         VkCommandBuffer                             commandBuffer,
2866         const VkRenderPassBeginInfo*                pRenderPassBegin,
2867         VkSubpassContents                           contents)
2868 {
2869         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2870         RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2871         RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2872
2873         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2874                                                            cmd_buffer->cs, 2048);
2875         MAYBE_UNUSED VkResult result;
2876
2877         cmd_buffer->state.framebuffer = framebuffer;
2878         cmd_buffer->state.pass = pass;
2879         cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2880
2881         result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2882         if (result != VK_SUCCESS)
2883                 return;
2884
2885         radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2886         assert(cmd_buffer->cs->cdw <= cdw_max);
2887
2888         radv_cmd_buffer_clear_subpass(cmd_buffer);
2889 }
2890
2891 void radv_CmdNextSubpass(
2892     VkCommandBuffer                             commandBuffer,
2893     VkSubpassContents                           contents)
2894 {
2895         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2896
2897         radv_cmd_buffer_resolve_subpass(cmd_buffer);
2898
2899         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2900                                               2048);
2901
2902         radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2903         radv_cmd_buffer_clear_subpass(cmd_buffer);
2904 }
2905
2906 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2907 {
2908         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2909         for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2910                 if (!pipeline->shaders[stage])
2911                         continue;
2912                 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2913                 if (loc->sgpr_idx == -1)
2914                         continue;
2915                 uint32_t base_reg = pipeline->user_data_0[stage];
2916                 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2917
2918         }
2919         if (pipeline->gs_copy_shader) {
2920                 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2921                 if (loc->sgpr_idx != -1) {
2922                         uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2923                         radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2924                 }
2925         }
2926 }
2927
2928 static void
2929 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2930                          uint32_t vertex_count)
2931 {
2932         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2933         radeon_emit(cmd_buffer->cs, vertex_count);
2934         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2935                                     S_0287F0_USE_OPAQUE(0));
2936 }
2937
2938 static void
2939 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2940                                  uint64_t index_va,
2941                                  uint32_t index_count)
2942 {
2943         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2944         radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2945         radeon_emit(cmd_buffer->cs, index_va);
2946         radeon_emit(cmd_buffer->cs, index_va >> 32);
2947         radeon_emit(cmd_buffer->cs, index_count);
2948         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2949 }
2950
2951 static void
2952 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2953                                   bool indexed,
2954                                   uint32_t draw_count,
2955                                   uint64_t count_va,
2956                                   uint32_t stride)
2957 {
2958         struct radeon_winsys_cs *cs = cmd_buffer->cs;
2959         unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2960                                       : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2961         bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
2962         uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2963         assert(base_reg);
2964
2965         /* just reset draw state for vertex data */
2966         cmd_buffer->state.last_first_instance = -1;
2967         cmd_buffer->state.last_num_instances = -1;
2968         cmd_buffer->state.last_vertex_offset = -1;
2969
2970         if (draw_count == 1 && !count_va && !draw_id_enable) {
2971                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2972                                      PKT3_DRAW_INDIRECT, 3, false));
2973                 radeon_emit(cs, 0);
2974                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2975                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2976                 radeon_emit(cs, di_src_sel);
2977         } else {
2978                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2979                                      PKT3_DRAW_INDIRECT_MULTI,
2980                                      8, false));
2981                 radeon_emit(cs, 0);
2982                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2983                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2984                 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2985                             S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2986                             S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2987                 radeon_emit(cs, draw_count); /* count */
2988                 radeon_emit(cs, count_va); /* count_addr */
2989                 radeon_emit(cs, count_va >> 32);
2990                 radeon_emit(cs, stride); /* stride */
2991                 radeon_emit(cs, di_src_sel);
2992         }
2993 }
2994
2995 struct radv_draw_info {
2996         /**
2997          * Number of vertices.
2998          */
2999         uint32_t count;
3000
3001         /**
3002          * Index of the first vertex.
3003          */
3004         int32_t vertex_offset;
3005
3006         /**
3007          * First instance id.
3008          */
3009         uint32_t first_instance;
3010
3011         /**
3012          * Number of instances.
3013          */
3014         uint32_t instance_count;
3015
3016         /**
3017          * First index (indexed draws only).
3018          */
3019         uint32_t first_index;
3020
3021         /**
3022          * Whether it's an indexed draw.
3023          */
3024         bool indexed;
3025
3026         /**
3027          * Indirect draw parameters resource.
3028          */
3029         struct radv_buffer *indirect;
3030         uint64_t indirect_offset;
3031         uint32_t stride;
3032
3033         /**
3034          * Draw count parameters resource.
3035          */
3036         struct radv_buffer *count_buffer;
3037         uint64_t count_buffer_offset;
3038 };
3039
3040 static void
3041 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3042                        const struct radv_draw_info *info)
3043 {
3044         struct radv_cmd_state *state = &cmd_buffer->state;
3045         struct radeon_winsys *ws = cmd_buffer->device->ws;
3046         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3047
3048         if (info->indirect) {
3049                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3050                 uint64_t count_va = 0;
3051
3052                 va += info->indirect->offset + info->indirect_offset;
3053
3054                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3055
3056                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3057                 radeon_emit(cs, 1);
3058                 radeon_emit(cs, va);
3059                 radeon_emit(cs, va >> 32);
3060
3061                 if (info->count_buffer) {
3062                         count_va = radv_buffer_get_va(info->count_buffer->bo);
3063                         count_va += info->count_buffer->offset +
3064                                     info->count_buffer_offset;
3065
3066                         radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3067                 }
3068
3069                 if (!state->subpass->view_mask) {
3070                         radv_cs_emit_indirect_draw_packet(cmd_buffer,
3071                                                           info->indexed,
3072                                                           info->count,
3073                                                           count_va,
3074                                                           info->stride);
3075                 } else {
3076                         unsigned i;
3077                         for_each_bit(i, state->subpass->view_mask) {
3078                                 radv_emit_view_index(cmd_buffer, i);
3079
3080                                 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3081                                                                   info->indexed,
3082                                                                   info->count,
3083                                                                   count_va,
3084                                                                   info->stride);
3085                         }
3086                 }
3087         } else {
3088                 assert(state->pipeline->graphics.vtx_base_sgpr);
3089
3090                 if (info->vertex_offset != state->last_vertex_offset ||
3091                     info->first_instance != state->last_first_instance) {
3092                         radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3093                                               state->pipeline->graphics.vtx_emit_num);
3094
3095                         radeon_emit(cs, info->vertex_offset);
3096                         radeon_emit(cs, info->first_instance);
3097                         if (state->pipeline->graphics.vtx_emit_num == 3)
3098                                 radeon_emit(cs, 0);
3099                         state->last_first_instance = info->first_instance;
3100                         state->last_vertex_offset = info->vertex_offset;
3101                 }
3102
3103                 if (state->last_num_instances != info->instance_count) {
3104                         radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3105                         radeon_emit(cs, info->instance_count);
3106                         state->last_num_instances = info->instance_count;
3107                 }
3108
3109                 if (info->indexed) {
3110                         int index_size = state->index_type ? 4 : 2;
3111                         uint64_t index_va;
3112
3113                         index_va = state->index_va;
3114                         index_va += info->first_index * index_size;
3115
3116                         if (!state->subpass->view_mask) {
3117                                 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3118                                                                  index_va,
3119                                                                  info->count);
3120                         } else {
3121                                 unsigned i;
3122                                 for_each_bit(i, state->subpass->view_mask) {
3123                                         radv_emit_view_index(cmd_buffer, i);
3124
3125                                         radv_cs_emit_draw_indexed_packet(cmd_buffer,
3126                                                                          index_va,
3127                                                                          info->count);
3128                                 }
3129                         }
3130                 } else {
3131                         if (!state->subpass->view_mask) {
3132                                 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3133                         } else {
3134                                 unsigned i;
3135                                 for_each_bit(i, state->subpass->view_mask) {
3136                                         radv_emit_view_index(cmd_buffer, i);
3137
3138                                         radv_cs_emit_draw_packet(cmd_buffer,
3139                                                                  info->count);
3140                                 }
3141                         }
3142                 }
3143         }
3144 }
3145
3146 static void
3147 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3148                               const struct radv_draw_info *info)
3149 {
3150         if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3151             cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3152                 radv_emit_rbplus_state(cmd_buffer);
3153
3154         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3155                 radv_emit_graphics_pipeline(cmd_buffer);
3156
3157         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3158                 radv_emit_framebuffer_state(cmd_buffer);
3159
3160         if (info->indexed) {
3161                 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3162                         radv_emit_index_buffer(cmd_buffer);
3163         } else {
3164                 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3165                  * so the state must be re-emitted before the next indexed
3166                  * draw.
3167                  */
3168                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3169                         cmd_buffer->state.last_index_type = -1;
3170                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3171                 }
3172         }
3173
3174         radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3175
3176         radv_emit_draw_registers(cmd_buffer, info->indexed,
3177                                  info->instance_count > 1, info->indirect,
3178                                  info->indirect ? 0 : info->count);
3179 }
3180
3181 static void
3182 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3183           const struct radv_draw_info *info)
3184 {
3185         bool has_prefetch =
3186                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3187         bool pipeline_is_dirty =
3188                 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3189                 cmd_buffer->state.pipeline &&
3190                 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3191
3192         MAYBE_UNUSED unsigned cdw_max =
3193                 radeon_check_space(cmd_buffer->device->ws,
3194                                    cmd_buffer->cs, 4096);
3195
3196         /* Use optimal packet order based on whether we need to sync the
3197          * pipeline.
3198          */
3199         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3200                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3201                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3202                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3203                 /* If we have to wait for idle, set all states first, so that
3204                  * all SET packets are processed in parallel with previous draw
3205                  * calls. Then upload descriptors, set shader pointers, and
3206                  * draw, and prefetch at the end. This ensures that the time
3207                  * the CUs are idle is very short. (there are only SET_SH
3208                  * packets between the wait and the draw)
3209                  */
3210                 radv_emit_all_graphics_states(cmd_buffer, info);
3211                 si_emit_cache_flush(cmd_buffer);
3212                 /* <-- CUs are idle here --> */
3213
3214                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3215
3216                 radv_emit_draw_packets(cmd_buffer, info);
3217                 /* <-- CUs are busy here --> */
3218
3219                 /* Start prefetches after the draw has been started. Both will
3220                  * run in parallel, but starting the draw first is more
3221                  * important.
3222                  */
3223                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3224                         radv_emit_prefetch_L2(cmd_buffer,
3225                                               cmd_buffer->state.pipeline, false);
3226                 }
3227         } else {
3228                 /* If we don't wait for idle, start prefetches first, then set
3229                  * states, and draw at the end.
3230                  */
3231                 si_emit_cache_flush(cmd_buffer);
3232
3233                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3234                         /* Only prefetch the vertex shader and VBO descriptors
3235                          * in order to start the draw as soon as possible.
3236                          */
3237                         radv_emit_prefetch_L2(cmd_buffer,
3238                                               cmd_buffer->state.pipeline, true);
3239                 }
3240
3241                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3242
3243                 radv_emit_all_graphics_states(cmd_buffer, info);
3244                 radv_emit_draw_packets(cmd_buffer, info);
3245
3246                 /* Prefetch the remaining shaders after the draw has been
3247                  * started.
3248                  */
3249                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3250                         radv_emit_prefetch_L2(cmd_buffer,
3251                                               cmd_buffer->state.pipeline, false);
3252                 }
3253         }
3254
3255         assert(cmd_buffer->cs->cdw <= cdw_max);
3256         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3257 }
3258
3259 void radv_CmdDraw(
3260         VkCommandBuffer                             commandBuffer,
3261         uint32_t                                    vertexCount,
3262         uint32_t                                    instanceCount,
3263         uint32_t                                    firstVertex,
3264         uint32_t                                    firstInstance)
3265 {
3266         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3267         struct radv_draw_info info = {};
3268
3269         info.count = vertexCount;
3270         info.instance_count = instanceCount;
3271         info.first_instance = firstInstance;
3272         info.vertex_offset = firstVertex;
3273
3274         radv_draw(cmd_buffer, &info);
3275 }
3276
3277 void radv_CmdDrawIndexed(
3278         VkCommandBuffer                             commandBuffer,
3279         uint32_t                                    indexCount,
3280         uint32_t                                    instanceCount,
3281         uint32_t                                    firstIndex,
3282         int32_t                                     vertexOffset,
3283         uint32_t                                    firstInstance)
3284 {
3285         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3286         struct radv_draw_info info = {};
3287
3288         info.indexed = true;
3289         info.count = indexCount;
3290         info.instance_count = instanceCount;
3291         info.first_index = firstIndex;
3292         info.vertex_offset = vertexOffset;
3293         info.first_instance = firstInstance;
3294
3295         radv_draw(cmd_buffer, &info);
3296 }
3297
3298 void radv_CmdDrawIndirect(
3299         VkCommandBuffer                             commandBuffer,
3300         VkBuffer                                    _buffer,
3301         VkDeviceSize                                offset,
3302         uint32_t                                    drawCount,
3303         uint32_t                                    stride)
3304 {
3305         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3306         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3307         struct radv_draw_info info = {};
3308
3309         info.count = drawCount;
3310         info.indirect = buffer;
3311         info.indirect_offset = offset;
3312         info.stride = stride;
3313
3314         radv_draw(cmd_buffer, &info);
3315 }
3316
3317 void radv_CmdDrawIndexedIndirect(
3318         VkCommandBuffer                             commandBuffer,
3319         VkBuffer                                    _buffer,
3320         VkDeviceSize                                offset,
3321         uint32_t                                    drawCount,
3322         uint32_t                                    stride)
3323 {
3324         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3325         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3326         struct radv_draw_info info = {};
3327
3328         info.indexed = true;
3329         info.count = drawCount;
3330         info.indirect = buffer;
3331         info.indirect_offset = offset;
3332         info.stride = stride;
3333
3334         radv_draw(cmd_buffer, &info);
3335 }
3336
3337 void radv_CmdDrawIndirectCountAMD(
3338         VkCommandBuffer                             commandBuffer,
3339         VkBuffer                                    _buffer,
3340         VkDeviceSize                                offset,
3341         VkBuffer                                    _countBuffer,
3342         VkDeviceSize                                countBufferOffset,
3343         uint32_t                                    maxDrawCount,
3344         uint32_t                                    stride)
3345 {
3346         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3347         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3348         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3349         struct radv_draw_info info = {};
3350
3351         info.count = maxDrawCount;
3352         info.indirect = buffer;
3353         info.indirect_offset = offset;
3354         info.count_buffer = count_buffer;
3355         info.count_buffer_offset = countBufferOffset;
3356         info.stride = stride;
3357
3358         radv_draw(cmd_buffer, &info);
3359 }
3360
3361 void radv_CmdDrawIndexedIndirectCountAMD(
3362         VkCommandBuffer                             commandBuffer,
3363         VkBuffer                                    _buffer,
3364         VkDeviceSize                                offset,
3365         VkBuffer                                    _countBuffer,
3366         VkDeviceSize                                countBufferOffset,
3367         uint32_t                                    maxDrawCount,
3368         uint32_t                                    stride)
3369 {
3370         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3371         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3372         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3373         struct radv_draw_info info = {};
3374
3375         info.indexed = true;
3376         info.count = maxDrawCount;
3377         info.indirect = buffer;
3378         info.indirect_offset = offset;
3379         info.count_buffer = count_buffer;
3380         info.count_buffer_offset = countBufferOffset;
3381         info.stride = stride;
3382
3383         radv_draw(cmd_buffer, &info);
3384 }
3385
3386 struct radv_dispatch_info {
3387         /**
3388          * Determine the layout of the grid (in block units) to be used.
3389          */
3390         uint32_t blocks[3];
3391
3392         /**
3393          * A starting offset for the grid. If unaligned is set, the offset
3394          * must still be aligned.
3395          */
3396         uint32_t offsets[3];
3397         /**
3398          * Whether it's an unaligned compute dispatch.
3399          */
3400         bool unaligned;
3401
3402         /**
3403          * Indirect compute parameters resource.
3404          */
3405         struct radv_buffer *indirect;
3406         uint64_t indirect_offset;
3407 };
3408
3409 static void
3410 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3411                            const struct radv_dispatch_info *info)
3412 {
3413         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3414         struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3415         unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3416         struct radeon_winsys *ws = cmd_buffer->device->ws;
3417         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3418         struct radv_userdata_info *loc;
3419
3420         loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3421                                     AC_UD_CS_GRID_SIZE);
3422
3423         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3424
3425         if (info->indirect) {
3426                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3427
3428                 va += info->indirect->offset + info->indirect_offset;
3429
3430                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3431
3432                 if (loc->sgpr_idx != -1) {
3433                         for (unsigned i = 0; i < 3; ++i) {
3434                                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3435                                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3436                                                 COPY_DATA_DST_SEL(COPY_DATA_REG));
3437                                 radeon_emit(cs, (va +  4 * i));
3438                                 radeon_emit(cs, (va + 4 * i) >> 32);
3439                                 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3440                                                  + loc->sgpr_idx * 4) >> 2) + i);
3441                                 radeon_emit(cs, 0);
3442                         }
3443                 }
3444
3445                 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3446                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3447                                         PKT3_SHADER_TYPE_S(1));
3448                         radeon_emit(cs, va);
3449                         radeon_emit(cs, va >> 32);
3450                         radeon_emit(cs, dispatch_initiator);
3451                 } else {
3452                         radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3453                                         PKT3_SHADER_TYPE_S(1));
3454                         radeon_emit(cs, 1);
3455                         radeon_emit(cs, va);
3456                         radeon_emit(cs, va >> 32);
3457
3458                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3459                                         PKT3_SHADER_TYPE_S(1));
3460                         radeon_emit(cs, 0);
3461                         radeon_emit(cs, dispatch_initiator);
3462                 }
3463         } else {
3464                 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3465                 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3466
3467                 if (info->unaligned) {
3468                         unsigned *cs_block_size = compute_shader->info.cs.block_size;
3469                         unsigned remainder[3];
3470
3471                         /* If aligned, these should be an entire block size,
3472                          * not 0.
3473                          */
3474                         remainder[0] = blocks[0] + cs_block_size[0] -
3475                                        align_u32_npot(blocks[0], cs_block_size[0]);
3476                         remainder[1] = blocks[1] + cs_block_size[1] -
3477                                        align_u32_npot(blocks[1], cs_block_size[1]);
3478                         remainder[2] = blocks[2] + cs_block_size[2] -
3479                                        align_u32_npot(blocks[2], cs_block_size[2]);
3480
3481                         blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3482                         blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3483                         blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3484
3485                         for(unsigned i = 0; i < 3; ++i) {
3486                                 assert(offsets[i] % cs_block_size[i] == 0);
3487                                 offsets[i] /= cs_block_size[i];
3488                         }
3489
3490                         radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3491                         radeon_emit(cs,
3492                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3493                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3494                         radeon_emit(cs,
3495                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3496                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3497                         radeon_emit(cs,
3498                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3499                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3500
3501                         dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3502                 }
3503
3504                 if (loc->sgpr_idx != -1) {
3505                         assert(!loc->indirect);
3506                         assert(loc->num_sgprs == 3);
3507
3508                         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3509                                                   loc->sgpr_idx * 4, 3);
3510                         radeon_emit(cs, blocks[0]);
3511                         radeon_emit(cs, blocks[1]);
3512                         radeon_emit(cs, blocks[2]);
3513                 }
3514
3515                 if (offsets[0] || offsets[1] || offsets[2]) {
3516                         radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3517                         radeon_emit(cs, offsets[0]);
3518                         radeon_emit(cs, offsets[1]);
3519                         radeon_emit(cs, offsets[2]);
3520
3521                         /* The blocks in the packet are not counts but end values. */
3522                         for (unsigned i = 0; i < 3; ++i)
3523                                 blocks[i] += offsets[i];
3524                 } else {
3525                         dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3526                 }
3527
3528                 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3529                                 PKT3_SHADER_TYPE_S(1));
3530                 radeon_emit(cs, blocks[0]);
3531                 radeon_emit(cs, blocks[1]);
3532                 radeon_emit(cs, blocks[2]);
3533                 radeon_emit(cs, dispatch_initiator);
3534         }
3535
3536         assert(cmd_buffer->cs->cdw <= cdw_max);
3537 }
3538
3539 static void
3540 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3541 {
3542         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3543         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3544 }
3545
3546 static void
3547 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3548               const struct radv_dispatch_info *info)
3549 {
3550         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3551         bool has_prefetch =
3552                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3553         bool pipeline_is_dirty = pipeline &&
3554                                  pipeline != cmd_buffer->state.emitted_compute_pipeline;
3555
3556         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3557                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3558                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3559                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3560                 /* If we have to wait for idle, set all states first, so that
3561                  * all SET packets are processed in parallel with previous draw
3562                  * calls. Then upload descriptors, set shader pointers, and
3563                  * dispatch, and prefetch at the end. This ensures that the
3564                  * time the CUs are idle is very short. (there are only SET_SH
3565                  * packets between the wait and the draw)
3566                  */
3567                 radv_emit_compute_pipeline(cmd_buffer);
3568                 si_emit_cache_flush(cmd_buffer);
3569                 /* <-- CUs are idle here --> */
3570
3571                 radv_upload_compute_shader_descriptors(cmd_buffer);
3572
3573                 radv_emit_dispatch_packets(cmd_buffer, info);
3574                 /* <-- CUs are busy here --> */
3575
3576                 /* Start prefetches after the dispatch has been started. Both
3577                  * will run in parallel, but starting the dispatch first is
3578                  * more important.
3579                  */
3580                 if (has_prefetch && pipeline_is_dirty) {
3581                         radv_emit_shader_prefetch(cmd_buffer,
3582                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3583                 }
3584         } else {
3585                 /* If we don't wait for idle, start prefetches first, then set
3586                  * states, and dispatch at the end.
3587                  */
3588                 si_emit_cache_flush(cmd_buffer);
3589
3590                 if (has_prefetch && pipeline_is_dirty) {
3591                         radv_emit_shader_prefetch(cmd_buffer,
3592                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3593                 }
3594
3595                 radv_upload_compute_shader_descriptors(cmd_buffer);
3596
3597                 radv_emit_compute_pipeline(cmd_buffer);
3598                 radv_emit_dispatch_packets(cmd_buffer, info);
3599         }
3600
3601         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3602 }
3603
3604 void radv_CmdDispatchBase(
3605         VkCommandBuffer                             commandBuffer,
3606         uint32_t                                    base_x,
3607         uint32_t                                    base_y,
3608         uint32_t                                    base_z,
3609         uint32_t                                    x,
3610         uint32_t                                    y,
3611         uint32_t                                    z)
3612 {
3613         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3614         struct radv_dispatch_info info = {};
3615
3616         info.blocks[0] = x;
3617         info.blocks[1] = y;
3618         info.blocks[2] = z;
3619
3620         info.offsets[0] = base_x;
3621         info.offsets[1] = base_y;
3622         info.offsets[2] = base_z;
3623         radv_dispatch(cmd_buffer, &info);
3624 }
3625
3626 void radv_CmdDispatch(
3627         VkCommandBuffer                             commandBuffer,
3628         uint32_t                                    x,
3629         uint32_t                                    y,
3630         uint32_t                                    z)
3631 {
3632         radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3633 }
3634
3635 void radv_CmdDispatchIndirect(
3636         VkCommandBuffer                             commandBuffer,
3637         VkBuffer                                    _buffer,
3638         VkDeviceSize                                offset)
3639 {
3640         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3641         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3642         struct radv_dispatch_info info = {};
3643
3644         info.indirect = buffer;
3645         info.indirect_offset = offset;
3646
3647         radv_dispatch(cmd_buffer, &info);
3648 }
3649
3650 void radv_unaligned_dispatch(
3651         struct radv_cmd_buffer                      *cmd_buffer,
3652         uint32_t                                    x,
3653         uint32_t                                    y,
3654         uint32_t                                    z)
3655 {
3656         struct radv_dispatch_info info = {};
3657
3658         info.blocks[0] = x;
3659         info.blocks[1] = y;
3660         info.blocks[2] = z;
3661         info.unaligned = 1;
3662
3663         radv_dispatch(cmd_buffer, &info);
3664 }
3665
3666 void radv_CmdEndRenderPass(
3667         VkCommandBuffer                             commandBuffer)
3668 {
3669         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3670
3671         radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3672
3673         radv_cmd_buffer_resolve_subpass(cmd_buffer);
3674
3675         for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3676                 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3677                 radv_handle_subpass_image_transition(cmd_buffer,
3678                                       (VkAttachmentReference){i, layout});
3679         }
3680
3681         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3682
3683         cmd_buffer->state.pass = NULL;
3684         cmd_buffer->state.subpass = NULL;
3685         cmd_buffer->state.attachments = NULL;
3686         cmd_buffer->state.framebuffer = NULL;
3687 }
3688
3689 /*
3690  * For HTILE we have the following interesting clear words:
3691  *   0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3692  *   0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3693  *   0xfffffff0: Clear depth to 1.0
3694  *   0x00000000: Clear depth to 0.0
3695  */
3696 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3697                                   struct radv_image *image,
3698                                   const VkImageSubresourceRange *range,
3699                                   uint32_t clear_word)
3700 {
3701         assert(range->baseMipLevel == 0);
3702         assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3703         unsigned layer_count = radv_get_layerCount(image, range);
3704         uint64_t size = image->surface.htile_slice_size * layer_count;
3705         uint64_t offset = image->offset + image->htile_offset +
3706                           image->surface.htile_slice_size * range->baseArrayLayer;
3707         struct radv_cmd_state *state = &cmd_buffer->state;
3708
3709         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3710                              RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3711
3712         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3713                                               size, clear_word);
3714
3715         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3716 }
3717
3718 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3719                                                struct radv_image *image,
3720                                                VkImageLayout src_layout,
3721                                                VkImageLayout dst_layout,
3722                                                unsigned src_queue_mask,
3723                                                unsigned dst_queue_mask,
3724                                                const VkImageSubresourceRange *range,
3725                                                VkImageAspectFlags pending_clears)
3726 {
3727         if (!radv_image_has_htile(image))
3728                 return;
3729
3730         if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3731             (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3732             cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3733             cmd_buffer->state.render_area.extent.width == image->info.width &&
3734             cmd_buffer->state.render_area.extent.height == image->info.height) {
3735                 /* The clear will initialize htile. */
3736                 return;
3737         } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3738                    radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3739                 /* TODO: merge with the clear if applicable */
3740                 radv_initialize_htile(cmd_buffer, image, range, 0);
3741         } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3742                    radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3743                 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3744                 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3745         } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3746                    !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3747                 VkImageSubresourceRange local_range = *range;
3748                 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3749                 local_range.baseMipLevel = 0;
3750                 local_range.levelCount = 1;
3751
3752                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3753                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3754
3755                 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3756
3757                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3758                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3759         }
3760 }
3761
3762 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3763                                   struct radv_image *image, uint32_t value)
3764 {
3765         struct radv_cmd_state *state = &cmd_buffer->state;
3766
3767         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3768                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3769
3770         state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
3771
3772         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3773 }
3774
3775 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3776                          struct radv_image *image, uint32_t value)
3777 {
3778         struct radv_cmd_state *state = &cmd_buffer->state;
3779
3780         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3781                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3782
3783         state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
3784
3785         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3786                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3787 }
3788
3789 /**
3790  * Initialize DCC/FMASK/CMASK metadata for a color image.
3791  */
3792 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
3793                                            struct radv_image *image,
3794                                            VkImageLayout src_layout,
3795                                            VkImageLayout dst_layout,
3796                                            unsigned src_queue_mask,
3797                                            unsigned dst_queue_mask)
3798 {
3799         if (radv_image_has_cmask(image)) {
3800                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
3801
3802                 /*  TODO: clarify this. */
3803                 if (radv_image_has_fmask(image)) {
3804                         value = 0xccccccccu;
3805                 }
3806
3807                 radv_initialise_cmask(cmd_buffer, image, value);
3808         }
3809
3810         if (radv_image_has_dcc(image)) {
3811                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
3812
3813                 if (radv_layout_dcc_compressed(image, dst_layout,
3814                                                dst_queue_mask)) {
3815                         value = 0x20202020u;
3816                 }
3817
3818                 radv_initialize_dcc(cmd_buffer, image, value);
3819         }
3820 }
3821
3822 /**
3823  * Handle color image transitions for DCC/FMASK/CMASK.
3824  */
3825 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
3826                                                struct radv_image *image,
3827                                                VkImageLayout src_layout,
3828                                                VkImageLayout dst_layout,
3829                                                unsigned src_queue_mask,
3830                                                unsigned dst_queue_mask,
3831                                                const VkImageSubresourceRange *range)
3832 {
3833         if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3834                 radv_init_color_image_metadata(cmd_buffer, image,
3835                                                src_layout, dst_layout,
3836                                                src_queue_mask, dst_queue_mask);
3837                 return;
3838         }
3839
3840         if (radv_image_has_dcc(image)) {
3841                 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
3842                         radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
3843                 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
3844                            !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
3845                         radv_decompress_dcc(cmd_buffer, image, range);
3846                 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3847                            !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3848                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3849                 }
3850         } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
3851                 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3852                     !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3853                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3854                 }
3855         }
3856 }
3857
3858 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3859                                          struct radv_image *image,
3860                                          VkImageLayout src_layout,
3861                                          VkImageLayout dst_layout,
3862                                          uint32_t src_family,
3863                                          uint32_t dst_family,
3864                                          const VkImageSubresourceRange *range,
3865                                          VkImageAspectFlags pending_clears)
3866 {
3867         if (image->exclusive && src_family != dst_family) {
3868                 /* This is an acquire or a release operation and there will be
3869                  * a corresponding release/acquire. Do the transition in the
3870                  * most flexible queue. */
3871
3872                 assert(src_family == cmd_buffer->queue_family_index ||
3873                        dst_family == cmd_buffer->queue_family_index);
3874
3875                 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3876                         return;
3877
3878                 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3879                     (src_family == RADV_QUEUE_GENERAL ||
3880                      dst_family == RADV_QUEUE_GENERAL))
3881                         return;
3882         }
3883
3884         unsigned src_queue_mask =
3885                 radv_image_queue_family_mask(image, src_family,
3886                                              cmd_buffer->queue_family_index);
3887         unsigned dst_queue_mask =
3888                 radv_image_queue_family_mask(image, dst_family,
3889                                              cmd_buffer->queue_family_index);
3890
3891         if (vk_format_is_depth(image->vk_format)) {
3892                 radv_handle_depth_image_transition(cmd_buffer, image,
3893                                                    src_layout, dst_layout,
3894                                                    src_queue_mask, dst_queue_mask,
3895                                                    range, pending_clears);
3896         } else {
3897                 radv_handle_color_image_transition(cmd_buffer, image,
3898                                                    src_layout, dst_layout,
3899                                                    src_queue_mask, dst_queue_mask,
3900                                                    range);
3901         }
3902 }
3903
3904 void radv_CmdPipelineBarrier(
3905         VkCommandBuffer                             commandBuffer,
3906         VkPipelineStageFlags                        srcStageMask,
3907         VkPipelineStageFlags                        destStageMask,
3908         VkBool32                                    byRegion,
3909         uint32_t                                    memoryBarrierCount,
3910         const VkMemoryBarrier*                      pMemoryBarriers,
3911         uint32_t                                    bufferMemoryBarrierCount,
3912         const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
3913         uint32_t                                    imageMemoryBarrierCount,
3914         const VkImageMemoryBarrier*                 pImageMemoryBarriers)
3915 {
3916         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3917         enum radv_cmd_flush_bits src_flush_bits = 0;
3918         enum radv_cmd_flush_bits dst_flush_bits = 0;
3919
3920         for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3921                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3922                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3923                                                         NULL);
3924         }
3925
3926         for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3927                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3928                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3929                                                         NULL);
3930         }
3931
3932         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3933                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3934                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3935                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3936                                                         image);
3937         }
3938
3939         radv_stage_flush(cmd_buffer, srcStageMask);
3940         cmd_buffer->state.flush_bits |= src_flush_bits;
3941
3942         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3943                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3944                 radv_handle_image_transition(cmd_buffer, image,
3945                                              pImageMemoryBarriers[i].oldLayout,
3946                                              pImageMemoryBarriers[i].newLayout,
3947                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
3948                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
3949                                              &pImageMemoryBarriers[i].subresourceRange,
3950                                              0);
3951         }
3952
3953         cmd_buffer->state.flush_bits |= dst_flush_bits;
3954 }
3955
3956
3957 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3958                         struct radv_event *event,
3959                         VkPipelineStageFlags stageMask,
3960                         unsigned value)
3961 {
3962         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3963         uint64_t va = radv_buffer_get_va(event->bo);
3964
3965         radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3966
3967         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3968
3969         /* TODO: this is overkill. Probably should figure something out from
3970          * the stage mask. */
3971
3972         si_cs_emit_write_event_eop(cs,
3973                                    cmd_buffer->state.predicating,
3974                                    cmd_buffer->device->physical_device->rad_info.chip_class,
3975                                    radv_cmd_buffer_uses_mec(cmd_buffer),
3976                                    V_028A90_BOTTOM_OF_PIPE_TS, 0,
3977                                    1, va, 2, value);
3978
3979         assert(cmd_buffer->cs->cdw <= cdw_max);
3980 }
3981
3982 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3983                       VkEvent _event,
3984                       VkPipelineStageFlags stageMask)
3985 {
3986         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3987         RADV_FROM_HANDLE(radv_event, event, _event);
3988
3989         write_event(cmd_buffer, event, stageMask, 1);
3990 }
3991
3992 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3993                         VkEvent _event,
3994                         VkPipelineStageFlags stageMask)
3995 {
3996         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3997         RADV_FROM_HANDLE(radv_event, event, _event);
3998
3999         write_event(cmd_buffer, event, stageMask, 0);
4000 }
4001
4002 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4003                         uint32_t eventCount,
4004                         const VkEvent* pEvents,
4005                         VkPipelineStageFlags srcStageMask,
4006                         VkPipelineStageFlags dstStageMask,
4007                         uint32_t memoryBarrierCount,
4008                         const VkMemoryBarrier* pMemoryBarriers,
4009                         uint32_t bufferMemoryBarrierCount,
4010                         const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4011                         uint32_t imageMemoryBarrierCount,
4012                         const VkImageMemoryBarrier* pImageMemoryBarriers)
4013 {
4014         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4015         struct radeon_winsys_cs *cs = cmd_buffer->cs;
4016
4017         for (unsigned i = 0; i < eventCount; ++i) {
4018                 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4019                 uint64_t va = radv_buffer_get_va(event->bo);
4020
4021                 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4022
4023                 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4024
4025                 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4026                 assert(cmd_buffer->cs->cdw <= cdw_max);
4027         }
4028
4029
4030         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4031                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4032
4033                 radv_handle_image_transition(cmd_buffer, image,
4034                                              pImageMemoryBarriers[i].oldLayout,
4035                                              pImageMemoryBarriers[i].newLayout,
4036                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
4037                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
4038                                              &pImageMemoryBarriers[i].subresourceRange,
4039                                              0);
4040         }
4041
4042         /* TODO: figure out how to do memory barriers without waiting */
4043         cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4044                                         RADV_CMD_FLAG_INV_GLOBAL_L2 |
4045                                         RADV_CMD_FLAG_INV_VMEM_L1 |
4046                                         RADV_CMD_FLAG_INV_SMEM_L1;
4047 }
4048
4049
4050 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4051                            uint32_t deviceMask)
4052 {
4053    /* No-op */
4054 }