src/amd/vulkan/radv_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "radv_private.h"
  29 #include "radv_radeon_winsys.h"
  30 #include "radv_shader.h"
  31 #include "radv_cs.h"
  32 #include "sid.h"
  33 #include "gfx9d.h"
  34 #include "vk_format.h"
  35 #include "radv_debug.h"
  36 #include "radv_meta.h"
  37
  38 #include "ac_debug.h"
  39
  40 enum {
  41         RADV_PREFETCH_VBO_DESCRIPTORS   = (1 << 0),
  42         RADV_PREFETCH_VS                = (1 << 1),
  43         RADV_PREFETCH_TCS               = (1 << 2),
  44         RADV_PREFETCH_TES               = (1 << 3),
  45         RADV_PREFETCH_GS                = (1 << 4),
  46         RADV_PREFETCH_PS                = (1 << 5),
  47         RADV_PREFETCH_SHADERS           = (RADV_PREFETCH_VS  |
  48                                            RADV_PREFETCH_TCS |
  49                                            RADV_PREFETCH_TES |
  50                                            RADV_PREFETCH_GS  |
  51                                            RADV_PREFETCH_PS)
  52 };
  53
  54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
  55                                          struct radv_image *image,
  56                                          VkImageLayout src_layout,
  57                                          VkImageLayout dst_layout,
  58                                          uint32_t src_family,
  59                                          uint32_t dst_family,
  60                                          const VkImageSubresourceRange *range,
  61                                          VkImageAspectFlags pending_clears);
  62
  63 const struct radv_dynamic_state default_dynamic_state = {
  64         .viewport = {
  65                 .count = 0,
  66         },
  67         .scissor = {
  68                 .count = 0,
  69         },
  70         .line_width = 1.0f,
  71         .depth_bias = {
  72                 .bias = 0.0f,
  73                 .clamp = 0.0f,
  74                 .slope = 0.0f,
  75         },
  76         .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
  77         .depth_bounds = {
  78                 .min = 0.0f,
  79                 .max = 1.0f,
  80         },
  81         .stencil_compare_mask = {
  82                 .front = ~0u,
  83                 .back = ~0u,
  84         },
  85         .stencil_write_mask = {
  86                 .front = ~0u,
  87                 .back = ~0u,
  88         },
  89         .stencil_reference = {
  90                 .front = 0u,
  91                 .back = 0u,
  92         },
  93 };
  94
  95 static void
  96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
  97                         const struct radv_dynamic_state *src)
  98 {
  99         struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
 100         uint32_t copy_mask = src->mask;
 101         uint32_t dest_mask = 0;
 102
 103         /* Make sure to copy the number of viewports/scissors because they can
 104          * only be specified at pipeline creation time.
 105          */
 106         dest->viewport.count = src->viewport.count;
 107         dest->scissor.count = src->scissor.count;
 108         dest->discard_rectangle.count = src->discard_rectangle.count;
 109
 110         if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
 111                 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
 112                            src->viewport.count * sizeof(VkViewport))) {
 113                         typed_memcpy(dest->viewport.viewports,
 114                                      src->viewport.viewports,
 115                                      src->viewport.count);
 116                         dest_mask |= RADV_DYNAMIC_VIEWPORT;
 117                 }
 118         }
 119
 120         if (copy_mask & RADV_DYNAMIC_SCISSOR) {
 121                 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
 122                            src->scissor.count * sizeof(VkRect2D))) {
 123                         typed_memcpy(dest->scissor.scissors,
 124                                      src->scissor.scissors, src->scissor.count);
 125                         dest_mask |= RADV_DYNAMIC_SCISSOR;
 126                 }
 127         }
 128
 129         if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
 130                 if (dest->line_width != src->line_width) {
 131                         dest->line_width = src->line_width;
 132                         dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
 133                 }
 134         }
 135
 136         if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
 137                 if (memcmp(&dest->depth_bias, &src->depth_bias,
 138                            sizeof(src->depth_bias))) {
 139                         dest->depth_bias = src->depth_bias;
 140                         dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
 141                 }
 142         }
 143
 144         if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
 145                 if (memcmp(&dest->blend_constants, &src->blend_constants,
 146                            sizeof(src->blend_constants))) {
 147                         typed_memcpy(dest->blend_constants,
 148                                      src->blend_constants, 4);
 149                         dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
 150                 }
 151         }
 152
 153         if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
 154                 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
 155                            sizeof(src->depth_bounds))) {
 156                         dest->depth_bounds = src->depth_bounds;
 157                         dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
 158                 }
 159         }
 160
 161         if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
 162                 if (memcmp(&dest->stencil_compare_mask,
 163                            &src->stencil_compare_mask,
 164                            sizeof(src->stencil_compare_mask))) {
 165                         dest->stencil_compare_mask = src->stencil_compare_mask;
 166                         dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
 167                 }
 168         }
 169
 170         if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
 171                 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
 172                            sizeof(src->stencil_write_mask))) {
 173                         dest->stencil_write_mask = src->stencil_write_mask;
 174                         dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
 175                 }
 176         }
 177
 178         if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
 179                 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
 180                            sizeof(src->stencil_reference))) {
 181                         dest->stencil_reference = src->stencil_reference;
 182                         dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
 183                 }
 184         }
 185
 186         if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
 187                 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
 188                            src->discard_rectangle.count * sizeof(VkRect2D))) {
 189                         typed_memcpy(dest->discard_rectangle.rectangles,
 190                                      src->discard_rectangle.rectangles,
 191                                      src->discard_rectangle.count);
 192                         dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
 193                 }
 194         }
 195
 196         cmd_buffer->state.dirty |= dest_mask;
 197 }
 198
 199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
 200 {
 201         return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
 202                cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
 203 }
 204
 205 enum ring_type radv_queue_family_to_ring(int f) {
 206         switch (f) {
 207         case RADV_QUEUE_GENERAL:
 208                 return RING_GFX;
 209         case RADV_QUEUE_COMPUTE:
 210                 return RING_COMPUTE;
 211         case RADV_QUEUE_TRANSFER:
 212                 return RING_DMA;
 213         default:
 214                 unreachable("Unknown queue family");
 215         }
 216 }
 217
 218 static VkResult radv_create_cmd_buffer(
 219         struct radv_device *                         device,
 220         struct radv_cmd_pool *                       pool,
 221         VkCommandBufferLevel                        level,
 222         VkCommandBuffer*                            pCommandBuffer)
 223 {
 224         struct radv_cmd_buffer *cmd_buffer;
 225         unsigned ring;
 226         cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
 227                                VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 228         if (cmd_buffer == NULL)
 229                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 230
 231         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
 232         cmd_buffer->device = device;
 233         cmd_buffer->pool = pool;
 234         cmd_buffer->level = level;
 235
 236         if (pool) {
 237                 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
 238                 cmd_buffer->queue_family_index = pool->queue_family_index;
 239
 240         } else {
 241                 /* Init the pool_link so we can safely call list_del when we destroy
 242                  * the command buffer
 243                  */
 244                 list_inithead(&cmd_buffer->pool_link);
 245                 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
 246         }
 247
 248         ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
 249
 250         cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
 251         if (!cmd_buffer->cs) {
 252                 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 253                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 254         }
 255
 256         *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
 257
 258         list_inithead(&cmd_buffer->upload.list);
 259
 260         return VK_SUCCESS;
 261 }
 262
 263 static void
 264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
 265 {
 266         list_del(&cmd_buffer->pool_link);
 267
 268         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 269                                  &cmd_buffer->upload.list, list) {
 270                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 271                 list_del(&up->list);
 272                 free(up);
 273         }
 274
 275         if (cmd_buffer->upload.upload_bo)
 276                 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
 277         cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
 278
 279         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
 280                 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
 281
 282         vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 283 }
 284
 285 static VkResult
 286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 287 {
 288
 289         cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
 290
 291         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 292                                  &cmd_buffer->upload.list, list) {
 293                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 294                 list_del(&up->list);
 295                 free(up);
 296         }
 297
 298         cmd_buffer->push_constant_stages = 0;
 299         cmd_buffer->scratch_size_needed = 0;
 300         cmd_buffer->compute_scratch_size_needed = 0;
 301         cmd_buffer->esgs_ring_size_needed = 0;
 302         cmd_buffer->gsvs_ring_size_needed = 0;
 303         cmd_buffer->tess_rings_needed = false;
 304         cmd_buffer->sample_positions_needed = false;
 305
 306         if (cmd_buffer->upload.upload_bo)
 307                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 308                                    cmd_buffer->upload.upload_bo, 8);
 309         cmd_buffer->upload.offset = 0;
 310
 311         cmd_buffer->record_result = VK_SUCCESS;
 312
 313         cmd_buffer->ring_offsets_idx = -1;
 314
 315         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
 316                 cmd_buffer->descriptors[i].dirty = 0;
 317                 cmd_buffer->descriptors[i].valid = 0;
 318                 cmd_buffer->descriptors[i].push_dirty = false;
 319         }
 320
 321         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 322                 void *fence_ptr;
 323                 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
 324                                              &cmd_buffer->gfx9_fence_offset,
 325                                              &fence_ptr);
 326                 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
 327         }
 328
 329         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
 330
 331         return cmd_buffer->record_result;
 332 }
 333
 334 static bool
 335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
 336                                   uint64_t min_needed)
 337 {
 338         uint64_t new_size;
 339         struct radeon_winsys_bo *bo;
 340         struct radv_cmd_buffer_upload *upload;
 341         struct radv_device *device = cmd_buffer->device;
 342
 343         new_size = MAX2(min_needed, 16 * 1024);
 344         new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
 345
 346         bo = device->ws->buffer_create(device->ws,
 347                                        new_size, 4096,
 348                                        RADEON_DOMAIN_GTT,
 349                                        RADEON_FLAG_CPU_ACCESS|
 350                                        RADEON_FLAG_NO_INTERPROCESS_SHARING |
 351                                        RADEON_FLAG_32BIT);
 352
 353         if (!bo) {
 354                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 355                 return false;
 356         }
 357
 358         radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
 359         if (cmd_buffer->upload.upload_bo) {
 360                 upload = malloc(sizeof(*upload));
 361
 362                 if (!upload) {
 363                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
 364                         device->ws->buffer_destroy(bo);
 365                         return false;
 366                 }
 367
 368                 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
 369                 list_add(&upload->list, &cmd_buffer->upload.list);
 370         }
 371
 372         cmd_buffer->upload.upload_bo = bo;
 373         cmd_buffer->upload.size = new_size;
 374         cmd_buffer->upload.offset = 0;
 375         cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
 376
 377         if (!cmd_buffer->upload.map) {
 378                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 379                 return false;
 380         }
 381
 382         return true;
 383 }
 384
 385 bool
 386 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
 387                              unsigned size,
 388                              unsigned alignment,
 389                              unsigned *out_offset,
 390                              void **ptr)
 391 {
 392         uint64_t offset = align(cmd_buffer->upload.offset, alignment);
 393         if (offset + size > cmd_buffer->upload.size) {
 394                 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
 395                         return false;
 396                 offset = 0;
 397         }
 398
 399         *out_offset = offset;
 400         *ptr = cmd_buffer->upload.map + offset;
 401
 402         cmd_buffer->upload.offset = offset + size;
 403         return true;
 404 }
 405
 406 bool
 407 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
 408                             unsigned size, unsigned alignment,
 409                             const void *data, unsigned *out_offset)
 410 {
 411         uint8_t *ptr;
 412
 413         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
 414                                           out_offset, (void **)&ptr))
 415                 return false;
 416
 417         if (ptr)
 418                 memcpy(ptr, data, size);
 419
 420         return true;
 421 }
 422
 423 static void
 424 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
 425                             unsigned count, const uint32_t *data)
 426 {
 427         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
 428         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
 429                     S_370_WR_CONFIRM(1) |
 430                     S_370_ENGINE_SEL(V_370_ME));
 431         radeon_emit(cs, va);
 432         radeon_emit(cs, va >> 32);
 433         radeon_emit_array(cs, data, count);
 434 }
 435
 436 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
 437 {
 438         struct radv_device *device = cmd_buffer->device;
 439         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 440         uint64_t va;
 441
 442         va = radv_buffer_get_va(device->trace_bo);
 443         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
 444                 va += 4;
 445
 446         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
 447
 448         ++cmd_buffer->state.trace_id;
 449         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 450         radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
 451         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
 452         radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
 453 }
 454
 455 static void
 456 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
 457                            enum radv_cmd_flush_bits flags)
 458 {
 459         if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
 460                 uint32_t *ptr = NULL;
 461                 uint64_t va = 0;
 462
 463                 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
 464                                 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
 465
 466                 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
 467                         va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
 468                              cmd_buffer->gfx9_fence_offset;
 469                         ptr = &cmd_buffer->gfx9_fence_idx;
 470                 }
 471
 472                 /* Force wait for graphics or compute engines to be idle. */
 473                 si_cs_emit_cache_flush(cmd_buffer->cs,
 474                                        cmd_buffer->device->physical_device->rad_info.chip_class,
 475                                        ptr, va,
 476                                        radv_cmd_buffer_uses_mec(cmd_buffer),
 477                                        flags);
 478         }
 479
 480         if (unlikely(cmd_buffer->device->trace_bo))
 481                 radv_cmd_buffer_trace_emit(cmd_buffer);
 482 }
 483
 484 static void
 485 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
 486                    struct radv_pipeline *pipeline, enum ring_type ring)
 487 {
 488         struct radv_device *device = cmd_buffer->device;
 489         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 490         uint32_t data[2];
 491         uint64_t va;
 492
 493         va = radv_buffer_get_va(device->trace_bo);
 494
 495         switch (ring) {
 496         case RING_GFX:
 497                 va += 8;
 498                 break;
 499         case RING_COMPUTE:
 500                 va += 16;
 501                 break;
 502         default:
 503                 assert(!"invalid ring type");
 504         }
 505
 506         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 507                                                            cmd_buffer->cs, 6);
 508
 509         data[0] = (uintptr_t)pipeline;
 510         data[1] = (uintptr_t)pipeline >> 32;
 511
 512         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 513         radv_emit_write_data_packet(cs, va, 2, data);
 514 }
 515
 516 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 517                              VkPipelineBindPoint bind_point,
 518                              struct radv_descriptor_set *set,
 519                              unsigned idx)
 520 {
 521         struct radv_descriptor_state *descriptors_state =
 522                 radv_get_descriptors_state(cmd_buffer, bind_point);
 523
 524         descriptors_state->sets[idx] = set;
 525         if (set)
 526                 descriptors_state->valid |= (1u << idx);
 527         else
 528                 descriptors_state->valid &= ~(1u << idx);
 529         descriptors_state->dirty |= (1u << idx);
 530 }
 531
 532 static void
 533 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
 534                       VkPipelineBindPoint bind_point)
 535 {
 536         struct radv_descriptor_state *descriptors_state =
 537                 radv_get_descriptors_state(cmd_buffer, bind_point);
 538         struct radv_device *device = cmd_buffer->device;
 539         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 540         uint32_t data[MAX_SETS * 2] = {};
 541         uint64_t va;
 542         unsigned i;
 543         va = radv_buffer_get_va(device->trace_bo) + 24;
 544
 545         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 546                                                            cmd_buffer->cs, 4 + MAX_SETS * 2);
 547
 548         for_each_bit(i, descriptors_state->valid) {
 549                 struct radv_descriptor_set *set = descriptors_state->sets[i];
 550                 data[i * 2] = (uintptr_t)set;
 551                 data[i * 2 + 1] = (uintptr_t)set >> 32;
 552         }
 553
 554         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 555         radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
 556 }
 557
 558 struct radv_userdata_info *
 559 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
 560                       gl_shader_stage stage,
 561                       int idx)
 562 {
 563         struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
 564         return &shader->info.user_sgprs_locs.shader_data[idx];
 565 }
 566
 567 static void
 568 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
 569                            struct radv_pipeline *pipeline,
 570                            gl_shader_stage stage,
 571                            int idx, uint64_t va)
 572 {
 573         struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
 574         uint32_t base_reg = pipeline->user_data_0[stage];
 575         if (loc->sgpr_idx == -1)
 576                 return;
 577
 578         assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
 579         assert(!loc->indirect);
 580
 581         radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
 582                                  base_reg + loc->sgpr_idx * 4, va, false);
 583 }
 584
 585 static void
 586 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
 587                               struct radv_pipeline *pipeline,
 588                               struct radv_descriptor_state *descriptors_state,
 589                               gl_shader_stage stage)
 590 {
 591         struct radv_device *device = cmd_buffer->device;
 592         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 593         uint32_t sh_base = pipeline->user_data_0[stage];
 594         struct radv_userdata_locations *locs =
 595                 &pipeline->shaders[stage]->info.user_sgprs_locs;
 596         unsigned mask;
 597
 598         mask = descriptors_state->dirty & descriptors_state->valid;
 599
 600         for (int i = 0; i < MAX_SETS; i++) {
 601                 struct radv_userdata_info *loc = &locs->descriptor_sets[i];
 602                 if (loc->sgpr_idx != -1 && !loc->indirect)
 603                         continue;
 604                 mask &= ~(1 << i);
 605         }
 606
 607         while (mask) {
 608                 int start, count;
 609
 610                 u_bit_scan_consecutive_range(&mask, &start, &count);
 611
 612                 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
 613                 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
 614
 615                 radv_emit_shader_pointer_head(cs, sh_offset, count,
 616                                               HAVE_32BIT_POINTERS);
 617                 for (int i = 0; i < count; i++) {
 618                         struct radv_descriptor_set *set =
 619                                 descriptors_state->sets[start + i];
 620
 621                         radv_emit_shader_pointer_body(device, cs, set->va,
 622                                                       HAVE_32BIT_POINTERS);
 623                 }
 624         }
 625 }
 626
 627 static void
 628 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
 629                               struct radv_pipeline *pipeline)
 630 {
 631         int num_samples = pipeline->graphics.ms.num_samples;
 632         struct radv_multisample_state *ms = &pipeline->graphics.ms;
 633         struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
 634
 635         if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
 636                 cmd_buffer->sample_positions_needed = true;
 637
 638         if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
 639                 return;
 640
 641         radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
 642         radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
 643         radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
 644
 645         radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
 646
 647         radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
 648
 649         /* GFX9: Flush DFSM when the AA mode changes. */
 650         if (cmd_buffer->device->dfsm_allowed) {
 651                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 652                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
 653         }
 654 }
 655
 656 static void
 657 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
 658                           struct radv_shader_variant *shader)
 659 {
 660         uint64_t va;
 661
 662         if (!shader)
 663                 return;
 664
 665         va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 666
 667         si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
 668 }
 669
 670 static void
 671 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
 672                       struct radv_pipeline *pipeline,
 673                       bool vertex_stage_only)
 674 {
 675         struct radv_cmd_state *state = &cmd_buffer->state;
 676         uint32_t mask = state->prefetch_L2_mask;
 677
 678         if (vertex_stage_only) {
 679                 /* Fast prefetch path for starting draws as soon as possible.
 680                  */
 681                 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
 682                                                   RADV_PREFETCH_VBO_DESCRIPTORS);
 683         }
 684
 685         if (mask & RADV_PREFETCH_VS)
 686                 radv_emit_shader_prefetch(cmd_buffer,
 687                                           pipeline->shaders[MESA_SHADER_VERTEX]);
 688
 689         if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
 690                 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
 691
 692         if (mask & RADV_PREFETCH_TCS)
 693                 radv_emit_shader_prefetch(cmd_buffer,
 694                                           pipeline->shaders[MESA_SHADER_TESS_CTRL]);
 695
 696         if (mask & RADV_PREFETCH_TES)
 697                 radv_emit_shader_prefetch(cmd_buffer,
 698                                           pipeline->shaders[MESA_SHADER_TESS_EVAL]);
 699
 700         if (mask & RADV_PREFETCH_GS) {
 701                 radv_emit_shader_prefetch(cmd_buffer,
 702                                           pipeline->shaders[MESA_SHADER_GEOMETRY]);
 703                 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
 704         }
 705
 706         if (mask & RADV_PREFETCH_PS)
 707                 radv_emit_shader_prefetch(cmd_buffer,
 708                                           pipeline->shaders[MESA_SHADER_FRAGMENT]);
 709
 710         state->prefetch_L2_mask &= ~mask;
 711 }
 712
 713 static void
 714 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
 715 {
 716         if (!cmd_buffer->device->physical_device->rbplus_allowed)
 717                 return;
 718
 719         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 720         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
 721         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 722
 723         unsigned sx_ps_downconvert = 0;
 724         unsigned sx_blend_opt_epsilon = 0;
 725         unsigned sx_blend_opt_control = 0;
 726
 727         for (unsigned i = 0; i < subpass->color_count; ++i) {
 728                 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
 729                         continue;
 730
 731                 int idx = subpass->color_attachments[i].attachment;
 732                 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
 733
 734                 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
 735                 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
 736                 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
 737                 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
 738
 739                 bool has_alpha, has_rgb;
 740
 741                 /* Set if RGB and A are present. */
 742                 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
 743
 744                 if (format == V_028C70_COLOR_8 ||
 745                     format == V_028C70_COLOR_16 ||
 746                     format == V_028C70_COLOR_32)
 747                         has_rgb = !has_alpha;
 748                 else
 749                         has_rgb = true;
 750
 751                 /* Check the colormask and export format. */
 752                 if (!(colormask & 0x7))
 753                         has_rgb = false;
 754                 if (!(colormask & 0x8))
 755                         has_alpha = false;
 756
 757                 if (spi_format == V_028714_SPI_SHADER_ZERO) {
 758                         has_rgb = false;
 759                         has_alpha = false;
 760                 }
 761
 762                 /* Disable value checking for disabled channels. */
 763                 if (!has_rgb)
 764                         sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 765                 if (!has_alpha)
 766                         sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 767
 768                 /* Enable down-conversion for 32bpp and smaller formats. */
 769                 switch (format) {
 770                 case V_028C70_COLOR_8:
 771                 case V_028C70_COLOR_8_8:
 772                 case V_028C70_COLOR_8_8_8_8:
 773                         /* For 1 and 2-channel formats, use the superset thereof. */
 774                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
 775                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 776                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 777                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
 778                                 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
 779                         }
 780                         break;
 781
 782                 case V_028C70_COLOR_5_6_5:
 783                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 784                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
 785                                 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
 786                         }
 787                         break;
 788
 789                 case V_028C70_COLOR_1_5_5_5:
 790                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 791                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
 792                                 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
 793                         }
 794                         break;
 795
 796                 case V_028C70_COLOR_4_4_4_4:
 797                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 798                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
 799                                 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
 800                         }
 801                         break;
 802
 803                 case V_028C70_COLOR_32:
 804                         if (swap == V_028C70_SWAP_STD &&
 805                             spi_format == V_028714_SPI_SHADER_32_R)
 806                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
 807                         else if (swap == V_028C70_SWAP_ALT_REV &&
 808                                  spi_format == V_028714_SPI_SHADER_32_AR)
 809                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
 810                         break;
 811
 812                 case V_028C70_COLOR_16:
 813                 case V_028C70_COLOR_16_16:
 814                         /* For 1-channel formats, use the superset thereof. */
 815                         if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
 816                             spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
 817                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 818                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 819                                 if (swap == V_028C70_SWAP_STD ||
 820                                     swap == V_028C70_SWAP_STD_REV)
 821                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
 822                                 else
 823                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
 824                         }
 825                         break;
 826
 827                 case V_028C70_COLOR_10_11_11:
 828                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 829                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
 830                                 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
 831                         }
 832                         break;
 833
 834                 case V_028C70_COLOR_2_10_10_10:
 835                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 836                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
 837                                 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
 838                         }
 839                         break;
 840                 }
 841         }
 842
 843         radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
 844         radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
 845         radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
 846         radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
 847 }
 848
 849 static void
 850 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
 851 {
 852         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 853
 854         if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
 855                 return;
 856
 857         radv_update_multisample_state(cmd_buffer, pipeline);
 858
 859         cmd_buffer->scratch_size_needed =
 860                                   MAX2(cmd_buffer->scratch_size_needed,
 861                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
 862
 863         if (!cmd_buffer->state.emitted_pipeline ||
 864             cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
 865              pipeline->graphics.can_use_guardband)
 866                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
 867
 868         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
 869
 870         for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
 871                 if (!pipeline->shaders[i])
 872                         continue;
 873
 874                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 875                                    pipeline->shaders[i]->bo, 8);
 876         }
 877
 878         if (radv_pipeline_has_gs(pipeline))
 879                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 880                                    pipeline->gs_copy_shader->bo, 8);
 881
 882         if (unlikely(cmd_buffer->device->trace_bo))
 883                 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
 884
 885         cmd_buffer->state.emitted_pipeline = pipeline;
 886
 887         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
 888 }
 889
 890 static void
 891 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
 892 {
 893         si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
 894                           cmd_buffer->state.dynamic.viewport.viewports);
 895 }
 896
 897 static void
 898 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
 899 {
 900         uint32_t count = cmd_buffer->state.dynamic.scissor.count;
 901
 902         si_write_scissors(cmd_buffer->cs, 0, count,
 903                           cmd_buffer->state.dynamic.scissor.scissors,
 904                           cmd_buffer->state.dynamic.viewport.viewports,
 905                           cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
 906 }
 907
 908 static void
 909 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
 910 {
 911         if (!cmd_buffer->state.dynamic.discard_rectangle.count)
 912                 return;
 913
 914         radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
 915                                    cmd_buffer->state.dynamic.discard_rectangle.count * 2);
 916         for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
 917                 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
 918                 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
 919                 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
 920                                             S_028214_BR_Y(rect.offset.y + rect.extent.height));
 921         }
 922 }
 923
 924 static void
 925 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
 926 {
 927         unsigned width = cmd_buffer->state.dynamic.line_width * 8;
 928
 929         radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
 930                                S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
 931 }
 932
 933 static void
 934 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
 935 {
 936         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 937
 938         radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
 939         radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
 940 }
 941
 942 static void
 943 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
 944 {
 945         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 946
 947         radeon_set_context_reg_seq(cmd_buffer->cs,
 948                                    R_028430_DB_STENCILREFMASK, 2);
 949         radeon_emit(cmd_buffer->cs,
 950                     S_028430_STENCILTESTVAL(d->stencil_reference.front) |
 951                     S_028430_STENCILMASK(d->stencil_compare_mask.front) |
 952                     S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
 953                     S_028430_STENCILOPVAL(1));
 954         radeon_emit(cmd_buffer->cs,
 955                     S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
 956                     S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
 957                     S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
 958                     S_028434_STENCILOPVAL_BF(1));
 959 }
 960
 961 static void
 962 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
 963 {
 964         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 965
 966         radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
 967                                fui(d->depth_bounds.min));
 968         radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
 969                                fui(d->depth_bounds.max));
 970 }
 971
 972 static void
 973 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
 974 {
 975         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 976         unsigned slope = fui(d->depth_bias.slope * 16.0f);
 977         unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
 978
 979
 980         radeon_set_context_reg_seq(cmd_buffer->cs,
 981                                    R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
 982         radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
 983         radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
 984         radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
 985         radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
 986         radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
 987 }
 988
 989 static void
 990 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
 991                          int index,
 992                          struct radv_attachment_info *att,
 993                          struct radv_image *image,
 994                          VkImageLayout layout)
 995 {
 996         bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
 997         struct radv_color_buffer_info *cb = &att->cb;
 998         uint32_t cb_color_info = cb->cb_color_info;
 999
1000         if (!radv_layout_dcc_compressed(image, layout,
1001                                         radv_image_queue_family_mask(image,
1002                                                                      cmd_buffer->queue_family_index,
1003                                                                      cmd_buffer->queue_family_index))) {
1004                 cb_color_info &= C_028C70_DCC_ENABLE;
1005         }
1006
1007         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1008                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1009                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1010                 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1011                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1012                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1013                 radeon_emit(cmd_buffer->cs, cb_color_info);
1014                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1015                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1016                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1017                 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1018                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1019                 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1020
1021                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1022                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1023                 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1024
1025                 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1026                                        S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1027         } else {
1028                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1029                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1030                 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1031                 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1032                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1033                 radeon_emit(cmd_buffer->cs, cb_color_info);
1034                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1035                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1036                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1037                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1038                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1039                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1040
1041                 if (is_vi) { /* DCC BASE */
1042                         radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1043                 }
1044         }
1045 }
1046
1047 static void
1048 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1049                              struct radv_ds_buffer_info *ds,
1050                              struct radv_image *image, VkImageLayout layout,
1051                              bool requires_cond_write)
1052 {
1053         uint32_t db_z_info = ds->db_z_info;
1054         uint32_t db_z_info_reg;
1055
1056         if (!radv_image_is_tc_compat_htile(image))
1057                 return;
1058
1059         if (!radv_layout_has_htile(image, layout,
1060                                    radv_image_queue_family_mask(image,
1061                                                                 cmd_buffer->queue_family_index,
1062                                                                 cmd_buffer->queue_family_index))) {
1063                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1064         }
1065
1066         db_z_info &= C_028040_ZRANGE_PRECISION;
1067
1068         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1069                 db_z_info_reg = R_028038_DB_Z_INFO;
1070         } else {
1071                 db_z_info_reg = R_028040_DB_Z_INFO;
1072         }
1073
1074         /* When we don't know the last fast clear value we need to emit a
1075          * conditional packet, otherwise we can update DB_Z_INFO directly.
1076          */
1077         if (requires_cond_write) {
1078                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1079
1080                 const uint32_t write_space = 0 << 8;    /* register */
1081                 const uint32_t poll_space = 1 << 4;     /* memory */
1082                 const uint32_t function = 3 << 0;       /* equal to the reference */
1083                 const uint32_t options = write_space | poll_space | function;
1084                 radeon_emit(cmd_buffer->cs, options);
1085
1086                 /* poll address - location of the depth clear value */
1087                 uint64_t va = radv_buffer_get_va(image->bo);
1088                 va += image->offset + image->clear_value_offset;
1089
1090                 /* In presence of stencil format, we have to adjust the base
1091                  * address because the first value is the stencil clear value.
1092                  */
1093                 if (vk_format_is_stencil(image->vk_format))
1094                         va += 4;
1095
1096                 radeon_emit(cmd_buffer->cs, va);
1097                 radeon_emit(cmd_buffer->cs, va >> 32);
1098
1099                 radeon_emit(cmd_buffer->cs, fui(0.0f));          /* reference value */
1100                 radeon_emit(cmd_buffer->cs, (uint32_t)-1);       /* comparison mask */
1101                 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1102                 radeon_emit(cmd_buffer->cs, 0u);                 /* write address high */
1103                 radeon_emit(cmd_buffer->cs, db_z_info);
1104         } else {
1105                 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1106         }
1107 }
1108
1109 static void
1110 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1111                       struct radv_ds_buffer_info *ds,
1112                       struct radv_image *image,
1113                       VkImageLayout layout)
1114 {
1115         uint32_t db_z_info = ds->db_z_info;
1116         uint32_t db_stencil_info = ds->db_stencil_info;
1117
1118         if (!radv_layout_has_htile(image, layout,
1119                                    radv_image_queue_family_mask(image,
1120                                                                 cmd_buffer->queue_family_index,
1121                                                                 cmd_buffer->queue_family_index))) {
1122                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1123                 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1124         }
1125
1126         radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1127         radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1128
1129
1130         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1131                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1132                 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1133                 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1134                 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1135
1136                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1137                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* DB_Z_INFO */
1138                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* DB_STENCIL_INFO */
1139                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* DB_Z_READ_BASE */
1140                 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32));        /* DB_Z_READ_BASE_HI */
1141                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* DB_STENCIL_READ_BASE */
1142                 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1143                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* DB_Z_WRITE_BASE */
1144                 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32));       /* DB_Z_WRITE_BASE_HI */
1145                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1146                 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1147
1148                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1149                 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1150                 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1151         } else {
1152                 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1153
1154                 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1155                 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1156                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* R_028040_DB_Z_INFO */
1157                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* R_028044_DB_STENCIL_INFO */
1158                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* R_028048_DB_Z_READ_BASE */
1159                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* R_02804C_DB_STENCIL_READ_BASE */
1160                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* R_028050_DB_Z_WRITE_BASE */
1161                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1162                 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1163                 radeon_emit(cmd_buffer->cs, ds->db_depth_slice);        /* R_02805C_DB_DEPTH_SLICE */
1164
1165         }
1166
1167         /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1168         radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1169
1170         radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1171                                ds->pa_su_poly_offset_db_fmt_cntl);
1172 }
1173
1174 /**
1175  * Update the fast clear depth/stencil values if the image is bound as a
1176  * depth/stencil buffer.
1177  */
1178 static void
1179 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1180                                 struct radv_image *image,
1181                                 VkClearDepthStencilValue ds_clear_value)
1182 {
1183         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1184         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1185         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1186         struct radv_attachment_info *att;
1187         uint32_t att_idx;
1188
1189         if (!framebuffer || !subpass)
1190                 return;
1191
1192         att_idx = subpass->depth_stencil_attachment.attachment;
1193         if (att_idx == VK_ATTACHMENT_UNUSED)
1194                 return;
1195
1196         att = &framebuffer->attachments[att_idx];
1197         if (att->attachment->image != image)
1198                 return;
1199
1200         radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1201         radeon_emit(cs, ds_clear_value.stencil);
1202         radeon_emit(cs, fui(ds_clear_value.depth));
1203 }
1204
1205 void
1206 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1207                           struct radv_image *image,
1208                           VkClearDepthStencilValue ds_clear_value,
1209                           VkImageAspectFlags aspects)
1210 {
1211         uint64_t va = radv_buffer_get_va(image->bo);
1212         va += image->offset + image->clear_value_offset;
1213
1214         assert(radv_image_has_htile(image));
1215
1216         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1217         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1218                                     S_370_WR_CONFIRM(1) |
1219                                     S_370_ENGINE_SEL(V_370_PFP));
1220         radeon_emit(cmd_buffer->cs, va);
1221         radeon_emit(cmd_buffer->cs, va >> 32);
1222         radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1223         radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1224
1225         radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value);
1226
1227         /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1228          * only needed when clearing Z to 0.0.
1229          */
1230         if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1231             ds_clear_value.depth == 0.0) {
1232                 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1233                 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1234
1235                 if (!framebuffer || !subpass)
1236                         return;
1237
1238                 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
1239                         return;
1240
1241                 int idx = subpass->depth_stencil_attachment.attachment;
1242                 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1243                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1244                 struct radv_image *image = att->attachment->image;
1245
1246                 /* Only needed if the image is currently bound as the depth
1247                  * surface.
1248                  */
1249                 if (att->attachment->image != image)
1250                         return;
1251
1252                 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1253                                              layout, false);
1254         }
1255 }
1256
1257 static void
1258 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1259                            struct radv_image *image)
1260 {
1261         uint64_t va = radv_buffer_get_va(image->bo);
1262         va += image->offset + image->clear_value_offset;
1263
1264         if (!radv_image_has_htile(image))
1265                 return;
1266
1267         radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1268         radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1269                                     COPY_DATA_DST_SEL(COPY_DATA_REG) |
1270                                     COPY_DATA_COUNT_SEL);
1271         radeon_emit(cmd_buffer->cs, va);
1272         radeon_emit(cmd_buffer->cs, va >> 32);
1273         radeon_emit(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR >> 2);
1274         radeon_emit(cmd_buffer->cs, 0);
1275
1276         radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1277         radeon_emit(cmd_buffer->cs, 0);
1278 }
1279
1280 /*
1281  * With DCC some colors don't require CMASK elimination before being
1282  * used as a texture. This sets a predicate value to determine if the
1283  * cmask eliminate is required.
1284  */
1285 void
1286 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1287                                   struct radv_image *image,
1288                                   bool value)
1289 {
1290         uint64_t pred_val = value;
1291         uint64_t va = radv_buffer_get_va(image->bo);
1292         va += image->offset + image->dcc_pred_offset;
1293
1294         assert(radv_image_has_dcc(image));
1295
1296         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1297         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1298                                     S_370_WR_CONFIRM(1) |
1299                                     S_370_ENGINE_SEL(V_370_PFP));
1300         radeon_emit(cmd_buffer->cs, va);
1301         radeon_emit(cmd_buffer->cs, va >> 32);
1302         radeon_emit(cmd_buffer->cs, pred_val);
1303         radeon_emit(cmd_buffer->cs, pred_val >> 32);
1304 }
1305
1306 /**
1307  * Update the fast clear color values if the image is bound as a color buffer.
1308  */
1309 static void
1310 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1311                                    struct radv_image *image,
1312                                    int cb_idx,
1313                                    uint32_t color_values[2])
1314 {
1315         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1316         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1317         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1318         struct radv_attachment_info *att;
1319         uint32_t att_idx;
1320
1321         if (!framebuffer || !subpass)
1322                 return;
1323
1324         att_idx = subpass->color_attachments[cb_idx].attachment;
1325         if (att_idx == VK_ATTACHMENT_UNUSED)
1326                 return;
1327
1328         att = &framebuffer->attachments[att_idx];
1329         if (att->attachment->image != image)
1330                 return;
1331
1332         radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1333         radeon_emit(cs, color_values[0]);
1334         radeon_emit(cs, color_values[1]);
1335 }
1336
1337 /**
1338  * Set the clear color values to the image's metadata.
1339  */
1340 void
1341 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1342                               struct radv_image *image,
1343                               int cb_idx,
1344                               uint32_t color_values[2])
1345 {
1346         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1347         uint64_t va = radv_buffer_get_va(image->bo);
1348
1349         va += image->offset + image->clear_value_offset;
1350
1351         assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1352
1353         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1354         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1355                         S_370_WR_CONFIRM(1) |
1356                         S_370_ENGINE_SEL(V_370_PFP));
1357         radeon_emit(cs, va);
1358         radeon_emit(cs, va >> 32);
1359         radeon_emit(cs, color_values[0]);
1360         radeon_emit(cs, color_values[1]);
1361
1362         radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1363                                            color_values);
1364 }
1365
1366 /**
1367  * Load the clear color values from the image's metadata.
1368  */
1369 static void
1370 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1371                                struct radv_image *image,
1372                                int cb_idx)
1373 {
1374         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1375         uint64_t va = radv_buffer_get_va(image->bo);
1376
1377         va += image->offset + image->clear_value_offset;
1378
1379         if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1380                 return;
1381
1382         uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1383
1384         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1385         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1386                         COPY_DATA_DST_SEL(COPY_DATA_REG) |
1387                         COPY_DATA_COUNT_SEL);
1388         radeon_emit(cs, va);
1389         radeon_emit(cs, va >> 32);
1390         radeon_emit(cs, reg >> 2);
1391         radeon_emit(cs, 0);
1392
1393         radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1394         radeon_emit(cs, 0);
1395 }
1396
1397 static void
1398 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1399 {
1400         int i;
1401         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1402         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1403
1404         /* this may happen for inherited secondary recording */
1405         if (!framebuffer)
1406                 return;
1407
1408         for (i = 0; i < 8; ++i) {
1409                 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1410                         radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1411                                        S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1412                         continue;
1413                 }
1414
1415                 int idx = subpass->color_attachments[i].attachment;
1416                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1417                 struct radv_image *image = att->attachment->image;
1418                 VkImageLayout layout = subpass->color_attachments[i].layout;
1419
1420                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1421
1422                 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1423                 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1424
1425                 radv_load_color_clear_metadata(cmd_buffer, image, i);
1426         }
1427
1428         if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1429                 int idx = subpass->depth_stencil_attachment.attachment;
1430                 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1431                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1432                 struct radv_image *image = att->attachment->image;
1433                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1434                 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1435                                                                                 cmd_buffer->queue_family_index,
1436                                                                                 cmd_buffer->queue_family_index);
1437                 /* We currently don't support writing decompressed HTILE */
1438                 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1439                        radv_layout_is_htile_compressed(image, layout, queue_mask));
1440
1441                 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1442
1443                 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1444                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1445                         cmd_buffer->state.offset_scale = att->ds.offset_scale;
1446                 }
1447                 radv_load_depth_clear_regs(cmd_buffer, image);
1448         } else {
1449                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1450                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1451                 else
1452                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1453
1454                 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1455                 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1456         }
1457         radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1458                                S_028208_BR_X(framebuffer->width) |
1459                                S_028208_BR_Y(framebuffer->height));
1460
1461         if (cmd_buffer->device->dfsm_allowed) {
1462                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1463                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1464         }
1465
1466         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1467 }
1468
1469 static void
1470 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1471 {
1472         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1473         struct radv_cmd_state *state = &cmd_buffer->state;
1474
1475         if (state->index_type != state->last_index_type) {
1476                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1477                         radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1478                                                    2, state->index_type);
1479                 } else {
1480                         radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1481                         radeon_emit(cs, state->index_type);
1482                 }
1483
1484                 state->last_index_type = state->index_type;
1485         }
1486
1487         radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1488         radeon_emit(cs, state->index_va);
1489         radeon_emit(cs, state->index_va >> 32);
1490
1491         radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1492         radeon_emit(cs, state->max_index_count);
1493
1494         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1495 }
1496
1497 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1498 {
1499         bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1500         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1501         uint32_t pa_sc_mode_cntl_1 =
1502                 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1503         uint32_t db_count_control;
1504
1505         if(!cmd_buffer->state.active_occlusion_queries) {
1506                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1507                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1508                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1509                             has_perfect_queries) {
1510                                 /* Re-enable out-of-order rasterization if the
1511                                  * bound pipeline supports it and if it's has
1512                                  * been disabled before starting any perfect
1513                                  * occlusion queries.
1514                                  */
1515                                 radeon_set_context_reg(cmd_buffer->cs,
1516                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1517                                                        pa_sc_mode_cntl_1);
1518                         }
1519                         db_count_control = 0;
1520                 } else {
1521                         db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1522                 }
1523         } else {
1524                 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1525                 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1526
1527                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1528                         db_count_control =
1529                                 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1530                                 S_028004_SAMPLE_RATE(sample_rate) |
1531                                 S_028004_ZPASS_ENABLE(1) |
1532                                 S_028004_SLICE_EVEN_ENABLE(1) |
1533                                 S_028004_SLICE_ODD_ENABLE(1);
1534
1535                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1536                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1537                             has_perfect_queries) {
1538                                 /* If the bound pipeline has enabled
1539                                  * out-of-order rasterization, we should
1540                                  * disable it before starting any perfect
1541                                  * occlusion queries.
1542                                  */
1543                                 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1544
1545                                 radeon_set_context_reg(cmd_buffer->cs,
1546                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1547                                                        pa_sc_mode_cntl_1);
1548                         }
1549                 } else {
1550                         db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1551                                 S_028004_SAMPLE_RATE(sample_rate);
1552                 }
1553         }
1554
1555         radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1556 }
1557
1558 static void
1559 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1560 {
1561         uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1562
1563         if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1564                 radv_emit_viewport(cmd_buffer);
1565
1566         if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1567             !cmd_buffer->device->physical_device->has_scissor_bug)
1568                 radv_emit_scissor(cmd_buffer);
1569
1570         if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1571                 radv_emit_line_width(cmd_buffer);
1572
1573         if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1574                 radv_emit_blend_constants(cmd_buffer);
1575
1576         if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1577                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1578                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1579                 radv_emit_stencil(cmd_buffer);
1580
1581         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1582                 radv_emit_depth_bounds(cmd_buffer);
1583
1584         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1585                 radv_emit_depth_bias(cmd_buffer);
1586
1587         if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1588                 radv_emit_discard_rectangle(cmd_buffer);
1589
1590         cmd_buffer->state.dirty &= ~states;
1591 }
1592
1593 static void
1594 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1595                             VkPipelineBindPoint bind_point)
1596 {
1597         struct radv_descriptor_state *descriptors_state =
1598                 radv_get_descriptors_state(cmd_buffer, bind_point);
1599         struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1600         unsigned bo_offset;
1601
1602         if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1603                                          set->mapped_ptr,
1604                                          &bo_offset))
1605                 return;
1606
1607         set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1608         set->va += bo_offset;
1609 }
1610
1611 static void
1612 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1613                                     VkPipelineBindPoint bind_point)
1614 {
1615         struct radv_descriptor_state *descriptors_state =
1616                 radv_get_descriptors_state(cmd_buffer, bind_point);
1617         uint32_t size = MAX_SETS * 2 * 4;
1618         uint32_t offset;
1619         void *ptr;
1620
1621         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1622                                           256, &offset, &ptr))
1623                 return;
1624
1625         for (unsigned i = 0; i < MAX_SETS; i++) {
1626                 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1627                 uint64_t set_va = 0;
1628                 struct radv_descriptor_set *set = descriptors_state->sets[i];
1629                 if (descriptors_state->valid & (1u << i))
1630                         set_va = set->va;
1631                 uptr[0] = set_va & 0xffffffff;
1632                 uptr[1] = set_va >> 32;
1633         }
1634
1635         uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1636         va += offset;
1637
1638         if (cmd_buffer->state.pipeline) {
1639                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1640                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1641                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1642
1643                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1644                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1645                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1646
1647                 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1648                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1649                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1650
1651                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1652                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1653                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1654
1655                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1656                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1657                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1658         }
1659
1660         if (cmd_buffer->state.compute_pipeline)
1661                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1662                                            AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1663 }
1664
1665 static void
1666 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1667                        VkShaderStageFlags stages)
1668 {
1669         VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1670                                          VK_PIPELINE_BIND_POINT_COMPUTE :
1671                                          VK_PIPELINE_BIND_POINT_GRAPHICS;
1672         struct radv_descriptor_state *descriptors_state =
1673                 radv_get_descriptors_state(cmd_buffer, bind_point);
1674
1675         if (!descriptors_state->dirty)
1676                 return;
1677
1678         if (descriptors_state->push_dirty)
1679                 radv_flush_push_descriptors(cmd_buffer, bind_point);
1680
1681         if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1682             (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1683                 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1684         }
1685
1686         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1687                                                            cmd_buffer->cs,
1688                                                            MAX_SETS * MESA_SHADER_STAGES * 4);
1689
1690         if (cmd_buffer->state.pipeline) {
1691                 radv_foreach_stage(stage, stages) {
1692                         if (!cmd_buffer->state.pipeline->shaders[stage])
1693                                 continue;
1694
1695                         radv_emit_descriptor_pointers(cmd_buffer,
1696                                                       cmd_buffer->state.pipeline,
1697                                                       descriptors_state, stage);
1698                 }
1699         }
1700
1701         if (cmd_buffer->state.compute_pipeline &&
1702             (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1703                 radv_emit_descriptor_pointers(cmd_buffer,
1704                                               cmd_buffer->state.compute_pipeline,
1705                                               descriptors_state,
1706                                               MESA_SHADER_COMPUTE);
1707         }
1708
1709         descriptors_state->dirty = 0;
1710         descriptors_state->push_dirty = false;
1711
1712         if (unlikely(cmd_buffer->device->trace_bo))
1713                 radv_save_descriptors(cmd_buffer, bind_point);
1714
1715         assert(cmd_buffer->cs->cdw <= cdw_max);
1716 }
1717
1718 static void
1719 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1720                      VkShaderStageFlags stages)
1721 {
1722         struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1723                                          ? cmd_buffer->state.compute_pipeline
1724                                          : cmd_buffer->state.pipeline;
1725         struct radv_pipeline_layout *layout = pipeline->layout;
1726         struct radv_shader_variant *shader, *prev_shader;
1727         unsigned offset;
1728         void *ptr;
1729         uint64_t va;
1730
1731         stages &= cmd_buffer->push_constant_stages;
1732         if (!stages ||
1733             (!layout->push_constant_size && !layout->dynamic_offset_count))
1734                 return;
1735
1736         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1737                                           16 * layout->dynamic_offset_count,
1738                                           256, &offset, &ptr))
1739                 return;
1740
1741         memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1742         memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1743                16 * layout->dynamic_offset_count);
1744
1745         va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1746         va += offset;
1747
1748         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1749                                                            cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1750
1751         prev_shader = NULL;
1752         radv_foreach_stage(stage, stages) {
1753                 shader = radv_get_shader(pipeline, stage);
1754
1755                 /* Avoid redundantly emitting the address for merged stages. */
1756                 if (shader && shader != prev_shader) {
1757                         radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1758                                                    AC_UD_PUSH_CONSTANTS, va);
1759
1760                         prev_shader = shader;
1761                 }
1762         }
1763
1764         cmd_buffer->push_constant_stages &= ~stages;
1765         assert(cmd_buffer->cs->cdw <= cdw_max);
1766 }
1767
1768 static void
1769 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1770                               bool pipeline_is_dirty)
1771 {
1772         if ((pipeline_is_dirty ||
1773             (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1774             cmd_buffer->state.pipeline->vertex_elements.count &&
1775             radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1776                 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1777                 unsigned vb_offset;
1778                 void *vb_ptr;
1779                 uint32_t i = 0;
1780                 uint32_t count = velems->count;
1781                 uint64_t va;
1782
1783                 /* allocate some descriptor state for vertex buffers */
1784                 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1785                                                   &vb_offset, &vb_ptr))
1786                         return;
1787
1788                 for (i = 0; i < count; i++) {
1789                         uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1790                         uint32_t offset;
1791                         int vb = velems->binding[i];
1792                         struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1793                         uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1794
1795                         va = radv_buffer_get_va(buffer->bo);
1796
1797                         offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1798                         va += offset + buffer->offset;
1799                         desc[0] = va;
1800                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1801                         if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1802                                 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1803                         else
1804                                 desc[2] = buffer->size - offset;
1805                         desc[3] = velems->rsrc_word3[i];
1806                 }
1807
1808                 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1809                 va += vb_offset;
1810
1811                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1812                                            AC_UD_VS_VERTEX_BUFFERS, va);
1813
1814                 cmd_buffer->state.vb_va = va;
1815                 cmd_buffer->state.vb_size = count * 16;
1816                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1817         }
1818         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1819 }
1820
1821 static void
1822 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1823 {
1824         radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1825         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1826         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1827 }
1828
1829 static void
1830 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1831                          bool instanced_draw, bool indirect_draw,
1832                          uint32_t draw_vertex_count)
1833 {
1834         struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1835         struct radv_cmd_state *state = &cmd_buffer->state;
1836         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1837         uint32_t ia_multi_vgt_param;
1838         int32_t primitive_reset_en;
1839
1840         /* Draw state. */
1841         ia_multi_vgt_param =
1842                 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1843                                           indirect_draw, draw_vertex_count);
1844
1845         if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1846                 if (info->chip_class >= GFX9) {
1847                         radeon_set_uconfig_reg_idx(cs,
1848                                                    R_030960_IA_MULTI_VGT_PARAM,
1849                                                    4, ia_multi_vgt_param);
1850                 } else if (info->chip_class >= CIK) {
1851                         radeon_set_context_reg_idx(cs,
1852                                                    R_028AA8_IA_MULTI_VGT_PARAM,
1853                                                    1, ia_multi_vgt_param);
1854                 } else {
1855                         radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1856                                                ia_multi_vgt_param);
1857                 }
1858                 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1859         }
1860
1861         /* Primitive restart. */
1862         primitive_reset_en =
1863                 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1864
1865         if (primitive_reset_en != state->last_primitive_reset_en) {
1866                 state->last_primitive_reset_en = primitive_reset_en;
1867                 if (info->chip_class >= GFX9) {
1868                         radeon_set_uconfig_reg(cs,
1869                                                R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1870                                                primitive_reset_en);
1871                 } else {
1872                         radeon_set_context_reg(cs,
1873                                                R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1874                                                primitive_reset_en);
1875                 }
1876         }
1877
1878         if (primitive_reset_en) {
1879                 uint32_t primitive_reset_index =
1880                         state->index_type ? 0xffffffffu : 0xffffu;
1881
1882                 if (primitive_reset_index != state->last_primitive_reset_index) {
1883                         radeon_set_context_reg(cs,
1884                                                R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1885                                                primitive_reset_index);
1886                         state->last_primitive_reset_index = primitive_reset_index;
1887                 }
1888         }
1889 }
1890
1891 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1892                              VkPipelineStageFlags src_stage_mask)
1893 {
1894         if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1895                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1896                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1897                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1898                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1899         }
1900
1901         if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1902                               VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1903                               VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1904                               VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1905                               VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1906                               VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1907                               VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1908                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1909                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1910                               VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1911                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1912                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1913         } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1914                                      VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1915                                      VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1916                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1917         }
1918 }
1919
1920 static enum radv_cmd_flush_bits
1921 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1922                                   VkAccessFlags src_flags)
1923 {
1924         enum radv_cmd_flush_bits flush_bits = 0;
1925         uint32_t b;
1926         for_each_bit(b, src_flags) {
1927                 switch ((VkAccessFlagBits)(1 << b)) {
1928                 case VK_ACCESS_SHADER_WRITE_BIT:
1929                         flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1930                         break;
1931                 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1932                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1933                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1934                         break;
1935                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1936                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1937                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1938                         break;
1939                 case VK_ACCESS_TRANSFER_WRITE_BIT:
1940                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1941                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1942                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1943                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1944                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
1945                         break;
1946                 default:
1947                         break;
1948                 }
1949         }
1950         return flush_bits;
1951 }
1952
1953 static enum radv_cmd_flush_bits
1954 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1955                       VkAccessFlags dst_flags,
1956                       struct radv_image *image)
1957 {
1958         enum radv_cmd_flush_bits flush_bits = 0;
1959         uint32_t b;
1960         for_each_bit(b, dst_flags) {
1961                 switch ((VkAccessFlagBits)(1 << b)) {
1962                 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1963                 case VK_ACCESS_INDEX_READ_BIT:
1964                         break;
1965                 case VK_ACCESS_UNIFORM_READ_BIT:
1966                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1967                         break;
1968                 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1969                 case VK_ACCESS_SHADER_READ_BIT:
1970                 case VK_ACCESS_TRANSFER_READ_BIT:
1971                 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1972                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1973                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
1974                         break;
1975                 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1976                         /* TODO: change to image && when the image gets passed
1977                          * through from the subpass. */
1978                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1979                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1980                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1981                         break;
1982                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1983                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1984                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1985                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1986                         break;
1987                 default:
1988                         break;
1989                 }
1990         }
1991         return flush_bits;
1992 }
1993
1994 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1995 {
1996         cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1997         radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1998         cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1999                                                               NULL);
2000 }
2001
2002 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2003                                                  VkAttachmentReference att)
2004 {
2005         unsigned idx = att.attachment;
2006         struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2007         VkImageSubresourceRange range;
2008         range.aspectMask = 0;
2009         range.baseMipLevel = view->base_mip;
2010         range.levelCount = 1;
2011         range.baseArrayLayer = view->base_layer;
2012         range.layerCount = cmd_buffer->state.framebuffer->layers;
2013
2014         radv_handle_image_transition(cmd_buffer,
2015                                      view->image,
2016                                      cmd_buffer->state.attachments[idx].current_layout,
2017                                      att.layout, 0, 0, &range,
2018                                      cmd_buffer->state.attachments[idx].pending_clear_aspects);
2019
2020         cmd_buffer->state.attachments[idx].current_layout = att.layout;
2021
2022
2023 }
2024
2025 void
2026 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2027                             const struct radv_subpass *subpass, bool transitions)
2028 {
2029         if (transitions) {
2030                 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2031
2032                 for (unsigned i = 0; i < subpass->color_count; ++i) {
2033                         if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2034                                 radv_handle_subpass_image_transition(cmd_buffer,
2035                                                                      subpass->color_attachments[i]);
2036                 }
2037
2038                 for (unsigned i = 0; i < subpass->input_count; ++i) {
2039                         radv_handle_subpass_image_transition(cmd_buffer,
2040                                                         subpass->input_attachments[i]);
2041                 }
2042
2043                 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2044                         radv_handle_subpass_image_transition(cmd_buffer,
2045                                                         subpass->depth_stencil_attachment);
2046                 }
2047         }
2048
2049         cmd_buffer->state.subpass = subpass;
2050
2051         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2052 }
2053
2054 static VkResult
2055 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2056                                  struct radv_render_pass *pass,
2057                                  const VkRenderPassBeginInfo *info)
2058 {
2059         struct radv_cmd_state *state = &cmd_buffer->state;
2060
2061         if (pass->attachment_count == 0) {
2062                 state->attachments = NULL;
2063                 return VK_SUCCESS;
2064         }
2065
2066         state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2067                                         pass->attachment_count *
2068                                         sizeof(state->attachments[0]),
2069                                         8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2070         if (state->attachments == NULL) {
2071                 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2072                 return cmd_buffer->record_result;
2073         }
2074
2075         for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2076                 struct radv_render_pass_attachment *att = &pass->attachments[i];
2077                 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2078                 VkImageAspectFlags clear_aspects = 0;
2079
2080                 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2081                         /* color attachment */
2082                         if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2083                                 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2084                         }
2085                 } else {
2086                         /* depthstencil attachment */
2087                         if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2088                             att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2089                                 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2090                                 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2091                                     att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2092                                         clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2093                         }
2094                         if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2095                             att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2096                                 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2097                         }
2098                 }
2099
2100                 state->attachments[i].pending_clear_aspects = clear_aspects;
2101                 state->attachments[i].cleared_views = 0;
2102                 if (clear_aspects && info) {
2103                         assert(info->clearValueCount > i);
2104                         state->attachments[i].clear_value = info->pClearValues[i];
2105                 }
2106
2107                 state->attachments[i].current_layout = att->initial_layout;
2108         }
2109
2110         return VK_SUCCESS;
2111 }
2112
2113 VkResult radv_AllocateCommandBuffers(
2114         VkDevice _device,
2115         const VkCommandBufferAllocateInfo *pAllocateInfo,
2116         VkCommandBuffer *pCommandBuffers)
2117 {
2118         RADV_FROM_HANDLE(radv_device, device, _device);
2119         RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2120
2121         VkResult result = VK_SUCCESS;
2122         uint32_t i;
2123
2124         for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2125
2126                 if (!list_empty(&pool->free_cmd_buffers)) {
2127                         struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2128
2129                         list_del(&cmd_buffer->pool_link);
2130                         list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2131
2132                         result = radv_reset_cmd_buffer(cmd_buffer);
2133                         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2134                         cmd_buffer->level = pAllocateInfo->level;
2135
2136                         pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2137                 } else {
2138                         result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2139                                                         &pCommandBuffers[i]);
2140                 }
2141                 if (result != VK_SUCCESS)
2142                         break;
2143         }
2144
2145         if (result != VK_SUCCESS) {
2146                 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2147                                         i, pCommandBuffers);
2148
2149                 /* From the Vulkan 1.0.66 spec:
2150                  *
2151                  * "vkAllocateCommandBuffers can be used to create multiple
2152                  *  command buffers. If the creation of any of those command
2153                  *  buffers fails, the implementation must destroy all
2154                  *  successfully created command buffer objects from this
2155                  *  command, set all entries of the pCommandBuffers array to
2156                  *  NULL and return the error."
2157                  */
2158                 memset(pCommandBuffers, 0,
2159                        sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2160         }
2161
2162         return result;
2163 }
2164
2165 void radv_FreeCommandBuffers(
2166         VkDevice device,
2167         VkCommandPool commandPool,
2168         uint32_t commandBufferCount,
2169         const VkCommandBuffer *pCommandBuffers)
2170 {
2171         for (uint32_t i = 0; i < commandBufferCount; i++) {
2172                 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2173
2174                 if (cmd_buffer) {
2175                         if (cmd_buffer->pool) {
2176                                 list_del(&cmd_buffer->pool_link);
2177                                 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2178                         } else
2179                                 radv_cmd_buffer_destroy(cmd_buffer);
2180
2181                 }
2182         }
2183 }
2184
2185 VkResult radv_ResetCommandBuffer(
2186         VkCommandBuffer commandBuffer,
2187         VkCommandBufferResetFlags flags)
2188 {
2189         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2190         return radv_reset_cmd_buffer(cmd_buffer);
2191 }
2192
2193 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2194 {
2195         struct radv_device *device = cmd_buffer->device;
2196         if (device->gfx_init) {
2197                 uint64_t va = radv_buffer_get_va(device->gfx_init);
2198                 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2199                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2200                 radeon_emit(cmd_buffer->cs, va);
2201                 radeon_emit(cmd_buffer->cs, va >> 32);
2202                 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2203         } else
2204                 si_init_config(cmd_buffer);
2205 }
2206
2207 VkResult radv_BeginCommandBuffer(
2208         VkCommandBuffer commandBuffer,
2209         const VkCommandBufferBeginInfo *pBeginInfo)
2210 {
2211         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2212         VkResult result = VK_SUCCESS;
2213
2214         if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2215                 /* If the command buffer has already been resetted with
2216                  * vkResetCommandBuffer, no need to do it again.
2217                  */
2218                 result = radv_reset_cmd_buffer(cmd_buffer);
2219                 if (result != VK_SUCCESS)
2220                         return result;
2221         }
2222
2223         memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2224         cmd_buffer->state.last_primitive_reset_en = -1;
2225         cmd_buffer->state.last_index_type = -1;
2226         cmd_buffer->state.last_num_instances = -1;
2227         cmd_buffer->state.last_vertex_offset = -1;
2228         cmd_buffer->state.last_first_instance = -1;
2229         cmd_buffer->usage_flags = pBeginInfo->flags;
2230
2231         /* setup initial configuration into command buffer */
2232         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2233                 switch (cmd_buffer->queue_family_index) {
2234                 case RADV_QUEUE_GENERAL:
2235                         emit_gfx_buffer_state(cmd_buffer);
2236                         break;
2237                 case RADV_QUEUE_COMPUTE:
2238                         si_init_compute(cmd_buffer);
2239                         break;
2240                 case RADV_QUEUE_TRANSFER:
2241                 default:
2242                         break;
2243                 }
2244         }
2245
2246         if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2247                 assert(pBeginInfo->pInheritanceInfo);
2248                 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2249                 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2250
2251                 struct radv_subpass *subpass =
2252                         &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2253
2254                 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2255                 if (result != VK_SUCCESS)
2256                         return result;
2257
2258                 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2259         }
2260
2261         if (unlikely(cmd_buffer->device->trace_bo))
2262                 radv_cmd_buffer_trace_emit(cmd_buffer);
2263
2264         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2265
2266         return result;
2267 }
2268
2269 void radv_CmdBindVertexBuffers(
2270         VkCommandBuffer                             commandBuffer,
2271         uint32_t                                    firstBinding,
2272         uint32_t                                    bindingCount,
2273         const VkBuffer*                             pBuffers,
2274         const VkDeviceSize*                         pOffsets)
2275 {
2276         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2277         struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2278         bool changed = false;
2279
2280         /* We have to defer setting up vertex buffer since we need the buffer
2281          * stride from the pipeline. */
2282
2283         assert(firstBinding + bindingCount <= MAX_VBS);
2284         for (uint32_t i = 0; i < bindingCount; i++) {
2285                 uint32_t idx = firstBinding + i;
2286
2287                 if (!changed &&
2288                     (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2289                      vb[idx].offset != pOffsets[i])) {
2290                         changed = true;
2291                 }
2292
2293                 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2294                 vb[idx].offset = pOffsets[i];
2295
2296                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2297                                    vb[idx].buffer->bo, 8);
2298         }
2299
2300         if (!changed) {
2301                 /* No state changes. */
2302                 return;
2303         }
2304
2305         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2306 }
2307
2308 void radv_CmdBindIndexBuffer(
2309         VkCommandBuffer                             commandBuffer,
2310         VkBuffer buffer,
2311         VkDeviceSize offset,
2312         VkIndexType indexType)
2313 {
2314         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2315         RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2316
2317         if (cmd_buffer->state.index_buffer == index_buffer &&
2318             cmd_buffer->state.index_offset == offset &&
2319             cmd_buffer->state.index_type == indexType) {
2320                 /* No state changes. */
2321                 return;
2322         }
2323
2324         cmd_buffer->state.index_buffer = index_buffer;
2325         cmd_buffer->state.index_offset = offset;
2326         cmd_buffer->state.index_type = indexType; /* vk matches hw */
2327         cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2328         cmd_buffer->state.index_va += index_buffer->offset + offset;
2329
2330         int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2331         cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2332         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2333         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2334 }
2335
2336
2337 static void
2338 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2339                          VkPipelineBindPoint bind_point,
2340                          struct radv_descriptor_set *set, unsigned idx)
2341 {
2342         struct radeon_winsys *ws = cmd_buffer->device->ws;
2343
2344         radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2345         if (!set)
2346                 return;
2347
2348         assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2349
2350         if (!cmd_buffer->device->use_global_bo_list) {
2351                 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2352                         if (set->descriptors[j])
2353                                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2354         }
2355
2356         if(set->bo)
2357                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2358 }
2359
2360 void radv_CmdBindDescriptorSets(
2361         VkCommandBuffer                             commandBuffer,
2362         VkPipelineBindPoint                         pipelineBindPoint,
2363         VkPipelineLayout                            _layout,
2364         uint32_t                                    firstSet,
2365         uint32_t                                    descriptorSetCount,
2366         const VkDescriptorSet*                      pDescriptorSets,
2367         uint32_t                                    dynamicOffsetCount,
2368         const uint32_t*                             pDynamicOffsets)
2369 {
2370         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2371         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2372         unsigned dyn_idx = 0;
2373
2374         const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2375
2376         for (unsigned i = 0; i < descriptorSetCount; ++i) {
2377                 unsigned idx = i + firstSet;
2378                 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2379                 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2380
2381                 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2382                         unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2383                         uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2384                         assert(dyn_idx < dynamicOffsetCount);
2385
2386                         struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2387                         uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2388                         dst[0] = va;
2389                         dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2390                         dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2391                         dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2392                                  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2393                                  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2394                                  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2395                                  S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2396                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2397                         cmd_buffer->push_constant_stages |=
2398                                              set->layout->dynamic_shader_stages;
2399                 }
2400         }
2401 }
2402
2403 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2404                                           struct radv_descriptor_set *set,
2405                                           struct radv_descriptor_set_layout *layout,
2406                                           VkPipelineBindPoint bind_point)
2407 {
2408         struct radv_descriptor_state *descriptors_state =
2409                 radv_get_descriptors_state(cmd_buffer, bind_point);
2410         set->size = layout->size;
2411         set->layout = layout;
2412
2413         if (descriptors_state->push_set.capacity < set->size) {
2414                 size_t new_size = MAX2(set->size, 1024);
2415                 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2416                 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2417
2418                 free(set->mapped_ptr);
2419                 set->mapped_ptr = malloc(new_size);
2420
2421                 if (!set->mapped_ptr) {
2422                         descriptors_state->push_set.capacity = 0;
2423                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2424                         return false;
2425                 }
2426
2427                 descriptors_state->push_set.capacity = new_size;
2428         }
2429
2430         return true;
2431 }
2432
2433 void radv_meta_push_descriptor_set(
2434         struct radv_cmd_buffer*              cmd_buffer,
2435         VkPipelineBindPoint                  pipelineBindPoint,
2436         VkPipelineLayout                     _layout,
2437         uint32_t                             set,
2438         uint32_t                             descriptorWriteCount,
2439         const VkWriteDescriptorSet*          pDescriptorWrites)
2440 {
2441         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2442         struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2443         unsigned bo_offset;
2444
2445         assert(set == 0);
2446         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2447
2448         push_set->size = layout->set[set].layout->size;
2449         push_set->layout = layout->set[set].layout;
2450
2451         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2452                                           &bo_offset,
2453                                           (void**) &push_set->mapped_ptr))
2454                 return;
2455
2456         push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2457         push_set->va += bo_offset;
2458
2459         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2460                                     radv_descriptor_set_to_handle(push_set),
2461                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2462
2463         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2464 }
2465
2466 void radv_CmdPushDescriptorSetKHR(
2467         VkCommandBuffer                             commandBuffer,
2468         VkPipelineBindPoint                         pipelineBindPoint,
2469         VkPipelineLayout                            _layout,
2470         uint32_t                                    set,
2471         uint32_t                                    descriptorWriteCount,
2472         const VkWriteDescriptorSet*                 pDescriptorWrites)
2473 {
2474         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2475         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2476         struct radv_descriptor_state *descriptors_state =
2477                 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2478         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2479
2480         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2481
2482         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2483                                            layout->set[set].layout,
2484                                            pipelineBindPoint))
2485                 return;
2486
2487         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2488                                     radv_descriptor_set_to_handle(push_set),
2489                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2490
2491         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2492         descriptors_state->push_dirty = true;
2493 }
2494
2495 void radv_CmdPushDescriptorSetWithTemplateKHR(
2496         VkCommandBuffer                             commandBuffer,
2497         VkDescriptorUpdateTemplateKHR               descriptorUpdateTemplate,
2498         VkPipelineLayout                            _layout,
2499         uint32_t                                    set,
2500         const void*                                 pData)
2501 {
2502         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2503         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2504         RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2505         struct radv_descriptor_state *descriptors_state =
2506                 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2507         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2508
2509         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2510
2511         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2512                                            layout->set[set].layout,
2513                                            templ->bind_point))
2514                 return;
2515
2516         radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2517                                                  descriptorUpdateTemplate, pData);
2518
2519         radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2520         descriptors_state->push_dirty = true;
2521 }
2522
2523 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2524                            VkPipelineLayout layout,
2525                            VkShaderStageFlags stageFlags,
2526                            uint32_t offset,
2527                            uint32_t size,
2528                            const void* pValues)
2529 {
2530         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2531         memcpy(cmd_buffer->push_constants + offset, pValues, size);
2532         cmd_buffer->push_constant_stages |= stageFlags;
2533 }
2534
2535 VkResult radv_EndCommandBuffer(
2536         VkCommandBuffer                             commandBuffer)
2537 {
2538         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2539
2540         if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2541                 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2542                         cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2543                 si_emit_cache_flush(cmd_buffer);
2544         }
2545
2546         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2547
2548         if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2549                 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2550
2551         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2552
2553         return cmd_buffer->record_result;
2554 }
2555
2556 static void
2557 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2558 {
2559         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2560
2561         if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2562                 return;
2563
2564         cmd_buffer->state.emitted_compute_pipeline = pipeline;
2565
2566         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2567         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2568
2569         cmd_buffer->compute_scratch_size_needed =
2570                                   MAX2(cmd_buffer->compute_scratch_size_needed,
2571                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2572
2573         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2574                            pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
2575
2576         if (unlikely(cmd_buffer->device->trace_bo))
2577                 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2578 }
2579
2580 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2581                                             VkPipelineBindPoint bind_point)
2582 {
2583         struct radv_descriptor_state *descriptors_state =
2584                 radv_get_descriptors_state(cmd_buffer, bind_point);
2585
2586         descriptors_state->dirty |= descriptors_state->valid;
2587 }
2588
2589 void radv_CmdBindPipeline(
2590         VkCommandBuffer                             commandBuffer,
2591         VkPipelineBindPoint                         pipelineBindPoint,
2592         VkPipeline                                  _pipeline)
2593 {
2594         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2595         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2596
2597         switch (pipelineBindPoint) {
2598         case VK_PIPELINE_BIND_POINT_COMPUTE:
2599                 if (cmd_buffer->state.compute_pipeline == pipeline)
2600                         return;
2601                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2602
2603                 cmd_buffer->state.compute_pipeline = pipeline;
2604                 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2605                 break;
2606         case VK_PIPELINE_BIND_POINT_GRAPHICS:
2607                 if (cmd_buffer->state.pipeline == pipeline)
2608                         return;
2609                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2610
2611                 cmd_buffer->state.pipeline = pipeline;
2612                 if (!pipeline)
2613                         break;
2614
2615                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2616                 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2617
2618                 /* the new vertex shader might not have the same user regs */
2619                 cmd_buffer->state.last_first_instance = -1;
2620                 cmd_buffer->state.last_vertex_offset = -1;
2621
2622                 /* Prefetch all pipeline shaders at first draw time. */
2623                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2624
2625                 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2626
2627                 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2628                         cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2629                 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2630                         cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2631
2632                 if (radv_pipeline_has_tess(pipeline))
2633                         cmd_buffer->tess_rings_needed = true;
2634
2635                 if (radv_pipeline_has_gs(pipeline)) {
2636                         struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2637                                                                              AC_UD_SCRATCH_RING_OFFSETS);
2638                         if (cmd_buffer->ring_offsets_idx == -1)
2639                                 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2640                         else if (loc->sgpr_idx != -1)
2641                                 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2642                 }
2643                 break;
2644         default:
2645                 assert(!"invalid bind point");
2646                 break;
2647         }
2648 }
2649
2650 void radv_CmdSetViewport(
2651         VkCommandBuffer                             commandBuffer,
2652         uint32_t                                    firstViewport,
2653         uint32_t                                    viewportCount,
2654         const VkViewport*                           pViewports)
2655 {
2656         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2657         struct radv_cmd_state *state = &cmd_buffer->state;
2658         MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2659
2660         assert(firstViewport < MAX_VIEWPORTS);
2661         assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2662
2663         memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2664                viewportCount * sizeof(*pViewports));
2665
2666         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2667 }
2668
2669 void radv_CmdSetScissor(
2670         VkCommandBuffer                             commandBuffer,
2671         uint32_t                                    firstScissor,
2672         uint32_t                                    scissorCount,
2673         const VkRect2D*                             pScissors)
2674 {
2675         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2676         struct radv_cmd_state *state = &cmd_buffer->state;
2677         MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2678
2679         assert(firstScissor < MAX_SCISSORS);
2680         assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2681
2682         memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2683                scissorCount * sizeof(*pScissors));
2684
2685         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2686 }
2687
2688 void radv_CmdSetLineWidth(
2689         VkCommandBuffer                             commandBuffer,
2690         float                                       lineWidth)
2691 {
2692         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2693         cmd_buffer->state.dynamic.line_width = lineWidth;
2694         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2695 }
2696
2697 void radv_CmdSetDepthBias(
2698         VkCommandBuffer                             commandBuffer,
2699         float                                       depthBiasConstantFactor,
2700         float                                       depthBiasClamp,
2701         float                                       depthBiasSlopeFactor)
2702 {
2703         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2704
2705         cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2706         cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2707         cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2708
2709         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2710 }
2711
2712 void radv_CmdSetBlendConstants(
2713         VkCommandBuffer                             commandBuffer,
2714         const float                                 blendConstants[4])
2715 {
2716         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2717
2718         memcpy(cmd_buffer->state.dynamic.blend_constants,
2719                blendConstants, sizeof(float) * 4);
2720
2721         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2722 }
2723
2724 void radv_CmdSetDepthBounds(
2725         VkCommandBuffer                             commandBuffer,
2726         float                                       minDepthBounds,
2727         float                                       maxDepthBounds)
2728 {
2729         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2730
2731         cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2732         cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2733
2734         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2735 }
2736
2737 void radv_CmdSetStencilCompareMask(
2738         VkCommandBuffer                             commandBuffer,
2739         VkStencilFaceFlags                          faceMask,
2740         uint32_t                                    compareMask)
2741 {
2742         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2743
2744         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2745                 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2746         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2747                 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2748
2749         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2750 }
2751
2752 void radv_CmdSetStencilWriteMask(
2753         VkCommandBuffer                             commandBuffer,
2754         VkStencilFaceFlags                          faceMask,
2755         uint32_t                                    writeMask)
2756 {
2757         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2758
2759         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2760                 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2761         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2762                 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2763
2764         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2765 }
2766
2767 void radv_CmdSetStencilReference(
2768         VkCommandBuffer                             commandBuffer,
2769         VkStencilFaceFlags                          faceMask,
2770         uint32_t                                    reference)
2771 {
2772         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2773
2774         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2775                 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2776         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2777                 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2778
2779         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2780 }
2781
2782 void radv_CmdSetDiscardRectangleEXT(
2783         VkCommandBuffer                             commandBuffer,
2784         uint32_t                                    firstDiscardRectangle,
2785         uint32_t                                    discardRectangleCount,
2786         const VkRect2D*                             pDiscardRectangles)
2787 {
2788         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2789         struct radv_cmd_state *state = &cmd_buffer->state;
2790         MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2791
2792         assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2793         assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2794
2795         typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2796                      pDiscardRectangles, discardRectangleCount);
2797
2798         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2799 }
2800
2801 void radv_CmdExecuteCommands(
2802         VkCommandBuffer                             commandBuffer,
2803         uint32_t                                    commandBufferCount,
2804         const VkCommandBuffer*                      pCmdBuffers)
2805 {
2806         RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2807
2808         assert(commandBufferCount > 0);
2809
2810         /* Emit pending flushes on primary prior to executing secondary */
2811         si_emit_cache_flush(primary);
2812
2813         for (uint32_t i = 0; i < commandBufferCount; i++) {
2814                 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2815
2816                 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2817                                                     secondary->scratch_size_needed);
2818                 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2819                                                             secondary->compute_scratch_size_needed);
2820
2821                 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2822                         primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2823                 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2824                         primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2825                 if (secondary->tess_rings_needed)
2826                         primary->tess_rings_needed = true;
2827                 if (secondary->sample_positions_needed)
2828                         primary->sample_positions_needed = true;
2829
2830                 if (secondary->ring_offsets_idx != -1) {
2831                         if (primary->ring_offsets_idx == -1)
2832                                 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2833                         else
2834                                 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2835                 }
2836                 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2837
2838
2839                 /* When the secondary command buffer is compute only we don't
2840                  * need to re-emit the current graphics pipeline.
2841                  */
2842                 if (secondary->state.emitted_pipeline) {
2843                         primary->state.emitted_pipeline =
2844                                 secondary->state.emitted_pipeline;
2845                 }
2846
2847                 /* When the secondary command buffer is graphics only we don't
2848                  * need to re-emit the current compute pipeline.
2849                  */
2850                 if (secondary->state.emitted_compute_pipeline) {
2851                         primary->state.emitted_compute_pipeline =
2852                                 secondary->state.emitted_compute_pipeline;
2853                 }
2854
2855                 /* Only re-emit the draw packets when needed. */
2856                 if (secondary->state.last_primitive_reset_en != -1) {
2857                         primary->state.last_primitive_reset_en =
2858                                 secondary->state.last_primitive_reset_en;
2859                 }
2860
2861                 if (secondary->state.last_primitive_reset_index) {
2862                         primary->state.last_primitive_reset_index =
2863                                 secondary->state.last_primitive_reset_index;
2864                 }
2865
2866                 if (secondary->state.last_ia_multi_vgt_param) {
2867                         primary->state.last_ia_multi_vgt_param =
2868                                 secondary->state.last_ia_multi_vgt_param;
2869                 }
2870
2871                 primary->state.last_first_instance = secondary->state.last_first_instance;
2872                 primary->state.last_num_instances = secondary->state.last_num_instances;
2873                 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2874
2875                 if (secondary->state.last_index_type != -1) {
2876                         primary->state.last_index_type =
2877                                 secondary->state.last_index_type;
2878                 }
2879         }
2880
2881         /* After executing commands from secondary buffers we have to dirty
2882          * some states.
2883          */
2884         primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2885                                 RADV_CMD_DIRTY_INDEX_BUFFER |
2886                                 RADV_CMD_DIRTY_DYNAMIC_ALL;
2887         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2888         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2889 }
2890
2891 VkResult radv_CreateCommandPool(
2892         VkDevice                                    _device,
2893         const VkCommandPoolCreateInfo*              pCreateInfo,
2894         const VkAllocationCallbacks*                pAllocator,
2895         VkCommandPool*                              pCmdPool)
2896 {
2897         RADV_FROM_HANDLE(radv_device, device, _device);
2898         struct radv_cmd_pool *pool;
2899
2900         pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2901                            VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2902         if (pool == NULL)
2903                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2904
2905         if (pAllocator)
2906                 pool->alloc = *pAllocator;
2907         else
2908                 pool->alloc = device->alloc;
2909
2910         list_inithead(&pool->cmd_buffers);
2911         list_inithead(&pool->free_cmd_buffers);
2912
2913         pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2914
2915         *pCmdPool = radv_cmd_pool_to_handle(pool);
2916
2917         return VK_SUCCESS;
2918
2919 }
2920
2921 void radv_DestroyCommandPool(
2922         VkDevice                                    _device,
2923         VkCommandPool                               commandPool,
2924         const VkAllocationCallbacks*                pAllocator)
2925 {
2926         RADV_FROM_HANDLE(radv_device, device, _device);
2927         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2928
2929         if (!pool)
2930                 return;
2931
2932         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2933                                  &pool->cmd_buffers, pool_link) {
2934                 radv_cmd_buffer_destroy(cmd_buffer);
2935         }
2936
2937         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2938                                  &pool->free_cmd_buffers, pool_link) {
2939                 radv_cmd_buffer_destroy(cmd_buffer);
2940         }
2941
2942         vk_free2(&device->alloc, pAllocator, pool);
2943 }
2944
2945 VkResult radv_ResetCommandPool(
2946         VkDevice                                    device,
2947         VkCommandPool                               commandPool,
2948         VkCommandPoolResetFlags                     flags)
2949 {
2950         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2951         VkResult result;
2952
2953         list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2954                             &pool->cmd_buffers, pool_link) {
2955                 result = radv_reset_cmd_buffer(cmd_buffer);
2956                 if (result != VK_SUCCESS)
2957                         return result;
2958         }
2959
2960         return VK_SUCCESS;
2961 }
2962
2963 void radv_TrimCommandPool(
2964     VkDevice                                    device,
2965     VkCommandPool                               commandPool,
2966     VkCommandPoolTrimFlagsKHR                   flags)
2967 {
2968         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2969
2970         if (!pool)
2971                 return;
2972
2973         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2974                                  &pool->free_cmd_buffers, pool_link) {
2975                 radv_cmd_buffer_destroy(cmd_buffer);
2976         }
2977 }
2978
2979 void radv_CmdBeginRenderPass(
2980         VkCommandBuffer                             commandBuffer,
2981         const VkRenderPassBeginInfo*                pRenderPassBegin,
2982         VkSubpassContents                           contents)
2983 {
2984         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2985         RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2986         RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2987
2988         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2989                                                            cmd_buffer->cs, 2048);
2990         MAYBE_UNUSED VkResult result;
2991
2992         cmd_buffer->state.framebuffer = framebuffer;
2993         cmd_buffer->state.pass = pass;
2994         cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2995
2996         result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2997         if (result != VK_SUCCESS)
2998                 return;
2999
3000         radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3001         assert(cmd_buffer->cs->cdw <= cdw_max);
3002
3003         radv_cmd_buffer_clear_subpass(cmd_buffer);
3004 }
3005
3006 void radv_CmdNextSubpass(
3007     VkCommandBuffer                             commandBuffer,
3008     VkSubpassContents                           contents)
3009 {
3010         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3011
3012         radv_cmd_buffer_resolve_subpass(cmd_buffer);
3013
3014         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3015                                               2048);
3016
3017         radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3018         radv_cmd_buffer_clear_subpass(cmd_buffer);
3019 }
3020
3021 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3022 {
3023         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3024         for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3025                 if (!pipeline->shaders[stage])
3026                         continue;
3027                 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3028                 if (loc->sgpr_idx == -1)
3029                         continue;
3030                 uint32_t base_reg = pipeline->user_data_0[stage];
3031                 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3032
3033         }
3034         if (pipeline->gs_copy_shader) {
3035                 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3036                 if (loc->sgpr_idx != -1) {
3037                         uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3038                         radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3039                 }
3040         }
3041 }
3042
3043 static void
3044 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3045                          uint32_t vertex_count)
3046 {
3047         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3048         radeon_emit(cmd_buffer->cs, vertex_count);
3049         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3050                                     S_0287F0_USE_OPAQUE(0));
3051 }
3052
3053 static void
3054 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3055                                  uint64_t index_va,
3056                                  uint32_t index_count)
3057 {
3058         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3059         radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3060         radeon_emit(cmd_buffer->cs, index_va);
3061         radeon_emit(cmd_buffer->cs, index_va >> 32);
3062         radeon_emit(cmd_buffer->cs, index_count);
3063         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3064 }
3065
3066 static void
3067 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3068                                   bool indexed,
3069                                   uint32_t draw_count,
3070                                   uint64_t count_va,
3071                                   uint32_t stride)
3072 {
3073         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3074         unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3075                                       : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3076         bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3077         uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3078         assert(base_reg);
3079
3080         /* just reset draw state for vertex data */
3081         cmd_buffer->state.last_first_instance = -1;
3082         cmd_buffer->state.last_num_instances = -1;
3083         cmd_buffer->state.last_vertex_offset = -1;
3084
3085         if (draw_count == 1 && !count_va && !draw_id_enable) {
3086                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3087                                      PKT3_DRAW_INDIRECT, 3, false));
3088                 radeon_emit(cs, 0);
3089                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3090                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3091                 radeon_emit(cs, di_src_sel);
3092         } else {
3093                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3094                                      PKT3_DRAW_INDIRECT_MULTI,
3095                                      8, false));
3096                 radeon_emit(cs, 0);
3097                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3098                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3099                 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3100                             S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3101                             S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3102                 radeon_emit(cs, draw_count); /* count */
3103                 radeon_emit(cs, count_va); /* count_addr */
3104                 radeon_emit(cs, count_va >> 32);
3105                 radeon_emit(cs, stride); /* stride */
3106                 radeon_emit(cs, di_src_sel);
3107         }
3108 }
3109
3110 struct radv_draw_info {
3111         /**
3112          * Number of vertices.
3113          */
3114         uint32_t count;
3115
3116         /**
3117          * Index of the first vertex.
3118          */
3119         int32_t vertex_offset;
3120
3121         /**
3122          * First instance id.
3123          */
3124         uint32_t first_instance;
3125
3126         /**
3127          * Number of instances.
3128          */
3129         uint32_t instance_count;
3130
3131         /**
3132          * First index (indexed draws only).
3133          */
3134         uint32_t first_index;
3135
3136         /**
3137          * Whether it's an indexed draw.
3138          */
3139         bool indexed;
3140
3141         /**
3142          * Indirect draw parameters resource.
3143          */
3144         struct radv_buffer *indirect;
3145         uint64_t indirect_offset;
3146         uint32_t stride;
3147
3148         /**
3149          * Draw count parameters resource.
3150          */
3151         struct radv_buffer *count_buffer;
3152         uint64_t count_buffer_offset;
3153 };
3154
3155 static void
3156 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3157                        const struct radv_draw_info *info)
3158 {
3159         struct radv_cmd_state *state = &cmd_buffer->state;
3160         struct radeon_winsys *ws = cmd_buffer->device->ws;
3161         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3162
3163         if (info->indirect) {
3164                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3165                 uint64_t count_va = 0;
3166
3167                 va += info->indirect->offset + info->indirect_offset;
3168
3169                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3170
3171                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3172                 radeon_emit(cs, 1);
3173                 radeon_emit(cs, va);
3174                 radeon_emit(cs, va >> 32);
3175
3176                 if (info->count_buffer) {
3177                         count_va = radv_buffer_get_va(info->count_buffer->bo);
3178                         count_va += info->count_buffer->offset +
3179                                     info->count_buffer_offset;
3180
3181                         radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3182                 }
3183
3184                 if (!state->subpass->view_mask) {
3185                         radv_cs_emit_indirect_draw_packet(cmd_buffer,
3186                                                           info->indexed,
3187                                                           info->count,
3188                                                           count_va,
3189                                                           info->stride);
3190                 } else {
3191                         unsigned i;
3192                         for_each_bit(i, state->subpass->view_mask) {
3193                                 radv_emit_view_index(cmd_buffer, i);
3194
3195                                 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3196                                                                   info->indexed,
3197                                                                   info->count,
3198                                                                   count_va,
3199                                                                   info->stride);
3200                         }
3201                 }
3202         } else {
3203                 assert(state->pipeline->graphics.vtx_base_sgpr);
3204
3205                 if (info->vertex_offset != state->last_vertex_offset ||
3206                     info->first_instance != state->last_first_instance) {
3207                         radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3208                                               state->pipeline->graphics.vtx_emit_num);
3209
3210                         radeon_emit(cs, info->vertex_offset);
3211                         radeon_emit(cs, info->first_instance);
3212                         if (state->pipeline->graphics.vtx_emit_num == 3)
3213                                 radeon_emit(cs, 0);
3214                         state->last_first_instance = info->first_instance;
3215                         state->last_vertex_offset = info->vertex_offset;
3216                 }
3217
3218                 if (state->last_num_instances != info->instance_count) {
3219                         radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3220                         radeon_emit(cs, info->instance_count);
3221                         state->last_num_instances = info->instance_count;
3222                 }
3223
3224                 if (info->indexed) {
3225                         int index_size = state->index_type ? 4 : 2;
3226                         uint64_t index_va;
3227
3228                         index_va = state->index_va;
3229                         index_va += info->first_index * index_size;
3230
3231                         if (!state->subpass->view_mask) {
3232                                 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3233                                                                  index_va,
3234                                                                  info->count);
3235                         } else {
3236                                 unsigned i;
3237                                 for_each_bit(i, state->subpass->view_mask) {
3238                                         radv_emit_view_index(cmd_buffer, i);
3239
3240                                         radv_cs_emit_draw_indexed_packet(cmd_buffer,
3241                                                                          index_va,
3242                                                                          info->count);
3243                                 }
3244                         }
3245                 } else {
3246                         if (!state->subpass->view_mask) {
3247                                 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3248                         } else {
3249                                 unsigned i;
3250                                 for_each_bit(i, state->subpass->view_mask) {
3251                                         radv_emit_view_index(cmd_buffer, i);
3252
3253                                         radv_cs_emit_draw_packet(cmd_buffer,
3254                                                                  info->count);
3255                                 }
3256                         }
3257                 }
3258         }
3259 }
3260
3261 /*
3262  * Vega and raven have a bug which triggers if there are multiple context
3263  * register contexts active at the same time with different scissor values.
3264  *
3265  * There are two possible workarounds:
3266  * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3267  *    there is only ever 1 active set of scissor values at the same time.
3268  *
3269  * 2) Whenever the hardware switches contexts we have to set the scissor
3270  *    registers again even if it is a noop. That way the new context gets
3271  *    the correct scissor values.
3272  *
3273  * This implements option 2. radv_need_late_scissor_emission needs to
3274  * return true on affected HW if radv_emit_all_graphics_states sets
3275  * any context registers.
3276  */
3277 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3278                                             bool indexed_draw)
3279 {
3280         struct radv_cmd_state *state = &cmd_buffer->state;
3281
3282         if (!cmd_buffer->device->physical_device->has_scissor_bug)
3283                 return false;
3284
3285         /* Assume all state changes except  these two can imply context rolls. */
3286         if (cmd_buffer->state.dirty & ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3287                                         RADV_CMD_DIRTY_VERTEX_BUFFER |
3288                                         RADV_CMD_DIRTY_PIPELINE))
3289                 return true;
3290
3291         if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3292                 return true;
3293
3294         if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3295             (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3296                 return true;
3297
3298         return false;
3299 }
3300
3301 static void
3302 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3303                               const struct radv_draw_info *info)
3304 {
3305         bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3306
3307         if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3308             cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3309                 radv_emit_rbplus_state(cmd_buffer);
3310
3311         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3312                 radv_emit_graphics_pipeline(cmd_buffer);
3313
3314         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3315                 radv_emit_framebuffer_state(cmd_buffer);
3316
3317         if (info->indexed) {
3318                 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3319                         radv_emit_index_buffer(cmd_buffer);
3320         } else {
3321                 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3322                  * so the state must be re-emitted before the next indexed
3323                  * draw.
3324                  */
3325                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3326                         cmd_buffer->state.last_index_type = -1;
3327                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3328                 }
3329         }
3330
3331         radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3332
3333         radv_emit_draw_registers(cmd_buffer, info->indexed,
3334                                  info->instance_count > 1, info->indirect,
3335                                  info->indirect ? 0 : info->count);
3336
3337         if (late_scissor_emission)
3338                 radv_emit_scissor(cmd_buffer);
3339 }
3340
3341 static void
3342 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3343           const struct radv_draw_info *info)
3344 {
3345         bool has_prefetch =
3346                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3347         bool pipeline_is_dirty =
3348                 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3349                 cmd_buffer->state.pipeline &&
3350                 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3351
3352         MAYBE_UNUSED unsigned cdw_max =
3353                 radeon_check_space(cmd_buffer->device->ws,
3354                                    cmd_buffer->cs, 4096);
3355
3356         /* Use optimal packet order based on whether we need to sync the
3357          * pipeline.
3358          */
3359         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3360                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3361                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3362                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3363                 /* If we have to wait for idle, set all states first, so that
3364                  * all SET packets are processed in parallel with previous draw
3365                  * calls. Then upload descriptors, set shader pointers, and
3366                  * draw, and prefetch at the end. This ensures that the time
3367                  * the CUs are idle is very short. (there are only SET_SH
3368                  * packets between the wait and the draw)
3369                  */
3370                 radv_emit_all_graphics_states(cmd_buffer, info);
3371                 si_emit_cache_flush(cmd_buffer);
3372                 /* <-- CUs are idle here --> */
3373
3374                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3375
3376                 radv_emit_draw_packets(cmd_buffer, info);
3377                 /* <-- CUs are busy here --> */
3378
3379                 /* Start prefetches after the draw has been started. Both will
3380                  * run in parallel, but starting the draw first is more
3381                  * important.
3382                  */
3383                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3384                         radv_emit_prefetch_L2(cmd_buffer,
3385                                               cmd_buffer->state.pipeline, false);
3386                 }
3387         } else {
3388                 /* If we don't wait for idle, start prefetches first, then set
3389                  * states, and draw at the end.
3390                  */
3391                 si_emit_cache_flush(cmd_buffer);
3392
3393                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3394                         /* Only prefetch the vertex shader and VBO descriptors
3395                          * in order to start the draw as soon as possible.
3396                          */
3397                         radv_emit_prefetch_L2(cmd_buffer,
3398                                               cmd_buffer->state.pipeline, true);
3399                 }
3400
3401                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3402
3403                 radv_emit_all_graphics_states(cmd_buffer, info);
3404                 radv_emit_draw_packets(cmd_buffer, info);
3405
3406                 /* Prefetch the remaining shaders after the draw has been
3407                  * started.
3408                  */
3409                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3410                         radv_emit_prefetch_L2(cmd_buffer,
3411                                               cmd_buffer->state.pipeline, false);
3412                 }
3413         }
3414
3415         assert(cmd_buffer->cs->cdw <= cdw_max);
3416         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3417 }
3418
3419 void radv_CmdDraw(
3420         VkCommandBuffer                             commandBuffer,
3421         uint32_t                                    vertexCount,
3422         uint32_t                                    instanceCount,
3423         uint32_t                                    firstVertex,
3424         uint32_t                                    firstInstance)
3425 {
3426         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3427         struct radv_draw_info info = {};
3428
3429         info.count = vertexCount;
3430         info.instance_count = instanceCount;
3431         info.first_instance = firstInstance;
3432         info.vertex_offset = firstVertex;
3433
3434         radv_draw(cmd_buffer, &info);
3435 }
3436
3437 void radv_CmdDrawIndexed(
3438         VkCommandBuffer                             commandBuffer,
3439         uint32_t                                    indexCount,
3440         uint32_t                                    instanceCount,
3441         uint32_t                                    firstIndex,
3442         int32_t                                     vertexOffset,
3443         uint32_t                                    firstInstance)
3444 {
3445         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3446         struct radv_draw_info info = {};
3447
3448         info.indexed = true;
3449         info.count = indexCount;
3450         info.instance_count = instanceCount;
3451         info.first_index = firstIndex;
3452         info.vertex_offset = vertexOffset;
3453         info.first_instance = firstInstance;
3454
3455         radv_draw(cmd_buffer, &info);
3456 }
3457
3458 void radv_CmdDrawIndirect(
3459         VkCommandBuffer                             commandBuffer,
3460         VkBuffer                                    _buffer,
3461         VkDeviceSize                                offset,
3462         uint32_t                                    drawCount,
3463         uint32_t                                    stride)
3464 {
3465         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3466         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3467         struct radv_draw_info info = {};
3468
3469         info.count = drawCount;
3470         info.indirect = buffer;
3471         info.indirect_offset = offset;
3472         info.stride = stride;
3473
3474         radv_draw(cmd_buffer, &info);
3475 }
3476
3477 void radv_CmdDrawIndexedIndirect(
3478         VkCommandBuffer                             commandBuffer,
3479         VkBuffer                                    _buffer,
3480         VkDeviceSize                                offset,
3481         uint32_t                                    drawCount,
3482         uint32_t                                    stride)
3483 {
3484         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3485         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3486         struct radv_draw_info info = {};
3487
3488         info.indexed = true;
3489         info.count = drawCount;
3490         info.indirect = buffer;
3491         info.indirect_offset = offset;
3492         info.stride = stride;
3493
3494         radv_draw(cmd_buffer, &info);
3495 }
3496
3497 void radv_CmdDrawIndirectCountAMD(
3498         VkCommandBuffer                             commandBuffer,
3499         VkBuffer                                    _buffer,
3500         VkDeviceSize                                offset,
3501         VkBuffer                                    _countBuffer,
3502         VkDeviceSize                                countBufferOffset,
3503         uint32_t                                    maxDrawCount,
3504         uint32_t                                    stride)
3505 {
3506         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3507         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3508         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3509         struct radv_draw_info info = {};
3510
3511         info.count = maxDrawCount;
3512         info.indirect = buffer;
3513         info.indirect_offset = offset;
3514         info.count_buffer = count_buffer;
3515         info.count_buffer_offset = countBufferOffset;
3516         info.stride = stride;
3517
3518         radv_draw(cmd_buffer, &info);
3519 }
3520
3521 void radv_CmdDrawIndexedIndirectCountAMD(
3522         VkCommandBuffer                             commandBuffer,
3523         VkBuffer                                    _buffer,
3524         VkDeviceSize                                offset,
3525         VkBuffer                                    _countBuffer,
3526         VkDeviceSize                                countBufferOffset,
3527         uint32_t                                    maxDrawCount,
3528         uint32_t                                    stride)
3529 {
3530         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3531         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3532         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3533         struct radv_draw_info info = {};
3534
3535         info.indexed = true;
3536         info.count = maxDrawCount;
3537         info.indirect = buffer;
3538         info.indirect_offset = offset;
3539         info.count_buffer = count_buffer;
3540         info.count_buffer_offset = countBufferOffset;
3541         info.stride = stride;
3542
3543         radv_draw(cmd_buffer, &info);
3544 }
3545
3546 void radv_CmdDrawIndirectCountKHR(
3547         VkCommandBuffer                             commandBuffer,
3548         VkBuffer                                    _buffer,
3549         VkDeviceSize                                offset,
3550         VkBuffer                                    _countBuffer,
3551         VkDeviceSize                                countBufferOffset,
3552         uint32_t                                    maxDrawCount,
3553         uint32_t                                    stride)
3554 {
3555         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3556         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3557         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3558         struct radv_draw_info info = {};
3559
3560         info.count = maxDrawCount;
3561         info.indirect = buffer;
3562         info.indirect_offset = offset;
3563         info.count_buffer = count_buffer;
3564         info.count_buffer_offset = countBufferOffset;
3565         info.stride = stride;
3566
3567         radv_draw(cmd_buffer, &info);
3568 }
3569
3570 void radv_CmdDrawIndexedIndirectCountKHR(
3571         VkCommandBuffer                             commandBuffer,
3572         VkBuffer                                    _buffer,
3573         VkDeviceSize                                offset,
3574         VkBuffer                                    _countBuffer,
3575         VkDeviceSize                                countBufferOffset,
3576         uint32_t                                    maxDrawCount,
3577         uint32_t                                    stride)
3578 {
3579         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3580         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3581         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3582         struct radv_draw_info info = {};
3583
3584         info.indexed = true;
3585         info.count = maxDrawCount;
3586         info.indirect = buffer;
3587         info.indirect_offset = offset;
3588         info.count_buffer = count_buffer;
3589         info.count_buffer_offset = countBufferOffset;
3590         info.stride = stride;
3591
3592         radv_draw(cmd_buffer, &info);
3593 }
3594
3595 struct radv_dispatch_info {
3596         /**
3597          * Determine the layout of the grid (in block units) to be used.
3598          */
3599         uint32_t blocks[3];
3600
3601         /**
3602          * A starting offset for the grid. If unaligned is set, the offset
3603          * must still be aligned.
3604          */
3605         uint32_t offsets[3];
3606         /**
3607          * Whether it's an unaligned compute dispatch.
3608          */
3609         bool unaligned;
3610
3611         /**
3612          * Indirect compute parameters resource.
3613          */
3614         struct radv_buffer *indirect;
3615         uint64_t indirect_offset;
3616 };
3617
3618 static void
3619 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3620                            const struct radv_dispatch_info *info)
3621 {
3622         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3623         struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3624         unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3625         struct radeon_winsys *ws = cmd_buffer->device->ws;
3626         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3627         struct radv_userdata_info *loc;
3628
3629         loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3630                                     AC_UD_CS_GRID_SIZE);
3631
3632         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3633
3634         if (info->indirect) {
3635                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3636
3637                 va += info->indirect->offset + info->indirect_offset;
3638
3639                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3640
3641                 if (loc->sgpr_idx != -1) {
3642                         for (unsigned i = 0; i < 3; ++i) {
3643                                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3644                                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3645                                                 COPY_DATA_DST_SEL(COPY_DATA_REG));
3646                                 radeon_emit(cs, (va +  4 * i));
3647                                 radeon_emit(cs, (va + 4 * i) >> 32);
3648                                 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3649                                                  + loc->sgpr_idx * 4) >> 2) + i);
3650                                 radeon_emit(cs, 0);
3651                         }
3652                 }
3653
3654                 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3655                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3656                                         PKT3_SHADER_TYPE_S(1));
3657                         radeon_emit(cs, va);
3658                         radeon_emit(cs, va >> 32);
3659                         radeon_emit(cs, dispatch_initiator);
3660                 } else {
3661                         radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3662                                         PKT3_SHADER_TYPE_S(1));
3663                         radeon_emit(cs, 1);
3664                         radeon_emit(cs, va);
3665                         radeon_emit(cs, va >> 32);
3666
3667                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3668                                         PKT3_SHADER_TYPE_S(1));
3669                         radeon_emit(cs, 0);
3670                         radeon_emit(cs, dispatch_initiator);
3671                 }
3672         } else {
3673                 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3674                 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3675
3676                 if (info->unaligned) {
3677                         unsigned *cs_block_size = compute_shader->info.cs.block_size;
3678                         unsigned remainder[3];
3679
3680                         /* If aligned, these should be an entire block size,
3681                          * not 0.
3682                          */
3683                         remainder[0] = blocks[0] + cs_block_size[0] -
3684                                        align_u32_npot(blocks[0], cs_block_size[0]);
3685                         remainder[1] = blocks[1] + cs_block_size[1] -
3686                                        align_u32_npot(blocks[1], cs_block_size[1]);
3687                         remainder[2] = blocks[2] + cs_block_size[2] -
3688                                        align_u32_npot(blocks[2], cs_block_size[2]);
3689
3690                         blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3691                         blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3692                         blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3693
3694                         for(unsigned i = 0; i < 3; ++i) {
3695                                 assert(offsets[i] % cs_block_size[i] == 0);
3696                                 offsets[i] /= cs_block_size[i];
3697                         }
3698
3699                         radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3700                         radeon_emit(cs,
3701                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3702                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3703                         radeon_emit(cs,
3704                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3705                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3706                         radeon_emit(cs,
3707                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3708                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3709
3710                         dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3711                 }
3712
3713                 if (loc->sgpr_idx != -1) {
3714                         assert(!loc->indirect);
3715                         assert(loc->num_sgprs == 3);
3716
3717                         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3718                                                   loc->sgpr_idx * 4, 3);
3719                         radeon_emit(cs, blocks[0]);
3720                         radeon_emit(cs, blocks[1]);
3721                         radeon_emit(cs, blocks[2]);
3722                 }
3723
3724                 if (offsets[0] || offsets[1] || offsets[2]) {
3725                         radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3726                         radeon_emit(cs, offsets[0]);
3727                         radeon_emit(cs, offsets[1]);
3728                         radeon_emit(cs, offsets[2]);
3729
3730                         /* The blocks in the packet are not counts but end values. */
3731                         for (unsigned i = 0; i < 3; ++i)
3732                                 blocks[i] += offsets[i];
3733                 } else {
3734                         dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3735                 }
3736
3737                 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3738                                 PKT3_SHADER_TYPE_S(1));
3739                 radeon_emit(cs, blocks[0]);
3740                 radeon_emit(cs, blocks[1]);
3741                 radeon_emit(cs, blocks[2]);
3742                 radeon_emit(cs, dispatch_initiator);
3743         }
3744
3745         assert(cmd_buffer->cs->cdw <= cdw_max);
3746 }
3747
3748 static void
3749 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3750 {
3751         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3752         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3753 }
3754
3755 static void
3756 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3757               const struct radv_dispatch_info *info)
3758 {
3759         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3760         bool has_prefetch =
3761                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3762         bool pipeline_is_dirty = pipeline &&
3763                                  pipeline != cmd_buffer->state.emitted_compute_pipeline;
3764
3765         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3766                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3767                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3768                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3769                 /* If we have to wait for idle, set all states first, so that
3770                  * all SET packets are processed in parallel with previous draw
3771                  * calls. Then upload descriptors, set shader pointers, and
3772                  * dispatch, and prefetch at the end. This ensures that the
3773                  * time the CUs are idle is very short. (there are only SET_SH
3774                  * packets between the wait and the draw)
3775                  */
3776                 radv_emit_compute_pipeline(cmd_buffer);
3777                 si_emit_cache_flush(cmd_buffer);
3778                 /* <-- CUs are idle here --> */
3779
3780                 radv_upload_compute_shader_descriptors(cmd_buffer);
3781
3782                 radv_emit_dispatch_packets(cmd_buffer, info);
3783                 /* <-- CUs are busy here --> */
3784
3785                 /* Start prefetches after the dispatch has been started. Both
3786                  * will run in parallel, but starting the dispatch first is
3787                  * more important.
3788                  */
3789                 if (has_prefetch && pipeline_is_dirty) {
3790                         radv_emit_shader_prefetch(cmd_buffer,
3791                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3792                 }
3793         } else {
3794                 /* If we don't wait for idle, start prefetches first, then set
3795                  * states, and dispatch at the end.
3796                  */
3797                 si_emit_cache_flush(cmd_buffer);
3798
3799                 if (has_prefetch && pipeline_is_dirty) {
3800                         radv_emit_shader_prefetch(cmd_buffer,
3801                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3802                 }
3803
3804                 radv_upload_compute_shader_descriptors(cmd_buffer);
3805
3806                 radv_emit_compute_pipeline(cmd_buffer);
3807                 radv_emit_dispatch_packets(cmd_buffer, info);
3808         }
3809
3810         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3811 }
3812
3813 void radv_CmdDispatchBase(
3814         VkCommandBuffer                             commandBuffer,
3815         uint32_t                                    base_x,
3816         uint32_t                                    base_y,
3817         uint32_t                                    base_z,
3818         uint32_t                                    x,
3819         uint32_t                                    y,
3820         uint32_t                                    z)
3821 {
3822         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3823         struct radv_dispatch_info info = {};
3824
3825         info.blocks[0] = x;
3826         info.blocks[1] = y;
3827         info.blocks[2] = z;
3828
3829         info.offsets[0] = base_x;
3830         info.offsets[1] = base_y;
3831         info.offsets[2] = base_z;
3832         radv_dispatch(cmd_buffer, &info);
3833 }
3834
3835 void radv_CmdDispatch(
3836         VkCommandBuffer                             commandBuffer,
3837         uint32_t                                    x,
3838         uint32_t                                    y,
3839         uint32_t                                    z)
3840 {
3841         radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3842 }
3843
3844 void radv_CmdDispatchIndirect(
3845         VkCommandBuffer                             commandBuffer,
3846         VkBuffer                                    _buffer,
3847         VkDeviceSize                                offset)
3848 {
3849         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3850         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3851         struct radv_dispatch_info info = {};
3852
3853         info.indirect = buffer;
3854         info.indirect_offset = offset;
3855
3856         radv_dispatch(cmd_buffer, &info);
3857 }
3858
3859 void radv_unaligned_dispatch(
3860         struct radv_cmd_buffer                      *cmd_buffer,
3861         uint32_t                                    x,
3862         uint32_t                                    y,
3863         uint32_t                                    z)
3864 {
3865         struct radv_dispatch_info info = {};
3866
3867         info.blocks[0] = x;
3868         info.blocks[1] = y;
3869         info.blocks[2] = z;
3870         info.unaligned = 1;
3871
3872         radv_dispatch(cmd_buffer, &info);
3873 }
3874
3875 void radv_CmdEndRenderPass(
3876         VkCommandBuffer                             commandBuffer)
3877 {
3878         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3879
3880         radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3881
3882         radv_cmd_buffer_resolve_subpass(cmd_buffer);
3883
3884         for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3885                 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3886                 radv_handle_subpass_image_transition(cmd_buffer,
3887                                       (VkAttachmentReference){i, layout});
3888         }
3889
3890         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3891
3892         cmd_buffer->state.pass = NULL;
3893         cmd_buffer->state.subpass = NULL;
3894         cmd_buffer->state.attachments = NULL;
3895         cmd_buffer->state.framebuffer = NULL;
3896 }
3897
3898 /*
3899  * For HTILE we have the following interesting clear words:
3900  *   0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3901  *   0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3902  *   0xfffffff0: Clear depth to 1.0
3903  *   0x00000000: Clear depth to 0.0
3904  */
3905 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3906                                   struct radv_image *image,
3907                                   const VkImageSubresourceRange *range,
3908                                   uint32_t clear_word)
3909 {
3910         assert(range->baseMipLevel == 0);
3911         assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3912         unsigned layer_count = radv_get_layerCount(image, range);
3913         uint64_t size = image->surface.htile_slice_size * layer_count;
3914         uint64_t offset = image->offset + image->htile_offset +
3915                           image->surface.htile_slice_size * range->baseArrayLayer;
3916         struct radv_cmd_state *state = &cmd_buffer->state;
3917
3918         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3919                              RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3920
3921         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3922                                               size, clear_word);
3923
3924         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3925
3926         /* Initialize the depth clear registers and update the ZRANGE_PRECISION
3927          * value for the TC-compat bug (because ZRANGE_PRECISION is 1 by
3928          * default). This is only needed whean clearing Z to 0.0f.
3929          */
3930         if (radv_image_is_tc_compat_htile(image) && clear_word == 0) {
3931                 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
3932                 VkClearDepthStencilValue value = {};
3933
3934                 if (vk_format_is_stencil(image->vk_format))
3935                         aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3936
3937                 radv_set_depth_clear_regs(cmd_buffer, image, value, aspects);
3938         }
3939 }
3940
3941 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3942                                                struct radv_image *image,
3943                                                VkImageLayout src_layout,
3944                                                VkImageLayout dst_layout,
3945                                                unsigned src_queue_mask,
3946                                                unsigned dst_queue_mask,
3947                                                const VkImageSubresourceRange *range,
3948                                                VkImageAspectFlags pending_clears)
3949 {
3950         if (!radv_image_has_htile(image))
3951                 return;
3952
3953         if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3954             (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3955             cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3956             cmd_buffer->state.render_area.extent.width == image->info.width &&
3957             cmd_buffer->state.render_area.extent.height == image->info.height) {
3958                 /* The clear will initialize htile. */
3959                 return;
3960         } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3961                    radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3962                 /* TODO: merge with the clear if applicable */
3963                 radv_initialize_htile(cmd_buffer, image, range, 0);
3964         } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3965                    radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3966                 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3967                 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3968         } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3969                    !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3970                 VkImageSubresourceRange local_range = *range;
3971                 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3972                 local_range.baseMipLevel = 0;
3973                 local_range.levelCount = 1;
3974
3975                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3976                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3977
3978                 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3979
3980                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3981                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3982         }
3983 }
3984
3985 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3986                                   struct radv_image *image, uint32_t value)
3987 {
3988         struct radv_cmd_state *state = &cmd_buffer->state;
3989
3990         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3991                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3992
3993         state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
3994
3995         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3996 }
3997
3998 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3999                          struct radv_image *image, uint32_t value)
4000 {
4001         struct radv_cmd_state *state = &cmd_buffer->state;
4002
4003         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4004                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4005
4006         state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4007
4008         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4009                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4010 }
4011
4012 /**
4013  * Initialize DCC/FMASK/CMASK metadata for a color image.
4014  */
4015 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4016                                            struct radv_image *image,
4017                                            VkImageLayout src_layout,
4018                                            VkImageLayout dst_layout,
4019                                            unsigned src_queue_mask,
4020                                            unsigned dst_queue_mask)
4021 {
4022         if (radv_image_has_cmask(image)) {
4023                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4024
4025                 /*  TODO: clarify this. */
4026                 if (radv_image_has_fmask(image)) {
4027                         value = 0xccccccccu;
4028                 }
4029
4030                 radv_initialise_cmask(cmd_buffer, image, value);
4031         }
4032
4033         if (radv_image_has_dcc(image)) {
4034                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4035
4036                 if (radv_layout_dcc_compressed(image, dst_layout,
4037                                                dst_queue_mask)) {
4038                         value = 0x20202020u;
4039                 }
4040
4041                 radv_initialize_dcc(cmd_buffer, image, value);
4042         }
4043 }
4044
4045 /**
4046  * Handle color image transitions for DCC/FMASK/CMASK.
4047  */
4048 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4049                                                struct radv_image *image,
4050                                                VkImageLayout src_layout,
4051                                                VkImageLayout dst_layout,
4052                                                unsigned src_queue_mask,
4053                                                unsigned dst_queue_mask,
4054                                                const VkImageSubresourceRange *range)
4055 {
4056         if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4057                 radv_init_color_image_metadata(cmd_buffer, image,
4058                                                src_layout, dst_layout,
4059                                                src_queue_mask, dst_queue_mask);
4060                 return;
4061         }
4062
4063         if (radv_image_has_dcc(image)) {
4064                 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4065                         radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4066                 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4067                            !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4068                         radv_decompress_dcc(cmd_buffer, image, range);
4069                 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4070                            !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4071                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4072                 }
4073         } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4074                 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4075                     !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4076                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4077                 }
4078         }
4079 }
4080
4081 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4082                                          struct radv_image *image,
4083                                          VkImageLayout src_layout,
4084                                          VkImageLayout dst_layout,
4085                                          uint32_t src_family,
4086                                          uint32_t dst_family,
4087                                          const VkImageSubresourceRange *range,
4088                                          VkImageAspectFlags pending_clears)
4089 {
4090         if (image->exclusive && src_family != dst_family) {
4091                 /* This is an acquire or a release operation and there will be
4092                  * a corresponding release/acquire. Do the transition in the
4093                  * most flexible queue. */
4094
4095                 assert(src_family == cmd_buffer->queue_family_index ||
4096                        dst_family == cmd_buffer->queue_family_index);
4097
4098                 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4099                         return;
4100
4101                 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4102                     (src_family == RADV_QUEUE_GENERAL ||
4103                      dst_family == RADV_QUEUE_GENERAL))
4104                         return;
4105         }
4106
4107         unsigned src_queue_mask =
4108                 radv_image_queue_family_mask(image, src_family,
4109                                              cmd_buffer->queue_family_index);
4110         unsigned dst_queue_mask =
4111                 radv_image_queue_family_mask(image, dst_family,
4112                                              cmd_buffer->queue_family_index);
4113
4114         if (vk_format_is_depth(image->vk_format)) {
4115                 radv_handle_depth_image_transition(cmd_buffer, image,
4116                                                    src_layout, dst_layout,
4117                                                    src_queue_mask, dst_queue_mask,
4118                                                    range, pending_clears);
4119         } else {
4120                 radv_handle_color_image_transition(cmd_buffer, image,
4121                                                    src_layout, dst_layout,
4122                                                    src_queue_mask, dst_queue_mask,
4123                                                    range);
4124         }
4125 }
4126
4127 void radv_CmdPipelineBarrier(
4128         VkCommandBuffer                             commandBuffer,
4129         VkPipelineStageFlags                        srcStageMask,
4130         VkPipelineStageFlags                        destStageMask,
4131         VkBool32                                    byRegion,
4132         uint32_t                                    memoryBarrierCount,
4133         const VkMemoryBarrier*                      pMemoryBarriers,
4134         uint32_t                                    bufferMemoryBarrierCount,
4135         const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
4136         uint32_t                                    imageMemoryBarrierCount,
4137         const VkImageMemoryBarrier*                 pImageMemoryBarriers)
4138 {
4139         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4140         enum radv_cmd_flush_bits src_flush_bits = 0;
4141         enum radv_cmd_flush_bits dst_flush_bits = 0;
4142
4143         for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4144                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
4145                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4146                                                         NULL);
4147         }
4148
4149         for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4150                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
4151                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4152                                                         NULL);
4153         }
4154
4155         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4156                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4157                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
4158                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4159                                                         image);
4160         }
4161
4162         radv_stage_flush(cmd_buffer, srcStageMask);
4163         cmd_buffer->state.flush_bits |= src_flush_bits;
4164
4165         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4166                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4167                 radv_handle_image_transition(cmd_buffer, image,
4168                                              pImageMemoryBarriers[i].oldLayout,
4169                                              pImageMemoryBarriers[i].newLayout,
4170                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
4171                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
4172                                              &pImageMemoryBarriers[i].subresourceRange,
4173                                              0);
4174         }
4175
4176         cmd_buffer->state.flush_bits |= dst_flush_bits;
4177 }
4178
4179
4180 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4181                         struct radv_event *event,
4182                         VkPipelineStageFlags stageMask,
4183                         unsigned value)
4184 {
4185         struct radeon_winsys_cs *cs = cmd_buffer->cs;
4186         uint64_t va = radv_buffer_get_va(event->bo);
4187
4188         radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4189
4190         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4191
4192         /* TODO: this is overkill. Probably should figure something out from
4193          * the stage mask. */
4194
4195         si_cs_emit_write_event_eop(cs,
4196                                    cmd_buffer->state.predicating,
4197                                    cmd_buffer->device->physical_device->rad_info.chip_class,
4198                                    radv_cmd_buffer_uses_mec(cmd_buffer),
4199                                    V_028A90_BOTTOM_OF_PIPE_TS, 0,
4200                                    1, va, 2, value);
4201
4202         assert(cmd_buffer->cs->cdw <= cdw_max);
4203 }
4204
4205 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4206                       VkEvent _event,
4207                       VkPipelineStageFlags stageMask)
4208 {
4209         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4210         RADV_FROM_HANDLE(radv_event, event, _event);
4211
4212         write_event(cmd_buffer, event, stageMask, 1);
4213 }
4214
4215 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4216                         VkEvent _event,
4217                         VkPipelineStageFlags stageMask)
4218 {
4219         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4220         RADV_FROM_HANDLE(radv_event, event, _event);
4221
4222         write_event(cmd_buffer, event, stageMask, 0);
4223 }
4224
4225 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4226                         uint32_t eventCount,
4227                         const VkEvent* pEvents,
4228                         VkPipelineStageFlags srcStageMask,
4229                         VkPipelineStageFlags dstStageMask,
4230                         uint32_t memoryBarrierCount,
4231                         const VkMemoryBarrier* pMemoryBarriers,
4232                         uint32_t bufferMemoryBarrierCount,
4233                         const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4234                         uint32_t imageMemoryBarrierCount,
4235                         const VkImageMemoryBarrier* pImageMemoryBarriers)
4236 {
4237         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4238         struct radeon_winsys_cs *cs = cmd_buffer->cs;
4239
4240         for (unsigned i = 0; i < eventCount; ++i) {
4241                 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4242                 uint64_t va = radv_buffer_get_va(event->bo);
4243
4244                 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4245
4246                 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4247
4248                 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4249                 assert(cmd_buffer->cs->cdw <= cdw_max);
4250         }
4251
4252
4253         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4254                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4255
4256                 radv_handle_image_transition(cmd_buffer, image,
4257                                              pImageMemoryBarriers[i].oldLayout,
4258                                              pImageMemoryBarriers[i].newLayout,
4259                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
4260                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
4261                                              &pImageMemoryBarriers[i].subresourceRange,
4262                                              0);
4263         }
4264
4265         /* TODO: figure out how to do memory barriers without waiting */
4266         cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4267                                         RADV_CMD_FLAG_INV_GLOBAL_L2 |
4268                                         RADV_CMD_FLAG_INV_VMEM_L1 |
4269                                         RADV_CMD_FLAG_INV_SMEM_L1;
4270 }
4271
4272
4273 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4274                            uint32_t deviceMask)
4275 {
4276    /* No-op */
4277 }