2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
49 const struct radv_dynamic_state default_dynamic_state = {
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
67 .stencil_compare_mask = {
71 .stencil_write_mask = {
75 .stencil_reference = {
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94 dest->discard_rectangle.count = src->discard_rectangle.count;
96 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
97 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
98 src->viewport.count * sizeof(VkViewport))) {
99 typed_memcpy(dest->viewport.viewports,
100 src->viewport.viewports,
101 src->viewport.count);
102 dest_mask |= RADV_DYNAMIC_VIEWPORT;
106 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
107 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
108 src->scissor.count * sizeof(VkRect2D))) {
109 typed_memcpy(dest->scissor.scissors,
110 src->scissor.scissors, src->scissor.count);
111 dest_mask |= RADV_DYNAMIC_SCISSOR;
115 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
116 if (dest->line_width != src->line_width) {
117 dest->line_width = src->line_width;
118 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
122 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
123 if (memcmp(&dest->depth_bias, &src->depth_bias,
124 sizeof(src->depth_bias))) {
125 dest->depth_bias = src->depth_bias;
126 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
130 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
131 if (memcmp(&dest->blend_constants, &src->blend_constants,
132 sizeof(src->blend_constants))) {
133 typed_memcpy(dest->blend_constants,
134 src->blend_constants, 4);
135 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
139 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
140 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
141 sizeof(src->depth_bounds))) {
142 dest->depth_bounds = src->depth_bounds;
143 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
147 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
148 if (memcmp(&dest->stencil_compare_mask,
149 &src->stencil_compare_mask,
150 sizeof(src->stencil_compare_mask))) {
151 dest->stencil_compare_mask = src->stencil_compare_mask;
152 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
156 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
157 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
158 sizeof(src->stencil_write_mask))) {
159 dest->stencil_write_mask = src->stencil_write_mask;
160 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
164 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
165 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
166 sizeof(src->stencil_reference))) {
167 dest->stencil_reference = src->stencil_reference;
168 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
172 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
173 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
174 src->discard_rectangle.count * sizeof(VkRect2D))) {
175 typed_memcpy(dest->discard_rectangle.rectangles,
176 src->discard_rectangle.rectangles,
177 src->discard_rectangle.count);
178 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
182 cmd_buffer->state.dirty |= dest_mask;
185 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
187 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
188 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
191 enum ring_type radv_queue_family_to_ring(int f) {
193 case RADV_QUEUE_GENERAL:
195 case RADV_QUEUE_COMPUTE:
197 case RADV_QUEUE_TRANSFER:
200 unreachable("Unknown queue family");
204 static VkResult radv_create_cmd_buffer(
205 struct radv_device * device,
206 struct radv_cmd_pool * pool,
207 VkCommandBufferLevel level,
208 VkCommandBuffer* pCommandBuffer)
210 struct radv_cmd_buffer *cmd_buffer;
212 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
213 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
214 if (cmd_buffer == NULL)
215 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
217 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
218 cmd_buffer->device = device;
219 cmd_buffer->pool = pool;
220 cmd_buffer->level = level;
223 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
224 cmd_buffer->queue_family_index = pool->queue_family_index;
227 /* Init the pool_link so we can safefly call list_del when we destroy
230 list_inithead(&cmd_buffer->pool_link);
231 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
234 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
236 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
237 if (!cmd_buffer->cs) {
238 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
239 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
242 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
244 list_inithead(&cmd_buffer->upload.list);
250 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
252 list_del(&cmd_buffer->pool_link);
254 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
255 &cmd_buffer->upload.list, list) {
256 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
261 if (cmd_buffer->upload.upload_bo)
262 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
263 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
265 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
266 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
268 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
272 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
275 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
277 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
278 &cmd_buffer->upload.list, list) {
279 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
284 cmd_buffer->push_constant_stages = 0;
285 cmd_buffer->scratch_size_needed = 0;
286 cmd_buffer->compute_scratch_size_needed = 0;
287 cmd_buffer->esgs_ring_size_needed = 0;
288 cmd_buffer->gsvs_ring_size_needed = 0;
289 cmd_buffer->tess_rings_needed = false;
290 cmd_buffer->sample_positions_needed = false;
292 if (cmd_buffer->upload.upload_bo)
293 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
294 cmd_buffer->upload.upload_bo, 8);
295 cmd_buffer->upload.offset = 0;
297 cmd_buffer->record_result = VK_SUCCESS;
299 cmd_buffer->ring_offsets_idx = -1;
301 for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
302 cmd_buffer->descriptors[i].dirty = 0;
303 cmd_buffer->descriptors[i].valid = 0;
304 cmd_buffer->descriptors[i].push_dirty = false;
307 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
309 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
310 &cmd_buffer->gfx9_fence_offset,
312 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
315 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
317 return cmd_buffer->record_result;
321 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
325 struct radeon_winsys_bo *bo;
326 struct radv_cmd_buffer_upload *upload;
327 struct radv_device *device = cmd_buffer->device;
329 new_size = MAX2(min_needed, 16 * 1024);
330 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
332 bo = device->ws->buffer_create(device->ws,
335 RADEON_FLAG_CPU_ACCESS|
336 RADEON_FLAG_NO_INTERPROCESS_SHARING);
339 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
343 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
344 if (cmd_buffer->upload.upload_bo) {
345 upload = malloc(sizeof(*upload));
348 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
349 device->ws->buffer_destroy(bo);
353 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
354 list_add(&upload->list, &cmd_buffer->upload.list);
357 cmd_buffer->upload.upload_bo = bo;
358 cmd_buffer->upload.size = new_size;
359 cmd_buffer->upload.offset = 0;
360 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
362 if (!cmd_buffer->upload.map) {
363 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
371 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
374 unsigned *out_offset,
377 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
378 if (offset + size > cmd_buffer->upload.size) {
379 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
384 *out_offset = offset;
385 *ptr = cmd_buffer->upload.map + offset;
387 cmd_buffer->upload.offset = offset + size;
392 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
393 unsigned size, unsigned alignment,
394 const void *data, unsigned *out_offset)
398 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
399 out_offset, (void **)&ptr))
403 memcpy(ptr, data, size);
409 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
410 unsigned count, const uint32_t *data)
412 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
413 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
414 S_370_WR_CONFIRM(1) |
415 S_370_ENGINE_SEL(V_370_ME));
417 radeon_emit(cs, va >> 32);
418 radeon_emit_array(cs, data, count);
421 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
423 struct radv_device *device = cmd_buffer->device;
424 struct radeon_winsys_cs *cs = cmd_buffer->cs;
427 va = radv_buffer_get_va(device->trace_bo);
428 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
431 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
433 ++cmd_buffer->state.trace_id;
434 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
435 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
436 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
437 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
441 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
442 enum radv_cmd_flush_bits flags)
444 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
445 uint32_t *ptr = NULL;
448 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
449 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
451 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
452 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
453 cmd_buffer->gfx9_fence_offset;
454 ptr = &cmd_buffer->gfx9_fence_idx;
457 /* Force wait for graphics or compute engines to be idle. */
458 si_cs_emit_cache_flush(cmd_buffer->cs,
459 cmd_buffer->device->physical_device->rad_info.chip_class,
461 radv_cmd_buffer_uses_mec(cmd_buffer),
465 if (unlikely(cmd_buffer->device->trace_bo))
466 radv_cmd_buffer_trace_emit(cmd_buffer);
470 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
471 struct radv_pipeline *pipeline, enum ring_type ring)
473 struct radv_device *device = cmd_buffer->device;
474 struct radeon_winsys_cs *cs = cmd_buffer->cs;
478 va = radv_buffer_get_va(device->trace_bo);
488 assert(!"invalid ring type");
491 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
494 data[0] = (uintptr_t)pipeline;
495 data[1] = (uintptr_t)pipeline >> 32;
497 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
498 radv_emit_write_data_packet(cs, va, 2, data);
501 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
502 VkPipelineBindPoint bind_point,
503 struct radv_descriptor_set *set,
506 struct radv_descriptor_state *descriptors_state =
507 radv_get_descriptors_state(cmd_buffer, bind_point);
509 descriptors_state->sets[idx] = set;
511 descriptors_state->valid |= (1u << idx);
513 descriptors_state->valid &= ~(1u << idx);
514 descriptors_state->dirty |= (1u << idx);
518 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
519 VkPipelineBindPoint bind_point)
521 struct radv_descriptor_state *descriptors_state =
522 radv_get_descriptors_state(cmd_buffer, bind_point);
523 struct radv_device *device = cmd_buffer->device;
524 struct radeon_winsys_cs *cs = cmd_buffer->cs;
525 uint32_t data[MAX_SETS * 2] = {};
528 va = radv_buffer_get_va(device->trace_bo) + 24;
530 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
531 cmd_buffer->cs, 4 + MAX_SETS * 2);
533 for_each_bit(i, descriptors_state->valid) {
534 struct radv_descriptor_set *set = descriptors_state->sets[i];
535 data[i * 2] = (uintptr_t)set;
536 data[i * 2 + 1] = (uintptr_t)set >> 32;
539 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
540 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
543 struct ac_userdata_info *
544 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
545 gl_shader_stage stage,
548 if (stage == MESA_SHADER_VERTEX) {
549 if (pipeline->shaders[MESA_SHADER_VERTEX])
550 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
551 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
552 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
553 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
554 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
555 } else if (stage == MESA_SHADER_TESS_EVAL) {
556 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
557 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
558 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
559 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
561 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
565 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
566 struct radv_pipeline *pipeline,
567 gl_shader_stage stage,
568 int idx, uint64_t va)
570 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
571 uint32_t base_reg = pipeline->user_data_0[stage];
572 if (loc->sgpr_idx == -1)
574 assert(loc->num_sgprs == 2);
575 assert(!loc->indirect);
576 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
577 radeon_emit(cmd_buffer->cs, va);
578 radeon_emit(cmd_buffer->cs, va >> 32);
582 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
583 struct radv_pipeline *pipeline)
585 int num_samples = pipeline->graphics.ms.num_samples;
586 struct radv_multisample_state *ms = &pipeline->graphics.ms;
587 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
589 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
590 cmd_buffer->sample_positions_needed = true;
592 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
595 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
596 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
597 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
599 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
601 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
603 /* GFX9: Flush DFSM when the AA mode changes. */
604 if (cmd_buffer->device->dfsm_allowed) {
605 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
606 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
613 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
616 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
617 si_cp_dma_prefetch(cmd_buffer, va, size);
621 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
623 if (cmd_buffer->state.vb_prefetch_dirty) {
624 radv_emit_prefetch_TC_L2_async(cmd_buffer,
625 cmd_buffer->state.vb_va,
626 cmd_buffer->state.vb_size);
627 cmd_buffer->state.vb_prefetch_dirty = false;
632 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
633 struct radv_shader_variant *shader)
635 struct radeon_winsys *ws = cmd_buffer->device->ws;
636 struct radeon_winsys_cs *cs = cmd_buffer->cs;
642 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
644 radv_cs_add_buffer(ws, cs, shader->bo, 8);
645 radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
649 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
650 struct radv_pipeline *pipeline)
652 radv_emit_shader_prefetch(cmd_buffer,
653 pipeline->shaders[MESA_SHADER_VERTEX]);
654 radv_emit_VBO_descriptors_prefetch(cmd_buffer);
655 radv_emit_shader_prefetch(cmd_buffer,
656 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
657 radv_emit_shader_prefetch(cmd_buffer,
658 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
659 radv_emit_shader_prefetch(cmd_buffer,
660 pipeline->shaders[MESA_SHADER_GEOMETRY]);
661 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
662 radv_emit_shader_prefetch(cmd_buffer,
663 pipeline->shaders[MESA_SHADER_FRAGMENT]);
667 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
669 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
671 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
674 radv_update_multisample_state(cmd_buffer, pipeline);
676 cmd_buffer->scratch_size_needed =
677 MAX2(cmd_buffer->scratch_size_needed,
678 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
680 if (!cmd_buffer->state.emitted_pipeline ||
681 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
682 pipeline->graphics.can_use_guardband)
683 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
685 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
687 if (unlikely(cmd_buffer->device->trace_bo))
688 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
690 cmd_buffer->state.emitted_pipeline = pipeline;
692 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
696 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
698 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
699 cmd_buffer->state.dynamic.viewport.viewports);
703 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
705 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
707 /* Vega10/Raven scissor bug workaround. This must be done before VPORT
708 * scissor registers are changed. There is also a more efficient but
709 * more involved alternative workaround.
711 if (cmd_buffer->device->physical_device->has_scissor_bug) {
712 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
713 si_emit_cache_flush(cmd_buffer);
715 si_write_scissors(cmd_buffer->cs, 0, count,
716 cmd_buffer->state.dynamic.scissor.scissors,
717 cmd_buffer->state.dynamic.viewport.viewports,
718 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
722 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
724 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
727 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
728 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
729 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
730 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
731 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
732 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
733 S_028214_BR_Y(rect.offset.y + rect.extent.height));
738 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
740 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
742 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
743 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
747 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
749 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
751 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
752 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
756 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
758 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
760 radeon_set_context_reg_seq(cmd_buffer->cs,
761 R_028430_DB_STENCILREFMASK, 2);
762 radeon_emit(cmd_buffer->cs,
763 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
764 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
765 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
766 S_028430_STENCILOPVAL(1));
767 radeon_emit(cmd_buffer->cs,
768 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
769 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
770 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
771 S_028434_STENCILOPVAL_BF(1));
775 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
777 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
779 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
780 fui(d->depth_bounds.min));
781 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
782 fui(d->depth_bounds.max));
786 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
788 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
789 unsigned slope = fui(d->depth_bias.slope * 16.0f);
790 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
793 radeon_set_context_reg_seq(cmd_buffer->cs,
794 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
795 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
796 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
797 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
798 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
799 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
803 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
805 struct radv_attachment_info *att,
806 struct radv_image *image,
807 VkImageLayout layout)
809 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
810 struct radv_color_buffer_info *cb = &att->cb;
811 uint32_t cb_color_info = cb->cb_color_info;
813 if (!radv_layout_dcc_compressed(image, layout,
814 radv_image_queue_family_mask(image,
815 cmd_buffer->queue_family_index,
816 cmd_buffer->queue_family_index))) {
817 cb_color_info &= C_028C70_DCC_ENABLE;
820 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
821 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
822 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
823 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
824 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
825 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
826 radeon_emit(cmd_buffer->cs, cb_color_info);
827 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
828 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
829 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
830 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
831 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
832 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
834 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
835 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
836 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
838 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
839 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
841 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
842 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
843 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
844 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
845 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
846 radeon_emit(cmd_buffer->cs, cb_color_info);
847 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
848 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
849 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
850 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
851 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
852 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
854 if (is_vi) { /* DCC BASE */
855 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
861 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
862 struct radv_ds_buffer_info *ds,
863 struct radv_image *image,
864 VkImageLayout layout)
866 uint32_t db_z_info = ds->db_z_info;
867 uint32_t db_stencil_info = ds->db_stencil_info;
869 if (!radv_layout_has_htile(image, layout,
870 radv_image_queue_family_mask(image,
871 cmd_buffer->queue_family_index,
872 cmd_buffer->queue_family_index))) {
873 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
874 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
877 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
878 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
881 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
882 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
883 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
884 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
885 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
887 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
888 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
889 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
890 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
891 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
892 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
893 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
894 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
895 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
896 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
897 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
899 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
900 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
901 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
903 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
905 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
906 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
907 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
908 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
909 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
910 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
911 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
912 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
913 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
914 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
918 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
919 ds->pa_su_poly_offset_db_fmt_cntl);
923 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
924 struct radv_image *image,
925 VkClearDepthStencilValue ds_clear_value,
926 VkImageAspectFlags aspects)
928 uint64_t va = radv_buffer_get_va(image->bo);
929 va += image->offset + image->clear_value_offset;
930 unsigned reg_offset = 0, reg_count = 0;
932 assert(image->surface.htile_size);
934 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
940 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
943 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
944 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
945 S_370_WR_CONFIRM(1) |
946 S_370_ENGINE_SEL(V_370_PFP));
947 radeon_emit(cmd_buffer->cs, va);
948 radeon_emit(cmd_buffer->cs, va >> 32);
949 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
950 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
951 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
952 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
954 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
955 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
956 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
957 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
958 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
962 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
963 struct radv_image *image)
965 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
966 uint64_t va = radv_buffer_get_va(image->bo);
967 va += image->offset + image->clear_value_offset;
968 unsigned reg_offset = 0, reg_count = 0;
970 if (!image->surface.htile_size)
973 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
979 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
982 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
983 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
984 COPY_DATA_DST_SEL(COPY_DATA_REG) |
985 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
986 radeon_emit(cmd_buffer->cs, va);
987 radeon_emit(cmd_buffer->cs, va >> 32);
988 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
989 radeon_emit(cmd_buffer->cs, 0);
991 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
992 radeon_emit(cmd_buffer->cs, 0);
996 *with DCC some colors don't require CMASK elimiation before being
997 * used as a texture. This sets a predicate value to determine if the
998 * cmask eliminate is required.
1001 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1002 struct radv_image *image,
1005 uint64_t pred_val = value;
1006 uint64_t va = radv_buffer_get_va(image->bo);
1007 va += image->offset + image->dcc_pred_offset;
1009 assert(image->surface.dcc_size);
1011 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1012 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1013 S_370_WR_CONFIRM(1) |
1014 S_370_ENGINE_SEL(V_370_PFP));
1015 radeon_emit(cmd_buffer->cs, va);
1016 radeon_emit(cmd_buffer->cs, va >> 32);
1017 radeon_emit(cmd_buffer->cs, pred_val);
1018 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1022 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1023 struct radv_image *image,
1025 uint32_t color_values[2])
1027 uint64_t va = radv_buffer_get_va(image->bo);
1028 va += image->offset + image->clear_value_offset;
1030 assert(image->cmask.size || image->surface.dcc_size);
1032 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1033 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1034 S_370_WR_CONFIRM(1) |
1035 S_370_ENGINE_SEL(V_370_PFP));
1036 radeon_emit(cmd_buffer->cs, va);
1037 radeon_emit(cmd_buffer->cs, va >> 32);
1038 radeon_emit(cmd_buffer->cs, color_values[0]);
1039 radeon_emit(cmd_buffer->cs, color_values[1]);
1041 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1042 radeon_emit(cmd_buffer->cs, color_values[0]);
1043 radeon_emit(cmd_buffer->cs, color_values[1]);
1047 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1048 struct radv_image *image,
1051 uint64_t va = radv_buffer_get_va(image->bo);
1052 va += image->offset + image->clear_value_offset;
1054 if (!image->cmask.size && !image->surface.dcc_size)
1057 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1059 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1060 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1061 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1062 COPY_DATA_COUNT_SEL);
1063 radeon_emit(cmd_buffer->cs, va);
1064 radeon_emit(cmd_buffer->cs, va >> 32);
1065 radeon_emit(cmd_buffer->cs, reg >> 2);
1066 radeon_emit(cmd_buffer->cs, 0);
1068 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1069 radeon_emit(cmd_buffer->cs, 0);
1073 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1076 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1077 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1079 /* this may happen for inherited secondary recording */
1083 for (i = 0; i < 8; ++i) {
1084 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1085 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1086 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1090 int idx = subpass->color_attachments[i].attachment;
1091 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1092 struct radv_image *image = att->attachment->image;
1093 VkImageLayout layout = subpass->color_attachments[i].layout;
1095 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1097 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1098 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1100 radv_load_color_clear_regs(cmd_buffer, image, i);
1103 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1104 int idx = subpass->depth_stencil_attachment.attachment;
1105 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1106 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1107 struct radv_image *image = att->attachment->image;
1108 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1109 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1110 cmd_buffer->queue_family_index,
1111 cmd_buffer->queue_family_index);
1112 /* We currently don't support writing decompressed HTILE */
1113 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1114 radv_layout_is_htile_compressed(image, layout, queue_mask));
1116 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1118 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1119 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1120 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1122 radv_load_depth_clear_regs(cmd_buffer, image);
1124 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1125 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1127 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1129 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1130 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1132 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1133 S_028208_BR_X(framebuffer->width) |
1134 S_028208_BR_Y(framebuffer->height));
1136 if (cmd_buffer->device->dfsm_allowed) {
1137 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1138 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1141 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1145 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1147 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1148 struct radv_cmd_state *state = &cmd_buffer->state;
1150 if (state->index_type != state->last_index_type) {
1151 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1152 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1153 2, state->index_type);
1155 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1156 radeon_emit(cs, state->index_type);
1159 state->last_index_type = state->index_type;
1162 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1163 radeon_emit(cs, state->index_va);
1164 radeon_emit(cs, state->index_va >> 32);
1166 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1167 radeon_emit(cs, state->max_index_count);
1169 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1172 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1174 uint32_t db_count_control;
1176 if(!cmd_buffer->state.active_occlusion_queries) {
1177 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1178 db_count_control = 0;
1180 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1183 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1184 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1185 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1186 S_028004_ZPASS_ENABLE(1) |
1187 S_028004_SLICE_EVEN_ENABLE(1) |
1188 S_028004_SLICE_ODD_ENABLE(1);
1190 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1191 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1195 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1199 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1201 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1203 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1204 radv_emit_viewport(cmd_buffer);
1206 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1207 radv_emit_scissor(cmd_buffer);
1209 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1210 radv_emit_line_width(cmd_buffer);
1212 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1213 radv_emit_blend_constants(cmd_buffer);
1215 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1216 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1217 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1218 radv_emit_stencil(cmd_buffer);
1220 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1221 radv_emit_depth_bounds(cmd_buffer);
1223 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1224 radv_emit_depth_bias(cmd_buffer);
1226 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1227 radv_emit_discard_rectangle(cmd_buffer);
1229 cmd_buffer->state.dirty &= ~states;
1233 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1234 struct radv_pipeline *pipeline,
1237 gl_shader_stage stage)
1239 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1240 uint32_t base_reg = pipeline->user_data_0[stage];
1242 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1245 assert(!desc_set_loc->indirect);
1246 assert(desc_set_loc->num_sgprs == 2);
1247 radeon_set_sh_reg_seq(cmd_buffer->cs,
1248 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1249 radeon_emit(cmd_buffer->cs, va);
1250 radeon_emit(cmd_buffer->cs, va >> 32);
1254 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1255 VkShaderStageFlags stages,
1256 struct radv_descriptor_set *set,
1259 if (cmd_buffer->state.pipeline) {
1260 radv_foreach_stage(stage, stages) {
1261 if (cmd_buffer->state.pipeline->shaders[stage])
1262 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1268 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1269 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1271 MESA_SHADER_COMPUTE);
1275 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1276 VkPipelineBindPoint bind_point)
1278 struct radv_descriptor_state *descriptors_state =
1279 radv_get_descriptors_state(cmd_buffer, bind_point);
1280 struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1283 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1288 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1289 set->va += bo_offset;
1293 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1294 VkPipelineBindPoint bind_point)
1296 struct radv_descriptor_state *descriptors_state =
1297 radv_get_descriptors_state(cmd_buffer, bind_point);
1298 uint32_t size = MAX_SETS * 2 * 4;
1302 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1303 256, &offset, &ptr))
1306 for (unsigned i = 0; i < MAX_SETS; i++) {
1307 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1308 uint64_t set_va = 0;
1309 struct radv_descriptor_set *set = descriptors_state->sets[i];
1310 if (descriptors_state->valid & (1u << i))
1312 uptr[0] = set_va & 0xffffffff;
1313 uptr[1] = set_va >> 32;
1316 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1319 if (cmd_buffer->state.pipeline) {
1320 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1321 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1322 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1324 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1325 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1326 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1328 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1329 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1330 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1332 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1333 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1334 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1336 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1337 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1338 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1341 if (cmd_buffer->state.compute_pipeline)
1342 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1343 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1347 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1348 VkShaderStageFlags stages)
1350 VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1351 VK_PIPELINE_BIND_POINT_COMPUTE :
1352 VK_PIPELINE_BIND_POINT_GRAPHICS;
1353 struct radv_descriptor_state *descriptors_state =
1354 radv_get_descriptors_state(cmd_buffer, bind_point);
1357 if (!descriptors_state->dirty)
1360 if (descriptors_state->push_dirty)
1361 radv_flush_push_descriptors(cmd_buffer, bind_point);
1363 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1364 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1365 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1368 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1370 MAX_SETS * MESA_SHADER_STAGES * 4);
1372 for_each_bit(i, descriptors_state->dirty) {
1373 struct radv_descriptor_set *set = descriptors_state->sets[i];
1374 if (!(descriptors_state->valid & (1u << i)))
1377 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1379 descriptors_state->dirty = 0;
1380 descriptors_state->push_dirty = false;
1382 if (unlikely(cmd_buffer->device->trace_bo))
1383 radv_save_descriptors(cmd_buffer, bind_point);
1385 assert(cmd_buffer->cs->cdw <= cdw_max);
1389 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1390 struct radv_pipeline *pipeline,
1391 VkShaderStageFlags stages)
1393 struct radv_pipeline_layout *layout = pipeline->layout;
1398 stages &= cmd_buffer->push_constant_stages;
1400 (!layout->push_constant_size && !layout->dynamic_offset_count))
1403 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1404 16 * layout->dynamic_offset_count,
1405 256, &offset, &ptr))
1408 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1409 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1410 16 * layout->dynamic_offset_count);
1412 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1415 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1416 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1418 radv_foreach_stage(stage, stages) {
1419 if (pipeline->shaders[stage]) {
1420 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1421 AC_UD_PUSH_CONSTANTS, va);
1425 cmd_buffer->push_constant_stages &= ~stages;
1426 assert(cmd_buffer->cs->cdw <= cdw_max);
1430 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1432 if ((pipeline_is_dirty ||
1433 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1434 cmd_buffer->state.pipeline->vertex_elements.count &&
1435 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1436 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1440 uint32_t count = velems->count;
1443 /* allocate some descriptor state for vertex buffers */
1444 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1445 &vb_offset, &vb_ptr))
1448 for (i = 0; i < count; i++) {
1449 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1451 int vb = velems->binding[i];
1452 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1453 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1455 va = radv_buffer_get_va(buffer->bo);
1457 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1458 va += offset + buffer->offset;
1460 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1461 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1462 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1464 desc[2] = buffer->size - offset;
1465 desc[3] = velems->rsrc_word3[i];
1468 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1471 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1472 AC_UD_VS_VERTEX_BUFFERS, va);
1474 cmd_buffer->state.vb_va = va;
1475 cmd_buffer->state.vb_size = count * 16;
1476 cmd_buffer->state.vb_prefetch_dirty = true;
1478 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1484 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1486 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1489 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1490 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1491 VK_SHADER_STAGE_ALL_GRAPHICS);
1497 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1498 bool instanced_draw, bool indirect_draw,
1499 uint32_t draw_vertex_count)
1501 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1502 struct radv_cmd_state *state = &cmd_buffer->state;
1503 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1504 uint32_t ia_multi_vgt_param;
1505 int32_t primitive_reset_en;
1508 ia_multi_vgt_param =
1509 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1510 indirect_draw, draw_vertex_count);
1512 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1513 if (info->chip_class >= GFX9) {
1514 radeon_set_uconfig_reg_idx(cs,
1515 R_030960_IA_MULTI_VGT_PARAM,
1516 4, ia_multi_vgt_param);
1517 } else if (info->chip_class >= CIK) {
1518 radeon_set_context_reg_idx(cs,
1519 R_028AA8_IA_MULTI_VGT_PARAM,
1520 1, ia_multi_vgt_param);
1522 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1523 ia_multi_vgt_param);
1525 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1528 /* Primitive restart. */
1529 primitive_reset_en =
1530 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1532 if (primitive_reset_en != state->last_primitive_reset_en) {
1533 state->last_primitive_reset_en = primitive_reset_en;
1534 if (info->chip_class >= GFX9) {
1535 radeon_set_uconfig_reg(cs,
1536 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1537 primitive_reset_en);
1539 radeon_set_context_reg(cs,
1540 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1541 primitive_reset_en);
1545 if (primitive_reset_en) {
1546 uint32_t primitive_reset_index =
1547 state->index_type ? 0xffffffffu : 0xffffu;
1549 if (primitive_reset_index != state->last_primitive_reset_index) {
1550 radeon_set_context_reg(cs,
1551 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1552 primitive_reset_index);
1553 state->last_primitive_reset_index = primitive_reset_index;
1558 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1559 VkPipelineStageFlags src_stage_mask)
1561 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1562 VK_PIPELINE_STAGE_TRANSFER_BIT |
1563 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1564 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1565 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1568 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1569 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1570 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1571 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1572 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1573 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1574 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1575 VK_PIPELINE_STAGE_TRANSFER_BIT |
1576 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1577 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1578 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1579 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1580 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1581 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1582 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1583 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1587 static enum radv_cmd_flush_bits
1588 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1589 VkAccessFlags src_flags)
1591 enum radv_cmd_flush_bits flush_bits = 0;
1593 for_each_bit(b, src_flags) {
1594 switch ((VkAccessFlagBits)(1 << b)) {
1595 case VK_ACCESS_SHADER_WRITE_BIT:
1596 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1598 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1599 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1600 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1602 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1603 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1604 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1606 case VK_ACCESS_TRANSFER_WRITE_BIT:
1607 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1608 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1609 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1610 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1611 RADV_CMD_FLAG_INV_GLOBAL_L2;
1620 static enum radv_cmd_flush_bits
1621 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1622 VkAccessFlags dst_flags,
1623 struct radv_image *image)
1625 enum radv_cmd_flush_bits flush_bits = 0;
1627 for_each_bit(b, dst_flags) {
1628 switch ((VkAccessFlagBits)(1 << b)) {
1629 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1630 case VK_ACCESS_INDEX_READ_BIT:
1632 case VK_ACCESS_UNIFORM_READ_BIT:
1633 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1635 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1636 case VK_ACCESS_SHADER_READ_BIT:
1637 case VK_ACCESS_TRANSFER_READ_BIT:
1638 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1639 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1640 RADV_CMD_FLAG_INV_GLOBAL_L2;
1642 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1643 /* TODO: change to image && when the image gets passed
1644 * through from the subpass. */
1645 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1646 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1647 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1649 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1650 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1651 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1652 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1661 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1663 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1664 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1665 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1669 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1670 VkAttachmentReference att)
1672 unsigned idx = att.attachment;
1673 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1674 VkImageSubresourceRange range;
1675 range.aspectMask = 0;
1676 range.baseMipLevel = view->base_mip;
1677 range.levelCount = 1;
1678 range.baseArrayLayer = view->base_layer;
1679 range.layerCount = cmd_buffer->state.framebuffer->layers;
1681 radv_handle_image_transition(cmd_buffer,
1683 cmd_buffer->state.attachments[idx].current_layout,
1684 att.layout, 0, 0, &range,
1685 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1687 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1693 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1694 const struct radv_subpass *subpass, bool transitions)
1697 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1699 for (unsigned i = 0; i < subpass->color_count; ++i) {
1700 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1701 radv_handle_subpass_image_transition(cmd_buffer,
1702 subpass->color_attachments[i]);
1705 for (unsigned i = 0; i < subpass->input_count; ++i) {
1706 radv_handle_subpass_image_transition(cmd_buffer,
1707 subpass->input_attachments[i]);
1710 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1711 radv_handle_subpass_image_transition(cmd_buffer,
1712 subpass->depth_stencil_attachment);
1716 cmd_buffer->state.subpass = subpass;
1718 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
1722 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1723 struct radv_render_pass *pass,
1724 const VkRenderPassBeginInfo *info)
1726 struct radv_cmd_state *state = &cmd_buffer->state;
1728 if (pass->attachment_count == 0) {
1729 state->attachments = NULL;
1733 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1734 pass->attachment_count *
1735 sizeof(state->attachments[0]),
1736 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1737 if (state->attachments == NULL) {
1738 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1739 return cmd_buffer->record_result;
1742 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1743 struct radv_render_pass_attachment *att = &pass->attachments[i];
1744 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1745 VkImageAspectFlags clear_aspects = 0;
1747 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1748 /* color attachment */
1749 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1750 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1753 /* depthstencil attachment */
1754 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1755 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1756 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1757 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1758 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1759 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1761 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1762 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1763 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1767 state->attachments[i].pending_clear_aspects = clear_aspects;
1768 state->attachments[i].cleared_views = 0;
1769 if (clear_aspects && info) {
1770 assert(info->clearValueCount > i);
1771 state->attachments[i].clear_value = info->pClearValues[i];
1774 state->attachments[i].current_layout = att->initial_layout;
1780 VkResult radv_AllocateCommandBuffers(
1782 const VkCommandBufferAllocateInfo *pAllocateInfo,
1783 VkCommandBuffer *pCommandBuffers)
1785 RADV_FROM_HANDLE(radv_device, device, _device);
1786 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1788 VkResult result = VK_SUCCESS;
1791 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1793 if (!list_empty(&pool->free_cmd_buffers)) {
1794 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1796 list_del(&cmd_buffer->pool_link);
1797 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1799 result = radv_reset_cmd_buffer(cmd_buffer);
1800 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1801 cmd_buffer->level = pAllocateInfo->level;
1803 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1805 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1806 &pCommandBuffers[i]);
1808 if (result != VK_SUCCESS)
1812 if (result != VK_SUCCESS) {
1813 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1814 i, pCommandBuffers);
1816 /* From the Vulkan 1.0.66 spec:
1818 * "vkAllocateCommandBuffers can be used to create multiple
1819 * command buffers. If the creation of any of those command
1820 * buffers fails, the implementation must destroy all
1821 * successfully created command buffer objects from this
1822 * command, set all entries of the pCommandBuffers array to
1823 * NULL and return the error."
1825 memset(pCommandBuffers, 0,
1826 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1832 void radv_FreeCommandBuffers(
1834 VkCommandPool commandPool,
1835 uint32_t commandBufferCount,
1836 const VkCommandBuffer *pCommandBuffers)
1838 for (uint32_t i = 0; i < commandBufferCount; i++) {
1839 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1842 if (cmd_buffer->pool) {
1843 list_del(&cmd_buffer->pool_link);
1844 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1846 radv_cmd_buffer_destroy(cmd_buffer);
1852 VkResult radv_ResetCommandBuffer(
1853 VkCommandBuffer commandBuffer,
1854 VkCommandBufferResetFlags flags)
1856 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1857 return radv_reset_cmd_buffer(cmd_buffer);
1860 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1862 struct radv_device *device = cmd_buffer->device;
1863 if (device->gfx_init) {
1864 uint64_t va = radv_buffer_get_va(device->gfx_init);
1865 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
1866 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1867 radeon_emit(cmd_buffer->cs, va);
1868 radeon_emit(cmd_buffer->cs, va >> 32);
1869 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1871 si_init_config(cmd_buffer);
1874 VkResult radv_BeginCommandBuffer(
1875 VkCommandBuffer commandBuffer,
1876 const VkCommandBufferBeginInfo *pBeginInfo)
1878 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1879 VkResult result = VK_SUCCESS;
1881 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
1882 /* If the command buffer has already been resetted with
1883 * vkResetCommandBuffer, no need to do it again.
1885 result = radv_reset_cmd_buffer(cmd_buffer);
1886 if (result != VK_SUCCESS)
1890 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1891 cmd_buffer->state.last_primitive_reset_en = -1;
1892 cmd_buffer->state.last_index_type = -1;
1893 cmd_buffer->state.last_num_instances = -1;
1894 cmd_buffer->state.last_vertex_offset = -1;
1895 cmd_buffer->state.last_first_instance = -1;
1896 cmd_buffer->usage_flags = pBeginInfo->flags;
1898 /* setup initial configuration into command buffer */
1899 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1900 switch (cmd_buffer->queue_family_index) {
1901 case RADV_QUEUE_GENERAL:
1902 emit_gfx_buffer_state(cmd_buffer);
1904 case RADV_QUEUE_COMPUTE:
1905 si_init_compute(cmd_buffer);
1907 case RADV_QUEUE_TRANSFER:
1913 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1914 assert(pBeginInfo->pInheritanceInfo);
1915 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1916 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1918 struct radv_subpass *subpass =
1919 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1921 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1922 if (result != VK_SUCCESS)
1925 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1928 if (unlikely(cmd_buffer->device->trace_bo))
1929 radv_cmd_buffer_trace_emit(cmd_buffer);
1931 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
1936 void radv_CmdBindVertexBuffers(
1937 VkCommandBuffer commandBuffer,
1938 uint32_t firstBinding,
1939 uint32_t bindingCount,
1940 const VkBuffer* pBuffers,
1941 const VkDeviceSize* pOffsets)
1943 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1944 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
1945 bool changed = false;
1947 /* We have to defer setting up vertex buffer since we need the buffer
1948 * stride from the pipeline. */
1950 assert(firstBinding + bindingCount <= MAX_VBS);
1951 for (uint32_t i = 0; i < bindingCount; i++) {
1952 uint32_t idx = firstBinding + i;
1955 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
1956 vb[idx].offset != pOffsets[i])) {
1960 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
1961 vb[idx].offset = pOffsets[i];
1963 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1964 vb[idx].buffer->bo, 8);
1968 /* No state changes. */
1972 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
1975 void radv_CmdBindIndexBuffer(
1976 VkCommandBuffer commandBuffer,
1978 VkDeviceSize offset,
1979 VkIndexType indexType)
1981 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1982 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
1984 if (cmd_buffer->state.index_buffer == index_buffer &&
1985 cmd_buffer->state.index_offset == offset &&
1986 cmd_buffer->state.index_type == indexType) {
1987 /* No state changes. */
1991 cmd_buffer->state.index_buffer = index_buffer;
1992 cmd_buffer->state.index_offset = offset;
1993 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1994 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
1995 cmd_buffer->state.index_va += index_buffer->offset + offset;
1997 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
1998 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
1999 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2000 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2005 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2006 VkPipelineBindPoint bind_point,
2007 struct radv_descriptor_set *set, unsigned idx)
2009 struct radeon_winsys *ws = cmd_buffer->device->ws;
2011 radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2015 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2017 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2018 if (set->descriptors[j])
2019 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2022 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2025 void radv_CmdBindDescriptorSets(
2026 VkCommandBuffer commandBuffer,
2027 VkPipelineBindPoint pipelineBindPoint,
2028 VkPipelineLayout _layout,
2030 uint32_t descriptorSetCount,
2031 const VkDescriptorSet* pDescriptorSets,
2032 uint32_t dynamicOffsetCount,
2033 const uint32_t* pDynamicOffsets)
2035 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2036 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2037 unsigned dyn_idx = 0;
2039 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2040 unsigned idx = i + firstSet;
2041 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2042 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2044 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2045 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2046 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2047 assert(dyn_idx < dynamicOffsetCount);
2049 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2050 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2052 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2053 dst[2] = range->size;
2054 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2055 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2056 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2057 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2058 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2059 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2060 cmd_buffer->push_constant_stages |=
2061 set->layout->dynamic_shader_stages;
2066 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2067 struct radv_descriptor_set *set,
2068 struct radv_descriptor_set_layout *layout,
2069 VkPipelineBindPoint bind_point)
2071 struct radv_descriptor_state *descriptors_state =
2072 radv_get_descriptors_state(cmd_buffer, bind_point);
2073 set->size = layout->size;
2074 set->layout = layout;
2076 if (descriptors_state->push_set.capacity < set->size) {
2077 size_t new_size = MAX2(set->size, 1024);
2078 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2079 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2081 free(set->mapped_ptr);
2082 set->mapped_ptr = malloc(new_size);
2084 if (!set->mapped_ptr) {
2085 descriptors_state->push_set.capacity = 0;
2086 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2090 descriptors_state->push_set.capacity = new_size;
2096 void radv_meta_push_descriptor_set(
2097 struct radv_cmd_buffer* cmd_buffer,
2098 VkPipelineBindPoint pipelineBindPoint,
2099 VkPipelineLayout _layout,
2101 uint32_t descriptorWriteCount,
2102 const VkWriteDescriptorSet* pDescriptorWrites)
2104 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2105 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2109 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2111 push_set->size = layout->set[set].layout->size;
2112 push_set->layout = layout->set[set].layout;
2114 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2116 (void**) &push_set->mapped_ptr))
2119 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2120 push_set->va += bo_offset;
2122 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2123 radv_descriptor_set_to_handle(push_set),
2124 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2126 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2129 void radv_CmdPushDescriptorSetKHR(
2130 VkCommandBuffer commandBuffer,
2131 VkPipelineBindPoint pipelineBindPoint,
2132 VkPipelineLayout _layout,
2134 uint32_t descriptorWriteCount,
2135 const VkWriteDescriptorSet* pDescriptorWrites)
2137 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2138 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2139 struct radv_descriptor_state *descriptors_state =
2140 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2141 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2143 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2145 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2146 layout->set[set].layout,
2150 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2151 radv_descriptor_set_to_handle(push_set),
2152 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2154 radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2155 descriptors_state->push_dirty = true;
2158 void radv_CmdPushDescriptorSetWithTemplateKHR(
2159 VkCommandBuffer commandBuffer,
2160 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2161 VkPipelineLayout _layout,
2165 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2166 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2167 RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2168 struct radv_descriptor_state *descriptors_state =
2169 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2170 struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2172 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2174 if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2175 layout->set[set].layout,
2179 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2180 descriptorUpdateTemplate, pData);
2182 radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2183 descriptors_state->push_dirty = true;
2186 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2187 VkPipelineLayout layout,
2188 VkShaderStageFlags stageFlags,
2191 const void* pValues)
2193 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2194 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2195 cmd_buffer->push_constant_stages |= stageFlags;
2198 VkResult radv_EndCommandBuffer(
2199 VkCommandBuffer commandBuffer)
2201 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2203 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2204 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2205 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2206 si_emit_cache_flush(cmd_buffer);
2209 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2211 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2212 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2214 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2216 return cmd_buffer->record_result;
2220 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2222 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2224 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2227 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2229 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2230 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2232 cmd_buffer->compute_scratch_size_needed =
2233 MAX2(cmd_buffer->compute_scratch_size_needed,
2234 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2236 if (unlikely(cmd_buffer->device->trace_bo))
2237 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2240 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2241 VkPipelineBindPoint bind_point)
2243 struct radv_descriptor_state *descriptors_state =
2244 radv_get_descriptors_state(cmd_buffer, bind_point);
2246 descriptors_state->dirty |= descriptors_state->valid;
2249 void radv_CmdBindPipeline(
2250 VkCommandBuffer commandBuffer,
2251 VkPipelineBindPoint pipelineBindPoint,
2252 VkPipeline _pipeline)
2254 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2255 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2257 switch (pipelineBindPoint) {
2258 case VK_PIPELINE_BIND_POINT_COMPUTE:
2259 if (cmd_buffer->state.compute_pipeline == pipeline)
2261 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2263 cmd_buffer->state.compute_pipeline = pipeline;
2264 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2266 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2267 if (cmd_buffer->state.pipeline == pipeline)
2269 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2271 cmd_buffer->state.pipeline = pipeline;
2275 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2276 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2278 /* the new vertex shader might not have the same user regs */
2279 cmd_buffer->state.last_first_instance = -1;
2280 cmd_buffer->state.last_vertex_offset = -1;
2282 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2284 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2285 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2286 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2287 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2289 if (radv_pipeline_has_tess(pipeline))
2290 cmd_buffer->tess_rings_needed = true;
2292 if (radv_pipeline_has_gs(pipeline)) {
2293 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2294 AC_UD_SCRATCH_RING_OFFSETS);
2295 if (cmd_buffer->ring_offsets_idx == -1)
2296 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2297 else if (loc->sgpr_idx != -1)
2298 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2302 assert(!"invalid bind point");
2307 void radv_CmdSetViewport(
2308 VkCommandBuffer commandBuffer,
2309 uint32_t firstViewport,
2310 uint32_t viewportCount,
2311 const VkViewport* pViewports)
2313 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2314 struct radv_cmd_state *state = &cmd_buffer->state;
2315 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2317 assert(firstViewport < MAX_VIEWPORTS);
2318 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2320 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2321 /* Try to skip unnecessary PS partial flushes when the viewports
2324 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2325 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2326 !memcmp(state->dynamic.viewport.viewports + firstViewport,
2327 pViewports, viewportCount * sizeof(*pViewports))) {
2332 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2333 viewportCount * sizeof(*pViewports));
2335 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2338 void radv_CmdSetScissor(
2339 VkCommandBuffer commandBuffer,
2340 uint32_t firstScissor,
2341 uint32_t scissorCount,
2342 const VkRect2D* pScissors)
2344 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2345 struct radv_cmd_state *state = &cmd_buffer->state;
2346 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2348 assert(firstScissor < MAX_SCISSORS);
2349 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2351 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2352 /* Try to skip unnecessary PS partial flushes when the scissors
2355 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2356 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2357 !memcmp(state->dynamic.scissor.scissors + firstScissor,
2358 pScissors, scissorCount * sizeof(*pScissors))) {
2363 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2364 scissorCount * sizeof(*pScissors));
2366 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2369 void radv_CmdSetLineWidth(
2370 VkCommandBuffer commandBuffer,
2373 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2374 cmd_buffer->state.dynamic.line_width = lineWidth;
2375 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2378 void radv_CmdSetDepthBias(
2379 VkCommandBuffer commandBuffer,
2380 float depthBiasConstantFactor,
2381 float depthBiasClamp,
2382 float depthBiasSlopeFactor)
2384 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2386 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2387 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2388 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2390 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2393 void radv_CmdSetBlendConstants(
2394 VkCommandBuffer commandBuffer,
2395 const float blendConstants[4])
2397 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2399 memcpy(cmd_buffer->state.dynamic.blend_constants,
2400 blendConstants, sizeof(float) * 4);
2402 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2405 void radv_CmdSetDepthBounds(
2406 VkCommandBuffer commandBuffer,
2407 float minDepthBounds,
2408 float maxDepthBounds)
2410 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2412 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2413 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2415 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2418 void radv_CmdSetStencilCompareMask(
2419 VkCommandBuffer commandBuffer,
2420 VkStencilFaceFlags faceMask,
2421 uint32_t compareMask)
2423 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2425 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2426 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2427 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2428 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2430 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2433 void radv_CmdSetStencilWriteMask(
2434 VkCommandBuffer commandBuffer,
2435 VkStencilFaceFlags faceMask,
2438 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2440 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2441 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2442 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2443 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2445 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2448 void radv_CmdSetStencilReference(
2449 VkCommandBuffer commandBuffer,
2450 VkStencilFaceFlags faceMask,
2453 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2455 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2456 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2457 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2458 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2460 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2463 void radv_CmdSetDiscardRectangleEXT(
2464 VkCommandBuffer commandBuffer,
2465 uint32_t firstDiscardRectangle,
2466 uint32_t discardRectangleCount,
2467 const VkRect2D* pDiscardRectangles)
2469 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2470 struct radv_cmd_state *state = &cmd_buffer->state;
2471 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2473 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2474 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2476 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2477 pDiscardRectangles, discardRectangleCount);
2479 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2482 void radv_CmdExecuteCommands(
2483 VkCommandBuffer commandBuffer,
2484 uint32_t commandBufferCount,
2485 const VkCommandBuffer* pCmdBuffers)
2487 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2489 assert(commandBufferCount > 0);
2491 /* Emit pending flushes on primary prior to executing secondary */
2492 si_emit_cache_flush(primary);
2494 for (uint32_t i = 0; i < commandBufferCount; i++) {
2495 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2497 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2498 secondary->scratch_size_needed);
2499 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2500 secondary->compute_scratch_size_needed);
2502 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2503 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2504 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2505 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2506 if (secondary->tess_rings_needed)
2507 primary->tess_rings_needed = true;
2508 if (secondary->sample_positions_needed)
2509 primary->sample_positions_needed = true;
2511 if (secondary->ring_offsets_idx != -1) {
2512 if (primary->ring_offsets_idx == -1)
2513 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2515 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2517 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2520 /* When the secondary command buffer is compute only we don't
2521 * need to re-emit the current graphics pipeline.
2523 if (secondary->state.emitted_pipeline) {
2524 primary->state.emitted_pipeline =
2525 secondary->state.emitted_pipeline;
2528 /* When the secondary command buffer is graphics only we don't
2529 * need to re-emit the current compute pipeline.
2531 if (secondary->state.emitted_compute_pipeline) {
2532 primary->state.emitted_compute_pipeline =
2533 secondary->state.emitted_compute_pipeline;
2536 /* Only re-emit the draw packets when needed. */
2537 if (secondary->state.last_primitive_reset_en != -1) {
2538 primary->state.last_primitive_reset_en =
2539 secondary->state.last_primitive_reset_en;
2542 if (secondary->state.last_primitive_reset_index) {
2543 primary->state.last_primitive_reset_index =
2544 secondary->state.last_primitive_reset_index;
2547 if (secondary->state.last_ia_multi_vgt_param) {
2548 primary->state.last_ia_multi_vgt_param =
2549 secondary->state.last_ia_multi_vgt_param;
2552 if (secondary->state.last_first_instance != -1) {
2553 primary->state.last_first_instance =
2554 secondary->state.last_first_instance;
2557 if (secondary->state.last_num_instances != -1) {
2558 primary->state.last_num_instances =
2559 secondary->state.last_num_instances;
2562 if (secondary->state.last_vertex_offset != -1) {
2563 primary->state.last_vertex_offset =
2564 secondary->state.last_vertex_offset;
2567 if (secondary->state.last_index_type != -1) {
2568 primary->state.last_index_type =
2569 secondary->state.last_index_type;
2573 /* After executing commands from secondary buffers we have to dirty
2576 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2577 RADV_CMD_DIRTY_INDEX_BUFFER |
2578 RADV_CMD_DIRTY_DYNAMIC_ALL;
2579 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2580 radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2583 VkResult radv_CreateCommandPool(
2585 const VkCommandPoolCreateInfo* pCreateInfo,
2586 const VkAllocationCallbacks* pAllocator,
2587 VkCommandPool* pCmdPool)
2589 RADV_FROM_HANDLE(radv_device, device, _device);
2590 struct radv_cmd_pool *pool;
2592 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2593 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2595 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2598 pool->alloc = *pAllocator;
2600 pool->alloc = device->alloc;
2602 list_inithead(&pool->cmd_buffers);
2603 list_inithead(&pool->free_cmd_buffers);
2605 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2607 *pCmdPool = radv_cmd_pool_to_handle(pool);
2613 void radv_DestroyCommandPool(
2615 VkCommandPool commandPool,
2616 const VkAllocationCallbacks* pAllocator)
2618 RADV_FROM_HANDLE(radv_device, device, _device);
2619 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2624 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2625 &pool->cmd_buffers, pool_link) {
2626 radv_cmd_buffer_destroy(cmd_buffer);
2629 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2630 &pool->free_cmd_buffers, pool_link) {
2631 radv_cmd_buffer_destroy(cmd_buffer);
2634 vk_free2(&device->alloc, pAllocator, pool);
2637 VkResult radv_ResetCommandPool(
2639 VkCommandPool commandPool,
2640 VkCommandPoolResetFlags flags)
2642 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2645 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2646 &pool->cmd_buffers, pool_link) {
2647 result = radv_reset_cmd_buffer(cmd_buffer);
2648 if (result != VK_SUCCESS)
2655 void radv_TrimCommandPool(
2657 VkCommandPool commandPool,
2658 VkCommandPoolTrimFlagsKHR flags)
2660 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2665 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2666 &pool->free_cmd_buffers, pool_link) {
2667 radv_cmd_buffer_destroy(cmd_buffer);
2671 void radv_CmdBeginRenderPass(
2672 VkCommandBuffer commandBuffer,
2673 const VkRenderPassBeginInfo* pRenderPassBegin,
2674 VkSubpassContents contents)
2676 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2677 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2678 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2680 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2681 cmd_buffer->cs, 2048);
2682 MAYBE_UNUSED VkResult result;
2684 cmd_buffer->state.framebuffer = framebuffer;
2685 cmd_buffer->state.pass = pass;
2686 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2688 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2689 if (result != VK_SUCCESS)
2692 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2693 assert(cmd_buffer->cs->cdw <= cdw_max);
2695 radv_cmd_buffer_clear_subpass(cmd_buffer);
2698 void radv_CmdNextSubpass(
2699 VkCommandBuffer commandBuffer,
2700 VkSubpassContents contents)
2702 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2704 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2706 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2709 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2710 radv_cmd_buffer_clear_subpass(cmd_buffer);
2713 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2715 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2716 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2717 if (!pipeline->shaders[stage])
2719 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2720 if (loc->sgpr_idx == -1)
2722 uint32_t base_reg = pipeline->user_data_0[stage];
2723 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2726 if (pipeline->gs_copy_shader) {
2727 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2728 if (loc->sgpr_idx != -1) {
2729 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2730 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2736 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2737 uint32_t vertex_count)
2739 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2740 radeon_emit(cmd_buffer->cs, vertex_count);
2741 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2742 S_0287F0_USE_OPAQUE(0));
2746 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2748 uint32_t index_count)
2750 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2751 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2752 radeon_emit(cmd_buffer->cs, index_va);
2753 radeon_emit(cmd_buffer->cs, index_va >> 32);
2754 radeon_emit(cmd_buffer->cs, index_count);
2755 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2759 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2761 uint32_t draw_count,
2765 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2766 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2767 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2768 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
2769 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2772 /* just reset draw state for vertex data */
2773 cmd_buffer->state.last_first_instance = -1;
2774 cmd_buffer->state.last_num_instances = -1;
2775 cmd_buffer->state.last_vertex_offset = -1;
2777 if (draw_count == 1 && !count_va && !draw_id_enable) {
2778 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2779 PKT3_DRAW_INDIRECT, 3, false));
2781 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2782 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2783 radeon_emit(cs, di_src_sel);
2785 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2786 PKT3_DRAW_INDIRECT_MULTI,
2789 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2790 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2791 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2792 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2793 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2794 radeon_emit(cs, draw_count); /* count */
2795 radeon_emit(cs, count_va); /* count_addr */
2796 radeon_emit(cs, count_va >> 32);
2797 radeon_emit(cs, stride); /* stride */
2798 radeon_emit(cs, di_src_sel);
2802 struct radv_draw_info {
2804 * Number of vertices.
2809 * Index of the first vertex.
2811 int32_t vertex_offset;
2814 * First instance id.
2816 uint32_t first_instance;
2819 * Number of instances.
2821 uint32_t instance_count;
2824 * First index (indexed draws only).
2826 uint32_t first_index;
2829 * Whether it's an indexed draw.
2834 * Indirect draw parameters resource.
2836 struct radv_buffer *indirect;
2837 uint64_t indirect_offset;
2841 * Draw count parameters resource.
2843 struct radv_buffer *count_buffer;
2844 uint64_t count_buffer_offset;
2848 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
2849 const struct radv_draw_info *info)
2851 struct radv_cmd_state *state = &cmd_buffer->state;
2852 struct radeon_winsys *ws = cmd_buffer->device->ws;
2853 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2855 if (info->indirect) {
2856 uint64_t va = radv_buffer_get_va(info->indirect->bo);
2857 uint64_t count_va = 0;
2859 va += info->indirect->offset + info->indirect_offset;
2861 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
2863 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2865 radeon_emit(cs, va);
2866 radeon_emit(cs, va >> 32);
2868 if (info->count_buffer) {
2869 count_va = radv_buffer_get_va(info->count_buffer->bo);
2870 count_va += info->count_buffer->offset +
2871 info->count_buffer_offset;
2873 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
2876 if (!state->subpass->view_mask) {
2877 radv_cs_emit_indirect_draw_packet(cmd_buffer,
2884 for_each_bit(i, state->subpass->view_mask) {
2885 radv_emit_view_index(cmd_buffer, i);
2887 radv_cs_emit_indirect_draw_packet(cmd_buffer,
2895 assert(state->pipeline->graphics.vtx_base_sgpr);
2897 if (info->vertex_offset != state->last_vertex_offset ||
2898 info->first_instance != state->last_first_instance) {
2899 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
2900 state->pipeline->graphics.vtx_emit_num);
2902 radeon_emit(cs, info->vertex_offset);
2903 radeon_emit(cs, info->first_instance);
2904 if (state->pipeline->graphics.vtx_emit_num == 3)
2906 state->last_first_instance = info->first_instance;
2907 state->last_vertex_offset = info->vertex_offset;
2910 if (state->last_num_instances != info->instance_count) {
2911 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
2912 radeon_emit(cs, info->instance_count);
2913 state->last_num_instances = info->instance_count;
2916 if (info->indexed) {
2917 int index_size = state->index_type ? 4 : 2;
2920 index_va = state->index_va;
2921 index_va += info->first_index * index_size;
2923 if (!state->subpass->view_mask) {
2924 radv_cs_emit_draw_indexed_packet(cmd_buffer,
2929 for_each_bit(i, state->subpass->view_mask) {
2930 radv_emit_view_index(cmd_buffer, i);
2932 radv_cs_emit_draw_indexed_packet(cmd_buffer,
2938 if (!state->subpass->view_mask) {
2939 radv_cs_emit_draw_packet(cmd_buffer, info->count);
2942 for_each_bit(i, state->subpass->view_mask) {
2943 radv_emit_view_index(cmd_buffer, i);
2945 radv_cs_emit_draw_packet(cmd_buffer,
2954 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
2955 const struct radv_draw_info *info)
2957 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
2958 radv_emit_graphics_pipeline(cmd_buffer);
2960 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
2961 radv_emit_framebuffer_state(cmd_buffer);
2963 if (info->indexed) {
2964 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
2965 radv_emit_index_buffer(cmd_buffer);
2967 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
2968 * so the state must be re-emitted before the next indexed
2971 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
2972 cmd_buffer->state.last_index_type = -1;
2973 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2977 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
2979 radv_emit_draw_registers(cmd_buffer, info->indexed,
2980 info->instance_count > 1, info->indirect,
2981 info->indirect ? 0 : info->count);
2985 radv_draw(struct radv_cmd_buffer *cmd_buffer,
2986 const struct radv_draw_info *info)
2988 bool pipeline_is_dirty =
2989 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
2990 cmd_buffer->state.pipeline &&
2991 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
2993 MAYBE_UNUSED unsigned cdw_max =
2994 radeon_check_space(cmd_buffer->device->ws,
2995 cmd_buffer->cs, 4096);
2997 /* Use optimal packet order based on whether we need to sync the
3000 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3001 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3002 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3003 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3004 /* If we have to wait for idle, set all states first, so that
3005 * all SET packets are processed in parallel with previous draw
3006 * calls. Then upload descriptors, set shader pointers, and
3007 * draw, and prefetch at the end. This ensures that the time
3008 * the CUs are idle is very short. (there are only SET_SH
3009 * packets between the wait and the draw)
3011 radv_emit_all_graphics_states(cmd_buffer, info);
3012 si_emit_cache_flush(cmd_buffer);
3013 /* <-- CUs are idle here --> */
3015 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3018 radv_emit_draw_packets(cmd_buffer, info);
3019 /* <-- CUs are busy here --> */
3021 /* Start prefetches after the draw has been started. Both will
3022 * run in parallel, but starting the draw first is more
3025 if (pipeline_is_dirty) {
3026 radv_emit_prefetch(cmd_buffer,
3027 cmd_buffer->state.pipeline);
3030 /* If we don't wait for idle, start prefetches first, then set
3031 * states, and draw at the end.
3033 si_emit_cache_flush(cmd_buffer);
3035 if (pipeline_is_dirty) {
3036 radv_emit_prefetch(cmd_buffer,
3037 cmd_buffer->state.pipeline);
3040 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3043 radv_emit_all_graphics_states(cmd_buffer, info);
3044 radv_emit_draw_packets(cmd_buffer, info);
3047 assert(cmd_buffer->cs->cdw <= cdw_max);
3048 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3052 VkCommandBuffer commandBuffer,
3053 uint32_t vertexCount,
3054 uint32_t instanceCount,
3055 uint32_t firstVertex,
3056 uint32_t firstInstance)
3058 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3059 struct radv_draw_info info = {};
3061 info.count = vertexCount;
3062 info.instance_count = instanceCount;
3063 info.first_instance = firstInstance;
3064 info.vertex_offset = firstVertex;
3066 radv_draw(cmd_buffer, &info);
3069 void radv_CmdDrawIndexed(
3070 VkCommandBuffer commandBuffer,
3071 uint32_t indexCount,
3072 uint32_t instanceCount,
3073 uint32_t firstIndex,
3074 int32_t vertexOffset,
3075 uint32_t firstInstance)
3077 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3078 struct radv_draw_info info = {};
3080 info.indexed = true;
3081 info.count = indexCount;
3082 info.instance_count = instanceCount;
3083 info.first_index = firstIndex;
3084 info.vertex_offset = vertexOffset;
3085 info.first_instance = firstInstance;
3087 radv_draw(cmd_buffer, &info);
3090 void radv_CmdDrawIndirect(
3091 VkCommandBuffer commandBuffer,
3093 VkDeviceSize offset,
3097 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3098 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3099 struct radv_draw_info info = {};
3101 info.count = drawCount;
3102 info.indirect = buffer;
3103 info.indirect_offset = offset;
3104 info.stride = stride;
3106 radv_draw(cmd_buffer, &info);
3109 void radv_CmdDrawIndexedIndirect(
3110 VkCommandBuffer commandBuffer,
3112 VkDeviceSize offset,
3116 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3117 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3118 struct radv_draw_info info = {};
3120 info.indexed = true;
3121 info.count = drawCount;
3122 info.indirect = buffer;
3123 info.indirect_offset = offset;
3124 info.stride = stride;
3126 radv_draw(cmd_buffer, &info);
3129 void radv_CmdDrawIndirectCountAMD(
3130 VkCommandBuffer commandBuffer,
3132 VkDeviceSize offset,
3133 VkBuffer _countBuffer,
3134 VkDeviceSize countBufferOffset,
3135 uint32_t maxDrawCount,
3138 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3139 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3140 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3141 struct radv_draw_info info = {};
3143 info.count = maxDrawCount;
3144 info.indirect = buffer;
3145 info.indirect_offset = offset;
3146 info.count_buffer = count_buffer;
3147 info.count_buffer_offset = countBufferOffset;
3148 info.stride = stride;
3150 radv_draw(cmd_buffer, &info);
3153 void radv_CmdDrawIndexedIndirectCountAMD(
3154 VkCommandBuffer commandBuffer,
3156 VkDeviceSize offset,
3157 VkBuffer _countBuffer,
3158 VkDeviceSize countBufferOffset,
3159 uint32_t maxDrawCount,
3162 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3163 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3164 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3165 struct radv_draw_info info = {};
3167 info.indexed = true;
3168 info.count = maxDrawCount;
3169 info.indirect = buffer;
3170 info.indirect_offset = offset;
3171 info.count_buffer = count_buffer;
3172 info.count_buffer_offset = countBufferOffset;
3173 info.stride = stride;
3175 radv_draw(cmd_buffer, &info);
3178 struct radv_dispatch_info {
3180 * Determine the layout of the grid (in block units) to be used.
3185 * A starting offset for the grid. If unaligned is set, the offset
3186 * must still be aligned.
3188 uint32_t offsets[3];
3190 * Whether it's an unaligned compute dispatch.
3195 * Indirect compute parameters resource.
3197 struct radv_buffer *indirect;
3198 uint64_t indirect_offset;
3202 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3203 const struct radv_dispatch_info *info)
3205 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3206 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3207 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3208 struct radeon_winsys *ws = cmd_buffer->device->ws;
3209 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3210 struct ac_userdata_info *loc;
3212 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3213 AC_UD_CS_GRID_SIZE);
3215 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3217 if (info->indirect) {
3218 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3220 va += info->indirect->offset + info->indirect_offset;
3222 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3224 if (loc->sgpr_idx != -1) {
3225 for (unsigned i = 0; i < 3; ++i) {
3226 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3227 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3228 COPY_DATA_DST_SEL(COPY_DATA_REG));
3229 radeon_emit(cs, (va + 4 * i));
3230 radeon_emit(cs, (va + 4 * i) >> 32);
3231 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3232 + loc->sgpr_idx * 4) >> 2) + i);
3237 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3238 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3239 PKT3_SHADER_TYPE_S(1));
3240 radeon_emit(cs, va);
3241 radeon_emit(cs, va >> 32);
3242 radeon_emit(cs, dispatch_initiator);
3244 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3245 PKT3_SHADER_TYPE_S(1));
3247 radeon_emit(cs, va);
3248 radeon_emit(cs, va >> 32);
3250 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3251 PKT3_SHADER_TYPE_S(1));
3253 radeon_emit(cs, dispatch_initiator);
3256 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3257 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3259 if (info->unaligned) {
3260 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3261 unsigned remainder[3];
3263 /* If aligned, these should be an entire block size,
3266 remainder[0] = blocks[0] + cs_block_size[0] -
3267 align_u32_npot(blocks[0], cs_block_size[0]);
3268 remainder[1] = blocks[1] + cs_block_size[1] -
3269 align_u32_npot(blocks[1], cs_block_size[1]);
3270 remainder[2] = blocks[2] + cs_block_size[2] -
3271 align_u32_npot(blocks[2], cs_block_size[2]);
3273 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3274 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3275 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3277 for(unsigned i = 0; i < 3; ++i) {
3278 assert(offsets[i] % cs_block_size[i] == 0);
3279 offsets[i] /= cs_block_size[i];
3282 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3284 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3285 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3287 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3288 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3290 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3291 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3293 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3296 if (loc->sgpr_idx != -1) {
3297 assert(!loc->indirect);
3298 assert(loc->num_sgprs == 3);
3300 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3301 loc->sgpr_idx * 4, 3);
3302 radeon_emit(cs, blocks[0]);
3303 radeon_emit(cs, blocks[1]);
3304 radeon_emit(cs, blocks[2]);
3307 if (offsets[0] || offsets[1] || offsets[2]) {
3308 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3309 radeon_emit(cs, offsets[0]);
3310 radeon_emit(cs, offsets[1]);
3311 radeon_emit(cs, offsets[2]);
3313 /* The blocks in the packet are not counts but end values. */
3314 for (unsigned i = 0; i < 3; ++i)
3315 blocks[i] += offsets[i];
3317 dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3320 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3321 PKT3_SHADER_TYPE_S(1));
3322 radeon_emit(cs, blocks[0]);
3323 radeon_emit(cs, blocks[1]);
3324 radeon_emit(cs, blocks[2]);
3325 radeon_emit(cs, dispatch_initiator);
3328 assert(cmd_buffer->cs->cdw <= cdw_max);
3332 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3334 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3335 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3336 VK_SHADER_STAGE_COMPUTE_BIT);
3340 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3341 const struct radv_dispatch_info *info)
3343 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3344 bool pipeline_is_dirty = pipeline &&
3345 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3347 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3348 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3349 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3350 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3351 /* If we have to wait for idle, set all states first, so that
3352 * all SET packets are processed in parallel with previous draw
3353 * calls. Then upload descriptors, set shader pointers, and
3354 * dispatch, and prefetch at the end. This ensures that the
3355 * time the CUs are idle is very short. (there are only SET_SH
3356 * packets between the wait and the draw)
3358 radv_emit_compute_pipeline(cmd_buffer);
3359 si_emit_cache_flush(cmd_buffer);
3360 /* <-- CUs are idle here --> */
3362 radv_upload_compute_shader_descriptors(cmd_buffer);
3364 radv_emit_dispatch_packets(cmd_buffer, info);
3365 /* <-- CUs are busy here --> */
3367 /* Start prefetches after the dispatch has been started. Both
3368 * will run in parallel, but starting the dispatch first is
3371 if (pipeline_is_dirty) {
3372 radv_emit_shader_prefetch(cmd_buffer,
3373 pipeline->shaders[MESA_SHADER_COMPUTE]);
3376 /* If we don't wait for idle, start prefetches first, then set
3377 * states, and dispatch at the end.
3379 si_emit_cache_flush(cmd_buffer);
3381 if (pipeline_is_dirty) {
3382 radv_emit_shader_prefetch(cmd_buffer,
3383 pipeline->shaders[MESA_SHADER_COMPUTE]);
3386 radv_upload_compute_shader_descriptors(cmd_buffer);
3388 radv_emit_compute_pipeline(cmd_buffer);
3389 radv_emit_dispatch_packets(cmd_buffer, info);
3392 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3395 void radv_CmdDispatchBase(
3396 VkCommandBuffer commandBuffer,
3404 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3405 struct radv_dispatch_info info = {};
3411 info.offsets[0] = base_x;
3412 info.offsets[1] = base_y;
3413 info.offsets[2] = base_z;
3414 radv_dispatch(cmd_buffer, &info);
3417 void radv_CmdDispatch(
3418 VkCommandBuffer commandBuffer,
3423 radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3426 void radv_CmdDispatchIndirect(
3427 VkCommandBuffer commandBuffer,
3429 VkDeviceSize offset)
3431 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3432 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3433 struct radv_dispatch_info info = {};
3435 info.indirect = buffer;
3436 info.indirect_offset = offset;
3438 radv_dispatch(cmd_buffer, &info);
3441 void radv_unaligned_dispatch(
3442 struct radv_cmd_buffer *cmd_buffer,
3447 struct radv_dispatch_info info = {};
3454 radv_dispatch(cmd_buffer, &info);
3457 void radv_CmdEndRenderPass(
3458 VkCommandBuffer commandBuffer)
3460 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3462 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3464 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3466 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3467 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3468 radv_handle_subpass_image_transition(cmd_buffer,
3469 (VkAttachmentReference){i, layout});
3472 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3474 cmd_buffer->state.pass = NULL;
3475 cmd_buffer->state.subpass = NULL;
3476 cmd_buffer->state.attachments = NULL;
3477 cmd_buffer->state.framebuffer = NULL;
3481 * For HTILE we have the following interesting clear words:
3482 * 0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3483 * 0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3484 * 0xfffffff0: Clear depth to 1.0
3485 * 0x00000000: Clear depth to 0.0
3487 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3488 struct radv_image *image,
3489 const VkImageSubresourceRange *range,
3490 uint32_t clear_word)
3492 assert(range->baseMipLevel == 0);
3493 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3494 unsigned layer_count = radv_get_layerCount(image, range);
3495 uint64_t size = image->surface.htile_slice_size * layer_count;
3496 uint64_t offset = image->offset + image->htile_offset +
3497 image->surface.htile_slice_size * range->baseArrayLayer;
3498 struct radv_cmd_state *state = &cmd_buffer->state;
3500 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3501 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3503 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3506 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3509 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3510 struct radv_image *image,
3511 VkImageLayout src_layout,
3512 VkImageLayout dst_layout,
3513 unsigned src_queue_mask,
3514 unsigned dst_queue_mask,
3515 const VkImageSubresourceRange *range,
3516 VkImageAspectFlags pending_clears)
3518 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3519 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3520 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3521 cmd_buffer->state.render_area.extent.width == image->info.width &&
3522 cmd_buffer->state.render_area.extent.height == image->info.height) {
3523 /* The clear will initialize htile. */
3525 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3526 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3527 /* TODO: merge with the clear if applicable */
3528 radv_initialize_htile(cmd_buffer, image, range, 0);
3529 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3530 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3531 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3532 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3533 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3534 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3535 VkImageSubresourceRange local_range = *range;
3536 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3537 local_range.baseMipLevel = 0;
3538 local_range.levelCount = 1;
3540 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3541 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3543 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3545 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3546 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3550 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3551 struct radv_image *image, uint32_t value)
3553 struct radv_cmd_state *state = &cmd_buffer->state;
3555 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3556 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3558 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3559 image->offset + image->cmask.offset,
3560 image->cmask.size, value);
3562 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3565 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3566 struct radv_image *image,
3567 VkImageLayout src_layout,
3568 VkImageLayout dst_layout,
3569 unsigned src_queue_mask,
3570 unsigned dst_queue_mask,
3571 const VkImageSubresourceRange *range)
3573 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3574 if (image->fmask.size)
3575 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3577 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3578 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3579 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3580 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3584 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3585 struct radv_image *image, uint32_t value)
3587 struct radv_cmd_state *state = &cmd_buffer->state;
3589 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3590 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3592 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3593 image->offset + image->dcc_offset,
3594 image->surface.dcc_size, value);
3596 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3597 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3600 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3601 struct radv_image *image,
3602 VkImageLayout src_layout,
3603 VkImageLayout dst_layout,
3604 unsigned src_queue_mask,
3605 unsigned dst_queue_mask,
3606 const VkImageSubresourceRange *range)
3608 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
3609 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
3610 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3611 radv_initialize_dcc(cmd_buffer, image,
3612 radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask) ?
3613 0x20202020u : 0xffffffffu);
3614 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
3615 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
3616 radv_decompress_dcc(cmd_buffer, image, range);
3617 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3618 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3619 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3623 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3624 struct radv_image *image,
3625 VkImageLayout src_layout,
3626 VkImageLayout dst_layout,
3627 uint32_t src_family,
3628 uint32_t dst_family,
3629 const VkImageSubresourceRange *range,
3630 VkImageAspectFlags pending_clears)
3632 if (image->exclusive && src_family != dst_family) {
3633 /* This is an acquire or a release operation and there will be
3634 * a corresponding release/acquire. Do the transition in the
3635 * most flexible queue. */
3637 assert(src_family == cmd_buffer->queue_family_index ||
3638 dst_family == cmd_buffer->queue_family_index);
3640 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3643 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3644 (src_family == RADV_QUEUE_GENERAL ||
3645 dst_family == RADV_QUEUE_GENERAL))
3649 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3650 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3652 if (image->surface.htile_size)
3653 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3654 dst_layout, src_queue_mask,
3655 dst_queue_mask, range,
3658 if (image->cmask.size || image->fmask.size)
3659 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3660 dst_layout, src_queue_mask,
3661 dst_queue_mask, range);
3663 if (image->surface.dcc_size)
3664 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3665 dst_layout, src_queue_mask,
3666 dst_queue_mask, range);
3669 void radv_CmdPipelineBarrier(
3670 VkCommandBuffer commandBuffer,
3671 VkPipelineStageFlags srcStageMask,
3672 VkPipelineStageFlags destStageMask,
3674 uint32_t memoryBarrierCount,
3675 const VkMemoryBarrier* pMemoryBarriers,
3676 uint32_t bufferMemoryBarrierCount,
3677 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3678 uint32_t imageMemoryBarrierCount,
3679 const VkImageMemoryBarrier* pImageMemoryBarriers)
3681 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3682 enum radv_cmd_flush_bits src_flush_bits = 0;
3683 enum radv_cmd_flush_bits dst_flush_bits = 0;
3685 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3686 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3687 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3691 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3692 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3693 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3697 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3698 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3699 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3700 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3704 radv_stage_flush(cmd_buffer, srcStageMask);
3705 cmd_buffer->state.flush_bits |= src_flush_bits;
3707 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3708 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3709 radv_handle_image_transition(cmd_buffer, image,
3710 pImageMemoryBarriers[i].oldLayout,
3711 pImageMemoryBarriers[i].newLayout,
3712 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3713 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3714 &pImageMemoryBarriers[i].subresourceRange,
3718 cmd_buffer->state.flush_bits |= dst_flush_bits;
3722 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3723 struct radv_event *event,
3724 VkPipelineStageFlags stageMask,
3727 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3728 uint64_t va = radv_buffer_get_va(event->bo);
3730 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3732 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3734 /* TODO: this is overkill. Probably should figure something out from
3735 * the stage mask. */
3737 si_cs_emit_write_event_eop(cs,
3738 cmd_buffer->state.predicating,
3739 cmd_buffer->device->physical_device->rad_info.chip_class,
3740 radv_cmd_buffer_uses_mec(cmd_buffer),
3741 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3744 assert(cmd_buffer->cs->cdw <= cdw_max);
3747 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3749 VkPipelineStageFlags stageMask)
3751 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3752 RADV_FROM_HANDLE(radv_event, event, _event);
3754 write_event(cmd_buffer, event, stageMask, 1);
3757 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3759 VkPipelineStageFlags stageMask)
3761 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3762 RADV_FROM_HANDLE(radv_event, event, _event);
3764 write_event(cmd_buffer, event, stageMask, 0);
3767 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3768 uint32_t eventCount,
3769 const VkEvent* pEvents,
3770 VkPipelineStageFlags srcStageMask,
3771 VkPipelineStageFlags dstStageMask,
3772 uint32_t memoryBarrierCount,
3773 const VkMemoryBarrier* pMemoryBarriers,
3774 uint32_t bufferMemoryBarrierCount,
3775 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3776 uint32_t imageMemoryBarrierCount,
3777 const VkImageMemoryBarrier* pImageMemoryBarriers)
3779 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3780 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3782 for (unsigned i = 0; i < eventCount; ++i) {
3783 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3784 uint64_t va = radv_buffer_get_va(event->bo);
3786 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3788 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3790 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3791 assert(cmd_buffer->cs->cdw <= cdw_max);
3795 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3796 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3798 radv_handle_image_transition(cmd_buffer, image,
3799 pImageMemoryBarriers[i].oldLayout,
3800 pImageMemoryBarriers[i].newLayout,
3801 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3802 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3803 &pImageMemoryBarriers[i].subresourceRange,
3807 /* TODO: figure out how to do memory barriers without waiting */
3808 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3809 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3810 RADV_CMD_FLAG_INV_VMEM_L1 |
3811 RADV_CMD_FLAG_INV_SMEM_L1;
3815 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
3816 uint32_t deviceMask)