src/amd/vulkan/radv_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "radv_private.h"
  29 #include "radv_radeon_winsys.h"
  30 #include "radv_shader.h"
  31 #include "radv_cs.h"
  32 #include "sid.h"
  33 #include "gfx9d.h"
  34 #include "vk_format.h"
  35 #include "radv_debug.h"
  36 #include "radv_meta.h"
  37
  38 #include "ac_debug.h"
  39
  40 enum {
  41         RADV_PREFETCH_VBO_DESCRIPTORS   = (1 << 0),
  42         RADV_PREFETCH_VS                = (1 << 1),
  43         RADV_PREFETCH_TCS               = (1 << 2),
  44         RADV_PREFETCH_TES               = (1 << 3),
  45         RADV_PREFETCH_GS                = (1 << 4),
  46         RADV_PREFETCH_PS                = (1 << 5),
  47         RADV_PREFETCH_SHADERS           = (RADV_PREFETCH_VS  |
  48                                            RADV_PREFETCH_TCS |
  49                                            RADV_PREFETCH_TES |
  50                                            RADV_PREFETCH_GS  |
  51                                            RADV_PREFETCH_PS)
  52 };
  53
  54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
  55                                          struct radv_image *image,
  56                                          VkImageLayout src_layout,
  57                                          VkImageLayout dst_layout,
  58                                          uint32_t src_family,
  59                                          uint32_t dst_family,
  60                                          const VkImageSubresourceRange *range,
  61                                          VkImageAspectFlags pending_clears);
  62
  63 const struct radv_dynamic_state default_dynamic_state = {
  64         .viewport = {
  65                 .count = 0,
  66         },
  67         .scissor = {
  68                 .count = 0,
  69         },
  70         .line_width = 1.0f,
  71         .depth_bias = {
  72                 .bias = 0.0f,
  73                 .clamp = 0.0f,
  74                 .slope = 0.0f,
  75         },
  76         .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
  77         .depth_bounds = {
  78                 .min = 0.0f,
  79                 .max = 1.0f,
  80         },
  81         .stencil_compare_mask = {
  82                 .front = ~0u,
  83                 .back = ~0u,
  84         },
  85         .stencil_write_mask = {
  86                 .front = ~0u,
  87                 .back = ~0u,
  88         },
  89         .stencil_reference = {
  90                 .front = 0u,
  91                 .back = 0u,
  92         },
  93 };
  94
  95 static void
  96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
  97                         const struct radv_dynamic_state *src)
  98 {
  99         struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
 100         uint32_t copy_mask = src->mask;
 101         uint32_t dest_mask = 0;
 102
 103         /* Make sure to copy the number of viewports/scissors because they can
 104          * only be specified at pipeline creation time.
 105          */
 106         dest->viewport.count = src->viewport.count;
 107         dest->scissor.count = src->scissor.count;
 108         dest->discard_rectangle.count = src->discard_rectangle.count;
 109
 110         if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
 111                 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
 112                            src->viewport.count * sizeof(VkViewport))) {
 113                         typed_memcpy(dest->viewport.viewports,
 114                                      src->viewport.viewports,
 115                                      src->viewport.count);
 116                         dest_mask |= RADV_DYNAMIC_VIEWPORT;
 117                 }
 118         }
 119
 120         if (copy_mask & RADV_DYNAMIC_SCISSOR) {
 121                 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
 122                            src->scissor.count * sizeof(VkRect2D))) {
 123                         typed_memcpy(dest->scissor.scissors,
 124                                      src->scissor.scissors, src->scissor.count);
 125                         dest_mask |= RADV_DYNAMIC_SCISSOR;
 126                 }
 127         }
 128
 129         if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
 130                 if (dest->line_width != src->line_width) {
 131                         dest->line_width = src->line_width;
 132                         dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
 133                 }
 134         }
 135
 136         if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
 137                 if (memcmp(&dest->depth_bias, &src->depth_bias,
 138                            sizeof(src->depth_bias))) {
 139                         dest->depth_bias = src->depth_bias;
 140                         dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
 141                 }
 142         }
 143
 144         if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
 145                 if (memcmp(&dest->blend_constants, &src->blend_constants,
 146                            sizeof(src->blend_constants))) {
 147                         typed_memcpy(dest->blend_constants,
 148                                      src->blend_constants, 4);
 149                         dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
 150                 }
 151         }
 152
 153         if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
 154                 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
 155                            sizeof(src->depth_bounds))) {
 156                         dest->depth_bounds = src->depth_bounds;
 157                         dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
 158                 }
 159         }
 160
 161         if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
 162                 if (memcmp(&dest->stencil_compare_mask,
 163                            &src->stencil_compare_mask,
 164                            sizeof(src->stencil_compare_mask))) {
 165                         dest->stencil_compare_mask = src->stencil_compare_mask;
 166                         dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
 167                 }
 168         }
 169
 170         if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
 171                 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
 172                            sizeof(src->stencil_write_mask))) {
 173                         dest->stencil_write_mask = src->stencil_write_mask;
 174                         dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
 175                 }
 176         }
 177
 178         if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
 179                 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
 180                            sizeof(src->stencil_reference))) {
 181                         dest->stencil_reference = src->stencil_reference;
 182                         dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
 183                 }
 184         }
 185
 186         if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
 187                 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
 188                            src->discard_rectangle.count * sizeof(VkRect2D))) {
 189                         typed_memcpy(dest->discard_rectangle.rectangles,
 190                                      src->discard_rectangle.rectangles,
 191                                      src->discard_rectangle.count);
 192                         dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
 193                 }
 194         }
 195
 196         cmd_buffer->state.dirty |= dest_mask;
 197 }
 198
 199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
 200 {
 201         return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
 202                cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
 203 }
 204
 205 enum ring_type radv_queue_family_to_ring(int f) {
 206         switch (f) {
 207         case RADV_QUEUE_GENERAL:
 208                 return RING_GFX;
 209         case RADV_QUEUE_COMPUTE:
 210                 return RING_COMPUTE;
 211         case RADV_QUEUE_TRANSFER:
 212                 return RING_DMA;
 213         default:
 214                 unreachable("Unknown queue family");
 215         }
 216 }
 217
 218 static VkResult radv_create_cmd_buffer(
 219         struct radv_device *                         device,
 220         struct radv_cmd_pool *                       pool,
 221         VkCommandBufferLevel                        level,
 222         VkCommandBuffer*                            pCommandBuffer)
 223 {
 224         struct radv_cmd_buffer *cmd_buffer;
 225         unsigned ring;
 226         cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
 227                                VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 228         if (cmd_buffer == NULL)
 229                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 230
 231         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
 232         cmd_buffer->device = device;
 233         cmd_buffer->pool = pool;
 234         cmd_buffer->level = level;
 235
 236         if (pool) {
 237                 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
 238                 cmd_buffer->queue_family_index = pool->queue_family_index;
 239
 240         } else {
 241                 /* Init the pool_link so we can safely call list_del when we destroy
 242                  * the command buffer
 243                  */
 244                 list_inithead(&cmd_buffer->pool_link);
 245                 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
 246         }
 247
 248         ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
 249
 250         cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
 251         if (!cmd_buffer->cs) {
 252                 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 253                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 254         }
 255
 256         *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
 257
 258         list_inithead(&cmd_buffer->upload.list);
 259
 260         return VK_SUCCESS;
 261 }
 262
 263 static void
 264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
 265 {
 266         list_del(&cmd_buffer->pool_link);
 267
 268         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 269                                  &cmd_buffer->upload.list, list) {
 270                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 271                 list_del(&up->list);
 272                 free(up);
 273         }
 274
 275         if (cmd_buffer->upload.upload_bo)
 276                 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
 277         cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
 278
 279         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
 280                 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
 281
 282         vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 283 }
 284
 285 static VkResult
 286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 287 {
 288
 289         cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
 290
 291         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 292                                  &cmd_buffer->upload.list, list) {
 293                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 294                 list_del(&up->list);
 295                 free(up);
 296         }
 297
 298         cmd_buffer->push_constant_stages = 0;
 299         cmd_buffer->scratch_size_needed = 0;
 300         cmd_buffer->compute_scratch_size_needed = 0;
 301         cmd_buffer->esgs_ring_size_needed = 0;
 302         cmd_buffer->gsvs_ring_size_needed = 0;
 303         cmd_buffer->tess_rings_needed = false;
 304         cmd_buffer->sample_positions_needed = false;
 305
 306         if (cmd_buffer->upload.upload_bo)
 307                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 308                                    cmd_buffer->upload.upload_bo, 8);
 309         cmd_buffer->upload.offset = 0;
 310
 311         cmd_buffer->record_result = VK_SUCCESS;
 312
 313         cmd_buffer->ring_offsets_idx = -1;
 314
 315         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
 316                 cmd_buffer->descriptors[i].dirty = 0;
 317                 cmd_buffer->descriptors[i].valid = 0;
 318                 cmd_buffer->descriptors[i].push_dirty = false;
 319         }
 320
 321         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 322                 void *fence_ptr;
 323                 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
 324                                              &cmd_buffer->gfx9_fence_offset,
 325                                              &fence_ptr);
 326                 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
 327         }
 328
 329         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
 330
 331         return cmd_buffer->record_result;
 332 }
 333
 334 static bool
 335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
 336                                   uint64_t min_needed)
 337 {
 338         uint64_t new_size;
 339         struct radeon_winsys_bo *bo;
 340         struct radv_cmd_buffer_upload *upload;
 341         struct radv_device *device = cmd_buffer->device;
 342
 343         new_size = MAX2(min_needed, 16 * 1024);
 344         new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
 345
 346         bo = device->ws->buffer_create(device->ws,
 347                                        new_size, 4096,
 348                                        RADEON_DOMAIN_GTT,
 349                                        RADEON_FLAG_CPU_ACCESS|
 350                                        RADEON_FLAG_NO_INTERPROCESS_SHARING |
 351                                        RADEON_FLAG_32BIT);
 352
 353         if (!bo) {
 354                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 355                 return false;
 356         }
 357
 358         radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
 359         if (cmd_buffer->upload.upload_bo) {
 360                 upload = malloc(sizeof(*upload));
 361
 362                 if (!upload) {
 363                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
 364                         device->ws->buffer_destroy(bo);
 365                         return false;
 366                 }
 367
 368                 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
 369                 list_add(&upload->list, &cmd_buffer->upload.list);
 370         }
 371
 372         cmd_buffer->upload.upload_bo = bo;
 373         cmd_buffer->upload.size = new_size;
 374         cmd_buffer->upload.offset = 0;
 375         cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
 376
 377         if (!cmd_buffer->upload.map) {
 378                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 379                 return false;
 380         }
 381
 382         return true;
 383 }
 384
 385 bool
 386 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
 387                              unsigned size,
 388                              unsigned alignment,
 389                              unsigned *out_offset,
 390                              void **ptr)
 391 {
 392         uint64_t offset = align(cmd_buffer->upload.offset, alignment);
 393         if (offset + size > cmd_buffer->upload.size) {
 394                 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
 395                         return false;
 396                 offset = 0;
 397         }
 398
 399         *out_offset = offset;
 400         *ptr = cmd_buffer->upload.map + offset;
 401
 402         cmd_buffer->upload.offset = offset + size;
 403         return true;
 404 }
 405
 406 bool
 407 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
 408                             unsigned size, unsigned alignment,
 409                             const void *data, unsigned *out_offset)
 410 {
 411         uint8_t *ptr;
 412
 413         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
 414                                           out_offset, (void **)&ptr))
 415                 return false;
 416
 417         if (ptr)
 418                 memcpy(ptr, data, size);
 419
 420         return true;
 421 }
 422
 423 static void
 424 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
 425                             unsigned count, const uint32_t *data)
 426 {
 427         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
 428         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
 429                     S_370_WR_CONFIRM(1) |
 430                     S_370_ENGINE_SEL(V_370_ME));
 431         radeon_emit(cs, va);
 432         radeon_emit(cs, va >> 32);
 433         radeon_emit_array(cs, data, count);
 434 }
 435
 436 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
 437 {
 438         struct radv_device *device = cmd_buffer->device;
 439         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 440         uint64_t va;
 441
 442         va = radv_buffer_get_va(device->trace_bo);
 443         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
 444                 va += 4;
 445
 446         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
 447
 448         ++cmd_buffer->state.trace_id;
 449         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 450         radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
 451         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
 452         radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
 453 }
 454
 455 static void
 456 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
 457                            enum radv_cmd_flush_bits flags)
 458 {
 459         if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
 460                 uint32_t *ptr = NULL;
 461                 uint64_t va = 0;
 462
 463                 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
 464                                 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
 465
 466                 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
 467                         va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
 468                              cmd_buffer->gfx9_fence_offset;
 469                         ptr = &cmd_buffer->gfx9_fence_idx;
 470                 }
 471
 472                 /* Force wait for graphics or compute engines to be idle. */
 473                 si_cs_emit_cache_flush(cmd_buffer->cs,
 474                                        cmd_buffer->device->physical_device->rad_info.chip_class,
 475                                        ptr, va,
 476                                        radv_cmd_buffer_uses_mec(cmd_buffer),
 477                                        flags);
 478         }
 479
 480         if (unlikely(cmd_buffer->device->trace_bo))
 481                 radv_cmd_buffer_trace_emit(cmd_buffer);
 482 }
 483
 484 static void
 485 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
 486                    struct radv_pipeline *pipeline, enum ring_type ring)
 487 {
 488         struct radv_device *device = cmd_buffer->device;
 489         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 490         uint32_t data[2];
 491         uint64_t va;
 492
 493         va = radv_buffer_get_va(device->trace_bo);
 494
 495         switch (ring) {
 496         case RING_GFX:
 497                 va += 8;
 498                 break;
 499         case RING_COMPUTE:
 500                 va += 16;
 501                 break;
 502         default:
 503                 assert(!"invalid ring type");
 504         }
 505
 506         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 507                                                            cmd_buffer->cs, 6);
 508
 509         data[0] = (uintptr_t)pipeline;
 510         data[1] = (uintptr_t)pipeline >> 32;
 511
 512         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 513         radv_emit_write_data_packet(cs, va, 2, data);
 514 }
 515
 516 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 517                              VkPipelineBindPoint bind_point,
 518                              struct radv_descriptor_set *set,
 519                              unsigned idx)
 520 {
 521         struct radv_descriptor_state *descriptors_state =
 522                 radv_get_descriptors_state(cmd_buffer, bind_point);
 523
 524         descriptors_state->sets[idx] = set;
 525         if (set)
 526                 descriptors_state->valid |= (1u << idx);
 527         else
 528                 descriptors_state->valid &= ~(1u << idx);
 529         descriptors_state->dirty |= (1u << idx);
 530 }
 531
 532 static void
 533 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
 534                       VkPipelineBindPoint bind_point)
 535 {
 536         struct radv_descriptor_state *descriptors_state =
 537                 radv_get_descriptors_state(cmd_buffer, bind_point);
 538         struct radv_device *device = cmd_buffer->device;
 539         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 540         uint32_t data[MAX_SETS * 2] = {};
 541         uint64_t va;
 542         unsigned i;
 543         va = radv_buffer_get_va(device->trace_bo) + 24;
 544
 545         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 546                                                            cmd_buffer->cs, 4 + MAX_SETS * 2);
 547
 548         for_each_bit(i, descriptors_state->valid) {
 549                 struct radv_descriptor_set *set = descriptors_state->sets[i];
 550                 data[i * 2] = (uintptr_t)set;
 551                 data[i * 2 + 1] = (uintptr_t)set >> 32;
 552         }
 553
 554         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 555         radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
 556 }
 557
 558 struct radv_userdata_info *
 559 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
 560                       gl_shader_stage stage,
 561                       int idx)
 562 {
 563         if (stage == MESA_SHADER_VERTEX) {
 564                 if (pipeline->shaders[MESA_SHADER_VERTEX])
 565                         return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
 566                 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
 567                         return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
 568                 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
 569                         return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
 570         } else if (stage == MESA_SHADER_TESS_EVAL) {
 571                 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
 572                         return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
 573                 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
 574                         return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
 575         }
 576         return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
 577 }
 578
 579 static void
 580 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
 581                            struct radv_pipeline *pipeline,
 582                            gl_shader_stage stage,
 583                            int idx, uint64_t va)
 584 {
 585         struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
 586         uint32_t base_reg = pipeline->user_data_0[stage];
 587         if (loc->sgpr_idx == -1)
 588                 return;
 589
 590         assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
 591         assert(!loc->indirect);
 592
 593         radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
 594                                  base_reg + loc->sgpr_idx * 4, va, false);
 595 }
 596
 597 static void
 598 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
 599                               struct radv_pipeline *pipeline,
 600                               struct radv_descriptor_state *descriptors_state,
 601                               gl_shader_stage stage)
 602 {
 603         struct radv_device *device = cmd_buffer->device;
 604         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 605         uint32_t sh_base = pipeline->user_data_0[stage];
 606         struct radv_userdata_locations *locs =
 607                 &pipeline->shaders[stage]->info.user_sgprs_locs;
 608         unsigned mask;
 609
 610         mask = descriptors_state->dirty & descriptors_state->valid;
 611
 612         for (int i = 0; i < MAX_SETS; i++) {
 613                 struct radv_userdata_info *loc = &locs->descriptor_sets[i];
 614                 if (loc->sgpr_idx != -1 && !loc->indirect)
 615                         continue;
 616                 mask &= ~(1 << i);
 617         }
 618
 619         while (mask) {
 620                 int start, count;
 621
 622                 u_bit_scan_consecutive_range(&mask, &start, &count);
 623
 624                 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
 625                 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
 626
 627                 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
 628                 for (int i = 0; i < count; i++) {
 629                         struct radv_descriptor_set *set =
 630                                 descriptors_state->sets[start + i];
 631
 632                         radv_emit_shader_pointer_body(device, cs, set->va, true);
 633                 }
 634         }
 635 }
 636
 637 static void
 638 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
 639                               struct radv_pipeline *pipeline)
 640 {
 641         int num_samples = pipeline->graphics.ms.num_samples;
 642         struct radv_multisample_state *ms = &pipeline->graphics.ms;
 643         struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
 644
 645         if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
 646                 cmd_buffer->sample_positions_needed = true;
 647
 648         if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
 649                 return;
 650
 651         radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
 652         radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
 653         radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
 654
 655         radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
 656
 657         radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
 658
 659         /* GFX9: Flush DFSM when the AA mode changes. */
 660         if (cmd_buffer->device->dfsm_allowed) {
 661                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 662                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
 663         }
 664 }
 665
 666 static void
 667 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
 668                           struct radv_shader_variant *shader)
 669 {
 670         uint64_t va;
 671
 672         if (!shader)
 673                 return;
 674
 675         va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 676
 677         si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
 678 }
 679
 680 static void
 681 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
 682                       struct radv_pipeline *pipeline,
 683                       bool vertex_stage_only)
 684 {
 685         struct radv_cmd_state *state = &cmd_buffer->state;
 686         uint32_t mask = state->prefetch_L2_mask;
 687
 688         if (vertex_stage_only) {
 689                 /* Fast prefetch path for starting draws as soon as possible.
 690                  */
 691                 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
 692                                                   RADV_PREFETCH_VBO_DESCRIPTORS);
 693         }
 694
 695         if (mask & RADV_PREFETCH_VS)
 696                 radv_emit_shader_prefetch(cmd_buffer,
 697                                           pipeline->shaders[MESA_SHADER_VERTEX]);
 698
 699         if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
 700                 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
 701
 702         if (mask & RADV_PREFETCH_TCS)
 703                 radv_emit_shader_prefetch(cmd_buffer,
 704                                           pipeline->shaders[MESA_SHADER_TESS_CTRL]);
 705
 706         if (mask & RADV_PREFETCH_TES)
 707                 radv_emit_shader_prefetch(cmd_buffer,
 708                                           pipeline->shaders[MESA_SHADER_TESS_EVAL]);
 709
 710         if (mask & RADV_PREFETCH_GS) {
 711                 radv_emit_shader_prefetch(cmd_buffer,
 712                                           pipeline->shaders[MESA_SHADER_GEOMETRY]);
 713                 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
 714         }
 715
 716         if (mask & RADV_PREFETCH_PS)
 717                 radv_emit_shader_prefetch(cmd_buffer,
 718                                           pipeline->shaders[MESA_SHADER_FRAGMENT]);
 719
 720         state->prefetch_L2_mask &= ~mask;
 721 }
 722
 723 static void
 724 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
 725 {
 726         if (!cmd_buffer->device->physical_device->rbplus_allowed)
 727                 return;
 728
 729         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 730         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
 731         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 732
 733         unsigned sx_ps_downconvert = 0;
 734         unsigned sx_blend_opt_epsilon = 0;
 735         unsigned sx_blend_opt_control = 0;
 736
 737         for (unsigned i = 0; i < subpass->color_count; ++i) {
 738                 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
 739                         continue;
 740
 741                 int idx = subpass->color_attachments[i].attachment;
 742                 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
 743
 744                 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
 745                 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
 746                 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
 747                 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
 748
 749                 bool has_alpha, has_rgb;
 750
 751                 /* Set if RGB and A are present. */
 752                 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
 753
 754                 if (format == V_028C70_COLOR_8 ||
 755                     format == V_028C70_COLOR_16 ||
 756                     format == V_028C70_COLOR_32)
 757                         has_rgb = !has_alpha;
 758                 else
 759                         has_rgb = true;
 760
 761                 /* Check the colormask and export format. */
 762                 if (!(colormask & 0x7))
 763                         has_rgb = false;
 764                 if (!(colormask & 0x8))
 765                         has_alpha = false;
 766
 767                 if (spi_format == V_028714_SPI_SHADER_ZERO) {
 768                         has_rgb = false;
 769                         has_alpha = false;
 770                 }
 771
 772                 /* Disable value checking for disabled channels. */
 773                 if (!has_rgb)
 774                         sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 775                 if (!has_alpha)
 776                         sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 777
 778                 /* Enable down-conversion for 32bpp and smaller formats. */
 779                 switch (format) {
 780                 case V_028C70_COLOR_8:
 781                 case V_028C70_COLOR_8_8:
 782                 case V_028C70_COLOR_8_8_8_8:
 783                         /* For 1 and 2-channel formats, use the superset thereof. */
 784                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
 785                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 786                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 787                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
 788                                 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
 789                         }
 790                         break;
 791
 792                 case V_028C70_COLOR_5_6_5:
 793                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 794                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
 795                                 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
 796                         }
 797                         break;
 798
 799                 case V_028C70_COLOR_1_5_5_5:
 800                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 801                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
 802                                 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
 803                         }
 804                         break;
 805
 806                 case V_028C70_COLOR_4_4_4_4:
 807                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 808                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
 809                                 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
 810                         }
 811                         break;
 812
 813                 case V_028C70_COLOR_32:
 814                         if (swap == V_028C70_SWAP_STD &&
 815                             spi_format == V_028714_SPI_SHADER_32_R)
 816                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
 817                         else if (swap == V_028C70_SWAP_ALT_REV &&
 818                                  spi_format == V_028714_SPI_SHADER_32_AR)
 819                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
 820                         break;
 821
 822                 case V_028C70_COLOR_16:
 823                 case V_028C70_COLOR_16_16:
 824                         /* For 1-channel formats, use the superset thereof. */
 825                         if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
 826                             spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
 827                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 828                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 829                                 if (swap == V_028C70_SWAP_STD ||
 830                                     swap == V_028C70_SWAP_STD_REV)
 831                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
 832                                 else
 833                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
 834                         }
 835                         break;
 836
 837                 case V_028C70_COLOR_10_11_11:
 838                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 839                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
 840                                 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
 841                         }
 842                         break;
 843
 844                 case V_028C70_COLOR_2_10_10_10:
 845                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 846                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
 847                                 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
 848                         }
 849                         break;
 850                 }
 851         }
 852
 853         radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
 854         radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
 855         radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
 856         radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
 857 }
 858
 859 static void
 860 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
 861 {
 862         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 863
 864         if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
 865                 return;
 866
 867         radv_update_multisample_state(cmd_buffer, pipeline);
 868
 869         cmd_buffer->scratch_size_needed =
 870                                   MAX2(cmd_buffer->scratch_size_needed,
 871                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
 872
 873         if (!cmd_buffer->state.emitted_pipeline ||
 874             cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
 875              pipeline->graphics.can_use_guardband)
 876                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
 877
 878         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
 879
 880         for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
 881                 if (!pipeline->shaders[i])
 882                         continue;
 883
 884                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 885                                    pipeline->shaders[i]->bo, 8);
 886         }
 887
 888         if (radv_pipeline_has_gs(pipeline))
 889                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 890                                    pipeline->gs_copy_shader->bo, 8);
 891
 892         if (unlikely(cmd_buffer->device->trace_bo))
 893                 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
 894
 895         cmd_buffer->state.emitted_pipeline = pipeline;
 896
 897         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
 898 }
 899
 900 static void
 901 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
 902 {
 903         si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
 904                           cmd_buffer->state.dynamic.viewport.viewports);
 905 }
 906
 907 static void
 908 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
 909 {
 910         uint32_t count = cmd_buffer->state.dynamic.scissor.count;
 911
 912         si_write_scissors(cmd_buffer->cs, 0, count,
 913                           cmd_buffer->state.dynamic.scissor.scissors,
 914                           cmd_buffer->state.dynamic.viewport.viewports,
 915                           cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
 916 }
 917
 918 static void
 919 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
 920 {
 921         if (!cmd_buffer->state.dynamic.discard_rectangle.count)
 922                 return;
 923
 924         radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
 925                                    cmd_buffer->state.dynamic.discard_rectangle.count * 2);
 926         for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
 927                 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
 928                 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
 929                 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
 930                                             S_028214_BR_Y(rect.offset.y + rect.extent.height));
 931         }
 932 }
 933
 934 static void
 935 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
 936 {
 937         unsigned width = cmd_buffer->state.dynamic.line_width * 8;
 938
 939         radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
 940                                S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
 941 }
 942
 943 static void
 944 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
 945 {
 946         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 947
 948         radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
 949         radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
 950 }
 951
 952 static void
 953 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
 954 {
 955         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 956
 957         radeon_set_context_reg_seq(cmd_buffer->cs,
 958                                    R_028430_DB_STENCILREFMASK, 2);
 959         radeon_emit(cmd_buffer->cs,
 960                     S_028430_STENCILTESTVAL(d->stencil_reference.front) |
 961                     S_028430_STENCILMASK(d->stencil_compare_mask.front) |
 962                     S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
 963                     S_028430_STENCILOPVAL(1));
 964         radeon_emit(cmd_buffer->cs,
 965                     S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
 966                     S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
 967                     S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
 968                     S_028434_STENCILOPVAL_BF(1));
 969 }
 970
 971 static void
 972 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
 973 {
 974         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 975
 976         radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
 977                                fui(d->depth_bounds.min));
 978         radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
 979                                fui(d->depth_bounds.max));
 980 }
 981
 982 static void
 983 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
 984 {
 985         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 986         unsigned slope = fui(d->depth_bias.slope * 16.0f);
 987         unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
 988
 989
 990         radeon_set_context_reg_seq(cmd_buffer->cs,
 991                                    R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
 992         radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
 993         radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
 994         radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
 995         radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
 996         radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
 997 }
 998
 999 static void
1000 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1001                          int index,
1002                          struct radv_attachment_info *att,
1003                          struct radv_image *image,
1004                          VkImageLayout layout)
1005 {
1006         bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1007         struct radv_color_buffer_info *cb = &att->cb;
1008         uint32_t cb_color_info = cb->cb_color_info;
1009
1010         if (!radv_layout_dcc_compressed(image, layout,
1011                                         radv_image_queue_family_mask(image,
1012                                                                      cmd_buffer->queue_family_index,
1013                                                                      cmd_buffer->queue_family_index))) {
1014                 cb_color_info &= C_028C70_DCC_ENABLE;
1015         }
1016
1017         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1018                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1019                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1020                 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1021                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1022                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1023                 radeon_emit(cmd_buffer->cs, cb_color_info);
1024                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1025                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1026                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1027                 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1028                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1029                 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1030
1031                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1032                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1033                 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1034
1035                 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1036                                        S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1037         } else {
1038                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1039                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1040                 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1041                 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1042                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1043                 radeon_emit(cmd_buffer->cs, cb_color_info);
1044                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1045                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1046                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1047                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1048                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1049                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1050
1051                 if (is_vi) { /* DCC BASE */
1052                         radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1053                 }
1054         }
1055 }
1056
1057 static void
1058 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1059                       struct radv_ds_buffer_info *ds,
1060                       struct radv_image *image,
1061                       VkImageLayout layout)
1062 {
1063         uint32_t db_z_info = ds->db_z_info;
1064         uint32_t db_stencil_info = ds->db_stencil_info;
1065
1066         if (!radv_layout_has_htile(image, layout,
1067                                    radv_image_queue_family_mask(image,
1068                                                                 cmd_buffer->queue_family_index,
1069                                                                 cmd_buffer->queue_family_index))) {
1070                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1071                 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1072         }
1073
1074         radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1075         radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1076
1077
1078         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1079                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1080                 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1081                 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1082                 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1083
1084                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1085                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* DB_Z_INFO */
1086                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* DB_STENCIL_INFO */
1087                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* DB_Z_READ_BASE */
1088                 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32));        /* DB_Z_READ_BASE_HI */
1089                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* DB_STENCIL_READ_BASE */
1090                 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1091                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* DB_Z_WRITE_BASE */
1092                 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32));       /* DB_Z_WRITE_BASE_HI */
1093                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1094                 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1095
1096                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1097                 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1098                 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1099         } else {
1100                 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1101
1102                 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1103                 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1104                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* R_028040_DB_Z_INFO */
1105                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* R_028044_DB_STENCIL_INFO */
1106                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* R_028048_DB_Z_READ_BASE */
1107                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* R_02804C_DB_STENCIL_READ_BASE */
1108                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* R_028050_DB_Z_WRITE_BASE */
1109                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1110                 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1111                 radeon_emit(cmd_buffer->cs, ds->db_depth_slice);        /* R_02805C_DB_DEPTH_SLICE */
1112
1113         }
1114
1115         radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1116                                ds->pa_su_poly_offset_db_fmt_cntl);
1117 }
1118
1119 void
1120 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1121                           struct radv_image *image,
1122                           VkClearDepthStencilValue ds_clear_value,
1123                           VkImageAspectFlags aspects)
1124 {
1125         uint64_t va = radv_buffer_get_va(image->bo);
1126         va += image->offset + image->clear_value_offset;
1127         unsigned reg_offset = 0, reg_count = 0;
1128
1129         assert(radv_image_has_htile(image));
1130
1131         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1132                 ++reg_count;
1133         } else {
1134                 ++reg_offset;
1135                 va += 4;
1136         }
1137         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1138                 ++reg_count;
1139
1140         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1141         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1142                                     S_370_WR_CONFIRM(1) |
1143                                     S_370_ENGINE_SEL(V_370_PFP));
1144         radeon_emit(cmd_buffer->cs, va);
1145         radeon_emit(cmd_buffer->cs, va >> 32);
1146         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1147                 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1148         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1149                 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1150
1151         radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1152         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1153                 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1154         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1155                 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1156 }
1157
1158 static void
1159 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1160                            struct radv_image *image)
1161 {
1162         VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1163         uint64_t va = radv_buffer_get_va(image->bo);
1164         va += image->offset + image->clear_value_offset;
1165         unsigned reg_offset = 0, reg_count = 0;
1166
1167         if (!radv_image_has_htile(image))
1168                 return;
1169
1170         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1171                 ++reg_count;
1172         } else {
1173                 ++reg_offset;
1174                 va += 4;
1175         }
1176         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1177                 ++reg_count;
1178
1179         radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1180         radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1181                                     COPY_DATA_DST_SEL(COPY_DATA_REG) |
1182                                     (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1183         radeon_emit(cmd_buffer->cs, va);
1184         radeon_emit(cmd_buffer->cs, va >> 32);
1185         radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1186         radeon_emit(cmd_buffer->cs, 0);
1187
1188         radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1189         radeon_emit(cmd_buffer->cs, 0);
1190 }
1191
1192 /*
1193  * With DCC some colors don't require CMASK elimination before being
1194  * used as a texture. This sets a predicate value to determine if the
1195  * cmask eliminate is required.
1196  */
1197 void
1198 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1199                                   struct radv_image *image,
1200                                   bool value)
1201 {
1202         uint64_t pred_val = value;
1203         uint64_t va = radv_buffer_get_va(image->bo);
1204         va += image->offset + image->dcc_pred_offset;
1205
1206         assert(radv_image_has_dcc(image));
1207
1208         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1209         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1210                                     S_370_WR_CONFIRM(1) |
1211                                     S_370_ENGINE_SEL(V_370_PFP));
1212         radeon_emit(cmd_buffer->cs, va);
1213         radeon_emit(cmd_buffer->cs, va >> 32);
1214         radeon_emit(cmd_buffer->cs, pred_val);
1215         radeon_emit(cmd_buffer->cs, pred_val >> 32);
1216 }
1217
1218 void
1219 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1220                           struct radv_image *image,
1221                           int idx,
1222                           uint32_t color_values[2])
1223 {
1224         uint64_t va = radv_buffer_get_va(image->bo);
1225         va += image->offset + image->clear_value_offset;
1226
1227         assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1228
1229         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1230         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1231                                     S_370_WR_CONFIRM(1) |
1232                                     S_370_ENGINE_SEL(V_370_PFP));
1233         radeon_emit(cmd_buffer->cs, va);
1234         radeon_emit(cmd_buffer->cs, va >> 32);
1235         radeon_emit(cmd_buffer->cs, color_values[0]);
1236         radeon_emit(cmd_buffer->cs, color_values[1]);
1237
1238         radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1239         radeon_emit(cmd_buffer->cs, color_values[0]);
1240         radeon_emit(cmd_buffer->cs, color_values[1]);
1241 }
1242
1243 static void
1244 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1245                            struct radv_image *image,
1246                            int idx)
1247 {
1248         uint64_t va = radv_buffer_get_va(image->bo);
1249         va += image->offset + image->clear_value_offset;
1250
1251         if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1252                 return;
1253
1254         uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1255
1256         radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1257         radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1258                                     COPY_DATA_DST_SEL(COPY_DATA_REG) |
1259                                     COPY_DATA_COUNT_SEL);
1260         radeon_emit(cmd_buffer->cs, va);
1261         radeon_emit(cmd_buffer->cs, va >> 32);
1262         radeon_emit(cmd_buffer->cs, reg >> 2);
1263         radeon_emit(cmd_buffer->cs, 0);
1264
1265         radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1266         radeon_emit(cmd_buffer->cs, 0);
1267 }
1268
1269 static void
1270 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1271 {
1272         int i;
1273         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1274         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1275
1276         /* this may happen for inherited secondary recording */
1277         if (!framebuffer)
1278                 return;
1279
1280         for (i = 0; i < 8; ++i) {
1281                 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1282                         radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1283                                        S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1284                         continue;
1285                 }
1286
1287                 int idx = subpass->color_attachments[i].attachment;
1288                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1289                 struct radv_image *image = att->attachment->image;
1290                 VkImageLayout layout = subpass->color_attachments[i].layout;
1291
1292                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1293
1294                 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1295                 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1296
1297                 radv_load_color_clear_regs(cmd_buffer, image, i);
1298         }
1299
1300         if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1301                 int idx = subpass->depth_stencil_attachment.attachment;
1302                 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1303                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1304                 struct radv_image *image = att->attachment->image;
1305                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1306                 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1307                                                                                 cmd_buffer->queue_family_index,
1308                                                                                 cmd_buffer->queue_family_index);
1309                 /* We currently don't support writing decompressed HTILE */
1310                 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1311                        radv_layout_is_htile_compressed(image, layout, queue_mask));
1312
1313                 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1314
1315                 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1316                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1317                         cmd_buffer->state.offset_scale = att->ds.offset_scale;
1318                 }
1319                 radv_load_depth_clear_regs(cmd_buffer, image);
1320         } else {
1321                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1322                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1323                 else
1324                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1325
1326                 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1327                 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1328         }
1329         radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1330                                S_028208_BR_X(framebuffer->width) |
1331                                S_028208_BR_Y(framebuffer->height));
1332
1333         if (cmd_buffer->device->dfsm_allowed) {
1334                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1335                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1336         }
1337
1338         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1339 }
1340
1341 static void
1342 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1343 {
1344         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1345         struct radv_cmd_state *state = &cmd_buffer->state;
1346
1347         if (state->index_type != state->last_index_type) {
1348                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1349                         radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1350                                                    2, state->index_type);
1351                 } else {
1352                         radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1353                         radeon_emit(cs, state->index_type);
1354                 }
1355
1356                 state->last_index_type = state->index_type;
1357         }
1358
1359         radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1360         radeon_emit(cs, state->index_va);
1361         radeon_emit(cs, state->index_va >> 32);
1362
1363         radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1364         radeon_emit(cs, state->max_index_count);
1365
1366         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1367 }
1368
1369 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1370 {
1371         bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1372         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1373         uint32_t pa_sc_mode_cntl_1 =
1374                 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1375         uint32_t db_count_control;
1376
1377         if(!cmd_buffer->state.active_occlusion_queries) {
1378                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1379                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1380                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1381                             has_perfect_queries) {
1382                                 /* Re-enable out-of-order rasterization if the
1383                                  * bound pipeline supports it and if it's has
1384                                  * been disabled before starting any perfect
1385                                  * occlusion queries.
1386                                  */
1387                                 radeon_set_context_reg(cmd_buffer->cs,
1388                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1389                                                        pa_sc_mode_cntl_1);
1390                         }
1391                         db_count_control = 0;
1392                 } else {
1393                         db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1394                 }
1395         } else {
1396                 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1397                 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1398
1399                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1400                         db_count_control =
1401                                 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1402                                 S_028004_SAMPLE_RATE(sample_rate) |
1403                                 S_028004_ZPASS_ENABLE(1) |
1404                                 S_028004_SLICE_EVEN_ENABLE(1) |
1405                                 S_028004_SLICE_ODD_ENABLE(1);
1406
1407                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1408                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1409                             has_perfect_queries) {
1410                                 /* If the bound pipeline has enabled
1411                                  * out-of-order rasterization, we should
1412                                  * disable it before starting any perfect
1413                                  * occlusion queries.
1414                                  */
1415                                 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1416
1417                                 radeon_set_context_reg(cmd_buffer->cs,
1418                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1419                                                        pa_sc_mode_cntl_1);
1420                         }
1421                 } else {
1422                         db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1423                                 S_028004_SAMPLE_RATE(sample_rate);
1424                 }
1425         }
1426
1427         radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1428 }
1429
1430 static void
1431 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1432 {
1433         uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1434
1435         if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1436                 radv_emit_viewport(cmd_buffer);
1437
1438         if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1439             !cmd_buffer->device->physical_device->has_scissor_bug)
1440                 radv_emit_scissor(cmd_buffer);
1441
1442         if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1443                 radv_emit_line_width(cmd_buffer);
1444
1445         if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1446                 radv_emit_blend_constants(cmd_buffer);
1447
1448         if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1449                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1450                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1451                 radv_emit_stencil(cmd_buffer);
1452
1453         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1454                 radv_emit_depth_bounds(cmd_buffer);
1455
1456         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1457                 radv_emit_depth_bias(cmd_buffer);
1458
1459         if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1460                 radv_emit_discard_rectangle(cmd_buffer);
1461
1462         cmd_buffer->state.dirty &= ~states;
1463 }
1464
1465 static void
1466 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1467                             VkPipelineBindPoint bind_point)
1468 {
1469         struct radv_descriptor_state *descriptors_state =
1470                 radv_get_descriptors_state(cmd_buffer, bind_point);
1471         struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1472         unsigned bo_offset;
1473
1474         if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1475                                          set->mapped_ptr,
1476                                          &bo_offset))
1477                 return;
1478
1479         set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1480         set->va += bo_offset;
1481 }
1482
1483 static void
1484 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1485                                     VkPipelineBindPoint bind_point)
1486 {
1487         struct radv_descriptor_state *descriptors_state =
1488                 radv_get_descriptors_state(cmd_buffer, bind_point);
1489         uint32_t size = MAX_SETS * 2 * 4;
1490         uint32_t offset;
1491         void *ptr;
1492
1493         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1494                                           256, &offset, &ptr))
1495                 return;
1496
1497         for (unsigned i = 0; i < MAX_SETS; i++) {
1498                 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1499                 uint64_t set_va = 0;
1500                 struct radv_descriptor_set *set = descriptors_state->sets[i];
1501                 if (descriptors_state->valid & (1u << i))
1502                         set_va = set->va;
1503                 uptr[0] = set_va & 0xffffffff;
1504                 uptr[1] = set_va >> 32;
1505         }
1506
1507         uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1508         va += offset;
1509
1510         if (cmd_buffer->state.pipeline) {
1511                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1512                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1513                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1514
1515                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1516                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1517                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1518
1519                 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1520                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1521                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1522
1523                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1524                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1525                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1526
1527                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1528                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1529                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1530         }
1531
1532         if (cmd_buffer->state.compute_pipeline)
1533                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1534                                            AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1535 }
1536
1537 static void
1538 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1539                        VkShaderStageFlags stages)
1540 {
1541         VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1542                                          VK_PIPELINE_BIND_POINT_COMPUTE :
1543                                          VK_PIPELINE_BIND_POINT_GRAPHICS;
1544         struct radv_descriptor_state *descriptors_state =
1545                 radv_get_descriptors_state(cmd_buffer, bind_point);
1546
1547         if (!descriptors_state->dirty)
1548                 return;
1549
1550         if (descriptors_state->push_dirty)
1551                 radv_flush_push_descriptors(cmd_buffer, bind_point);
1552
1553         if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1554             (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1555                 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1556         }
1557
1558         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1559                                                            cmd_buffer->cs,
1560                                                            MAX_SETS * MESA_SHADER_STAGES * 4);
1561
1562         if (cmd_buffer->state.pipeline) {
1563                 radv_foreach_stage(stage, stages) {
1564                         if (!cmd_buffer->state.pipeline->shaders[stage])
1565                                 continue;
1566
1567                         radv_emit_descriptor_pointers(cmd_buffer,
1568                                                       cmd_buffer->state.pipeline,
1569                                                       descriptors_state, stage);
1570                 }
1571         }
1572
1573         if (cmd_buffer->state.compute_pipeline &&
1574             (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1575                 radv_emit_descriptor_pointers(cmd_buffer,
1576                                               cmd_buffer->state.compute_pipeline,
1577                                               descriptors_state,
1578                                               MESA_SHADER_COMPUTE);
1579         }
1580
1581         descriptors_state->dirty = 0;
1582         descriptors_state->push_dirty = false;
1583
1584         if (unlikely(cmd_buffer->device->trace_bo))
1585                 radv_save_descriptors(cmd_buffer, bind_point);
1586
1587         assert(cmd_buffer->cs->cdw <= cdw_max);
1588 }
1589
1590 static void
1591 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1592                      VkShaderStageFlags stages)
1593 {
1594         struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1595                                          ? cmd_buffer->state.compute_pipeline
1596                                          : cmd_buffer->state.pipeline;
1597         struct radv_pipeline_layout *layout = pipeline->layout;
1598         unsigned offset;
1599         void *ptr;
1600         uint64_t va;
1601
1602         stages &= cmd_buffer->push_constant_stages;
1603         if (!stages ||
1604             (!layout->push_constant_size && !layout->dynamic_offset_count))
1605                 return;
1606
1607         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1608                                           16 * layout->dynamic_offset_count,
1609                                           256, &offset, &ptr))
1610                 return;
1611
1612         memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1613         memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1614                16 * layout->dynamic_offset_count);
1615
1616         va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1617         va += offset;
1618
1619         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1620                                                            cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1621
1622         radv_foreach_stage(stage, stages) {
1623                 if (pipeline->shaders[stage]) {
1624                         radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1625                                                    AC_UD_PUSH_CONSTANTS, va);
1626                 }
1627         }
1628
1629         cmd_buffer->push_constant_stages &= ~stages;
1630         assert(cmd_buffer->cs->cdw <= cdw_max);
1631 }
1632
1633 static void
1634 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1635                               bool pipeline_is_dirty)
1636 {
1637         if ((pipeline_is_dirty ||
1638             (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1639             cmd_buffer->state.pipeline->vertex_elements.count &&
1640             radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1641                 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1642                 unsigned vb_offset;
1643                 void *vb_ptr;
1644                 uint32_t i = 0;
1645                 uint32_t count = velems->count;
1646                 uint64_t va;
1647
1648                 /* allocate some descriptor state for vertex buffers */
1649                 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1650                                                   &vb_offset, &vb_ptr))
1651                         return;
1652
1653                 for (i = 0; i < count; i++) {
1654                         uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1655                         uint32_t offset;
1656                         int vb = velems->binding[i];
1657                         struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1658                         uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1659
1660                         va = radv_buffer_get_va(buffer->bo);
1661
1662                         offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1663                         va += offset + buffer->offset;
1664                         desc[0] = va;
1665                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1666                         if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1667                                 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1668                         else
1669                                 desc[2] = buffer->size - offset;
1670                         desc[3] = velems->rsrc_word3[i];
1671                 }
1672
1673                 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1674                 va += vb_offset;
1675
1676                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1677                                            AC_UD_VS_VERTEX_BUFFERS, va);
1678
1679                 cmd_buffer->state.vb_va = va;
1680                 cmd_buffer->state.vb_size = count * 16;
1681                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1682         }
1683         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1684 }
1685
1686 static void
1687 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1688 {
1689         radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1690         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1691         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1692 }
1693
1694 static void
1695 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1696                          bool instanced_draw, bool indirect_draw,
1697                          uint32_t draw_vertex_count)
1698 {
1699         struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1700         struct radv_cmd_state *state = &cmd_buffer->state;
1701         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1702         uint32_t ia_multi_vgt_param;
1703         int32_t primitive_reset_en;
1704
1705         /* Draw state. */
1706         ia_multi_vgt_param =
1707                 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1708                                           indirect_draw, draw_vertex_count);
1709
1710         if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1711                 if (info->chip_class >= GFX9) {
1712                         radeon_set_uconfig_reg_idx(cs,
1713                                                    R_030960_IA_MULTI_VGT_PARAM,
1714                                                    4, ia_multi_vgt_param);
1715                 } else if (info->chip_class >= CIK) {
1716                         radeon_set_context_reg_idx(cs,
1717                                                    R_028AA8_IA_MULTI_VGT_PARAM,
1718                                                    1, ia_multi_vgt_param);
1719                 } else {
1720                         radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1721                                                ia_multi_vgt_param);
1722                 }
1723                 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1724         }
1725
1726         /* Primitive restart. */
1727         primitive_reset_en =
1728                 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1729
1730         if (primitive_reset_en != state->last_primitive_reset_en) {
1731                 state->last_primitive_reset_en = primitive_reset_en;
1732                 if (info->chip_class >= GFX9) {
1733                         radeon_set_uconfig_reg(cs,
1734                                                R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1735                                                primitive_reset_en);
1736                 } else {
1737                         radeon_set_context_reg(cs,
1738                                                R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1739                                                primitive_reset_en);
1740                 }
1741         }
1742
1743         if (primitive_reset_en) {
1744                 uint32_t primitive_reset_index =
1745                         state->index_type ? 0xffffffffu : 0xffffu;
1746
1747                 if (primitive_reset_index != state->last_primitive_reset_index) {
1748                         radeon_set_context_reg(cs,
1749                                                R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1750                                                primitive_reset_index);
1751                         state->last_primitive_reset_index = primitive_reset_index;
1752                 }
1753         }
1754 }
1755
1756 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1757                              VkPipelineStageFlags src_stage_mask)
1758 {
1759         if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1760                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1761                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1762                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1763                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1764         }
1765
1766         if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1767                               VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1768                               VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1769                               VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1770                               VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1771                               VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1772                               VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1773                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1774                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1775                               VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1776                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1777                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1778         } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1779                                      VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1780                                      VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1781                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1782         }
1783 }
1784
1785 static enum radv_cmd_flush_bits
1786 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1787                                   VkAccessFlags src_flags)
1788 {
1789         enum radv_cmd_flush_bits flush_bits = 0;
1790         uint32_t b;
1791         for_each_bit(b, src_flags) {
1792                 switch ((VkAccessFlagBits)(1 << b)) {
1793                 case VK_ACCESS_SHADER_WRITE_BIT:
1794                         flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1795                         break;
1796                 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1797                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1798                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1799                         break;
1800                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1801                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1802                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1803                         break;
1804                 case VK_ACCESS_TRANSFER_WRITE_BIT:
1805                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1806                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1807                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1808                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1809                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
1810                         break;
1811                 default:
1812                         break;
1813                 }
1814         }
1815         return flush_bits;
1816 }
1817
1818 static enum radv_cmd_flush_bits
1819 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1820                       VkAccessFlags dst_flags,
1821                       struct radv_image *image)
1822 {
1823         enum radv_cmd_flush_bits flush_bits = 0;
1824         uint32_t b;
1825         for_each_bit(b, dst_flags) {
1826                 switch ((VkAccessFlagBits)(1 << b)) {
1827                 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1828                 case VK_ACCESS_INDEX_READ_BIT:
1829                         break;
1830                 case VK_ACCESS_UNIFORM_READ_BIT:
1831                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1832                         break;
1833                 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1834                 case VK_ACCESS_SHADER_READ_BIT:
1835                 case VK_ACCESS_TRANSFER_READ_BIT:
1836                 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1837                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1838                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
1839                         break;
1840                 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1841                         /* TODO: change to image && when the image gets passed
1842                          * through from the subpass. */
1843                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1844                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1845                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1846                         break;
1847                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1848                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1849                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1850                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1851                         break;
1852                 default:
1853                         break;
1854                 }
1855         }
1856         return flush_bits;
1857 }
1858
1859 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1860 {
1861         cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1862         radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1863         cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1864                                                               NULL);
1865 }
1866
1867 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1868                                                  VkAttachmentReference att)
1869 {
1870         unsigned idx = att.attachment;
1871         struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1872         VkImageSubresourceRange range;
1873         range.aspectMask = 0;
1874         range.baseMipLevel = view->base_mip;
1875         range.levelCount = 1;
1876         range.baseArrayLayer = view->base_layer;
1877         range.layerCount = cmd_buffer->state.framebuffer->layers;
1878
1879         radv_handle_image_transition(cmd_buffer,
1880                                      view->image,
1881                                      cmd_buffer->state.attachments[idx].current_layout,
1882                                      att.layout, 0, 0, &range,
1883                                      cmd_buffer->state.attachments[idx].pending_clear_aspects);
1884
1885         cmd_buffer->state.attachments[idx].current_layout = att.layout;
1886
1887
1888 }
1889
1890 void
1891 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1892                             const struct radv_subpass *subpass, bool transitions)
1893 {
1894         if (transitions) {
1895                 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1896
1897                 for (unsigned i = 0; i < subpass->color_count; ++i) {
1898                         if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1899                                 radv_handle_subpass_image_transition(cmd_buffer,
1900                                                                      subpass->color_attachments[i]);
1901                 }
1902
1903                 for (unsigned i = 0; i < subpass->input_count; ++i) {
1904                         radv_handle_subpass_image_transition(cmd_buffer,
1905                                                         subpass->input_attachments[i]);
1906                 }
1907
1908                 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1909                         radv_handle_subpass_image_transition(cmd_buffer,
1910                                                         subpass->depth_stencil_attachment);
1911                 }
1912         }
1913
1914         cmd_buffer->state.subpass = subpass;
1915
1916         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
1917 }
1918
1919 static VkResult
1920 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1921                                  struct radv_render_pass *pass,
1922                                  const VkRenderPassBeginInfo *info)
1923 {
1924         struct radv_cmd_state *state = &cmd_buffer->state;
1925
1926         if (pass->attachment_count == 0) {
1927                 state->attachments = NULL;
1928                 return VK_SUCCESS;
1929         }
1930
1931         state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1932                                         pass->attachment_count *
1933                                         sizeof(state->attachments[0]),
1934                                         8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1935         if (state->attachments == NULL) {
1936                 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1937                 return cmd_buffer->record_result;
1938         }
1939
1940         for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1941                 struct radv_render_pass_attachment *att = &pass->attachments[i];
1942                 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1943                 VkImageAspectFlags clear_aspects = 0;
1944
1945                 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1946                         /* color attachment */
1947                         if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1948                                 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1949                         }
1950                 } else {
1951                         /* depthstencil attachment */
1952                         if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1953                             att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1954                                 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1955                                 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1956                                     att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1957                                         clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1958                         }
1959                         if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1960                             att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1961                                 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1962                         }
1963                 }
1964
1965                 state->attachments[i].pending_clear_aspects = clear_aspects;
1966                 state->attachments[i].cleared_views = 0;
1967                 if (clear_aspects && info) {
1968                         assert(info->clearValueCount > i);
1969                         state->attachments[i].clear_value = info->pClearValues[i];
1970                 }
1971
1972                 state->attachments[i].current_layout = att->initial_layout;
1973         }
1974
1975         return VK_SUCCESS;
1976 }
1977
1978 VkResult radv_AllocateCommandBuffers(
1979         VkDevice _device,
1980         const VkCommandBufferAllocateInfo *pAllocateInfo,
1981         VkCommandBuffer *pCommandBuffers)
1982 {
1983         RADV_FROM_HANDLE(radv_device, device, _device);
1984         RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1985
1986         VkResult result = VK_SUCCESS;
1987         uint32_t i;
1988
1989         for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1990
1991                 if (!list_empty(&pool->free_cmd_buffers)) {
1992                         struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1993
1994                         list_del(&cmd_buffer->pool_link);
1995                         list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1996
1997                         result = radv_reset_cmd_buffer(cmd_buffer);
1998                         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1999                         cmd_buffer->level = pAllocateInfo->level;
2000
2001                         pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2002                 } else {
2003                         result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2004                                                         &pCommandBuffers[i]);
2005                 }
2006                 if (result != VK_SUCCESS)
2007                         break;
2008         }
2009
2010         if (result != VK_SUCCESS) {
2011                 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2012                                         i, pCommandBuffers);
2013
2014                 /* From the Vulkan 1.0.66 spec:
2015                  *
2016                  * "vkAllocateCommandBuffers can be used to create multiple
2017                  *  command buffers. If the creation of any of those command
2018                  *  buffers fails, the implementation must destroy all
2019                  *  successfully created command buffer objects from this
2020                  *  command, set all entries of the pCommandBuffers array to
2021                  *  NULL and return the error."
2022                  */
2023                 memset(pCommandBuffers, 0,
2024                        sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2025         }
2026
2027         return result;
2028 }
2029
2030 void radv_FreeCommandBuffers(
2031         VkDevice device,
2032         VkCommandPool commandPool,
2033         uint32_t commandBufferCount,
2034         const VkCommandBuffer *pCommandBuffers)
2035 {
2036         for (uint32_t i = 0; i < commandBufferCount; i++) {
2037                 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2038
2039                 if (cmd_buffer) {
2040                         if (cmd_buffer->pool) {
2041                                 list_del(&cmd_buffer->pool_link);
2042                                 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2043                         } else
2044                                 radv_cmd_buffer_destroy(cmd_buffer);
2045
2046                 }
2047         }
2048 }
2049
2050 VkResult radv_ResetCommandBuffer(
2051         VkCommandBuffer commandBuffer,
2052         VkCommandBufferResetFlags flags)
2053 {
2054         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2055         return radv_reset_cmd_buffer(cmd_buffer);
2056 }
2057
2058 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2059 {
2060         struct radv_device *device = cmd_buffer->device;
2061         if (device->gfx_init) {
2062                 uint64_t va = radv_buffer_get_va(device->gfx_init);
2063                 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2064                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2065                 radeon_emit(cmd_buffer->cs, va);
2066                 radeon_emit(cmd_buffer->cs, va >> 32);
2067                 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2068         } else
2069                 si_init_config(cmd_buffer);
2070 }
2071
2072 VkResult radv_BeginCommandBuffer(
2073         VkCommandBuffer commandBuffer,
2074         const VkCommandBufferBeginInfo *pBeginInfo)
2075 {
2076         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2077         VkResult result = VK_SUCCESS;
2078
2079         if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2080                 /* If the command buffer has already been resetted with
2081                  * vkResetCommandBuffer, no need to do it again.
2082                  */
2083                 result = radv_reset_cmd_buffer(cmd_buffer);
2084                 if (result != VK_SUCCESS)
2085                         return result;
2086         }
2087
2088         memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2089         cmd_buffer->state.last_primitive_reset_en = -1;
2090         cmd_buffer->state.last_index_type = -1;
2091         cmd_buffer->state.last_num_instances = -1;
2092         cmd_buffer->state.last_vertex_offset = -1;
2093         cmd_buffer->state.last_first_instance = -1;
2094         cmd_buffer->usage_flags = pBeginInfo->flags;
2095
2096         /* setup initial configuration into command buffer */
2097         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2098                 switch (cmd_buffer->queue_family_index) {
2099                 case RADV_QUEUE_GENERAL:
2100                         emit_gfx_buffer_state(cmd_buffer);
2101                         break;
2102                 case RADV_QUEUE_COMPUTE:
2103                         si_init_compute(cmd_buffer);
2104                         break;
2105                 case RADV_QUEUE_TRANSFER:
2106                 default:
2107                         break;
2108                 }
2109         }
2110
2111         if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2112                 assert(pBeginInfo->pInheritanceInfo);
2113                 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2114                 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2115
2116                 struct radv_subpass *subpass =
2117                         &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2118
2119                 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2120                 if (result != VK_SUCCESS)
2121                         return result;
2122
2123                 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2124         }
2125
2126         if (unlikely(cmd_buffer->device->trace_bo))
2127                 radv_cmd_buffer_trace_emit(cmd_buffer);
2128
2129         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2130
2131         return result;
2132 }
2133
2134 void radv_CmdBindVertexBuffers(
2135         VkCommandBuffer                             commandBuffer,
2136         uint32_t                                    firstBinding,
2137         uint32_t                                    bindingCount,
2138         const VkBuffer*                             pBuffers,
2139         const VkDeviceSize*                         pOffsets)
2140 {
2141         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2142         struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2143         bool changed = false;
2144
2145         /* We have to defer setting up vertex buffer since we need the buffer
2146          * stride from the pipeline. */
2147
2148         assert(firstBinding + bindingCount <= MAX_VBS);
2149         for (uint32_t i = 0; i < bindingCount; i++) {
2150                 uint32_t idx = firstBinding + i;
2151
2152                 if (!changed &&
2153                     (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2154                      vb[idx].offset != pOffsets[i])) {
2155                         changed = true;
2156                 }
2157
2158                 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2159                 vb[idx].offset = pOffsets[i];
2160
2161                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2162                                    vb[idx].buffer->bo, 8);
2163         }
2164
2165         if (!changed) {
2166                 /* No state changes. */
2167                 return;
2168         }
2169
2170         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2171 }
2172
2173 void radv_CmdBindIndexBuffer(
2174         VkCommandBuffer                             commandBuffer,
2175         VkBuffer buffer,
2176         VkDeviceSize offset,
2177         VkIndexType indexType)
2178 {
2179         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2180         RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2181
2182         if (cmd_buffer->state.index_buffer == index_buffer &&
2183             cmd_buffer->state.index_offset == offset &&
2184             cmd_buffer->state.index_type == indexType) {
2185                 /* No state changes. */
2186                 return;
2187         }
2188
2189         cmd_buffer->state.index_buffer = index_buffer;
2190         cmd_buffer->state.index_offset = offset;
2191         cmd_buffer->state.index_type = indexType; /* vk matches hw */
2192         cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2193         cmd_buffer->state.index_va += index_buffer->offset + offset;
2194
2195         int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2196         cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2197         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2198         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2199 }
2200
2201
2202 static void
2203 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2204                          VkPipelineBindPoint bind_point,
2205                          struct radv_descriptor_set *set, unsigned idx)
2206 {
2207         struct radeon_winsys *ws = cmd_buffer->device->ws;
2208
2209         radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2210         if (!set)
2211                 return;
2212
2213         assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2214
2215         if (!cmd_buffer->device->use_global_bo_list) {
2216                 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2217                         if (set->descriptors[j])
2218                                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2219         }
2220
2221         if(set->bo)
2222                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2223 }
2224
2225 void radv_CmdBindDescriptorSets(
2226         VkCommandBuffer                             commandBuffer,
2227         VkPipelineBindPoint                         pipelineBindPoint,
2228         VkPipelineLayout                            _layout,
2229         uint32_t                                    firstSet,
2230         uint32_t                                    descriptorSetCount,
2231         const VkDescriptorSet*                      pDescriptorSets,
2232         uint32_t                                    dynamicOffsetCount,
2233         const uint32_t*                             pDynamicOffsets)
2234 {
2235         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2236         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2237         unsigned dyn_idx = 0;
2238
2239         const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2240
2241         for (unsigned i = 0; i < descriptorSetCount; ++i) {
2242                 unsigned idx = i + firstSet;
2243                 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2244                 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2245
2246                 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2247                         unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2248                         uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2249                         assert(dyn_idx < dynamicOffsetCount);
2250
2251                         struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2252                         uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2253                         dst[0] = va;
2254                         dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2255                         dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2256                         dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2257                                  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2258                                  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2259                                  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2260                                  S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2261                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2262                         cmd_buffer->push_constant_stages |=
2263                                              set->layout->dynamic_shader_stages;
2264                 }
2265         }
2266 }
2267
2268 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2269                                           struct radv_descriptor_set *set,
2270                                           struct radv_descriptor_set_layout *layout,
2271                                           VkPipelineBindPoint bind_point)
2272 {
2273         struct radv_descriptor_state *descriptors_state =
2274                 radv_get_descriptors_state(cmd_buffer, bind_point);
2275         set->size = layout->size;
2276         set->layout = layout;
2277
2278         if (descriptors_state->push_set.capacity < set->size) {
2279                 size_t new_size = MAX2(set->size, 1024);
2280                 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2281                 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2282
2283                 free(set->mapped_ptr);
2284                 set->mapped_ptr = malloc(new_size);
2285
2286                 if (!set->mapped_ptr) {
2287                         descriptors_state->push_set.capacity = 0;
2288                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2289                         return false;
2290                 }
2291
2292                 descriptors_state->push_set.capacity = new_size;
2293         }
2294
2295         return true;
2296 }
2297
2298 void radv_meta_push_descriptor_set(
2299         struct radv_cmd_buffer*              cmd_buffer,
2300         VkPipelineBindPoint                  pipelineBindPoint,
2301         VkPipelineLayout                     _layout,
2302         uint32_t                             set,
2303         uint32_t                             descriptorWriteCount,
2304         const VkWriteDescriptorSet*          pDescriptorWrites)
2305 {
2306         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2307         struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2308         unsigned bo_offset;
2309
2310         assert(set == 0);
2311         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2312
2313         push_set->size = layout->set[set].layout->size;
2314         push_set->layout = layout->set[set].layout;
2315
2316         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2317                                           &bo_offset,
2318                                           (void**) &push_set->mapped_ptr))
2319                 return;
2320
2321         push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2322         push_set->va += bo_offset;
2323
2324         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2325                                     radv_descriptor_set_to_handle(push_set),
2326                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2327
2328         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2329 }
2330
2331 void radv_CmdPushDescriptorSetKHR(
2332         VkCommandBuffer                             commandBuffer,
2333         VkPipelineBindPoint                         pipelineBindPoint,
2334         VkPipelineLayout                            _layout,
2335         uint32_t                                    set,
2336         uint32_t                                    descriptorWriteCount,
2337         const VkWriteDescriptorSet*                 pDescriptorWrites)
2338 {
2339         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2340         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2341         struct radv_descriptor_state *descriptors_state =
2342                 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2343         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2344
2345         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2346
2347         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2348                                            layout->set[set].layout,
2349                                            pipelineBindPoint))
2350                 return;
2351
2352         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2353                                     radv_descriptor_set_to_handle(push_set),
2354                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2355
2356         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2357         descriptors_state->push_dirty = true;
2358 }
2359
2360 void radv_CmdPushDescriptorSetWithTemplateKHR(
2361         VkCommandBuffer                             commandBuffer,
2362         VkDescriptorUpdateTemplateKHR               descriptorUpdateTemplate,
2363         VkPipelineLayout                            _layout,
2364         uint32_t                                    set,
2365         const void*                                 pData)
2366 {
2367         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2368         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2369         RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2370         struct radv_descriptor_state *descriptors_state =
2371                 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2372         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2373
2374         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2375
2376         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2377                                            layout->set[set].layout,
2378                                            templ->bind_point))
2379                 return;
2380
2381         radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2382                                                  descriptorUpdateTemplate, pData);
2383
2384         radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2385         descriptors_state->push_dirty = true;
2386 }
2387
2388 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2389                            VkPipelineLayout layout,
2390                            VkShaderStageFlags stageFlags,
2391                            uint32_t offset,
2392                            uint32_t size,
2393                            const void* pValues)
2394 {
2395         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2396         memcpy(cmd_buffer->push_constants + offset, pValues, size);
2397         cmd_buffer->push_constant_stages |= stageFlags;
2398 }
2399
2400 VkResult radv_EndCommandBuffer(
2401         VkCommandBuffer                             commandBuffer)
2402 {
2403         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2404
2405         if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2406                 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2407                         cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2408                 si_emit_cache_flush(cmd_buffer);
2409         }
2410
2411         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2412
2413         if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2414                 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2415
2416         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2417
2418         return cmd_buffer->record_result;
2419 }
2420
2421 static void
2422 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2423 {
2424         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2425
2426         if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2427                 return;
2428
2429         cmd_buffer->state.emitted_compute_pipeline = pipeline;
2430
2431         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2432         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2433
2434         cmd_buffer->compute_scratch_size_needed =
2435                                   MAX2(cmd_buffer->compute_scratch_size_needed,
2436                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2437
2438         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2439                            pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
2440
2441         if (unlikely(cmd_buffer->device->trace_bo))
2442                 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2443 }
2444
2445 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2446                                             VkPipelineBindPoint bind_point)
2447 {
2448         struct radv_descriptor_state *descriptors_state =
2449                 radv_get_descriptors_state(cmd_buffer, bind_point);
2450
2451         descriptors_state->dirty |= descriptors_state->valid;
2452 }
2453
2454 void radv_CmdBindPipeline(
2455         VkCommandBuffer                             commandBuffer,
2456         VkPipelineBindPoint                         pipelineBindPoint,
2457         VkPipeline                                  _pipeline)
2458 {
2459         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2460         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2461
2462         switch (pipelineBindPoint) {
2463         case VK_PIPELINE_BIND_POINT_COMPUTE:
2464                 if (cmd_buffer->state.compute_pipeline == pipeline)
2465                         return;
2466                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2467
2468                 cmd_buffer->state.compute_pipeline = pipeline;
2469                 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2470                 break;
2471         case VK_PIPELINE_BIND_POINT_GRAPHICS:
2472                 if (cmd_buffer->state.pipeline == pipeline)
2473                         return;
2474                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2475
2476                 cmd_buffer->state.pipeline = pipeline;
2477                 if (!pipeline)
2478                         break;
2479
2480                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2481                 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2482
2483                 /* the new vertex shader might not have the same user regs */
2484                 cmd_buffer->state.last_first_instance = -1;
2485                 cmd_buffer->state.last_vertex_offset = -1;
2486
2487                 /* Prefetch all pipeline shaders at first draw time. */
2488                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2489
2490                 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2491
2492                 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2493                         cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2494                 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2495                         cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2496
2497                 if (radv_pipeline_has_tess(pipeline))
2498                         cmd_buffer->tess_rings_needed = true;
2499
2500                 if (radv_pipeline_has_gs(pipeline)) {
2501                         struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2502                                                                              AC_UD_SCRATCH_RING_OFFSETS);
2503                         if (cmd_buffer->ring_offsets_idx == -1)
2504                                 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2505                         else if (loc->sgpr_idx != -1)
2506                                 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2507                 }
2508                 break;
2509         default:
2510                 assert(!"invalid bind point");
2511                 break;
2512         }
2513 }
2514
2515 void radv_CmdSetViewport(
2516         VkCommandBuffer                             commandBuffer,
2517         uint32_t                                    firstViewport,
2518         uint32_t                                    viewportCount,
2519         const VkViewport*                           pViewports)
2520 {
2521         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2522         struct radv_cmd_state *state = &cmd_buffer->state;
2523         MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2524
2525         assert(firstViewport < MAX_VIEWPORTS);
2526         assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2527
2528         memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2529                viewportCount * sizeof(*pViewports));
2530
2531         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2532 }
2533
2534 void radv_CmdSetScissor(
2535         VkCommandBuffer                             commandBuffer,
2536         uint32_t                                    firstScissor,
2537         uint32_t                                    scissorCount,
2538         const VkRect2D*                             pScissors)
2539 {
2540         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2541         struct radv_cmd_state *state = &cmd_buffer->state;
2542         MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2543
2544         assert(firstScissor < MAX_SCISSORS);
2545         assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2546
2547         memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2548                scissorCount * sizeof(*pScissors));
2549
2550         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2551 }
2552
2553 void radv_CmdSetLineWidth(
2554         VkCommandBuffer                             commandBuffer,
2555         float                                       lineWidth)
2556 {
2557         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2558         cmd_buffer->state.dynamic.line_width = lineWidth;
2559         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2560 }
2561
2562 void radv_CmdSetDepthBias(
2563         VkCommandBuffer                             commandBuffer,
2564         float                                       depthBiasConstantFactor,
2565         float                                       depthBiasClamp,
2566         float                                       depthBiasSlopeFactor)
2567 {
2568         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2569
2570         cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2571         cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2572         cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2573
2574         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2575 }
2576
2577 void radv_CmdSetBlendConstants(
2578         VkCommandBuffer                             commandBuffer,
2579         const float                                 blendConstants[4])
2580 {
2581         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2582
2583         memcpy(cmd_buffer->state.dynamic.blend_constants,
2584                blendConstants, sizeof(float) * 4);
2585
2586         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2587 }
2588
2589 void radv_CmdSetDepthBounds(
2590         VkCommandBuffer                             commandBuffer,
2591         float                                       minDepthBounds,
2592         float                                       maxDepthBounds)
2593 {
2594         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2595
2596         cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2597         cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2598
2599         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2600 }
2601
2602 void radv_CmdSetStencilCompareMask(
2603         VkCommandBuffer                             commandBuffer,
2604         VkStencilFaceFlags                          faceMask,
2605         uint32_t                                    compareMask)
2606 {
2607         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2608
2609         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2610                 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2611         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2612                 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2613
2614         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2615 }
2616
2617 void radv_CmdSetStencilWriteMask(
2618         VkCommandBuffer                             commandBuffer,
2619         VkStencilFaceFlags                          faceMask,
2620         uint32_t                                    writeMask)
2621 {
2622         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2623
2624         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2625                 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2626         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2627                 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2628
2629         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2630 }
2631
2632 void radv_CmdSetStencilReference(
2633         VkCommandBuffer                             commandBuffer,
2634         VkStencilFaceFlags                          faceMask,
2635         uint32_t                                    reference)
2636 {
2637         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2638
2639         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2640                 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2641         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2642                 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2643
2644         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2645 }
2646
2647 void radv_CmdSetDiscardRectangleEXT(
2648         VkCommandBuffer                             commandBuffer,
2649         uint32_t                                    firstDiscardRectangle,
2650         uint32_t                                    discardRectangleCount,
2651         const VkRect2D*                             pDiscardRectangles)
2652 {
2653         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2654         struct radv_cmd_state *state = &cmd_buffer->state;
2655         MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2656
2657         assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2658         assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2659
2660         typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2661                      pDiscardRectangles, discardRectangleCount);
2662
2663         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2664 }
2665
2666 void radv_CmdExecuteCommands(
2667         VkCommandBuffer                             commandBuffer,
2668         uint32_t                                    commandBufferCount,
2669         const VkCommandBuffer*                      pCmdBuffers)
2670 {
2671         RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2672
2673         assert(commandBufferCount > 0);
2674
2675         /* Emit pending flushes on primary prior to executing secondary */
2676         si_emit_cache_flush(primary);
2677
2678         for (uint32_t i = 0; i < commandBufferCount; i++) {
2679                 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2680
2681                 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2682                                                     secondary->scratch_size_needed);
2683                 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2684                                                             secondary->compute_scratch_size_needed);
2685
2686                 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2687                         primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2688                 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2689                         primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2690                 if (secondary->tess_rings_needed)
2691                         primary->tess_rings_needed = true;
2692                 if (secondary->sample_positions_needed)
2693                         primary->sample_positions_needed = true;
2694
2695                 if (secondary->ring_offsets_idx != -1) {
2696                         if (primary->ring_offsets_idx == -1)
2697                                 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2698                         else
2699                                 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2700                 }
2701                 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2702
2703
2704                 /* When the secondary command buffer is compute only we don't
2705                  * need to re-emit the current graphics pipeline.
2706                  */
2707                 if (secondary->state.emitted_pipeline) {
2708                         primary->state.emitted_pipeline =
2709                                 secondary->state.emitted_pipeline;
2710                 }
2711
2712                 /* When the secondary command buffer is graphics only we don't
2713                  * need to re-emit the current compute pipeline.
2714                  */
2715                 if (secondary->state.emitted_compute_pipeline) {
2716                         primary->state.emitted_compute_pipeline =
2717                                 secondary->state.emitted_compute_pipeline;
2718                 }
2719
2720                 /* Only re-emit the draw packets when needed. */
2721                 if (secondary->state.last_primitive_reset_en != -1) {
2722                         primary->state.last_primitive_reset_en =
2723                                 secondary->state.last_primitive_reset_en;
2724                 }
2725
2726                 if (secondary->state.last_primitive_reset_index) {
2727                         primary->state.last_primitive_reset_index =
2728                                 secondary->state.last_primitive_reset_index;
2729                 }
2730
2731                 if (secondary->state.last_ia_multi_vgt_param) {
2732                         primary->state.last_ia_multi_vgt_param =
2733                                 secondary->state.last_ia_multi_vgt_param;
2734                 }
2735
2736                 primary->state.last_first_instance = secondary->state.last_first_instance;
2737                 primary->state.last_num_instances = secondary->state.last_num_instances;
2738                 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2739
2740                 if (secondary->state.last_index_type != -1) {
2741                         primary->state.last_index_type =
2742                                 secondary->state.last_index_type;
2743                 }
2744         }
2745
2746         /* After executing commands from secondary buffers we have to dirty
2747          * some states.
2748          */
2749         primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2750                                 RADV_CMD_DIRTY_INDEX_BUFFER |
2751                                 RADV_CMD_DIRTY_DYNAMIC_ALL;
2752         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2753         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2754 }
2755
2756 VkResult radv_CreateCommandPool(
2757         VkDevice                                    _device,
2758         const VkCommandPoolCreateInfo*              pCreateInfo,
2759         const VkAllocationCallbacks*                pAllocator,
2760         VkCommandPool*                              pCmdPool)
2761 {
2762         RADV_FROM_HANDLE(radv_device, device, _device);
2763         struct radv_cmd_pool *pool;
2764
2765         pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2766                            VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2767         if (pool == NULL)
2768                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2769
2770         if (pAllocator)
2771                 pool->alloc = *pAllocator;
2772         else
2773                 pool->alloc = device->alloc;
2774
2775         list_inithead(&pool->cmd_buffers);
2776         list_inithead(&pool->free_cmd_buffers);
2777
2778         pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2779
2780         *pCmdPool = radv_cmd_pool_to_handle(pool);
2781
2782         return VK_SUCCESS;
2783
2784 }
2785
2786 void radv_DestroyCommandPool(
2787         VkDevice                                    _device,
2788         VkCommandPool                               commandPool,
2789         const VkAllocationCallbacks*                pAllocator)
2790 {
2791         RADV_FROM_HANDLE(radv_device, device, _device);
2792         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2793
2794         if (!pool)
2795                 return;
2796
2797         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2798                                  &pool->cmd_buffers, pool_link) {
2799                 radv_cmd_buffer_destroy(cmd_buffer);
2800         }
2801
2802         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2803                                  &pool->free_cmd_buffers, pool_link) {
2804                 radv_cmd_buffer_destroy(cmd_buffer);
2805         }
2806
2807         vk_free2(&device->alloc, pAllocator, pool);
2808 }
2809
2810 VkResult radv_ResetCommandPool(
2811         VkDevice                                    device,
2812         VkCommandPool                               commandPool,
2813         VkCommandPoolResetFlags                     flags)
2814 {
2815         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2816         VkResult result;
2817
2818         list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2819                             &pool->cmd_buffers, pool_link) {
2820                 result = radv_reset_cmd_buffer(cmd_buffer);
2821                 if (result != VK_SUCCESS)
2822                         return result;
2823         }
2824
2825         return VK_SUCCESS;
2826 }
2827
2828 void radv_TrimCommandPool(
2829     VkDevice                                    device,
2830     VkCommandPool                               commandPool,
2831     VkCommandPoolTrimFlagsKHR                   flags)
2832 {
2833         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2834
2835         if (!pool)
2836                 return;
2837
2838         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2839                                  &pool->free_cmd_buffers, pool_link) {
2840                 radv_cmd_buffer_destroy(cmd_buffer);
2841         }
2842 }
2843
2844 void radv_CmdBeginRenderPass(
2845         VkCommandBuffer                             commandBuffer,
2846         const VkRenderPassBeginInfo*                pRenderPassBegin,
2847         VkSubpassContents                           contents)
2848 {
2849         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2850         RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2851         RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2852
2853         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2854                                                            cmd_buffer->cs, 2048);
2855         MAYBE_UNUSED VkResult result;
2856
2857         cmd_buffer->state.framebuffer = framebuffer;
2858         cmd_buffer->state.pass = pass;
2859         cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2860
2861         result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2862         if (result != VK_SUCCESS)
2863                 return;
2864
2865         radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2866         assert(cmd_buffer->cs->cdw <= cdw_max);
2867
2868         radv_cmd_buffer_clear_subpass(cmd_buffer);
2869 }
2870
2871 void radv_CmdNextSubpass(
2872     VkCommandBuffer                             commandBuffer,
2873     VkSubpassContents                           contents)
2874 {
2875         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2876
2877         radv_cmd_buffer_resolve_subpass(cmd_buffer);
2878
2879         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2880                                               2048);
2881
2882         radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2883         radv_cmd_buffer_clear_subpass(cmd_buffer);
2884 }
2885
2886 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2887 {
2888         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2889         for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2890                 if (!pipeline->shaders[stage])
2891                         continue;
2892                 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2893                 if (loc->sgpr_idx == -1)
2894                         continue;
2895                 uint32_t base_reg = pipeline->user_data_0[stage];
2896                 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2897
2898         }
2899         if (pipeline->gs_copy_shader) {
2900                 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2901                 if (loc->sgpr_idx != -1) {
2902                         uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2903                         radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2904                 }
2905         }
2906 }
2907
2908 static void
2909 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2910                          uint32_t vertex_count)
2911 {
2912         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2913         radeon_emit(cmd_buffer->cs, vertex_count);
2914         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2915                                     S_0287F0_USE_OPAQUE(0));
2916 }
2917
2918 static void
2919 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2920                                  uint64_t index_va,
2921                                  uint32_t index_count)
2922 {
2923         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2924         radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2925         radeon_emit(cmd_buffer->cs, index_va);
2926         radeon_emit(cmd_buffer->cs, index_va >> 32);
2927         radeon_emit(cmd_buffer->cs, index_count);
2928         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2929 }
2930
2931 static void
2932 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2933                                   bool indexed,
2934                                   uint32_t draw_count,
2935                                   uint64_t count_va,
2936                                   uint32_t stride)
2937 {
2938         struct radeon_winsys_cs *cs = cmd_buffer->cs;
2939         unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2940                                       : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2941         bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
2942         uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2943         assert(base_reg);
2944
2945         /* just reset draw state for vertex data */
2946         cmd_buffer->state.last_first_instance = -1;
2947         cmd_buffer->state.last_num_instances = -1;
2948         cmd_buffer->state.last_vertex_offset = -1;
2949
2950         if (draw_count == 1 && !count_va && !draw_id_enable) {
2951                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2952                                      PKT3_DRAW_INDIRECT, 3, false));
2953                 radeon_emit(cs, 0);
2954                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2955                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2956                 radeon_emit(cs, di_src_sel);
2957         } else {
2958                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2959                                      PKT3_DRAW_INDIRECT_MULTI,
2960                                      8, false));
2961                 radeon_emit(cs, 0);
2962                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2963                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2964                 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2965                             S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2966                             S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2967                 radeon_emit(cs, draw_count); /* count */
2968                 radeon_emit(cs, count_va); /* count_addr */
2969                 radeon_emit(cs, count_va >> 32);
2970                 radeon_emit(cs, stride); /* stride */
2971                 radeon_emit(cs, di_src_sel);
2972         }
2973 }
2974
2975 struct radv_draw_info {
2976         /**
2977          * Number of vertices.
2978          */
2979         uint32_t count;
2980
2981         /**
2982          * Index of the first vertex.
2983          */
2984         int32_t vertex_offset;
2985
2986         /**
2987          * First instance id.
2988          */
2989         uint32_t first_instance;
2990
2991         /**
2992          * Number of instances.
2993          */
2994         uint32_t instance_count;
2995
2996         /**
2997          * First index (indexed draws only).
2998          */
2999         uint32_t first_index;
3000
3001         /**
3002          * Whether it's an indexed draw.
3003          */
3004         bool indexed;
3005
3006         /**
3007          * Indirect draw parameters resource.
3008          */
3009         struct radv_buffer *indirect;
3010         uint64_t indirect_offset;
3011         uint32_t stride;
3012
3013         /**
3014          * Draw count parameters resource.
3015          */
3016         struct radv_buffer *count_buffer;
3017         uint64_t count_buffer_offset;
3018 };
3019
3020 static void
3021 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3022                        const struct radv_draw_info *info)
3023 {
3024         struct radv_cmd_state *state = &cmd_buffer->state;
3025         struct radeon_winsys *ws = cmd_buffer->device->ws;
3026         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3027
3028         if (info->indirect) {
3029                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3030                 uint64_t count_va = 0;
3031
3032                 va += info->indirect->offset + info->indirect_offset;
3033
3034                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3035
3036                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3037                 radeon_emit(cs, 1);
3038                 radeon_emit(cs, va);
3039                 radeon_emit(cs, va >> 32);
3040
3041                 if (info->count_buffer) {
3042                         count_va = radv_buffer_get_va(info->count_buffer->bo);
3043                         count_va += info->count_buffer->offset +
3044                                     info->count_buffer_offset;
3045
3046                         radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3047                 }
3048
3049                 if (!state->subpass->view_mask) {
3050                         radv_cs_emit_indirect_draw_packet(cmd_buffer,
3051                                                           info->indexed,
3052                                                           info->count,
3053                                                           count_va,
3054                                                           info->stride);
3055                 } else {
3056                         unsigned i;
3057                         for_each_bit(i, state->subpass->view_mask) {
3058                                 radv_emit_view_index(cmd_buffer, i);
3059
3060                                 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3061                                                                   info->indexed,
3062                                                                   info->count,
3063                                                                   count_va,
3064                                                                   info->stride);
3065                         }
3066                 }
3067         } else {
3068                 assert(state->pipeline->graphics.vtx_base_sgpr);
3069
3070                 if (info->vertex_offset != state->last_vertex_offset ||
3071                     info->first_instance != state->last_first_instance) {
3072                         radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3073                                               state->pipeline->graphics.vtx_emit_num);
3074
3075                         radeon_emit(cs, info->vertex_offset);
3076                         radeon_emit(cs, info->first_instance);
3077                         if (state->pipeline->graphics.vtx_emit_num == 3)
3078                                 radeon_emit(cs, 0);
3079                         state->last_first_instance = info->first_instance;
3080                         state->last_vertex_offset = info->vertex_offset;
3081                 }
3082
3083                 if (state->last_num_instances != info->instance_count) {
3084                         radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3085                         radeon_emit(cs, info->instance_count);
3086                         state->last_num_instances = info->instance_count;
3087                 }
3088
3089                 if (info->indexed) {
3090                         int index_size = state->index_type ? 4 : 2;
3091                         uint64_t index_va;
3092
3093                         index_va = state->index_va;
3094                         index_va += info->first_index * index_size;
3095
3096                         if (!state->subpass->view_mask) {
3097                                 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3098                                                                  index_va,
3099                                                                  info->count);
3100                         } else {
3101                                 unsigned i;
3102                                 for_each_bit(i, state->subpass->view_mask) {
3103                                         radv_emit_view_index(cmd_buffer, i);
3104
3105                                         radv_cs_emit_draw_indexed_packet(cmd_buffer,
3106                                                                          index_va,
3107                                                                          info->count);
3108                                 }
3109                         }
3110                 } else {
3111                         if (!state->subpass->view_mask) {
3112                                 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3113                         } else {
3114                                 unsigned i;
3115                                 for_each_bit(i, state->subpass->view_mask) {
3116                                         radv_emit_view_index(cmd_buffer, i);
3117
3118                                         radv_cs_emit_draw_packet(cmd_buffer,
3119                                                                  info->count);
3120                                 }
3121                         }
3122                 }
3123         }
3124 }
3125
3126 /*
3127  * Vega and raven have a bug which triggers if there are multiple context
3128  * register contexts active at the same time with different scissor values.
3129  *
3130  * There are two possible workarounds:
3131  * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3132  *    there is only ever 1 active set of scissor values at the same time.
3133  *
3134  * 2) Whenever the hardware switches contexts we have to set the scissor
3135  *    registers again even if it is a noop. That way the new context gets
3136  *    the correct scissor values.
3137  *
3138  * This implements option 2. radv_need_late_scissor_emission needs to
3139  * return true on affected HW if radv_emit_all_graphics_states sets
3140  * any context registers.
3141  */
3142 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3143                                             bool indexed_draw)
3144 {
3145         struct radv_cmd_state *state = &cmd_buffer->state;
3146
3147         if (!cmd_buffer->device->physical_device->has_scissor_bug)
3148                 return false;
3149
3150         /* Assume all state changes except  these two can imply context rolls. */
3151         if (cmd_buffer->state.dirty & ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3152                                         RADV_CMD_DIRTY_VERTEX_BUFFER |
3153                                         RADV_CMD_DIRTY_PIPELINE))
3154                 return true;
3155
3156         if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3157                 return true;
3158
3159         if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3160             (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3161                 return true;
3162
3163         return false;
3164 }
3165
3166 static void
3167 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3168                               const struct radv_draw_info *info)
3169 {
3170         bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3171
3172         if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3173             cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3174                 radv_emit_rbplus_state(cmd_buffer);
3175
3176         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3177                 radv_emit_graphics_pipeline(cmd_buffer);
3178
3179         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3180                 radv_emit_framebuffer_state(cmd_buffer);
3181
3182         if (info->indexed) {
3183                 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3184                         radv_emit_index_buffer(cmd_buffer);
3185         } else {
3186                 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3187                  * so the state must be re-emitted before the next indexed
3188                  * draw.
3189                  */
3190                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3191                         cmd_buffer->state.last_index_type = -1;
3192                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3193                 }
3194         }
3195
3196         radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3197
3198         radv_emit_draw_registers(cmd_buffer, info->indexed,
3199                                  info->instance_count > 1, info->indirect,
3200                                  info->indirect ? 0 : info->count);
3201
3202         if (late_scissor_emission)
3203                 radv_emit_scissor(cmd_buffer);
3204 }
3205
3206 static void
3207 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3208           const struct radv_draw_info *info)
3209 {
3210         bool has_prefetch =
3211                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3212         bool pipeline_is_dirty =
3213                 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3214                 cmd_buffer->state.pipeline &&
3215                 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3216
3217         MAYBE_UNUSED unsigned cdw_max =
3218                 radeon_check_space(cmd_buffer->device->ws,
3219                                    cmd_buffer->cs, 4096);
3220
3221         /* Use optimal packet order based on whether we need to sync the
3222          * pipeline.
3223          */
3224         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3225                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3226                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3227                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3228                 /* If we have to wait for idle, set all states first, so that
3229                  * all SET packets are processed in parallel with previous draw
3230                  * calls. Then upload descriptors, set shader pointers, and
3231                  * draw, and prefetch at the end. This ensures that the time
3232                  * the CUs are idle is very short. (there are only SET_SH
3233                  * packets between the wait and the draw)
3234                  */
3235                 radv_emit_all_graphics_states(cmd_buffer, info);
3236                 si_emit_cache_flush(cmd_buffer);
3237                 /* <-- CUs are idle here --> */
3238
3239                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3240
3241                 radv_emit_draw_packets(cmd_buffer, info);
3242                 /* <-- CUs are busy here --> */
3243
3244                 /* Start prefetches after the draw has been started. Both will
3245                  * run in parallel, but starting the draw first is more
3246                  * important.
3247                  */
3248                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3249                         radv_emit_prefetch_L2(cmd_buffer,
3250                                               cmd_buffer->state.pipeline, false);
3251                 }
3252         } else {
3253                 /* If we don't wait for idle, start prefetches first, then set
3254                  * states, and draw at the end.
3255                  */
3256                 si_emit_cache_flush(cmd_buffer);
3257
3258                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3259                         /* Only prefetch the vertex shader and VBO descriptors
3260                          * in order to start the draw as soon as possible.
3261                          */
3262                         radv_emit_prefetch_L2(cmd_buffer,
3263                                               cmd_buffer->state.pipeline, true);
3264                 }
3265
3266                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3267
3268                 radv_emit_all_graphics_states(cmd_buffer, info);
3269                 radv_emit_draw_packets(cmd_buffer, info);
3270
3271                 /* Prefetch the remaining shaders after the draw has been
3272                  * started.
3273                  */
3274                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3275                         radv_emit_prefetch_L2(cmd_buffer,
3276                                               cmd_buffer->state.pipeline, false);
3277                 }
3278         }
3279
3280         assert(cmd_buffer->cs->cdw <= cdw_max);
3281         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3282 }
3283
3284 void radv_CmdDraw(
3285         VkCommandBuffer                             commandBuffer,
3286         uint32_t                                    vertexCount,
3287         uint32_t                                    instanceCount,
3288         uint32_t                                    firstVertex,
3289         uint32_t                                    firstInstance)
3290 {
3291         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3292         struct radv_draw_info info = {};
3293
3294         info.count = vertexCount;
3295         info.instance_count = instanceCount;
3296         info.first_instance = firstInstance;
3297         info.vertex_offset = firstVertex;
3298
3299         radv_draw(cmd_buffer, &info);
3300 }
3301
3302 void radv_CmdDrawIndexed(
3303         VkCommandBuffer                             commandBuffer,
3304         uint32_t                                    indexCount,
3305         uint32_t                                    instanceCount,
3306         uint32_t                                    firstIndex,
3307         int32_t                                     vertexOffset,
3308         uint32_t                                    firstInstance)
3309 {
3310         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3311         struct radv_draw_info info = {};
3312
3313         info.indexed = true;
3314         info.count = indexCount;
3315         info.instance_count = instanceCount;
3316         info.first_index = firstIndex;
3317         info.vertex_offset = vertexOffset;
3318         info.first_instance = firstInstance;
3319
3320         radv_draw(cmd_buffer, &info);
3321 }
3322
3323 void radv_CmdDrawIndirect(
3324         VkCommandBuffer                             commandBuffer,
3325         VkBuffer                                    _buffer,
3326         VkDeviceSize                                offset,
3327         uint32_t                                    drawCount,
3328         uint32_t                                    stride)
3329 {
3330         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3331         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3332         struct radv_draw_info info = {};
3333
3334         info.count = drawCount;
3335         info.indirect = buffer;
3336         info.indirect_offset = offset;
3337         info.stride = stride;
3338
3339         radv_draw(cmd_buffer, &info);
3340 }
3341
3342 void radv_CmdDrawIndexedIndirect(
3343         VkCommandBuffer                             commandBuffer,
3344         VkBuffer                                    _buffer,
3345         VkDeviceSize                                offset,
3346         uint32_t                                    drawCount,
3347         uint32_t                                    stride)
3348 {
3349         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3350         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3351         struct radv_draw_info info = {};
3352
3353         info.indexed = true;
3354         info.count = drawCount;
3355         info.indirect = buffer;
3356         info.indirect_offset = offset;
3357         info.stride = stride;
3358
3359         radv_draw(cmd_buffer, &info);
3360 }
3361
3362 void radv_CmdDrawIndirectCountAMD(
3363         VkCommandBuffer                             commandBuffer,
3364         VkBuffer                                    _buffer,
3365         VkDeviceSize                                offset,
3366         VkBuffer                                    _countBuffer,
3367         VkDeviceSize                                countBufferOffset,
3368         uint32_t                                    maxDrawCount,
3369         uint32_t                                    stride)
3370 {
3371         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3372         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3373         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3374         struct radv_draw_info info = {};
3375
3376         info.count = maxDrawCount;
3377         info.indirect = buffer;
3378         info.indirect_offset = offset;
3379         info.count_buffer = count_buffer;
3380         info.count_buffer_offset = countBufferOffset;
3381         info.stride = stride;
3382
3383         radv_draw(cmd_buffer, &info);
3384 }
3385
3386 void radv_CmdDrawIndexedIndirectCountAMD(
3387         VkCommandBuffer                             commandBuffer,
3388         VkBuffer                                    _buffer,
3389         VkDeviceSize                                offset,
3390         VkBuffer                                    _countBuffer,
3391         VkDeviceSize                                countBufferOffset,
3392         uint32_t                                    maxDrawCount,
3393         uint32_t                                    stride)
3394 {
3395         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3396         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3397         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3398         struct radv_draw_info info = {};
3399
3400         info.indexed = true;
3401         info.count = maxDrawCount;
3402         info.indirect = buffer;
3403         info.indirect_offset = offset;
3404         info.count_buffer = count_buffer;
3405         info.count_buffer_offset = countBufferOffset;
3406         info.stride = stride;
3407
3408         radv_draw(cmd_buffer, &info);
3409 }
3410
3411 void radv_CmdDrawIndirectCountKHR(
3412         VkCommandBuffer                             commandBuffer,
3413         VkBuffer                                    _buffer,
3414         VkDeviceSize                                offset,
3415         VkBuffer                                    _countBuffer,
3416         VkDeviceSize                                countBufferOffset,
3417         uint32_t                                    maxDrawCount,
3418         uint32_t                                    stride)
3419 {
3420         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3421         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3422         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3423         struct radv_draw_info info = {};
3424
3425         info.count = maxDrawCount;
3426         info.indirect = buffer;
3427         info.indirect_offset = offset;
3428         info.count_buffer = count_buffer;
3429         info.count_buffer_offset = countBufferOffset;
3430         info.stride = stride;
3431
3432         radv_draw(cmd_buffer, &info);
3433 }
3434
3435 void radv_CmdDrawIndexedIndirectCountKHR(
3436         VkCommandBuffer                             commandBuffer,
3437         VkBuffer                                    _buffer,
3438         VkDeviceSize                                offset,
3439         VkBuffer                                    _countBuffer,
3440         VkDeviceSize                                countBufferOffset,
3441         uint32_t                                    maxDrawCount,
3442         uint32_t                                    stride)
3443 {
3444         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3445         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3446         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3447         struct radv_draw_info info = {};
3448
3449         info.indexed = true;
3450         info.count = maxDrawCount;
3451         info.indirect = buffer;
3452         info.indirect_offset = offset;
3453         info.count_buffer = count_buffer;
3454         info.count_buffer_offset = countBufferOffset;
3455         info.stride = stride;
3456
3457         radv_draw(cmd_buffer, &info);
3458 }
3459
3460 struct radv_dispatch_info {
3461         /**
3462          * Determine the layout of the grid (in block units) to be used.
3463          */
3464         uint32_t blocks[3];
3465
3466         /**
3467          * A starting offset for the grid. If unaligned is set, the offset
3468          * must still be aligned.
3469          */
3470         uint32_t offsets[3];
3471         /**
3472          * Whether it's an unaligned compute dispatch.
3473          */
3474         bool unaligned;
3475
3476         /**
3477          * Indirect compute parameters resource.
3478          */
3479         struct radv_buffer *indirect;
3480         uint64_t indirect_offset;
3481 };
3482
3483 static void
3484 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3485                            const struct radv_dispatch_info *info)
3486 {
3487         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3488         struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3489         unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3490         struct radeon_winsys *ws = cmd_buffer->device->ws;
3491         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3492         struct radv_userdata_info *loc;
3493
3494         loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3495                                     AC_UD_CS_GRID_SIZE);
3496
3497         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3498
3499         if (info->indirect) {
3500                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3501
3502                 va += info->indirect->offset + info->indirect_offset;
3503
3504                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3505
3506                 if (loc->sgpr_idx != -1) {
3507                         for (unsigned i = 0; i < 3; ++i) {
3508                                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3509                                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3510                                                 COPY_DATA_DST_SEL(COPY_DATA_REG));
3511                                 radeon_emit(cs, (va +  4 * i));
3512                                 radeon_emit(cs, (va + 4 * i) >> 32);
3513                                 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3514                                                  + loc->sgpr_idx * 4) >> 2) + i);
3515                                 radeon_emit(cs, 0);
3516                         }
3517                 }
3518
3519                 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3520                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3521                                         PKT3_SHADER_TYPE_S(1));
3522                         radeon_emit(cs, va);
3523                         radeon_emit(cs, va >> 32);
3524                         radeon_emit(cs, dispatch_initiator);
3525                 } else {
3526                         radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3527                                         PKT3_SHADER_TYPE_S(1));
3528                         radeon_emit(cs, 1);
3529                         radeon_emit(cs, va);
3530                         radeon_emit(cs, va >> 32);
3531
3532                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3533                                         PKT3_SHADER_TYPE_S(1));
3534                         radeon_emit(cs, 0);
3535                         radeon_emit(cs, dispatch_initiator);
3536                 }
3537         } else {
3538                 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3539                 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3540
3541                 if (info->unaligned) {
3542                         unsigned *cs_block_size = compute_shader->info.cs.block_size;
3543                         unsigned remainder[3];
3544
3545                         /* If aligned, these should be an entire block size,
3546                          * not 0.
3547                          */
3548                         remainder[0] = blocks[0] + cs_block_size[0] -
3549                                        align_u32_npot(blocks[0], cs_block_size[0]);
3550                         remainder[1] = blocks[1] + cs_block_size[1] -
3551                                        align_u32_npot(blocks[1], cs_block_size[1]);
3552                         remainder[2] = blocks[2] + cs_block_size[2] -
3553                                        align_u32_npot(blocks[2], cs_block_size[2]);
3554
3555                         blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3556                         blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3557                         blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3558
3559                         for(unsigned i = 0; i < 3; ++i) {
3560                                 assert(offsets[i] % cs_block_size[i] == 0);
3561                                 offsets[i] /= cs_block_size[i];
3562                         }
3563
3564                         radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3565                         radeon_emit(cs,
3566                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3567                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3568                         radeon_emit(cs,
3569                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3570                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3571                         radeon_emit(cs,
3572                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3573                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3574
3575                         dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3576                 }
3577
3578                 if (loc->sgpr_idx != -1) {
3579                         assert(!loc->indirect);
3580                         assert(loc->num_sgprs == 3);
3581
3582                         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3583                                                   loc->sgpr_idx * 4, 3);
3584                         radeon_emit(cs, blocks[0]);
3585                         radeon_emit(cs, blocks[1]);
3586                         radeon_emit(cs, blocks[2]);
3587                 }
3588
3589                 if (offsets[0] || offsets[1] || offsets[2]) {
3590                         radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3591                         radeon_emit(cs, offsets[0]);
3592                         radeon_emit(cs, offsets[1]);
3593                         radeon_emit(cs, offsets[2]);
3594
3595                         /* The blocks in the packet are not counts but end values. */
3596                         for (unsigned i = 0; i < 3; ++i)
3597                                 blocks[i] += offsets[i];
3598                 } else {
3599                         dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3600                 }
3601
3602                 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3603                                 PKT3_SHADER_TYPE_S(1));
3604                 radeon_emit(cs, blocks[0]);
3605                 radeon_emit(cs, blocks[1]);
3606                 radeon_emit(cs, blocks[2]);
3607                 radeon_emit(cs, dispatch_initiator);
3608         }
3609
3610         assert(cmd_buffer->cs->cdw <= cdw_max);
3611 }
3612
3613 static void
3614 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3615 {
3616         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3617         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3618 }
3619
3620 static void
3621 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3622               const struct radv_dispatch_info *info)
3623 {
3624         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3625         bool has_prefetch =
3626                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3627         bool pipeline_is_dirty = pipeline &&
3628                                  pipeline != cmd_buffer->state.emitted_compute_pipeline;
3629
3630         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3631                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3632                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3633                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3634                 /* If we have to wait for idle, set all states first, so that
3635                  * all SET packets are processed in parallel with previous draw
3636                  * calls. Then upload descriptors, set shader pointers, and
3637                  * dispatch, and prefetch at the end. This ensures that the
3638                  * time the CUs are idle is very short. (there are only SET_SH
3639                  * packets between the wait and the draw)
3640                  */
3641                 radv_emit_compute_pipeline(cmd_buffer);
3642                 si_emit_cache_flush(cmd_buffer);
3643                 /* <-- CUs are idle here --> */
3644
3645                 radv_upload_compute_shader_descriptors(cmd_buffer);
3646
3647                 radv_emit_dispatch_packets(cmd_buffer, info);
3648                 /* <-- CUs are busy here --> */
3649
3650                 /* Start prefetches after the dispatch has been started. Both
3651                  * will run in parallel, but starting the dispatch first is
3652                  * more important.
3653                  */
3654                 if (has_prefetch && pipeline_is_dirty) {
3655                         radv_emit_shader_prefetch(cmd_buffer,
3656                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3657                 }
3658         } else {
3659                 /* If we don't wait for idle, start prefetches first, then set
3660                  * states, and dispatch at the end.
3661                  */
3662                 si_emit_cache_flush(cmd_buffer);
3663
3664                 if (has_prefetch && pipeline_is_dirty) {
3665                         radv_emit_shader_prefetch(cmd_buffer,
3666                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3667                 }
3668
3669                 radv_upload_compute_shader_descriptors(cmd_buffer);
3670
3671                 radv_emit_compute_pipeline(cmd_buffer);
3672                 radv_emit_dispatch_packets(cmd_buffer, info);
3673         }
3674
3675         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3676 }
3677
3678 void radv_CmdDispatchBase(
3679         VkCommandBuffer                             commandBuffer,
3680         uint32_t                                    base_x,
3681         uint32_t                                    base_y,
3682         uint32_t                                    base_z,
3683         uint32_t                                    x,
3684         uint32_t                                    y,
3685         uint32_t                                    z)
3686 {
3687         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3688         struct radv_dispatch_info info = {};
3689
3690         info.blocks[0] = x;
3691         info.blocks[1] = y;
3692         info.blocks[2] = z;
3693
3694         info.offsets[0] = base_x;
3695         info.offsets[1] = base_y;
3696         info.offsets[2] = base_z;
3697         radv_dispatch(cmd_buffer, &info);
3698 }
3699
3700 void radv_CmdDispatch(
3701         VkCommandBuffer                             commandBuffer,
3702         uint32_t                                    x,
3703         uint32_t                                    y,
3704         uint32_t                                    z)
3705 {
3706         radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3707 }
3708
3709 void radv_CmdDispatchIndirect(
3710         VkCommandBuffer                             commandBuffer,
3711         VkBuffer                                    _buffer,
3712         VkDeviceSize                                offset)
3713 {
3714         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3715         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3716         struct radv_dispatch_info info = {};
3717
3718         info.indirect = buffer;
3719         info.indirect_offset = offset;
3720
3721         radv_dispatch(cmd_buffer, &info);
3722 }
3723
3724 void radv_unaligned_dispatch(
3725         struct radv_cmd_buffer                      *cmd_buffer,
3726         uint32_t                                    x,
3727         uint32_t                                    y,
3728         uint32_t                                    z)
3729 {
3730         struct radv_dispatch_info info = {};
3731
3732         info.blocks[0] = x;
3733         info.blocks[1] = y;
3734         info.blocks[2] = z;
3735         info.unaligned = 1;
3736
3737         radv_dispatch(cmd_buffer, &info);
3738 }
3739
3740 void radv_CmdEndRenderPass(
3741         VkCommandBuffer                             commandBuffer)
3742 {
3743         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3744
3745         radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3746
3747         radv_cmd_buffer_resolve_subpass(cmd_buffer);
3748
3749         for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3750                 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3751                 radv_handle_subpass_image_transition(cmd_buffer,
3752                                       (VkAttachmentReference){i, layout});
3753         }
3754
3755         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3756
3757         cmd_buffer->state.pass = NULL;
3758         cmd_buffer->state.subpass = NULL;
3759         cmd_buffer->state.attachments = NULL;
3760         cmd_buffer->state.framebuffer = NULL;
3761 }
3762
3763 /*
3764  * For HTILE we have the following interesting clear words:
3765  *   0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3766  *   0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3767  *   0xfffffff0: Clear depth to 1.0
3768  *   0x00000000: Clear depth to 0.0
3769  */
3770 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3771                                   struct radv_image *image,
3772                                   const VkImageSubresourceRange *range,
3773                                   uint32_t clear_word)
3774 {
3775         assert(range->baseMipLevel == 0);
3776         assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3777         unsigned layer_count = radv_get_layerCount(image, range);
3778         uint64_t size = image->surface.htile_slice_size * layer_count;
3779         uint64_t offset = image->offset + image->htile_offset +
3780                           image->surface.htile_slice_size * range->baseArrayLayer;
3781         struct radv_cmd_state *state = &cmd_buffer->state;
3782
3783         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3784                              RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3785
3786         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3787                                               size, clear_word);
3788
3789         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3790 }
3791
3792 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3793                                                struct radv_image *image,
3794                                                VkImageLayout src_layout,
3795                                                VkImageLayout dst_layout,
3796                                                unsigned src_queue_mask,
3797                                                unsigned dst_queue_mask,
3798                                                const VkImageSubresourceRange *range,
3799                                                VkImageAspectFlags pending_clears)
3800 {
3801         if (!radv_image_has_htile(image))
3802                 return;
3803
3804         if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3805             (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3806             cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3807             cmd_buffer->state.render_area.extent.width == image->info.width &&
3808             cmd_buffer->state.render_area.extent.height == image->info.height) {
3809                 /* The clear will initialize htile. */
3810                 return;
3811         } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3812                    radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3813                 /* TODO: merge with the clear if applicable */
3814                 radv_initialize_htile(cmd_buffer, image, range, 0);
3815         } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3816                    radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3817                 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3818                 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3819         } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3820                    !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3821                 VkImageSubresourceRange local_range = *range;
3822                 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3823                 local_range.baseMipLevel = 0;
3824                 local_range.levelCount = 1;
3825
3826                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3827                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3828
3829                 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3830
3831                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3832                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3833         }
3834 }
3835
3836 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3837                                   struct radv_image *image, uint32_t value)
3838 {
3839         struct radv_cmd_state *state = &cmd_buffer->state;
3840
3841         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3842                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3843
3844         state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
3845
3846         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3847 }
3848
3849 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3850                          struct radv_image *image, uint32_t value)
3851 {
3852         struct radv_cmd_state *state = &cmd_buffer->state;
3853
3854         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3855                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3856
3857         state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
3858
3859         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3860                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3861 }
3862
3863 /**
3864  * Initialize DCC/FMASK/CMASK metadata for a color image.
3865  */
3866 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
3867                                            struct radv_image *image,
3868                                            VkImageLayout src_layout,
3869                                            VkImageLayout dst_layout,
3870                                            unsigned src_queue_mask,
3871                                            unsigned dst_queue_mask)
3872 {
3873         if (radv_image_has_cmask(image)) {
3874                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
3875
3876                 /*  TODO: clarify this. */
3877                 if (radv_image_has_fmask(image)) {
3878                         value = 0xccccccccu;
3879                 }
3880
3881                 radv_initialise_cmask(cmd_buffer, image, value);
3882         }
3883
3884         if (radv_image_has_dcc(image)) {
3885                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
3886
3887                 if (radv_layout_dcc_compressed(image, dst_layout,
3888                                                dst_queue_mask)) {
3889                         value = 0x20202020u;
3890                 }
3891
3892                 radv_initialize_dcc(cmd_buffer, image, value);
3893         }
3894 }
3895
3896 /**
3897  * Handle color image transitions for DCC/FMASK/CMASK.
3898  */
3899 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
3900                                                struct radv_image *image,
3901                                                VkImageLayout src_layout,
3902                                                VkImageLayout dst_layout,
3903                                                unsigned src_queue_mask,
3904                                                unsigned dst_queue_mask,
3905                                                const VkImageSubresourceRange *range)
3906 {
3907         if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3908                 radv_init_color_image_metadata(cmd_buffer, image,
3909                                                src_layout, dst_layout,
3910                                                src_queue_mask, dst_queue_mask);
3911                 return;
3912         }
3913
3914         if (radv_image_has_dcc(image)) {
3915                 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
3916                         radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
3917                 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
3918                            !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
3919                         radv_decompress_dcc(cmd_buffer, image, range);
3920                 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3921                            !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3922                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3923                 }
3924         } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
3925                 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3926                     !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3927                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3928                 }
3929         }
3930 }
3931
3932 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3933                                          struct radv_image *image,
3934                                          VkImageLayout src_layout,
3935                                          VkImageLayout dst_layout,
3936                                          uint32_t src_family,
3937                                          uint32_t dst_family,
3938                                          const VkImageSubresourceRange *range,
3939                                          VkImageAspectFlags pending_clears)
3940 {
3941         if (image->exclusive && src_family != dst_family) {
3942                 /* This is an acquire or a release operation and there will be
3943                  * a corresponding release/acquire. Do the transition in the
3944                  * most flexible queue. */
3945
3946                 assert(src_family == cmd_buffer->queue_family_index ||
3947                        dst_family == cmd_buffer->queue_family_index);
3948
3949                 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3950                         return;
3951
3952                 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3953                     (src_family == RADV_QUEUE_GENERAL ||
3954                      dst_family == RADV_QUEUE_GENERAL))
3955                         return;
3956         }
3957
3958         unsigned src_queue_mask =
3959                 radv_image_queue_family_mask(image, src_family,
3960                                              cmd_buffer->queue_family_index);
3961         unsigned dst_queue_mask =
3962                 radv_image_queue_family_mask(image, dst_family,
3963                                              cmd_buffer->queue_family_index);
3964
3965         if (vk_format_is_depth(image->vk_format)) {
3966                 radv_handle_depth_image_transition(cmd_buffer, image,
3967                                                    src_layout, dst_layout,
3968                                                    src_queue_mask, dst_queue_mask,
3969                                                    range, pending_clears);
3970         } else {
3971                 radv_handle_color_image_transition(cmd_buffer, image,
3972                                                    src_layout, dst_layout,
3973                                                    src_queue_mask, dst_queue_mask,
3974                                                    range);
3975         }
3976 }
3977
3978 void radv_CmdPipelineBarrier(
3979         VkCommandBuffer                             commandBuffer,
3980         VkPipelineStageFlags                        srcStageMask,
3981         VkPipelineStageFlags                        destStageMask,
3982         VkBool32                                    byRegion,
3983         uint32_t                                    memoryBarrierCount,
3984         const VkMemoryBarrier*                      pMemoryBarriers,
3985         uint32_t                                    bufferMemoryBarrierCount,
3986         const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
3987         uint32_t                                    imageMemoryBarrierCount,
3988         const VkImageMemoryBarrier*                 pImageMemoryBarriers)
3989 {
3990         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3991         enum radv_cmd_flush_bits src_flush_bits = 0;
3992         enum radv_cmd_flush_bits dst_flush_bits = 0;
3993
3994         for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3995                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3996                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3997                                                         NULL);
3998         }
3999
4000         for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4001                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
4002                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4003                                                         NULL);
4004         }
4005
4006         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4007                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4008                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
4009                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4010                                                         image);
4011         }
4012
4013         radv_stage_flush(cmd_buffer, srcStageMask);
4014         cmd_buffer->state.flush_bits |= src_flush_bits;
4015
4016         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4017                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4018                 radv_handle_image_transition(cmd_buffer, image,
4019                                              pImageMemoryBarriers[i].oldLayout,
4020                                              pImageMemoryBarriers[i].newLayout,
4021                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
4022                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
4023                                              &pImageMemoryBarriers[i].subresourceRange,
4024                                              0);
4025         }
4026
4027         cmd_buffer->state.flush_bits |= dst_flush_bits;
4028 }
4029
4030
4031 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4032                         struct radv_event *event,
4033                         VkPipelineStageFlags stageMask,
4034                         unsigned value)
4035 {
4036         struct radeon_winsys_cs *cs = cmd_buffer->cs;
4037         uint64_t va = radv_buffer_get_va(event->bo);
4038
4039         radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4040
4041         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4042
4043         /* TODO: this is overkill. Probably should figure something out from
4044          * the stage mask. */
4045
4046         si_cs_emit_write_event_eop(cs,
4047                                    cmd_buffer->state.predicating,
4048                                    cmd_buffer->device->physical_device->rad_info.chip_class,
4049                                    radv_cmd_buffer_uses_mec(cmd_buffer),
4050                                    V_028A90_BOTTOM_OF_PIPE_TS, 0,
4051                                    1, va, 2, value);
4052
4053         assert(cmd_buffer->cs->cdw <= cdw_max);
4054 }
4055
4056 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4057                       VkEvent _event,
4058                       VkPipelineStageFlags stageMask)
4059 {
4060         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4061         RADV_FROM_HANDLE(radv_event, event, _event);
4062
4063         write_event(cmd_buffer, event, stageMask, 1);
4064 }
4065
4066 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4067                         VkEvent _event,
4068                         VkPipelineStageFlags stageMask)
4069 {
4070         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4071         RADV_FROM_HANDLE(radv_event, event, _event);
4072
4073         write_event(cmd_buffer, event, stageMask, 0);
4074 }
4075
4076 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4077                         uint32_t eventCount,
4078                         const VkEvent* pEvents,
4079                         VkPipelineStageFlags srcStageMask,
4080                         VkPipelineStageFlags dstStageMask,
4081                         uint32_t memoryBarrierCount,
4082                         const VkMemoryBarrier* pMemoryBarriers,
4083                         uint32_t bufferMemoryBarrierCount,
4084                         const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4085                         uint32_t imageMemoryBarrierCount,
4086                         const VkImageMemoryBarrier* pImageMemoryBarriers)
4087 {
4088         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4089         struct radeon_winsys_cs *cs = cmd_buffer->cs;
4090
4091         for (unsigned i = 0; i < eventCount; ++i) {
4092                 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4093                 uint64_t va = radv_buffer_get_va(event->bo);
4094
4095                 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4096
4097                 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4098
4099                 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4100                 assert(cmd_buffer->cs->cdw <= cdw_max);
4101         }
4102
4103
4104         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4105                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4106
4107                 radv_handle_image_transition(cmd_buffer, image,
4108                                              pImageMemoryBarriers[i].oldLayout,
4109                                              pImageMemoryBarriers[i].newLayout,
4110                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
4111                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
4112                                              &pImageMemoryBarriers[i].subresourceRange,
4113                                              0);
4114         }
4115
4116         /* TODO: figure out how to do memory barriers without waiting */
4117         cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4118                                         RADV_CMD_FLAG_INV_GLOBAL_L2 |
4119                                         RADV_CMD_FLAG_INV_VMEM_L1 |
4120                                         RADV_CMD_FLAG_INV_SMEM_L1;
4121 }
4122
4123
4124 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4125                            uint32_t deviceMask)
4126 {
4127    /* No-op */
4128 }