src/amd/vulkan/radv_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "radv_private.h"
  29 #include "radv_radeon_winsys.h"
  30 #include "radv_shader.h"
  31 #include "radv_cs.h"
  32 #include "sid.h"
  33 #include "gfx9d.h"
  34 #include "vk_format.h"
  35 #include "radv_debug.h"
  36 #include "radv_meta.h"
  37
  38 #include "ac_debug.h"
  39
  40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
  41                                          struct radv_image *image,
  42                                          VkImageLayout src_layout,
  43                                          VkImageLayout dst_layout,
  44                                          uint32_t src_family,
  45                                          uint32_t dst_family,
  46                                          const VkImageSubresourceRange *range,
  47                                          VkImageAspectFlags pending_clears);
  48
  49 const struct radv_dynamic_state default_dynamic_state = {
  50         .viewport = {
  51                 .count = 0,
  52         },
  53         .scissor = {
  54                 .count = 0,
  55         },
  56         .line_width = 1.0f,
  57         .depth_bias = {
  58                 .bias = 0.0f,
  59                 .clamp = 0.0f,
  60                 .slope = 0.0f,
  61         },
  62         .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
  63         .depth_bounds = {
  64                 .min = 0.0f,
  65                 .max = 1.0f,
  66         },
  67         .stencil_compare_mask = {
  68                 .front = ~0u,
  69                 .back = ~0u,
  70         },
  71         .stencil_write_mask = {
  72                 .front = ~0u,
  73                 .back = ~0u,
  74         },
  75         .stencil_reference = {
  76                 .front = 0u,
  77                 .back = 0u,
  78         },
  79 };
  80
  81 static void
  82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
  83                         const struct radv_dynamic_state *src)
  84 {
  85         struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
  86         uint32_t copy_mask = src->mask;
  87         uint32_t dest_mask = 0;
  88
  89         /* Make sure to copy the number of viewports/scissors because they can
  90          * only be specified at pipeline creation time.
  91          */
  92         dest->viewport.count = src->viewport.count;
  93         dest->scissor.count = src->scissor.count;
  94         dest->discard_rectangle.count = src->discard_rectangle.count;
  95
  96         if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
  97                 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
  98                            src->viewport.count * sizeof(VkViewport))) {
  99                         typed_memcpy(dest->viewport.viewports,
 100                                      src->viewport.viewports,
 101                                      src->viewport.count);
 102                         dest_mask |= RADV_DYNAMIC_VIEWPORT;
 103                 }
 104         }
 105
 106         if (copy_mask & RADV_DYNAMIC_SCISSOR) {
 107                 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
 108                            src->scissor.count * sizeof(VkRect2D))) {
 109                         typed_memcpy(dest->scissor.scissors,
 110                                      src->scissor.scissors, src->scissor.count);
 111                         dest_mask |= RADV_DYNAMIC_SCISSOR;
 112                 }
 113         }
 114
 115         if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
 116                 if (dest->line_width != src->line_width) {
 117                         dest->line_width = src->line_width;
 118                         dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
 119                 }
 120         }
 121
 122         if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
 123                 if (memcmp(&dest->depth_bias, &src->depth_bias,
 124                            sizeof(src->depth_bias))) {
 125                         dest->depth_bias = src->depth_bias;
 126                         dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
 127                 }
 128         }
 129
 130         if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
 131                 if (memcmp(&dest->blend_constants, &src->blend_constants,
 132                            sizeof(src->blend_constants))) {
 133                         typed_memcpy(dest->blend_constants,
 134                                      src->blend_constants, 4);
 135                         dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
 136                 }
 137         }
 138
 139         if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
 140                 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
 141                            sizeof(src->depth_bounds))) {
 142                         dest->depth_bounds = src->depth_bounds;
 143                         dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
 144                 }
 145         }
 146
 147         if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
 148                 if (memcmp(&dest->stencil_compare_mask,
 149                            &src->stencil_compare_mask,
 150                            sizeof(src->stencil_compare_mask))) {
 151                         dest->stencil_compare_mask = src->stencil_compare_mask;
 152                         dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
 153                 }
 154         }
 155
 156         if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
 157                 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
 158                            sizeof(src->stencil_write_mask))) {
 159                         dest->stencil_write_mask = src->stencil_write_mask;
 160                         dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
 161                 }
 162         }
 163
 164         if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
 165                 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
 166                            sizeof(src->stencil_reference))) {
 167                         dest->stencil_reference = src->stencil_reference;
 168                         dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
 169                 }
 170         }
 171
 172         if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
 173                 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
 174                            src->discard_rectangle.count * sizeof(VkRect2D))) {
 175                         typed_memcpy(dest->discard_rectangle.rectangles,
 176                                      src->discard_rectangle.rectangles,
 177                                      src->discard_rectangle.count);
 178                         dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
 179                 }
 180         }
 181
 182         cmd_buffer->state.dirty |= dest_mask;
 183 }
 184
 185 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
 186 {
 187         return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
 188                cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
 189 }
 190
 191 enum ring_type radv_queue_family_to_ring(int f) {
 192         switch (f) {
 193         case RADV_QUEUE_GENERAL:
 194                 return RING_GFX;
 195         case RADV_QUEUE_COMPUTE:
 196                 return RING_COMPUTE;
 197         case RADV_QUEUE_TRANSFER:
 198                 return RING_DMA;
 199         default:
 200                 unreachable("Unknown queue family");
 201         }
 202 }
 203
 204 static VkResult radv_create_cmd_buffer(
 205         struct radv_device *                         device,
 206         struct radv_cmd_pool *                       pool,
 207         VkCommandBufferLevel                        level,
 208         VkCommandBuffer*                            pCommandBuffer)
 209 {
 210         struct radv_cmd_buffer *cmd_buffer;
 211         unsigned ring;
 212         cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
 213                                VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 214         if (cmd_buffer == NULL)
 215                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 216
 217         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
 218         cmd_buffer->device = device;
 219         cmd_buffer->pool = pool;
 220         cmd_buffer->level = level;
 221
 222         if (pool) {
 223                 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
 224                 cmd_buffer->queue_family_index = pool->queue_family_index;
 225
 226         } else {
 227                 /* Init the pool_link so we can safefly call list_del when we destroy
 228                  * the command buffer
 229                  */
 230                 list_inithead(&cmd_buffer->pool_link);
 231                 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
 232         }
 233
 234         ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
 235
 236         cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
 237         if (!cmd_buffer->cs) {
 238                 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 239                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 240         }
 241
 242         *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
 243
 244         list_inithead(&cmd_buffer->upload.list);
 245
 246         return VK_SUCCESS;
 247 }
 248
 249 static void
 250 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
 251 {
 252         list_del(&cmd_buffer->pool_link);
 253
 254         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 255                                  &cmd_buffer->upload.list, list) {
 256                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 257                 list_del(&up->list);
 258                 free(up);
 259         }
 260
 261         if (cmd_buffer->upload.upload_bo)
 262                 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
 263         cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
 264
 265         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
 266                 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
 267
 268         vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 269 }
 270
 271 static VkResult
 272 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 273 {
 274
 275         cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
 276
 277         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 278                                  &cmd_buffer->upload.list, list) {
 279                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 280                 list_del(&up->list);
 281                 free(up);
 282         }
 283
 284         cmd_buffer->push_constant_stages = 0;
 285         cmd_buffer->scratch_size_needed = 0;
 286         cmd_buffer->compute_scratch_size_needed = 0;
 287         cmd_buffer->esgs_ring_size_needed = 0;
 288         cmd_buffer->gsvs_ring_size_needed = 0;
 289         cmd_buffer->tess_rings_needed = false;
 290         cmd_buffer->sample_positions_needed = false;
 291
 292         if (cmd_buffer->upload.upload_bo)
 293                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 294                                    cmd_buffer->upload.upload_bo, 8);
 295         cmd_buffer->upload.offset = 0;
 296
 297         cmd_buffer->record_result = VK_SUCCESS;
 298
 299         cmd_buffer->ring_offsets_idx = -1;
 300
 301         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
 302                 cmd_buffer->descriptors[i].dirty = 0;
 303                 cmd_buffer->descriptors[i].valid = 0;
 304                 cmd_buffer->descriptors[i].push_dirty = false;
 305         }
 306
 307         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 308                 void *fence_ptr;
 309                 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
 310                                              &cmd_buffer->gfx9_fence_offset,
 311                                              &fence_ptr);
 312                 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
 313         }
 314
 315         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
 316
 317         return cmd_buffer->record_result;
 318 }
 319
 320 static bool
 321 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
 322                                   uint64_t min_needed)
 323 {
 324         uint64_t new_size;
 325         struct radeon_winsys_bo *bo;
 326         struct radv_cmd_buffer_upload *upload;
 327         struct radv_device *device = cmd_buffer->device;
 328
 329         new_size = MAX2(min_needed, 16 * 1024);
 330         new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
 331
 332         bo = device->ws->buffer_create(device->ws,
 333                                        new_size, 4096,
 334                                        RADEON_DOMAIN_GTT,
 335                                        RADEON_FLAG_CPU_ACCESS|
 336                                        RADEON_FLAG_NO_INTERPROCESS_SHARING);
 337
 338         if (!bo) {
 339                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 340                 return false;
 341         }
 342
 343         radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
 344         if (cmd_buffer->upload.upload_bo) {
 345                 upload = malloc(sizeof(*upload));
 346
 347                 if (!upload) {
 348                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
 349                         device->ws->buffer_destroy(bo);
 350                         return false;
 351                 }
 352
 353                 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
 354                 list_add(&upload->list, &cmd_buffer->upload.list);
 355         }
 356
 357         cmd_buffer->upload.upload_bo = bo;
 358         cmd_buffer->upload.size = new_size;
 359         cmd_buffer->upload.offset = 0;
 360         cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
 361
 362         if (!cmd_buffer->upload.map) {
 363                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 364                 return false;
 365         }
 366
 367         return true;
 368 }
 369
 370 bool
 371 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
 372                              unsigned size,
 373                              unsigned alignment,
 374                              unsigned *out_offset,
 375                              void **ptr)
 376 {
 377         uint64_t offset = align(cmd_buffer->upload.offset, alignment);
 378         if (offset + size > cmd_buffer->upload.size) {
 379                 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
 380                         return false;
 381                 offset = 0;
 382         }
 383
 384         *out_offset = offset;
 385         *ptr = cmd_buffer->upload.map + offset;
 386
 387         cmd_buffer->upload.offset = offset + size;
 388         return true;
 389 }
 390
 391 bool
 392 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
 393                             unsigned size, unsigned alignment,
 394                             const void *data, unsigned *out_offset)
 395 {
 396         uint8_t *ptr;
 397
 398         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
 399                                           out_offset, (void **)&ptr))
 400                 return false;
 401
 402         if (ptr)
 403                 memcpy(ptr, data, size);
 404
 405         return true;
 406 }
 407
 408 static void
 409 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
 410                             unsigned count, const uint32_t *data)
 411 {
 412         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
 413         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
 414                     S_370_WR_CONFIRM(1) |
 415                     S_370_ENGINE_SEL(V_370_ME));
 416         radeon_emit(cs, va);
 417         radeon_emit(cs, va >> 32);
 418         radeon_emit_array(cs, data, count);
 419 }
 420
 421 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
 422 {
 423         struct radv_device *device = cmd_buffer->device;
 424         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 425         uint64_t va;
 426
 427         va = radv_buffer_get_va(device->trace_bo);
 428         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
 429                 va += 4;
 430
 431         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
 432
 433         ++cmd_buffer->state.trace_id;
 434         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 435         radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
 436         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
 437         radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
 438 }
 439
 440 static void
 441 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
 442                            enum radv_cmd_flush_bits flags)
 443 {
 444         if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
 445                 uint32_t *ptr = NULL;
 446                 uint64_t va = 0;
 447
 448                 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
 449                                 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
 450
 451                 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
 452                         va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
 453                              cmd_buffer->gfx9_fence_offset;
 454                         ptr = &cmd_buffer->gfx9_fence_idx;
 455                 }
 456
 457                 /* Force wait for graphics or compute engines to be idle. */
 458                 si_cs_emit_cache_flush(cmd_buffer->cs,
 459                                        cmd_buffer->device->physical_device->rad_info.chip_class,
 460                                        ptr, va,
 461                                        radv_cmd_buffer_uses_mec(cmd_buffer),
 462                                        flags);
 463         }
 464
 465         if (unlikely(cmd_buffer->device->trace_bo))
 466                 radv_cmd_buffer_trace_emit(cmd_buffer);
 467 }
 468
 469 static void
 470 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
 471                    struct radv_pipeline *pipeline, enum ring_type ring)
 472 {
 473         struct radv_device *device = cmd_buffer->device;
 474         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 475         uint32_t data[2];
 476         uint64_t va;
 477
 478         va = radv_buffer_get_va(device->trace_bo);
 479
 480         switch (ring) {
 481         case RING_GFX:
 482                 va += 8;
 483                 break;
 484         case RING_COMPUTE:
 485                 va += 16;
 486                 break;
 487         default:
 488                 assert(!"invalid ring type");
 489         }
 490
 491         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 492                                                            cmd_buffer->cs, 6);
 493
 494         data[0] = (uintptr_t)pipeline;
 495         data[1] = (uintptr_t)pipeline >> 32;
 496
 497         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 498         radv_emit_write_data_packet(cs, va, 2, data);
 499 }
 500
 501 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 502                              VkPipelineBindPoint bind_point,
 503                              struct radv_descriptor_set *set,
 504                              unsigned idx)
 505 {
 506         struct radv_descriptor_state *descriptors_state =
 507                 radv_get_descriptors_state(cmd_buffer, bind_point);
 508
 509         descriptors_state->sets[idx] = set;
 510         if (set)
 511                 descriptors_state->valid |= (1u << idx);
 512         else
 513                 descriptors_state->valid &= ~(1u << idx);
 514         descriptors_state->dirty |= (1u << idx);
 515 }
 516
 517 static void
 518 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
 519                       VkPipelineBindPoint bind_point)
 520 {
 521         struct radv_descriptor_state *descriptors_state =
 522                 radv_get_descriptors_state(cmd_buffer, bind_point);
 523         struct radv_device *device = cmd_buffer->device;
 524         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 525         uint32_t data[MAX_SETS * 2] = {};
 526         uint64_t va;
 527         unsigned i;
 528         va = radv_buffer_get_va(device->trace_bo) + 24;
 529
 530         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 531                                                            cmd_buffer->cs, 4 + MAX_SETS * 2);
 532
 533         for_each_bit(i, descriptors_state->valid) {
 534                 struct radv_descriptor_set *set = descriptors_state->sets[i];
 535                 data[i * 2] = (uintptr_t)set;
 536                 data[i * 2 + 1] = (uintptr_t)set >> 32;
 537         }
 538
 539         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 540         radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
 541 }
 542
 543 struct radv_userdata_info *
 544 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
 545                       gl_shader_stage stage,
 546                       int idx)
 547 {
 548         if (stage == MESA_SHADER_VERTEX) {
 549                 if (pipeline->shaders[MESA_SHADER_VERTEX])
 550                         return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
 551                 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
 552                         return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
 553                 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
 554                         return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
 555         } else if (stage == MESA_SHADER_TESS_EVAL) {
 556                 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
 557                         return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
 558                 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
 559                         return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
 560         }
 561         return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
 562 }
 563
 564 static void
 565 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
 566                            struct radv_pipeline *pipeline,
 567                            gl_shader_stage stage,
 568                            int idx, uint64_t va)
 569 {
 570         struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
 571         uint32_t base_reg = pipeline->user_data_0[stage];
 572         if (loc->sgpr_idx == -1)
 573                 return;
 574         assert(loc->num_sgprs == 2);
 575         assert(!loc->indirect);
 576         radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
 577         radeon_emit(cmd_buffer->cs, va);
 578         radeon_emit(cmd_buffer->cs, va >> 32);
 579 }
 580
 581 static void
 582 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
 583                               struct radv_pipeline *pipeline)
 584 {
 585         int num_samples = pipeline->graphics.ms.num_samples;
 586         struct radv_multisample_state *ms = &pipeline->graphics.ms;
 587         struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
 588
 589         if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
 590                 cmd_buffer->sample_positions_needed = true;
 591
 592         if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
 593                 return;
 594
 595         radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
 596         radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
 597         radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
 598
 599         radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
 600
 601         radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
 602
 603         /* GFX9: Flush DFSM when the AA mode changes. */
 604         if (cmd_buffer->device->dfsm_allowed) {
 605                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 606                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
 607         }
 608 }
 609
 610
 611
 612 static inline void
 613 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
 614                                unsigned size)
 615 {
 616         if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
 617                 si_cp_dma_prefetch(cmd_buffer, va, size);
 618 }
 619
 620 static void
 621 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
 622 {
 623         if (cmd_buffer->state.vb_prefetch_dirty) {
 624                 radv_emit_prefetch_TC_L2_async(cmd_buffer,
 625                                                cmd_buffer->state.vb_va,
 626                                                cmd_buffer->state.vb_size);
 627                 cmd_buffer->state.vb_prefetch_dirty = false;
 628         }
 629 }
 630
 631 static void
 632 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
 633                           struct radv_shader_variant *shader)
 634 {
 635         struct radeon_winsys *ws = cmd_buffer->device->ws;
 636         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 637         uint64_t va;
 638
 639         if (!shader)
 640                 return;
 641
 642         va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 643
 644         radv_cs_add_buffer(ws, cs, shader->bo, 8);
 645         radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
 646 }
 647
 648 static void
 649 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
 650                    struct radv_pipeline *pipeline)
 651 {
 652         radv_emit_shader_prefetch(cmd_buffer,
 653                                   pipeline->shaders[MESA_SHADER_VERTEX]);
 654         radv_emit_VBO_descriptors_prefetch(cmd_buffer);
 655         radv_emit_shader_prefetch(cmd_buffer,
 656                                   pipeline->shaders[MESA_SHADER_TESS_CTRL]);
 657         radv_emit_shader_prefetch(cmd_buffer,
 658                                   pipeline->shaders[MESA_SHADER_TESS_EVAL]);
 659         radv_emit_shader_prefetch(cmd_buffer,
 660                                   pipeline->shaders[MESA_SHADER_GEOMETRY]);
 661         radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
 662         radv_emit_shader_prefetch(cmd_buffer,
 663                                   pipeline->shaders[MESA_SHADER_FRAGMENT]);
 664 }
 665
 666 static void
 667 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
 668 {
 669         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 670
 671         if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
 672                 return;
 673
 674         radv_update_multisample_state(cmd_buffer, pipeline);
 675
 676         cmd_buffer->scratch_size_needed =
 677                                   MAX2(cmd_buffer->scratch_size_needed,
 678                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
 679
 680         if (!cmd_buffer->state.emitted_pipeline ||
 681             cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
 682              pipeline->graphics.can_use_guardband)
 683                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
 684
 685         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
 686
 687         if (unlikely(cmd_buffer->device->trace_bo))
 688                 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
 689
 690         cmd_buffer->state.emitted_pipeline = pipeline;
 691
 692         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
 693 }
 694
 695 static void
 696 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
 697 {
 698         si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
 699                           cmd_buffer->state.dynamic.viewport.viewports);
 700 }
 701
 702 static void
 703 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
 704 {
 705         uint32_t count = cmd_buffer->state.dynamic.scissor.count;
 706
 707         /* Vega10/Raven scissor bug workaround. This must be done before VPORT
 708          * scissor registers are changed. There is also a more efficient but
 709          * more involved alternative workaround.
 710          */
 711         if (cmd_buffer->device->physical_device->has_scissor_bug) {
 712                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
 713                 si_emit_cache_flush(cmd_buffer);
 714         }
 715         si_write_scissors(cmd_buffer->cs, 0, count,
 716                           cmd_buffer->state.dynamic.scissor.scissors,
 717                           cmd_buffer->state.dynamic.viewport.viewports,
 718                           cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
 719 }
 720
 721 static void
 722 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
 723 {
 724         if (!cmd_buffer->state.dynamic.discard_rectangle.count)
 725                 return;
 726
 727         radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
 728                                    cmd_buffer->state.dynamic.discard_rectangle.count * 2);
 729         for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
 730                 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
 731                 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
 732                 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
 733                                             S_028214_BR_Y(rect.offset.y + rect.extent.height));
 734         }
 735 }
 736
 737 static void
 738 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
 739 {
 740         unsigned width = cmd_buffer->state.dynamic.line_width * 8;
 741
 742         radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
 743                                S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
 744 }
 745
 746 static void
 747 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
 748 {
 749         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 750
 751         radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
 752         radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
 753 }
 754
 755 static void
 756 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
 757 {
 758         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 759
 760         radeon_set_context_reg_seq(cmd_buffer->cs,
 761                                    R_028430_DB_STENCILREFMASK, 2);
 762         radeon_emit(cmd_buffer->cs,
 763                     S_028430_STENCILTESTVAL(d->stencil_reference.front) |
 764                     S_028430_STENCILMASK(d->stencil_compare_mask.front) |
 765                     S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
 766                     S_028430_STENCILOPVAL(1));
 767         radeon_emit(cmd_buffer->cs,
 768                     S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
 769                     S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
 770                     S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
 771                     S_028434_STENCILOPVAL_BF(1));
 772 }
 773
 774 static void
 775 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
 776 {
 777         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 778
 779         radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
 780                                fui(d->depth_bounds.min));
 781         radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
 782                                fui(d->depth_bounds.max));
 783 }
 784
 785 static void
 786 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
 787 {
 788         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 789         unsigned slope = fui(d->depth_bias.slope * 16.0f);
 790         unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
 791
 792
 793         radeon_set_context_reg_seq(cmd_buffer->cs,
 794                                    R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
 795         radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
 796         radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
 797         radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
 798         radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
 799         radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
 800 }
 801
 802 static void
 803 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
 804                          int index,
 805                          struct radv_attachment_info *att,
 806                          struct radv_image *image,
 807                          VkImageLayout layout)
 808 {
 809         bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
 810         struct radv_color_buffer_info *cb = &att->cb;
 811         uint32_t cb_color_info = cb->cb_color_info;
 812
 813         if (!radv_layout_dcc_compressed(image, layout,
 814                                         radv_image_queue_family_mask(image,
 815                                                                      cmd_buffer->queue_family_index,
 816                                                                      cmd_buffer->queue_family_index))) {
 817                 cb_color_info &= C_028C70_DCC_ENABLE;
 818         }
 819
 820         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 821                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
 822                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
 823                 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
 824                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
 825                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
 826                 radeon_emit(cmd_buffer->cs, cb_color_info);
 827                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
 828                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
 829                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
 830                 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
 831                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
 832                 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
 833
 834                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
 835                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
 836                 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
 837
 838                 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
 839                                        S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
 840         } else {
 841                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
 842                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
 843                 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
 844                 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
 845                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
 846                 radeon_emit(cmd_buffer->cs, cb_color_info);
 847                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
 848                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
 849                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
 850                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
 851                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
 852                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
 853
 854                 if (is_vi) { /* DCC BASE */
 855                         radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
 856                 }
 857         }
 858 }
 859
 860 static void
 861 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
 862                       struct radv_ds_buffer_info *ds,
 863                       struct radv_image *image,
 864                       VkImageLayout layout)
 865 {
 866         uint32_t db_z_info = ds->db_z_info;
 867         uint32_t db_stencil_info = ds->db_stencil_info;
 868
 869         if (!radv_layout_has_htile(image, layout,
 870                                    radv_image_queue_family_mask(image,
 871                                                                 cmd_buffer->queue_family_index,
 872                                                                 cmd_buffer->queue_family_index))) {
 873                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
 874                 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
 875         }
 876
 877         radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
 878         radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
 879
 880
 881         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 882                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
 883                 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
 884                 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
 885                 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
 886
 887                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
 888                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* DB_Z_INFO */
 889                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* DB_STENCIL_INFO */
 890                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* DB_Z_READ_BASE */
 891                 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32));        /* DB_Z_READ_BASE_HI */
 892                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* DB_STENCIL_READ_BASE */
 893                 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
 894                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* DB_Z_WRITE_BASE */
 895                 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32));       /* DB_Z_WRITE_BASE_HI */
 896                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
 897                 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
 898
 899                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
 900                 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
 901                 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
 902         } else {
 903                 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
 904
 905                 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
 906                 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
 907                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* R_028040_DB_Z_INFO */
 908                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* R_028044_DB_STENCIL_INFO */
 909                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* R_028048_DB_Z_READ_BASE */
 910                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* R_02804C_DB_STENCIL_READ_BASE */
 911                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* R_028050_DB_Z_WRITE_BASE */
 912                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
 913                 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
 914                 radeon_emit(cmd_buffer->cs, ds->db_depth_slice);        /* R_02805C_DB_DEPTH_SLICE */
 915
 916         }
 917
 918         radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
 919                                ds->pa_su_poly_offset_db_fmt_cntl);
 920 }
 921
 922 void
 923 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
 924                           struct radv_image *image,
 925                           VkClearDepthStencilValue ds_clear_value,
 926                           VkImageAspectFlags aspects)
 927 {
 928         uint64_t va = radv_buffer_get_va(image->bo);
 929         va += image->offset + image->clear_value_offset;
 930         unsigned reg_offset = 0, reg_count = 0;
 931
 932         assert(image->surface.htile_size);
 933
 934         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 935                 ++reg_count;
 936         } else {
 937                 ++reg_offset;
 938                 va += 4;
 939         }
 940         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
 941                 ++reg_count;
 942
 943         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
 944         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
 945                                     S_370_WR_CONFIRM(1) |
 946                                     S_370_ENGINE_SEL(V_370_PFP));
 947         radeon_emit(cmd_buffer->cs, va);
 948         radeon_emit(cmd_buffer->cs, va >> 32);
 949         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
 950                 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
 951         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
 952                 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
 953
 954         radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
 955         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
 956                 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
 957         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
 958                 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
 959 }
 960
 961 static void
 962 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
 963                            struct radv_image *image)
 964 {
 965         VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
 966         uint64_t va = radv_buffer_get_va(image->bo);
 967         va += image->offset + image->clear_value_offset;
 968         unsigned reg_offset = 0, reg_count = 0;
 969
 970         if (!image->surface.htile_size)
 971                 return;
 972
 973         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 974                 ++reg_count;
 975         } else {
 976                 ++reg_offset;
 977                 va += 4;
 978         }
 979         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
 980                 ++reg_count;
 981
 982         radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
 983         radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
 984                                     COPY_DATA_DST_SEL(COPY_DATA_REG) |
 985                                     (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
 986         radeon_emit(cmd_buffer->cs, va);
 987         radeon_emit(cmd_buffer->cs, va >> 32);
 988         radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
 989         radeon_emit(cmd_buffer->cs, 0);
 990
 991         radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
 992         radeon_emit(cmd_buffer->cs, 0);
 993 }
 994
 995 /*
 996  *with DCC some colors don't require CMASK elimiation before being
 997  * used as a texture. This sets a predicate value to determine if the
 998  * cmask eliminate is required.
 999  */
1000 void
1001 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1002                                   struct radv_image *image,
1003                                   bool value)
1004 {
1005         uint64_t pred_val = value;
1006         uint64_t va = radv_buffer_get_va(image->bo);
1007         va += image->offset + image->dcc_pred_offset;
1008
1009         assert(image->surface.dcc_size);
1010
1011         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1012         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1013                                     S_370_WR_CONFIRM(1) |
1014                                     S_370_ENGINE_SEL(V_370_PFP));
1015         radeon_emit(cmd_buffer->cs, va);
1016         radeon_emit(cmd_buffer->cs, va >> 32);
1017         radeon_emit(cmd_buffer->cs, pred_val);
1018         radeon_emit(cmd_buffer->cs, pred_val >> 32);
1019 }
1020
1021 void
1022 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1023                           struct radv_image *image,
1024                           int idx,
1025                           uint32_t color_values[2])
1026 {
1027         uint64_t va = radv_buffer_get_va(image->bo);
1028         va += image->offset + image->clear_value_offset;
1029
1030         assert(image->cmask.size || image->surface.dcc_size);
1031
1032         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1033         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1034                                     S_370_WR_CONFIRM(1) |
1035                                     S_370_ENGINE_SEL(V_370_PFP));
1036         radeon_emit(cmd_buffer->cs, va);
1037         radeon_emit(cmd_buffer->cs, va >> 32);
1038         radeon_emit(cmd_buffer->cs, color_values[0]);
1039         radeon_emit(cmd_buffer->cs, color_values[1]);
1040
1041         radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1042         radeon_emit(cmd_buffer->cs, color_values[0]);
1043         radeon_emit(cmd_buffer->cs, color_values[1]);
1044 }
1045
1046 static void
1047 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1048                            struct radv_image *image,
1049                            int idx)
1050 {
1051         uint64_t va = radv_buffer_get_va(image->bo);
1052         va += image->offset + image->clear_value_offset;
1053
1054         if (!image->cmask.size && !image->surface.dcc_size)
1055                 return;
1056
1057         uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1058
1059         radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1060         radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1061                                     COPY_DATA_DST_SEL(COPY_DATA_REG) |
1062                                     COPY_DATA_COUNT_SEL);
1063         radeon_emit(cmd_buffer->cs, va);
1064         radeon_emit(cmd_buffer->cs, va >> 32);
1065         radeon_emit(cmd_buffer->cs, reg >> 2);
1066         radeon_emit(cmd_buffer->cs, 0);
1067
1068         radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1069         radeon_emit(cmd_buffer->cs, 0);
1070 }
1071
1072 static void
1073 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1074 {
1075         int i;
1076         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1077         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1078
1079         /* this may happen for inherited secondary recording */
1080         if (!framebuffer)
1081                 return;
1082
1083         for (i = 0; i < 8; ++i) {
1084                 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1085                         radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1086                                        S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1087                         continue;
1088                 }
1089
1090                 int idx = subpass->color_attachments[i].attachment;
1091                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1092                 struct radv_image *image = att->attachment->image;
1093                 VkImageLayout layout = subpass->color_attachments[i].layout;
1094
1095                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1096
1097                 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1098                 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1099
1100                 radv_load_color_clear_regs(cmd_buffer, image, i);
1101         }
1102
1103         if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1104                 int idx = subpass->depth_stencil_attachment.attachment;
1105                 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1106                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1107                 struct radv_image *image = att->attachment->image;
1108                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1109                 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1110                                                                                 cmd_buffer->queue_family_index,
1111                                                                                 cmd_buffer->queue_family_index);
1112                 /* We currently don't support writing decompressed HTILE */
1113                 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1114                        radv_layout_is_htile_compressed(image, layout, queue_mask));
1115
1116                 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1117
1118                 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1119                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1120                         cmd_buffer->state.offset_scale = att->ds.offset_scale;
1121                 }
1122                 radv_load_depth_clear_regs(cmd_buffer, image);
1123         } else {
1124                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1125                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1126                 else
1127                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1128
1129                 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1130                 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1131         }
1132         radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1133                                S_028208_BR_X(framebuffer->width) |
1134                                S_028208_BR_Y(framebuffer->height));
1135
1136         if (cmd_buffer->device->dfsm_allowed) {
1137                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1138                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1139         }
1140
1141         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1142 }
1143
1144 static void
1145 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1146 {
1147         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1148         struct radv_cmd_state *state = &cmd_buffer->state;
1149
1150         if (state->index_type != state->last_index_type) {
1151                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1152                         radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1153                                                    2, state->index_type);
1154                 } else {
1155                         radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1156                         radeon_emit(cs, state->index_type);
1157                 }
1158
1159                 state->last_index_type = state->index_type;
1160         }
1161
1162         radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1163         radeon_emit(cs, state->index_va);
1164         radeon_emit(cs, state->index_va >> 32);
1165
1166         radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1167         radeon_emit(cs, state->max_index_count);
1168
1169         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1170 }
1171
1172 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1173 {
1174         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1175         uint32_t pa_sc_mode_cntl_1 =
1176                 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1177         uint32_t db_count_control;
1178
1179         if(!cmd_buffer->state.active_occlusion_queries) {
1180                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1181                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1182                             pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
1183                                 /* Re-enable out-of-order rasterization if the
1184                                  * bound pipeline supports it and if it's has
1185                                  * been disabled before starting occlusion
1186                                  * queries.
1187                                  */
1188                                 radeon_set_context_reg(cmd_buffer->cs,
1189                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1190                                                        pa_sc_mode_cntl_1);
1191                         }
1192                         db_count_control = 0;
1193                 } else {
1194                         db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1195                 }
1196         } else {
1197                 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1198                 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1199
1200                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1201                         db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1202                                 S_028004_SAMPLE_RATE(sample_rate) |
1203                                 S_028004_ZPASS_ENABLE(1) |
1204                                 S_028004_SLICE_EVEN_ENABLE(1) |
1205                                 S_028004_SLICE_ODD_ENABLE(1);
1206
1207                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1208                             pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
1209                                 /* If the bound pipeline has enabled
1210                                  * out-of-order rasterization, we should
1211                                  * disable it before starting occlusion
1212                                  * queries.
1213                                  */
1214                                 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1215
1216                                 radeon_set_context_reg(cmd_buffer->cs,
1217                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1218                                                        pa_sc_mode_cntl_1);
1219                         }
1220                 } else {
1221                         db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1222                                 S_028004_SAMPLE_RATE(sample_rate);
1223                 }
1224         }
1225
1226         radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1227 }
1228
1229 static void
1230 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1231 {
1232         uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1233
1234         if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1235                 radv_emit_viewport(cmd_buffer);
1236
1237         if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1238                 radv_emit_scissor(cmd_buffer);
1239
1240         if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1241                 radv_emit_line_width(cmd_buffer);
1242
1243         if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1244                 radv_emit_blend_constants(cmd_buffer);
1245
1246         if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1247                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1248                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1249                 radv_emit_stencil(cmd_buffer);
1250
1251         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1252                 radv_emit_depth_bounds(cmd_buffer);
1253
1254         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1255                 radv_emit_depth_bias(cmd_buffer);
1256
1257         if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1258                 radv_emit_discard_rectangle(cmd_buffer);
1259
1260         cmd_buffer->state.dirty &= ~states;
1261 }
1262
1263 static void
1264 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1265                                    struct radv_pipeline *pipeline,
1266                                    int idx,
1267                                    uint64_t va,
1268                                    gl_shader_stage stage)
1269 {
1270         struct radv_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1271         uint32_t base_reg = pipeline->user_data_0[stage];
1272
1273         if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1274                 return;
1275
1276         assert(!desc_set_loc->indirect);
1277         assert(desc_set_loc->num_sgprs == 2);
1278         radeon_set_sh_reg_seq(cmd_buffer->cs,
1279                               base_reg + desc_set_loc->sgpr_idx * 4, 2);
1280         radeon_emit(cmd_buffer->cs, va);
1281         radeon_emit(cmd_buffer->cs, va >> 32);
1282 }
1283
1284 static void
1285 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1286                                   VkShaderStageFlags stages,
1287                                   struct radv_descriptor_set *set,
1288                                   unsigned idx)
1289 {
1290         if (cmd_buffer->state.pipeline) {
1291                 radv_foreach_stage(stage, stages) {
1292                         if (cmd_buffer->state.pipeline->shaders[stage])
1293                                 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1294                                                                    idx, set->va,
1295                                                                    stage);
1296                 }
1297         }
1298
1299         if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1300                 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1301                                                    idx, set->va,
1302                                                    MESA_SHADER_COMPUTE);
1303 }
1304
1305 static void
1306 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1307                             VkPipelineBindPoint bind_point)
1308 {
1309         struct radv_descriptor_state *descriptors_state =
1310                 radv_get_descriptors_state(cmd_buffer, bind_point);
1311         struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1312         unsigned bo_offset;
1313
1314         if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1315                                          set->mapped_ptr,
1316                                          &bo_offset))
1317                 return;
1318
1319         set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1320         set->va += bo_offset;
1321 }
1322
1323 static void
1324 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1325                                     VkPipelineBindPoint bind_point)
1326 {
1327         struct radv_descriptor_state *descriptors_state =
1328                 radv_get_descriptors_state(cmd_buffer, bind_point);
1329         uint32_t size = MAX_SETS * 2 * 4;
1330         uint32_t offset;
1331         void *ptr;
1332
1333         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1334                                           256, &offset, &ptr))
1335                 return;
1336
1337         for (unsigned i = 0; i < MAX_SETS; i++) {
1338                 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1339                 uint64_t set_va = 0;
1340                 struct radv_descriptor_set *set = descriptors_state->sets[i];
1341                 if (descriptors_state->valid & (1u << i))
1342                         set_va = set->va;
1343                 uptr[0] = set_va & 0xffffffff;
1344                 uptr[1] = set_va >> 32;
1345         }
1346
1347         uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1348         va += offset;
1349
1350         if (cmd_buffer->state.pipeline) {
1351                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1352                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1353                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1354
1355                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1356                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1357                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1358
1359                 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1360                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1361                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1362
1363                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1364                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1365                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1366
1367                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1368                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1369                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1370         }
1371
1372         if (cmd_buffer->state.compute_pipeline)
1373                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1374                                            AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1375 }
1376
1377 static void
1378 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1379                        VkShaderStageFlags stages)
1380 {
1381         VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1382                                          VK_PIPELINE_BIND_POINT_COMPUTE :
1383                                          VK_PIPELINE_BIND_POINT_GRAPHICS;
1384         struct radv_descriptor_state *descriptors_state =
1385                 radv_get_descriptors_state(cmd_buffer, bind_point);
1386         unsigned i;
1387
1388         if (!descriptors_state->dirty)
1389                 return;
1390
1391         if (descriptors_state->push_dirty)
1392                 radv_flush_push_descriptors(cmd_buffer, bind_point);
1393
1394         if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1395             (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1396                 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1397         }
1398
1399         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1400                                                            cmd_buffer->cs,
1401                                                            MAX_SETS * MESA_SHADER_STAGES * 4);
1402
1403         for_each_bit(i, descriptors_state->dirty) {
1404                 struct radv_descriptor_set *set = descriptors_state->sets[i];
1405                 if (!(descriptors_state->valid & (1u << i)))
1406                         continue;
1407
1408                 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1409         }
1410         descriptors_state->dirty = 0;
1411         descriptors_state->push_dirty = false;
1412
1413         if (unlikely(cmd_buffer->device->trace_bo))
1414                 radv_save_descriptors(cmd_buffer, bind_point);
1415
1416         assert(cmd_buffer->cs->cdw <= cdw_max);
1417 }
1418
1419 static void
1420 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1421                      struct radv_pipeline *pipeline,
1422                      VkShaderStageFlags stages)
1423 {
1424         struct radv_pipeline_layout *layout = pipeline->layout;
1425         unsigned offset;
1426         void *ptr;
1427         uint64_t va;
1428
1429         stages &= cmd_buffer->push_constant_stages;
1430         if (!stages ||
1431             (!layout->push_constant_size && !layout->dynamic_offset_count))
1432                 return;
1433
1434         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1435                                           16 * layout->dynamic_offset_count,
1436                                           256, &offset, &ptr))
1437                 return;
1438
1439         memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1440         memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1441                16 * layout->dynamic_offset_count);
1442
1443         va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1444         va += offset;
1445
1446         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1447                                                            cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1448
1449         radv_foreach_stage(stage, stages) {
1450                 if (pipeline->shaders[stage]) {
1451                         radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1452                                                    AC_UD_PUSH_CONSTANTS, va);
1453                 }
1454         }
1455
1456         cmd_buffer->push_constant_stages &= ~stages;
1457         assert(cmd_buffer->cs->cdw <= cdw_max);
1458 }
1459
1460 static bool
1461 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1462 {
1463         if ((pipeline_is_dirty ||
1464             (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1465             cmd_buffer->state.pipeline->vertex_elements.count &&
1466             radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1467                 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1468                 unsigned vb_offset;
1469                 void *vb_ptr;
1470                 uint32_t i = 0;
1471                 uint32_t count = velems->count;
1472                 uint64_t va;
1473
1474                 /* allocate some descriptor state for vertex buffers */
1475                 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1476                                                   &vb_offset, &vb_ptr))
1477                         return false;
1478
1479                 for (i = 0; i < count; i++) {
1480                         uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1481                         uint32_t offset;
1482                         int vb = velems->binding[i];
1483                         struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1484                         uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1485
1486                         va = radv_buffer_get_va(buffer->bo);
1487
1488                         offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1489                         va += offset + buffer->offset;
1490                         desc[0] = va;
1491                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1492                         if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1493                                 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1494                         else
1495                                 desc[2] = buffer->size - offset;
1496                         desc[3] = velems->rsrc_word3[i];
1497                 }
1498
1499                 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1500                 va += vb_offset;
1501
1502                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1503                                            AC_UD_VS_VERTEX_BUFFERS, va);
1504
1505                 cmd_buffer->state.vb_va = va;
1506                 cmd_buffer->state.vb_size = count * 16;
1507                 cmd_buffer->state.vb_prefetch_dirty = true;
1508         }
1509         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1510
1511         return true;
1512 }
1513
1514 static bool
1515 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1516 {
1517         if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1518                 return false;
1519
1520         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1521         radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1522                              VK_SHADER_STAGE_ALL_GRAPHICS);
1523
1524         return true;
1525 }
1526
1527 static void
1528 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1529                          bool instanced_draw, bool indirect_draw,
1530                          uint32_t draw_vertex_count)
1531 {
1532         struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1533         struct radv_cmd_state *state = &cmd_buffer->state;
1534         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1535         uint32_t ia_multi_vgt_param;
1536         int32_t primitive_reset_en;
1537
1538         /* Draw state. */
1539         ia_multi_vgt_param =
1540                 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1541                                           indirect_draw, draw_vertex_count);
1542
1543         if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1544                 if (info->chip_class >= GFX9) {
1545                         radeon_set_uconfig_reg_idx(cs,
1546                                                    R_030960_IA_MULTI_VGT_PARAM,
1547                                                    4, ia_multi_vgt_param);
1548                 } else if (info->chip_class >= CIK) {
1549                         radeon_set_context_reg_idx(cs,
1550                                                    R_028AA8_IA_MULTI_VGT_PARAM,
1551                                                    1, ia_multi_vgt_param);
1552                 } else {
1553                         radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1554                                                ia_multi_vgt_param);
1555                 }
1556                 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1557         }
1558
1559         /* Primitive restart. */
1560         primitive_reset_en =
1561                 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1562
1563         if (primitive_reset_en != state->last_primitive_reset_en) {
1564                 state->last_primitive_reset_en = primitive_reset_en;
1565                 if (info->chip_class >= GFX9) {
1566                         radeon_set_uconfig_reg(cs,
1567                                                R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1568                                                primitive_reset_en);
1569                 } else {
1570                         radeon_set_context_reg(cs,
1571                                                R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1572                                                primitive_reset_en);
1573                 }
1574         }
1575
1576         if (primitive_reset_en) {
1577                 uint32_t primitive_reset_index =
1578                         state->index_type ? 0xffffffffu : 0xffffu;
1579
1580                 if (primitive_reset_index != state->last_primitive_reset_index) {
1581                         radeon_set_context_reg(cs,
1582                                                R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1583                                                primitive_reset_index);
1584                         state->last_primitive_reset_index = primitive_reset_index;
1585                 }
1586         }
1587 }
1588
1589 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1590                              VkPipelineStageFlags src_stage_mask)
1591 {
1592         if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1593                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1594                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1595                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1596                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1597         }
1598
1599         if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1600                               VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1601                               VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1602                               VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1603                               VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1604                               VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1605                               VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1606                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1607                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1608                               VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1609                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1610                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1611         } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1612                                      VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1613                                      VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1614                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1615         }
1616 }
1617
1618 static enum radv_cmd_flush_bits
1619 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1620                                   VkAccessFlags src_flags)
1621 {
1622         enum radv_cmd_flush_bits flush_bits = 0;
1623         uint32_t b;
1624         for_each_bit(b, src_flags) {
1625                 switch ((VkAccessFlagBits)(1 << b)) {
1626                 case VK_ACCESS_SHADER_WRITE_BIT:
1627                         flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1628                         break;
1629                 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1630                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1631                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1632                         break;
1633                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1634                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1635                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1636                         break;
1637                 case VK_ACCESS_TRANSFER_WRITE_BIT:
1638                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1639                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1640                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1641                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1642                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
1643                         break;
1644                 default:
1645                         break;
1646                 }
1647         }
1648         return flush_bits;
1649 }
1650
1651 static enum radv_cmd_flush_bits
1652 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1653                       VkAccessFlags dst_flags,
1654                       struct radv_image *image)
1655 {
1656         enum radv_cmd_flush_bits flush_bits = 0;
1657         uint32_t b;
1658         for_each_bit(b, dst_flags) {
1659                 switch ((VkAccessFlagBits)(1 << b)) {
1660                 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1661                 case VK_ACCESS_INDEX_READ_BIT:
1662                         break;
1663                 case VK_ACCESS_UNIFORM_READ_BIT:
1664                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1665                         break;
1666                 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1667                 case VK_ACCESS_SHADER_READ_BIT:
1668                 case VK_ACCESS_TRANSFER_READ_BIT:
1669                 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1670                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1671                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
1672                         break;
1673                 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1674                         /* TODO: change to image && when the image gets passed
1675                          * through from the subpass. */
1676                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1677                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1678                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1679                         break;
1680                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1681                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1682                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1683                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1684                         break;
1685                 default:
1686                         break;
1687                 }
1688         }
1689         return flush_bits;
1690 }
1691
1692 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1693 {
1694         cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1695         radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1696         cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1697                                                               NULL);
1698 }
1699
1700 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1701                                                  VkAttachmentReference att)
1702 {
1703         unsigned idx = att.attachment;
1704         struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1705         VkImageSubresourceRange range;
1706         range.aspectMask = 0;
1707         range.baseMipLevel = view->base_mip;
1708         range.levelCount = 1;
1709         range.baseArrayLayer = view->base_layer;
1710         range.layerCount = cmd_buffer->state.framebuffer->layers;
1711
1712         radv_handle_image_transition(cmd_buffer,
1713                                      view->image,
1714                                      cmd_buffer->state.attachments[idx].current_layout,
1715                                      att.layout, 0, 0, &range,
1716                                      cmd_buffer->state.attachments[idx].pending_clear_aspects);
1717
1718         cmd_buffer->state.attachments[idx].current_layout = att.layout;
1719
1720
1721 }
1722
1723 void
1724 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1725                             const struct radv_subpass *subpass, bool transitions)
1726 {
1727         if (transitions) {
1728                 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1729
1730                 for (unsigned i = 0; i < subpass->color_count; ++i) {
1731                         if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1732                                 radv_handle_subpass_image_transition(cmd_buffer,
1733                                                                      subpass->color_attachments[i]);
1734                 }
1735
1736                 for (unsigned i = 0; i < subpass->input_count; ++i) {
1737                         radv_handle_subpass_image_transition(cmd_buffer,
1738                                                         subpass->input_attachments[i]);
1739                 }
1740
1741                 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1742                         radv_handle_subpass_image_transition(cmd_buffer,
1743                                                         subpass->depth_stencil_attachment);
1744                 }
1745         }
1746
1747         cmd_buffer->state.subpass = subpass;
1748
1749         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
1750 }
1751
1752 static VkResult
1753 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1754                                  struct radv_render_pass *pass,
1755                                  const VkRenderPassBeginInfo *info)
1756 {
1757         struct radv_cmd_state *state = &cmd_buffer->state;
1758
1759         if (pass->attachment_count == 0) {
1760                 state->attachments = NULL;
1761                 return VK_SUCCESS;
1762         }
1763
1764         state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1765                                         pass->attachment_count *
1766                                         sizeof(state->attachments[0]),
1767                                         8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1768         if (state->attachments == NULL) {
1769                 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1770                 return cmd_buffer->record_result;
1771         }
1772
1773         for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1774                 struct radv_render_pass_attachment *att = &pass->attachments[i];
1775                 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1776                 VkImageAspectFlags clear_aspects = 0;
1777
1778                 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1779                         /* color attachment */
1780                         if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1781                                 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1782                         }
1783                 } else {
1784                         /* depthstencil attachment */
1785                         if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1786                             att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1787                                 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1788                                 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1789                                     att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1790                                         clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1791                         }
1792                         if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1793                             att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1794                                 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1795                         }
1796                 }
1797
1798                 state->attachments[i].pending_clear_aspects = clear_aspects;
1799                 state->attachments[i].cleared_views = 0;
1800                 if (clear_aspects && info) {
1801                         assert(info->clearValueCount > i);
1802                         state->attachments[i].clear_value = info->pClearValues[i];
1803                 }
1804
1805                 state->attachments[i].current_layout = att->initial_layout;
1806         }
1807
1808         return VK_SUCCESS;
1809 }
1810
1811 VkResult radv_AllocateCommandBuffers(
1812         VkDevice _device,
1813         const VkCommandBufferAllocateInfo *pAllocateInfo,
1814         VkCommandBuffer *pCommandBuffers)
1815 {
1816         RADV_FROM_HANDLE(radv_device, device, _device);
1817         RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1818
1819         VkResult result = VK_SUCCESS;
1820         uint32_t i;
1821
1822         for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1823
1824                 if (!list_empty(&pool->free_cmd_buffers)) {
1825                         struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1826
1827                         list_del(&cmd_buffer->pool_link);
1828                         list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1829
1830                         result = radv_reset_cmd_buffer(cmd_buffer);
1831                         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1832                         cmd_buffer->level = pAllocateInfo->level;
1833
1834                         pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1835                 } else {
1836                         result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1837                                                         &pCommandBuffers[i]);
1838                 }
1839                 if (result != VK_SUCCESS)
1840                         break;
1841         }
1842
1843         if (result != VK_SUCCESS) {
1844                 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1845                                         i, pCommandBuffers);
1846
1847                 /* From the Vulkan 1.0.66 spec:
1848                  *
1849                  * "vkAllocateCommandBuffers can be used to create multiple
1850                  *  command buffers. If the creation of any of those command
1851                  *  buffers fails, the implementation must destroy all
1852                  *  successfully created command buffer objects from this
1853                  *  command, set all entries of the pCommandBuffers array to
1854                  *  NULL and return the error."
1855                  */
1856                 memset(pCommandBuffers, 0,
1857                        sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1858         }
1859
1860         return result;
1861 }
1862
1863 void radv_FreeCommandBuffers(
1864         VkDevice device,
1865         VkCommandPool commandPool,
1866         uint32_t commandBufferCount,
1867         const VkCommandBuffer *pCommandBuffers)
1868 {
1869         for (uint32_t i = 0; i < commandBufferCount; i++) {
1870                 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1871
1872                 if (cmd_buffer) {
1873                         if (cmd_buffer->pool) {
1874                                 list_del(&cmd_buffer->pool_link);
1875                                 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1876                         } else
1877                                 radv_cmd_buffer_destroy(cmd_buffer);
1878
1879                 }
1880         }
1881 }
1882
1883 VkResult radv_ResetCommandBuffer(
1884         VkCommandBuffer commandBuffer,
1885         VkCommandBufferResetFlags flags)
1886 {
1887         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1888         return radv_reset_cmd_buffer(cmd_buffer);
1889 }
1890
1891 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1892 {
1893         struct radv_device *device = cmd_buffer->device;
1894         if (device->gfx_init) {
1895                 uint64_t va = radv_buffer_get_va(device->gfx_init);
1896                 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
1897                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1898                 radeon_emit(cmd_buffer->cs, va);
1899                 radeon_emit(cmd_buffer->cs, va >> 32);
1900                 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1901         } else
1902                 si_init_config(cmd_buffer);
1903 }
1904
1905 VkResult radv_BeginCommandBuffer(
1906         VkCommandBuffer commandBuffer,
1907         const VkCommandBufferBeginInfo *pBeginInfo)
1908 {
1909         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1910         VkResult result = VK_SUCCESS;
1911
1912         if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
1913                 /* If the command buffer has already been resetted with
1914                  * vkResetCommandBuffer, no need to do it again.
1915                  */
1916                 result = radv_reset_cmd_buffer(cmd_buffer);
1917                 if (result != VK_SUCCESS)
1918                         return result;
1919         }
1920
1921         memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1922         cmd_buffer->state.last_primitive_reset_en = -1;
1923         cmd_buffer->state.last_index_type = -1;
1924         cmd_buffer->state.last_num_instances = -1;
1925         cmd_buffer->state.last_vertex_offset = -1;
1926         cmd_buffer->state.last_first_instance = -1;
1927         cmd_buffer->usage_flags = pBeginInfo->flags;
1928
1929         /* setup initial configuration into command buffer */
1930         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1931                 switch (cmd_buffer->queue_family_index) {
1932                 case RADV_QUEUE_GENERAL:
1933                         emit_gfx_buffer_state(cmd_buffer);
1934                         break;
1935                 case RADV_QUEUE_COMPUTE:
1936                         si_init_compute(cmd_buffer);
1937                         break;
1938                 case RADV_QUEUE_TRANSFER:
1939                 default:
1940                         break;
1941                 }
1942         }
1943
1944         if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1945                 assert(pBeginInfo->pInheritanceInfo);
1946                 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1947                 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1948
1949                 struct radv_subpass *subpass =
1950                         &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1951
1952                 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1953                 if (result != VK_SUCCESS)
1954                         return result;
1955
1956                 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1957         }
1958
1959         if (unlikely(cmd_buffer->device->trace_bo))
1960                 radv_cmd_buffer_trace_emit(cmd_buffer);
1961
1962         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
1963
1964         return result;
1965 }
1966
1967 void radv_CmdBindVertexBuffers(
1968         VkCommandBuffer                             commandBuffer,
1969         uint32_t                                    firstBinding,
1970         uint32_t                                    bindingCount,
1971         const VkBuffer*                             pBuffers,
1972         const VkDeviceSize*                         pOffsets)
1973 {
1974         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1975         struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
1976         bool changed = false;
1977
1978         /* We have to defer setting up vertex buffer since we need the buffer
1979          * stride from the pipeline. */
1980
1981         assert(firstBinding + bindingCount <= MAX_VBS);
1982         for (uint32_t i = 0; i < bindingCount; i++) {
1983                 uint32_t idx = firstBinding + i;
1984
1985                 if (!changed &&
1986                     (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
1987                      vb[idx].offset != pOffsets[i])) {
1988                         changed = true;
1989                 }
1990
1991                 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
1992                 vb[idx].offset = pOffsets[i];
1993
1994                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1995                                    vb[idx].buffer->bo, 8);
1996         }
1997
1998         if (!changed) {
1999                 /* No state changes. */
2000                 return;
2001         }
2002
2003         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2004 }
2005
2006 void radv_CmdBindIndexBuffer(
2007         VkCommandBuffer                             commandBuffer,
2008         VkBuffer buffer,
2009         VkDeviceSize offset,
2010         VkIndexType indexType)
2011 {
2012         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2013         RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2014
2015         if (cmd_buffer->state.index_buffer == index_buffer &&
2016             cmd_buffer->state.index_offset == offset &&
2017             cmd_buffer->state.index_type == indexType) {
2018                 /* No state changes. */
2019                 return;
2020         }
2021
2022         cmd_buffer->state.index_buffer = index_buffer;
2023         cmd_buffer->state.index_offset = offset;
2024         cmd_buffer->state.index_type = indexType; /* vk matches hw */
2025         cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2026         cmd_buffer->state.index_va += index_buffer->offset + offset;
2027
2028         int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2029         cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2030         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2031         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2032 }
2033
2034
2035 static void
2036 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2037                          VkPipelineBindPoint bind_point,
2038                          struct radv_descriptor_set *set, unsigned idx)
2039 {
2040         struct radeon_winsys *ws = cmd_buffer->device->ws;
2041
2042         radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2043         if (!set)
2044                 return;
2045
2046         assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2047
2048         for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2049                 if (set->descriptors[j])
2050                         radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2051
2052         if(set->bo)
2053                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2054 }
2055
2056 void radv_CmdBindDescriptorSets(
2057         VkCommandBuffer                             commandBuffer,
2058         VkPipelineBindPoint                         pipelineBindPoint,
2059         VkPipelineLayout                            _layout,
2060         uint32_t                                    firstSet,
2061         uint32_t                                    descriptorSetCount,
2062         const VkDescriptorSet*                      pDescriptorSets,
2063         uint32_t                                    dynamicOffsetCount,
2064         const uint32_t*                             pDynamicOffsets)
2065 {
2066         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2067         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2068         unsigned dyn_idx = 0;
2069
2070         for (unsigned i = 0; i < descriptorSetCount; ++i) {
2071                 unsigned idx = i + firstSet;
2072                 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2073                 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2074
2075                 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2076                         unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2077                         uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2078                         assert(dyn_idx < dynamicOffsetCount);
2079
2080                         struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2081                         uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2082                         dst[0] = va;
2083                         dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2084                         dst[2] = range->size;
2085                         dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2086                                  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2087                                  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2088                                  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2089                                  S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2090                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2091                         cmd_buffer->push_constant_stages |=
2092                                              set->layout->dynamic_shader_stages;
2093                 }
2094         }
2095 }
2096
2097 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2098                                           struct radv_descriptor_set *set,
2099                                           struct radv_descriptor_set_layout *layout,
2100                                           VkPipelineBindPoint bind_point)
2101 {
2102         struct radv_descriptor_state *descriptors_state =
2103                 radv_get_descriptors_state(cmd_buffer, bind_point);
2104         set->size = layout->size;
2105         set->layout = layout;
2106
2107         if (descriptors_state->push_set.capacity < set->size) {
2108                 size_t new_size = MAX2(set->size, 1024);
2109                 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2110                 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2111
2112                 free(set->mapped_ptr);
2113                 set->mapped_ptr = malloc(new_size);
2114
2115                 if (!set->mapped_ptr) {
2116                         descriptors_state->push_set.capacity = 0;
2117                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2118                         return false;
2119                 }
2120
2121                 descriptors_state->push_set.capacity = new_size;
2122         }
2123
2124         return true;
2125 }
2126
2127 void radv_meta_push_descriptor_set(
2128         struct radv_cmd_buffer*              cmd_buffer,
2129         VkPipelineBindPoint                  pipelineBindPoint,
2130         VkPipelineLayout                     _layout,
2131         uint32_t                             set,
2132         uint32_t                             descriptorWriteCount,
2133         const VkWriteDescriptorSet*          pDescriptorWrites)
2134 {
2135         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2136         struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2137         unsigned bo_offset;
2138
2139         assert(set == 0);
2140         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2141
2142         push_set->size = layout->set[set].layout->size;
2143         push_set->layout = layout->set[set].layout;
2144
2145         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2146                                           &bo_offset,
2147                                           (void**) &push_set->mapped_ptr))
2148                 return;
2149
2150         push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2151         push_set->va += bo_offset;
2152
2153         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2154                                     radv_descriptor_set_to_handle(push_set),
2155                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2156
2157         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2158 }
2159
2160 void radv_CmdPushDescriptorSetKHR(
2161         VkCommandBuffer                             commandBuffer,
2162         VkPipelineBindPoint                         pipelineBindPoint,
2163         VkPipelineLayout                            _layout,
2164         uint32_t                                    set,
2165         uint32_t                                    descriptorWriteCount,
2166         const VkWriteDescriptorSet*                 pDescriptorWrites)
2167 {
2168         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2169         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2170         struct radv_descriptor_state *descriptors_state =
2171                 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2172         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2173
2174         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2175
2176         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2177                                            layout->set[set].layout,
2178                                            pipelineBindPoint))
2179                 return;
2180
2181         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2182                                     radv_descriptor_set_to_handle(push_set),
2183                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2184
2185         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2186         descriptors_state->push_dirty = true;
2187 }
2188
2189 void radv_CmdPushDescriptorSetWithTemplateKHR(
2190         VkCommandBuffer                             commandBuffer,
2191         VkDescriptorUpdateTemplateKHR               descriptorUpdateTemplate,
2192         VkPipelineLayout                            _layout,
2193         uint32_t                                    set,
2194         const void*                                 pData)
2195 {
2196         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2197         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2198         RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2199         struct radv_descriptor_state *descriptors_state =
2200                 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2201         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2202
2203         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2204
2205         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2206                                            layout->set[set].layout,
2207                                            templ->bind_point))
2208                 return;
2209
2210         radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2211                                                  descriptorUpdateTemplate, pData);
2212
2213         radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2214         descriptors_state->push_dirty = true;
2215 }
2216
2217 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2218                            VkPipelineLayout layout,
2219                            VkShaderStageFlags stageFlags,
2220                            uint32_t offset,
2221                            uint32_t size,
2222                            const void* pValues)
2223 {
2224         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2225         memcpy(cmd_buffer->push_constants + offset, pValues, size);
2226         cmd_buffer->push_constant_stages |= stageFlags;
2227 }
2228
2229 VkResult radv_EndCommandBuffer(
2230         VkCommandBuffer                             commandBuffer)
2231 {
2232         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2233
2234         if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2235                 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2236                         cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2237                 si_emit_cache_flush(cmd_buffer);
2238         }
2239
2240         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2241
2242         if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2243                 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2244
2245         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2246
2247         return cmd_buffer->record_result;
2248 }
2249
2250 static void
2251 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2252 {
2253         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2254
2255         if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2256                 return;
2257
2258         cmd_buffer->state.emitted_compute_pipeline = pipeline;
2259
2260         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2261         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2262
2263         cmd_buffer->compute_scratch_size_needed =
2264                                   MAX2(cmd_buffer->compute_scratch_size_needed,
2265                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2266
2267         if (unlikely(cmd_buffer->device->trace_bo))
2268                 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2269 }
2270
2271 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2272                                             VkPipelineBindPoint bind_point)
2273 {
2274         struct radv_descriptor_state *descriptors_state =
2275                 radv_get_descriptors_state(cmd_buffer, bind_point);
2276
2277         descriptors_state->dirty |= descriptors_state->valid;
2278 }
2279
2280 void radv_CmdBindPipeline(
2281         VkCommandBuffer                             commandBuffer,
2282         VkPipelineBindPoint                         pipelineBindPoint,
2283         VkPipeline                                  _pipeline)
2284 {
2285         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2286         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2287
2288         switch (pipelineBindPoint) {
2289         case VK_PIPELINE_BIND_POINT_COMPUTE:
2290                 if (cmd_buffer->state.compute_pipeline == pipeline)
2291                         return;
2292                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2293
2294                 cmd_buffer->state.compute_pipeline = pipeline;
2295                 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2296                 break;
2297         case VK_PIPELINE_BIND_POINT_GRAPHICS:
2298                 if (cmd_buffer->state.pipeline == pipeline)
2299                         return;
2300                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2301
2302                 cmd_buffer->state.pipeline = pipeline;
2303                 if (!pipeline)
2304                         break;
2305
2306                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2307                 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2308
2309                 /* the new vertex shader might not have the same user regs */
2310                 cmd_buffer->state.last_first_instance = -1;
2311                 cmd_buffer->state.last_vertex_offset = -1;
2312
2313                 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2314
2315                 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2316                         cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2317                 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2318                         cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2319
2320                 if (radv_pipeline_has_tess(pipeline))
2321                         cmd_buffer->tess_rings_needed = true;
2322
2323                 if (radv_pipeline_has_gs(pipeline)) {
2324                         struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2325                                                                              AC_UD_SCRATCH_RING_OFFSETS);
2326                         if (cmd_buffer->ring_offsets_idx == -1)
2327                                 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2328                         else if (loc->sgpr_idx != -1)
2329                                 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2330                 }
2331                 break;
2332         default:
2333                 assert(!"invalid bind point");
2334                 break;
2335         }
2336 }
2337
2338 void radv_CmdSetViewport(
2339         VkCommandBuffer                             commandBuffer,
2340         uint32_t                                    firstViewport,
2341         uint32_t                                    viewportCount,
2342         const VkViewport*                           pViewports)
2343 {
2344         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2345         struct radv_cmd_state *state = &cmd_buffer->state;
2346         MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2347
2348         assert(firstViewport < MAX_VIEWPORTS);
2349         assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2350
2351         if (cmd_buffer->device->physical_device->has_scissor_bug) {
2352                 /* Try to skip unnecessary PS partial flushes when the viewports
2353                  * don't change.
2354                  */
2355                 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2356                                       RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2357                     !memcmp(state->dynamic.viewport.viewports + firstViewport,
2358                             pViewports, viewportCount * sizeof(*pViewports))) {
2359                         return;
2360                 }
2361         }
2362
2363         memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2364                viewportCount * sizeof(*pViewports));
2365
2366         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2367 }
2368
2369 void radv_CmdSetScissor(
2370         VkCommandBuffer                             commandBuffer,
2371         uint32_t                                    firstScissor,
2372         uint32_t                                    scissorCount,
2373         const VkRect2D*                             pScissors)
2374 {
2375         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2376         struct radv_cmd_state *state = &cmd_buffer->state;
2377         MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2378
2379         assert(firstScissor < MAX_SCISSORS);
2380         assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2381
2382         if (cmd_buffer->device->physical_device->has_scissor_bug) {
2383                 /* Try to skip unnecessary PS partial flushes when the scissors
2384                  * don't change.
2385                  */
2386                 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2387                                       RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2388                     !memcmp(state->dynamic.scissor.scissors + firstScissor,
2389                             pScissors, scissorCount * sizeof(*pScissors))) {
2390                         return;
2391                 }
2392         }
2393
2394         memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2395                scissorCount * sizeof(*pScissors));
2396
2397         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2398 }
2399
2400 void radv_CmdSetLineWidth(
2401         VkCommandBuffer                             commandBuffer,
2402         float                                       lineWidth)
2403 {
2404         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2405         cmd_buffer->state.dynamic.line_width = lineWidth;
2406         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2407 }
2408
2409 void radv_CmdSetDepthBias(
2410         VkCommandBuffer                             commandBuffer,
2411         float                                       depthBiasConstantFactor,
2412         float                                       depthBiasClamp,
2413         float                                       depthBiasSlopeFactor)
2414 {
2415         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2416
2417         cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2418         cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2419         cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2420
2421         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2422 }
2423
2424 void radv_CmdSetBlendConstants(
2425         VkCommandBuffer                             commandBuffer,
2426         const float                                 blendConstants[4])
2427 {
2428         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2429
2430         memcpy(cmd_buffer->state.dynamic.blend_constants,
2431                blendConstants, sizeof(float) * 4);
2432
2433         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2434 }
2435
2436 void radv_CmdSetDepthBounds(
2437         VkCommandBuffer                             commandBuffer,
2438         float                                       minDepthBounds,
2439         float                                       maxDepthBounds)
2440 {
2441         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2442
2443         cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2444         cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2445
2446         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2447 }
2448
2449 void radv_CmdSetStencilCompareMask(
2450         VkCommandBuffer                             commandBuffer,
2451         VkStencilFaceFlags                          faceMask,
2452         uint32_t                                    compareMask)
2453 {
2454         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2455
2456         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2457                 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2458         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2459                 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2460
2461         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2462 }
2463
2464 void radv_CmdSetStencilWriteMask(
2465         VkCommandBuffer                             commandBuffer,
2466         VkStencilFaceFlags                          faceMask,
2467         uint32_t                                    writeMask)
2468 {
2469         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2470
2471         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2472                 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2473         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2474                 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2475
2476         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2477 }
2478
2479 void radv_CmdSetStencilReference(
2480         VkCommandBuffer                             commandBuffer,
2481         VkStencilFaceFlags                          faceMask,
2482         uint32_t                                    reference)
2483 {
2484         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2485
2486         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2487                 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2488         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2489                 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2490
2491         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2492 }
2493
2494 void radv_CmdSetDiscardRectangleEXT(
2495         VkCommandBuffer                             commandBuffer,
2496         uint32_t                                    firstDiscardRectangle,
2497         uint32_t                                    discardRectangleCount,
2498         const VkRect2D*                             pDiscardRectangles)
2499 {
2500         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2501         struct radv_cmd_state *state = &cmd_buffer->state;
2502         MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2503
2504         assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2505         assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2506
2507         typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2508                      pDiscardRectangles, discardRectangleCount);
2509
2510         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2511 }
2512
2513 void radv_CmdExecuteCommands(
2514         VkCommandBuffer                             commandBuffer,
2515         uint32_t                                    commandBufferCount,
2516         const VkCommandBuffer*                      pCmdBuffers)
2517 {
2518         RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2519
2520         assert(commandBufferCount > 0);
2521
2522         /* Emit pending flushes on primary prior to executing secondary */
2523         si_emit_cache_flush(primary);
2524
2525         for (uint32_t i = 0; i < commandBufferCount; i++) {
2526                 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2527
2528                 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2529                                                     secondary->scratch_size_needed);
2530                 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2531                                                             secondary->compute_scratch_size_needed);
2532
2533                 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2534                         primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2535                 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2536                         primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2537                 if (secondary->tess_rings_needed)
2538                         primary->tess_rings_needed = true;
2539                 if (secondary->sample_positions_needed)
2540                         primary->sample_positions_needed = true;
2541
2542                 if (secondary->ring_offsets_idx != -1) {
2543                         if (primary->ring_offsets_idx == -1)
2544                                 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2545                         else
2546                                 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2547                 }
2548                 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2549
2550
2551                 /* When the secondary command buffer is compute only we don't
2552                  * need to re-emit the current graphics pipeline.
2553                  */
2554                 if (secondary->state.emitted_pipeline) {
2555                         primary->state.emitted_pipeline =
2556                                 secondary->state.emitted_pipeline;
2557                 }
2558
2559                 /* When the secondary command buffer is graphics only we don't
2560                  * need to re-emit the current compute pipeline.
2561                  */
2562                 if (secondary->state.emitted_compute_pipeline) {
2563                         primary->state.emitted_compute_pipeline =
2564                                 secondary->state.emitted_compute_pipeline;
2565                 }
2566
2567                 /* Only re-emit the draw packets when needed. */
2568                 if (secondary->state.last_primitive_reset_en != -1) {
2569                         primary->state.last_primitive_reset_en =
2570                                 secondary->state.last_primitive_reset_en;
2571                 }
2572
2573                 if (secondary->state.last_primitive_reset_index) {
2574                         primary->state.last_primitive_reset_index =
2575                                 secondary->state.last_primitive_reset_index;
2576                 }
2577
2578                 if (secondary->state.last_ia_multi_vgt_param) {
2579                         primary->state.last_ia_multi_vgt_param =
2580                                 secondary->state.last_ia_multi_vgt_param;
2581                 }
2582
2583                 if (secondary->state.last_first_instance != -1) {
2584                         primary->state.last_first_instance =
2585                                 secondary->state.last_first_instance;
2586                 }
2587
2588                 if (secondary->state.last_num_instances != -1) {
2589                         primary->state.last_num_instances =
2590                                 secondary->state.last_num_instances;
2591                 }
2592
2593                 if (secondary->state.last_vertex_offset != -1) {
2594                         primary->state.last_vertex_offset =
2595                                 secondary->state.last_vertex_offset;
2596                 }
2597
2598                 if (secondary->state.last_index_type != -1) {
2599                         primary->state.last_index_type =
2600                                 secondary->state.last_index_type;
2601                 }
2602         }
2603
2604         /* After executing commands from secondary buffers we have to dirty
2605          * some states.
2606          */
2607         primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2608                                 RADV_CMD_DIRTY_INDEX_BUFFER |
2609                                 RADV_CMD_DIRTY_DYNAMIC_ALL;
2610         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2611         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2612 }
2613
2614 VkResult radv_CreateCommandPool(
2615         VkDevice                                    _device,
2616         const VkCommandPoolCreateInfo*              pCreateInfo,
2617         const VkAllocationCallbacks*                pAllocator,
2618         VkCommandPool*                              pCmdPool)
2619 {
2620         RADV_FROM_HANDLE(radv_device, device, _device);
2621         struct radv_cmd_pool *pool;
2622
2623         pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2624                            VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2625         if (pool == NULL)
2626                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2627
2628         if (pAllocator)
2629                 pool->alloc = *pAllocator;
2630         else
2631                 pool->alloc = device->alloc;
2632
2633         list_inithead(&pool->cmd_buffers);
2634         list_inithead(&pool->free_cmd_buffers);
2635
2636         pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2637
2638         *pCmdPool = radv_cmd_pool_to_handle(pool);
2639
2640         return VK_SUCCESS;
2641
2642 }
2643
2644 void radv_DestroyCommandPool(
2645         VkDevice                                    _device,
2646         VkCommandPool                               commandPool,
2647         const VkAllocationCallbacks*                pAllocator)
2648 {
2649         RADV_FROM_HANDLE(radv_device, device, _device);
2650         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2651
2652         if (!pool)
2653                 return;
2654
2655         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2656                                  &pool->cmd_buffers, pool_link) {
2657                 radv_cmd_buffer_destroy(cmd_buffer);
2658         }
2659
2660         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2661                                  &pool->free_cmd_buffers, pool_link) {
2662                 radv_cmd_buffer_destroy(cmd_buffer);
2663         }
2664
2665         vk_free2(&device->alloc, pAllocator, pool);
2666 }
2667
2668 VkResult radv_ResetCommandPool(
2669         VkDevice                                    device,
2670         VkCommandPool                               commandPool,
2671         VkCommandPoolResetFlags                     flags)
2672 {
2673         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2674         VkResult result;
2675
2676         list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2677                             &pool->cmd_buffers, pool_link) {
2678                 result = radv_reset_cmd_buffer(cmd_buffer);
2679                 if (result != VK_SUCCESS)
2680                         return result;
2681         }
2682
2683         return VK_SUCCESS;
2684 }
2685
2686 void radv_TrimCommandPool(
2687     VkDevice                                    device,
2688     VkCommandPool                               commandPool,
2689     VkCommandPoolTrimFlagsKHR                   flags)
2690 {
2691         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2692
2693         if (!pool)
2694                 return;
2695
2696         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2697                                  &pool->free_cmd_buffers, pool_link) {
2698                 radv_cmd_buffer_destroy(cmd_buffer);
2699         }
2700 }
2701
2702 void radv_CmdBeginRenderPass(
2703         VkCommandBuffer                             commandBuffer,
2704         const VkRenderPassBeginInfo*                pRenderPassBegin,
2705         VkSubpassContents                           contents)
2706 {
2707         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2708         RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2709         RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2710
2711         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2712                                                            cmd_buffer->cs, 2048);
2713         MAYBE_UNUSED VkResult result;
2714
2715         cmd_buffer->state.framebuffer = framebuffer;
2716         cmd_buffer->state.pass = pass;
2717         cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2718
2719         result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2720         if (result != VK_SUCCESS)
2721                 return;
2722
2723         radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2724         assert(cmd_buffer->cs->cdw <= cdw_max);
2725
2726         radv_cmd_buffer_clear_subpass(cmd_buffer);
2727 }
2728
2729 void radv_CmdNextSubpass(
2730     VkCommandBuffer                             commandBuffer,
2731     VkSubpassContents                           contents)
2732 {
2733         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2734
2735         radv_cmd_buffer_resolve_subpass(cmd_buffer);
2736
2737         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2738                                               2048);
2739
2740         radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2741         radv_cmd_buffer_clear_subpass(cmd_buffer);
2742 }
2743
2744 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2745 {
2746         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2747         for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2748                 if (!pipeline->shaders[stage])
2749                         continue;
2750                 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2751                 if (loc->sgpr_idx == -1)
2752                         continue;
2753                 uint32_t base_reg = pipeline->user_data_0[stage];
2754                 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2755
2756         }
2757         if (pipeline->gs_copy_shader) {
2758                 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2759                 if (loc->sgpr_idx != -1) {
2760                         uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2761                         radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2762                 }
2763         }
2764 }
2765
2766 static void
2767 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2768                          uint32_t vertex_count)
2769 {
2770         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2771         radeon_emit(cmd_buffer->cs, vertex_count);
2772         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2773                                     S_0287F0_USE_OPAQUE(0));
2774 }
2775
2776 static void
2777 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2778                                  uint64_t index_va,
2779                                  uint32_t index_count)
2780 {
2781         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2782         radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2783         radeon_emit(cmd_buffer->cs, index_va);
2784         radeon_emit(cmd_buffer->cs, index_va >> 32);
2785         radeon_emit(cmd_buffer->cs, index_count);
2786         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2787 }
2788
2789 static void
2790 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2791                                   bool indexed,
2792                                   uint32_t draw_count,
2793                                   uint64_t count_va,
2794                                   uint32_t stride)
2795 {
2796         struct radeon_winsys_cs *cs = cmd_buffer->cs;
2797         unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2798                                       : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2799         bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
2800         uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2801         assert(base_reg);
2802
2803         /* just reset draw state for vertex data */
2804         cmd_buffer->state.last_first_instance = -1;
2805         cmd_buffer->state.last_num_instances = -1;
2806         cmd_buffer->state.last_vertex_offset = -1;
2807
2808         if (draw_count == 1 && !count_va && !draw_id_enable) {
2809                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2810                                      PKT3_DRAW_INDIRECT, 3, false));
2811                 radeon_emit(cs, 0);
2812                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2813                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2814                 radeon_emit(cs, di_src_sel);
2815         } else {
2816                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2817                                      PKT3_DRAW_INDIRECT_MULTI,
2818                                      8, false));
2819                 radeon_emit(cs, 0);
2820                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2821                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2822                 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2823                             S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2824                             S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2825                 radeon_emit(cs, draw_count); /* count */
2826                 radeon_emit(cs, count_va); /* count_addr */
2827                 radeon_emit(cs, count_va >> 32);
2828                 radeon_emit(cs, stride); /* stride */
2829                 radeon_emit(cs, di_src_sel);
2830         }
2831 }
2832
2833 struct radv_draw_info {
2834         /**
2835          * Number of vertices.
2836          */
2837         uint32_t count;
2838
2839         /**
2840          * Index of the first vertex.
2841          */
2842         int32_t vertex_offset;
2843
2844         /**
2845          * First instance id.
2846          */
2847         uint32_t first_instance;
2848
2849         /**
2850          * Number of instances.
2851          */
2852         uint32_t instance_count;
2853
2854         /**
2855          * First index (indexed draws only).
2856          */
2857         uint32_t first_index;
2858
2859         /**
2860          * Whether it's an indexed draw.
2861          */
2862         bool indexed;
2863
2864         /**
2865          * Indirect draw parameters resource.
2866          */
2867         struct radv_buffer *indirect;
2868         uint64_t indirect_offset;
2869         uint32_t stride;
2870
2871         /**
2872          * Draw count parameters resource.
2873          */
2874         struct radv_buffer *count_buffer;
2875         uint64_t count_buffer_offset;
2876 };
2877
2878 static void
2879 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
2880                        const struct radv_draw_info *info)
2881 {
2882         struct radv_cmd_state *state = &cmd_buffer->state;
2883         struct radeon_winsys *ws = cmd_buffer->device->ws;
2884         struct radeon_winsys_cs *cs = cmd_buffer->cs;
2885
2886         if (info->indirect) {
2887                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
2888                 uint64_t count_va = 0;
2889
2890                 va += info->indirect->offset + info->indirect_offset;
2891
2892                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
2893
2894                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2895                 radeon_emit(cs, 1);
2896                 radeon_emit(cs, va);
2897                 radeon_emit(cs, va >> 32);
2898
2899                 if (info->count_buffer) {
2900                         count_va = radv_buffer_get_va(info->count_buffer->bo);
2901                         count_va += info->count_buffer->offset +
2902                                     info->count_buffer_offset;
2903
2904                         radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
2905                 }
2906
2907                 if (!state->subpass->view_mask) {
2908                         radv_cs_emit_indirect_draw_packet(cmd_buffer,
2909                                                           info->indexed,
2910                                                           info->count,
2911                                                           count_va,
2912                                                           info->stride);
2913                 } else {
2914                         unsigned i;
2915                         for_each_bit(i, state->subpass->view_mask) {
2916                                 radv_emit_view_index(cmd_buffer, i);
2917
2918                                 radv_cs_emit_indirect_draw_packet(cmd_buffer,
2919                                                                   info->indexed,
2920                                                                   info->count,
2921                                                                   count_va,
2922                                                                   info->stride);
2923                         }
2924                 }
2925         } else {
2926                 assert(state->pipeline->graphics.vtx_base_sgpr);
2927
2928                 if (info->vertex_offset != state->last_vertex_offset ||
2929                     info->first_instance != state->last_first_instance) {
2930                         radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
2931                                               state->pipeline->graphics.vtx_emit_num);
2932
2933                         radeon_emit(cs, info->vertex_offset);
2934                         radeon_emit(cs, info->first_instance);
2935                         if (state->pipeline->graphics.vtx_emit_num == 3)
2936                                 radeon_emit(cs, 0);
2937                         state->last_first_instance = info->first_instance;
2938                         state->last_vertex_offset = info->vertex_offset;
2939                 }
2940
2941                 if (state->last_num_instances != info->instance_count) {
2942                         radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
2943                         radeon_emit(cs, info->instance_count);
2944                         state->last_num_instances = info->instance_count;
2945                 }
2946
2947                 if (info->indexed) {
2948                         int index_size = state->index_type ? 4 : 2;
2949                         uint64_t index_va;
2950
2951                         index_va = state->index_va;
2952                         index_va += info->first_index * index_size;
2953
2954                         if (!state->subpass->view_mask) {
2955                                 radv_cs_emit_draw_indexed_packet(cmd_buffer,
2956                                                                  index_va,
2957                                                                  info->count);
2958                         } else {
2959                                 unsigned i;
2960                                 for_each_bit(i, state->subpass->view_mask) {
2961                                         radv_emit_view_index(cmd_buffer, i);
2962
2963                                         radv_cs_emit_draw_indexed_packet(cmd_buffer,
2964                                                                          index_va,
2965                                                                          info->count);
2966                                 }
2967                         }
2968                 } else {
2969                         if (!state->subpass->view_mask) {
2970                                 radv_cs_emit_draw_packet(cmd_buffer, info->count);
2971                         } else {
2972                                 unsigned i;
2973                                 for_each_bit(i, state->subpass->view_mask) {
2974                                         radv_emit_view_index(cmd_buffer, i);
2975
2976                                         radv_cs_emit_draw_packet(cmd_buffer,
2977                                                                  info->count);
2978                                 }
2979                         }
2980                 }
2981         }
2982 }
2983
2984 static void
2985 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
2986                               const struct radv_draw_info *info)
2987 {
2988         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
2989                 radv_emit_graphics_pipeline(cmd_buffer);
2990
2991         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
2992                 radv_emit_framebuffer_state(cmd_buffer);
2993
2994         if (info->indexed) {
2995                 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
2996                         radv_emit_index_buffer(cmd_buffer);
2997         } else {
2998                 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
2999                  * so the state must be re-emitted before the next indexed
3000                  * draw.
3001                  */
3002                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3003                         cmd_buffer->state.last_index_type = -1;
3004                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3005                 }
3006         }
3007
3008         radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3009
3010         radv_emit_draw_registers(cmd_buffer, info->indexed,
3011                                  info->instance_count > 1, info->indirect,
3012                                  info->indirect ? 0 : info->count);
3013 }
3014
3015 static void
3016 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3017           const struct radv_draw_info *info)
3018 {
3019         bool pipeline_is_dirty =
3020                 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3021                 cmd_buffer->state.pipeline &&
3022                 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3023
3024         MAYBE_UNUSED unsigned cdw_max =
3025                 radeon_check_space(cmd_buffer->device->ws,
3026                                    cmd_buffer->cs, 4096);
3027
3028         /* Use optimal packet order based on whether we need to sync the
3029          * pipeline.
3030          */
3031         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3032                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3033                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3034                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3035                 /* If we have to wait for idle, set all states first, so that
3036                  * all SET packets are processed in parallel with previous draw
3037                  * calls. Then upload descriptors, set shader pointers, and
3038                  * draw, and prefetch at the end. This ensures that the time
3039                  * the CUs are idle is very short. (there are only SET_SH
3040                  * packets between the wait and the draw)
3041                  */
3042                 radv_emit_all_graphics_states(cmd_buffer, info);
3043                 si_emit_cache_flush(cmd_buffer);
3044                 /* <-- CUs are idle here --> */
3045
3046                 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3047                         return;
3048
3049                 radv_emit_draw_packets(cmd_buffer, info);
3050                 /* <-- CUs are busy here --> */
3051
3052                 /* Start prefetches after the draw has been started. Both will
3053                  * run in parallel, but starting the draw first is more
3054                  * important.
3055                  */
3056                 if (pipeline_is_dirty) {
3057                         radv_emit_prefetch(cmd_buffer,
3058                                            cmd_buffer->state.pipeline);
3059                 }
3060         } else {
3061                 /* If we don't wait for idle, start prefetches first, then set
3062                  * states, and draw at the end.
3063                  */
3064                 si_emit_cache_flush(cmd_buffer);
3065
3066                 if (pipeline_is_dirty) {
3067                         radv_emit_prefetch(cmd_buffer,
3068                                            cmd_buffer->state.pipeline);
3069                 }
3070
3071                 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3072                         return;
3073
3074                 radv_emit_all_graphics_states(cmd_buffer, info);
3075                 radv_emit_draw_packets(cmd_buffer, info);
3076         }
3077
3078         assert(cmd_buffer->cs->cdw <= cdw_max);
3079         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3080 }
3081
3082 void radv_CmdDraw(
3083         VkCommandBuffer                             commandBuffer,
3084         uint32_t                                    vertexCount,
3085         uint32_t                                    instanceCount,
3086         uint32_t                                    firstVertex,
3087         uint32_t                                    firstInstance)
3088 {
3089         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3090         struct radv_draw_info info = {};
3091
3092         info.count = vertexCount;
3093         info.instance_count = instanceCount;
3094         info.first_instance = firstInstance;
3095         info.vertex_offset = firstVertex;
3096
3097         radv_draw(cmd_buffer, &info);
3098 }
3099
3100 void radv_CmdDrawIndexed(
3101         VkCommandBuffer                             commandBuffer,
3102         uint32_t                                    indexCount,
3103         uint32_t                                    instanceCount,
3104         uint32_t                                    firstIndex,
3105         int32_t                                     vertexOffset,
3106         uint32_t                                    firstInstance)
3107 {
3108         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3109         struct radv_draw_info info = {};
3110
3111         info.indexed = true;
3112         info.count = indexCount;
3113         info.instance_count = instanceCount;
3114         info.first_index = firstIndex;
3115         info.vertex_offset = vertexOffset;
3116         info.first_instance = firstInstance;
3117
3118         radv_draw(cmd_buffer, &info);
3119 }
3120
3121 void radv_CmdDrawIndirect(
3122         VkCommandBuffer                             commandBuffer,
3123         VkBuffer                                    _buffer,
3124         VkDeviceSize                                offset,
3125         uint32_t                                    drawCount,
3126         uint32_t                                    stride)
3127 {
3128         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3129         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3130         struct radv_draw_info info = {};
3131
3132         info.count = drawCount;
3133         info.indirect = buffer;
3134         info.indirect_offset = offset;
3135         info.stride = stride;
3136
3137         radv_draw(cmd_buffer, &info);
3138 }
3139
3140 void radv_CmdDrawIndexedIndirect(
3141         VkCommandBuffer                             commandBuffer,
3142         VkBuffer                                    _buffer,
3143         VkDeviceSize                                offset,
3144         uint32_t                                    drawCount,
3145         uint32_t                                    stride)
3146 {
3147         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3148         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3149         struct radv_draw_info info = {};
3150
3151         info.indexed = true;
3152         info.count = drawCount;
3153         info.indirect = buffer;
3154         info.indirect_offset = offset;
3155         info.stride = stride;
3156
3157         radv_draw(cmd_buffer, &info);
3158 }
3159
3160 void radv_CmdDrawIndirectCountAMD(
3161         VkCommandBuffer                             commandBuffer,
3162         VkBuffer                                    _buffer,
3163         VkDeviceSize                                offset,
3164         VkBuffer                                    _countBuffer,
3165         VkDeviceSize                                countBufferOffset,
3166         uint32_t                                    maxDrawCount,
3167         uint32_t                                    stride)
3168 {
3169         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3170         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3171         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3172         struct radv_draw_info info = {};
3173
3174         info.count = maxDrawCount;
3175         info.indirect = buffer;
3176         info.indirect_offset = offset;
3177         info.count_buffer = count_buffer;
3178         info.count_buffer_offset = countBufferOffset;
3179         info.stride = stride;
3180
3181         radv_draw(cmd_buffer, &info);
3182 }
3183
3184 void radv_CmdDrawIndexedIndirectCountAMD(
3185         VkCommandBuffer                             commandBuffer,
3186         VkBuffer                                    _buffer,
3187         VkDeviceSize                                offset,
3188         VkBuffer                                    _countBuffer,
3189         VkDeviceSize                                countBufferOffset,
3190         uint32_t                                    maxDrawCount,
3191         uint32_t                                    stride)
3192 {
3193         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3194         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3195         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3196         struct radv_draw_info info = {};
3197
3198         info.indexed = true;
3199         info.count = maxDrawCount;
3200         info.indirect = buffer;
3201         info.indirect_offset = offset;
3202         info.count_buffer = count_buffer;
3203         info.count_buffer_offset = countBufferOffset;
3204         info.stride = stride;
3205
3206         radv_draw(cmd_buffer, &info);
3207 }
3208
3209 struct radv_dispatch_info {
3210         /**
3211          * Determine the layout of the grid (in block units) to be used.
3212          */
3213         uint32_t blocks[3];
3214
3215         /**
3216          * A starting offset for the grid. If unaligned is set, the offset
3217          * must still be aligned.
3218          */
3219         uint32_t offsets[3];
3220         /**
3221          * Whether it's an unaligned compute dispatch.
3222          */
3223         bool unaligned;
3224
3225         /**
3226          * Indirect compute parameters resource.
3227          */
3228         struct radv_buffer *indirect;
3229         uint64_t indirect_offset;
3230 };
3231
3232 static void
3233 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3234                            const struct radv_dispatch_info *info)
3235 {
3236         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3237         struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3238         unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3239         struct radeon_winsys *ws = cmd_buffer->device->ws;
3240         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3241         struct radv_userdata_info *loc;
3242
3243         loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3244                                     AC_UD_CS_GRID_SIZE);
3245
3246         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3247
3248         if (info->indirect) {
3249                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3250
3251                 va += info->indirect->offset + info->indirect_offset;
3252
3253                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3254
3255                 if (loc->sgpr_idx != -1) {
3256                         for (unsigned i = 0; i < 3; ++i) {
3257                                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3258                                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3259                                                 COPY_DATA_DST_SEL(COPY_DATA_REG));
3260                                 radeon_emit(cs, (va +  4 * i));
3261                                 radeon_emit(cs, (va + 4 * i) >> 32);
3262                                 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3263                                                  + loc->sgpr_idx * 4) >> 2) + i);
3264                                 radeon_emit(cs, 0);
3265                         }
3266                 }
3267
3268                 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3269                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3270                                         PKT3_SHADER_TYPE_S(1));
3271                         radeon_emit(cs, va);
3272                         radeon_emit(cs, va >> 32);
3273                         radeon_emit(cs, dispatch_initiator);
3274                 } else {
3275                         radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3276                                         PKT3_SHADER_TYPE_S(1));
3277                         radeon_emit(cs, 1);
3278                         radeon_emit(cs, va);
3279                         radeon_emit(cs, va >> 32);
3280
3281                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3282                                         PKT3_SHADER_TYPE_S(1));
3283                         radeon_emit(cs, 0);
3284                         radeon_emit(cs, dispatch_initiator);
3285                 }
3286         } else {
3287                 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3288                 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3289
3290                 if (info->unaligned) {
3291                         unsigned *cs_block_size = compute_shader->info.cs.block_size;
3292                         unsigned remainder[3];
3293
3294                         /* If aligned, these should be an entire block size,
3295                          * not 0.
3296                          */
3297                         remainder[0] = blocks[0] + cs_block_size[0] -
3298                                        align_u32_npot(blocks[0], cs_block_size[0]);
3299                         remainder[1] = blocks[1] + cs_block_size[1] -
3300                                        align_u32_npot(blocks[1], cs_block_size[1]);
3301                         remainder[2] = blocks[2] + cs_block_size[2] -
3302                                        align_u32_npot(blocks[2], cs_block_size[2]);
3303
3304                         blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3305                         blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3306                         blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3307
3308                         for(unsigned i = 0; i < 3; ++i) {
3309                                 assert(offsets[i] % cs_block_size[i] == 0);
3310                                 offsets[i] /= cs_block_size[i];
3311                         }
3312
3313                         radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3314                         radeon_emit(cs,
3315                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3316                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3317                         radeon_emit(cs,
3318                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3319                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3320                         radeon_emit(cs,
3321                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3322                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3323
3324                         dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3325                 }
3326
3327                 if (loc->sgpr_idx != -1) {
3328                         assert(!loc->indirect);
3329                         assert(loc->num_sgprs == 3);
3330
3331                         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3332                                                   loc->sgpr_idx * 4, 3);
3333                         radeon_emit(cs, blocks[0]);
3334                         radeon_emit(cs, blocks[1]);
3335                         radeon_emit(cs, blocks[2]);
3336                 }
3337
3338                 if (offsets[0] || offsets[1] || offsets[2]) {
3339                         radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3340                         radeon_emit(cs, offsets[0]);
3341                         radeon_emit(cs, offsets[1]);
3342                         radeon_emit(cs, offsets[2]);
3343
3344                         /* The blocks in the packet are not counts but end values. */
3345                         for (unsigned i = 0; i < 3; ++i)
3346                                 blocks[i] += offsets[i];
3347                 } else {
3348                         dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3349                 }
3350
3351                 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3352                                 PKT3_SHADER_TYPE_S(1));
3353                 radeon_emit(cs, blocks[0]);
3354                 radeon_emit(cs, blocks[1]);
3355                 radeon_emit(cs, blocks[2]);
3356                 radeon_emit(cs, dispatch_initiator);
3357         }
3358
3359         assert(cmd_buffer->cs->cdw <= cdw_max);
3360 }
3361
3362 static void
3363 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3364 {
3365         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3366         radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3367                              VK_SHADER_STAGE_COMPUTE_BIT);
3368 }
3369
3370 static void
3371 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3372               const struct radv_dispatch_info *info)
3373 {
3374         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3375         bool pipeline_is_dirty = pipeline &&
3376                                  pipeline != cmd_buffer->state.emitted_compute_pipeline;
3377
3378         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3379                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3380                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3381                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3382                 /* If we have to wait for idle, set all states first, so that
3383                  * all SET packets are processed in parallel with previous draw
3384                  * calls. Then upload descriptors, set shader pointers, and
3385                  * dispatch, and prefetch at the end. This ensures that the
3386                  * time the CUs are idle is very short. (there are only SET_SH
3387                  * packets between the wait and the draw)
3388                  */
3389                 radv_emit_compute_pipeline(cmd_buffer);
3390                 si_emit_cache_flush(cmd_buffer);
3391                 /* <-- CUs are idle here --> */
3392
3393                 radv_upload_compute_shader_descriptors(cmd_buffer);
3394
3395                 radv_emit_dispatch_packets(cmd_buffer, info);
3396                 /* <-- CUs are busy here --> */
3397
3398                 /* Start prefetches after the dispatch has been started. Both
3399                  * will run in parallel, but starting the dispatch first is
3400                  * more important.
3401                  */
3402                 if (pipeline_is_dirty) {
3403                         radv_emit_shader_prefetch(cmd_buffer,
3404                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3405                 }
3406         } else {
3407                 /* If we don't wait for idle, start prefetches first, then set
3408                  * states, and dispatch at the end.
3409                  */
3410                 si_emit_cache_flush(cmd_buffer);
3411
3412                 if (pipeline_is_dirty) {
3413                         radv_emit_shader_prefetch(cmd_buffer,
3414                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3415                 }
3416
3417                 radv_upload_compute_shader_descriptors(cmd_buffer);
3418
3419                 radv_emit_compute_pipeline(cmd_buffer);
3420                 radv_emit_dispatch_packets(cmd_buffer, info);
3421         }
3422
3423         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3424 }
3425
3426 void radv_CmdDispatchBase(
3427         VkCommandBuffer                             commandBuffer,
3428         uint32_t                                    base_x,
3429         uint32_t                                    base_y,
3430         uint32_t                                    base_z,
3431         uint32_t                                    x,
3432         uint32_t                                    y,
3433         uint32_t                                    z)
3434 {
3435         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3436         struct radv_dispatch_info info = {};
3437
3438         info.blocks[0] = x;
3439         info.blocks[1] = y;
3440         info.blocks[2] = z;
3441
3442         info.offsets[0] = base_x;
3443         info.offsets[1] = base_y;
3444         info.offsets[2] = base_z;
3445         radv_dispatch(cmd_buffer, &info);
3446 }
3447
3448 void radv_CmdDispatch(
3449         VkCommandBuffer                             commandBuffer,
3450         uint32_t                                    x,
3451         uint32_t                                    y,
3452         uint32_t                                    z)
3453 {
3454         radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3455 }
3456
3457 void radv_CmdDispatchIndirect(
3458         VkCommandBuffer                             commandBuffer,
3459         VkBuffer                                    _buffer,
3460         VkDeviceSize                                offset)
3461 {
3462         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3463         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3464         struct radv_dispatch_info info = {};
3465
3466         info.indirect = buffer;
3467         info.indirect_offset = offset;
3468
3469         radv_dispatch(cmd_buffer, &info);
3470 }
3471
3472 void radv_unaligned_dispatch(
3473         struct radv_cmd_buffer                      *cmd_buffer,
3474         uint32_t                                    x,
3475         uint32_t                                    y,
3476         uint32_t                                    z)
3477 {
3478         struct radv_dispatch_info info = {};
3479
3480         info.blocks[0] = x;
3481         info.blocks[1] = y;
3482         info.blocks[2] = z;
3483         info.unaligned = 1;
3484
3485         radv_dispatch(cmd_buffer, &info);
3486 }
3487
3488 void radv_CmdEndRenderPass(
3489         VkCommandBuffer                             commandBuffer)
3490 {
3491         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3492
3493         radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3494
3495         radv_cmd_buffer_resolve_subpass(cmd_buffer);
3496
3497         for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3498                 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3499                 radv_handle_subpass_image_transition(cmd_buffer,
3500                                       (VkAttachmentReference){i, layout});
3501         }
3502
3503         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3504
3505         cmd_buffer->state.pass = NULL;
3506         cmd_buffer->state.subpass = NULL;
3507         cmd_buffer->state.attachments = NULL;
3508         cmd_buffer->state.framebuffer = NULL;
3509 }
3510
3511 /*
3512  * For HTILE we have the following interesting clear words:
3513  *   0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3514  *   0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3515  *   0xfffffff0: Clear depth to 1.0
3516  *   0x00000000: Clear depth to 0.0
3517  */
3518 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3519                                   struct radv_image *image,
3520                                   const VkImageSubresourceRange *range,
3521                                   uint32_t clear_word)
3522 {
3523         assert(range->baseMipLevel == 0);
3524         assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3525         unsigned layer_count = radv_get_layerCount(image, range);
3526         uint64_t size = image->surface.htile_slice_size * layer_count;
3527         uint64_t offset = image->offset + image->htile_offset +
3528                           image->surface.htile_slice_size * range->baseArrayLayer;
3529         struct radv_cmd_state *state = &cmd_buffer->state;
3530
3531         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3532                              RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3533
3534         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3535                                               size, clear_word);
3536
3537         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3538 }
3539
3540 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3541                                                struct radv_image *image,
3542                                                VkImageLayout src_layout,
3543                                                VkImageLayout dst_layout,
3544                                                unsigned src_queue_mask,
3545                                                unsigned dst_queue_mask,
3546                                                const VkImageSubresourceRange *range,
3547                                                VkImageAspectFlags pending_clears)
3548 {
3549         if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3550             (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3551             cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3552             cmd_buffer->state.render_area.extent.width == image->info.width &&
3553             cmd_buffer->state.render_area.extent.height == image->info.height) {
3554                 /* The clear will initialize htile. */
3555                 return;
3556         } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3557                    radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3558                 /* TODO: merge with the clear if applicable */
3559                 radv_initialize_htile(cmd_buffer, image, range, 0);
3560         } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3561                    radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3562                 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3563                 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3564         } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3565                    !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3566                 VkImageSubresourceRange local_range = *range;
3567                 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3568                 local_range.baseMipLevel = 0;
3569                 local_range.levelCount = 1;
3570
3571                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3572                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3573
3574                 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3575
3576                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3577                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3578         }
3579 }
3580
3581 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3582                            struct radv_image *image, uint32_t value)
3583 {
3584         struct radv_cmd_state *state = &cmd_buffer->state;
3585
3586         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3587                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3588
3589         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3590                                               image->offset + image->cmask.offset,
3591                                               image->cmask.size, value);
3592
3593         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3594 }
3595
3596 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3597                                                struct radv_image *image,
3598                                                VkImageLayout src_layout,
3599                                                VkImageLayout dst_layout,
3600                                                unsigned src_queue_mask,
3601                                                unsigned dst_queue_mask,
3602                                                const VkImageSubresourceRange *range)
3603 {
3604         if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3605                 if (image->fmask.size)
3606                         radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3607                 else
3608                         radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3609         } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3610                    !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3611                 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3612         }
3613 }
3614
3615 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3616                          struct radv_image *image, uint32_t value)
3617 {
3618         struct radv_cmd_state *state = &cmd_buffer->state;
3619
3620         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3621                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3622
3623         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3624                                               image->offset + image->dcc_offset,
3625                                               image->surface.dcc_size, value);
3626
3627         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3628                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3629 }
3630
3631 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3632                                              struct radv_image *image,
3633                                              VkImageLayout src_layout,
3634                                              VkImageLayout dst_layout,
3635                                              unsigned src_queue_mask,
3636                                              unsigned dst_queue_mask,
3637                                              const VkImageSubresourceRange *range)
3638 {
3639         if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
3640                 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
3641         } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3642                 radv_initialize_dcc(cmd_buffer, image,
3643                                     radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask) ?
3644                                          0x20202020u : 0xffffffffu);
3645         } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
3646                    !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
3647                 radv_decompress_dcc(cmd_buffer, image, range);
3648         } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3649                    !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3650                 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3651         }
3652 }
3653
3654 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3655                                          struct radv_image *image,
3656                                          VkImageLayout src_layout,
3657                                          VkImageLayout dst_layout,
3658                                          uint32_t src_family,
3659                                          uint32_t dst_family,
3660                                          const VkImageSubresourceRange *range,
3661                                          VkImageAspectFlags pending_clears)
3662 {
3663         if (image->exclusive && src_family != dst_family) {
3664                 /* This is an acquire or a release operation and there will be
3665                  * a corresponding release/acquire. Do the transition in the
3666                  * most flexible queue. */
3667
3668                 assert(src_family == cmd_buffer->queue_family_index ||
3669                        dst_family == cmd_buffer->queue_family_index);
3670
3671                 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3672                         return;
3673
3674                 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3675                     (src_family == RADV_QUEUE_GENERAL ||
3676                      dst_family == RADV_QUEUE_GENERAL))
3677                         return;
3678         }
3679
3680         unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3681         unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3682
3683         if (image->surface.htile_size)
3684                 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3685                                                    dst_layout, src_queue_mask,
3686                                                    dst_queue_mask, range,
3687                                                    pending_clears);
3688
3689         if (image->cmask.size || image->fmask.size)
3690                 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3691                                                    dst_layout, src_queue_mask,
3692                                                    dst_queue_mask, range);
3693
3694         if (image->surface.dcc_size)
3695                 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3696                                                  dst_layout, src_queue_mask,
3697                                                  dst_queue_mask, range);
3698 }
3699
3700 void radv_CmdPipelineBarrier(
3701         VkCommandBuffer                             commandBuffer,
3702         VkPipelineStageFlags                        srcStageMask,
3703         VkPipelineStageFlags                        destStageMask,
3704         VkBool32                                    byRegion,
3705         uint32_t                                    memoryBarrierCount,
3706         const VkMemoryBarrier*                      pMemoryBarriers,
3707         uint32_t                                    bufferMemoryBarrierCount,
3708         const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
3709         uint32_t                                    imageMemoryBarrierCount,
3710         const VkImageMemoryBarrier*                 pImageMemoryBarriers)
3711 {
3712         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3713         enum radv_cmd_flush_bits src_flush_bits = 0;
3714         enum radv_cmd_flush_bits dst_flush_bits = 0;
3715
3716         for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3717                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3718                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3719                                                         NULL);
3720         }
3721
3722         for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3723                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3724                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3725                                                         NULL);
3726         }
3727
3728         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3729                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3730                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3731                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3732                                                         image);
3733         }
3734
3735         radv_stage_flush(cmd_buffer, srcStageMask);
3736         cmd_buffer->state.flush_bits |= src_flush_bits;
3737
3738         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3739                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3740                 radv_handle_image_transition(cmd_buffer, image,
3741                                              pImageMemoryBarriers[i].oldLayout,
3742                                              pImageMemoryBarriers[i].newLayout,
3743                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
3744                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
3745                                              &pImageMemoryBarriers[i].subresourceRange,
3746                                              0);
3747         }
3748
3749         cmd_buffer->state.flush_bits |= dst_flush_bits;
3750 }
3751
3752
3753 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3754                         struct radv_event *event,
3755                         VkPipelineStageFlags stageMask,
3756                         unsigned value)
3757 {
3758         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3759         uint64_t va = radv_buffer_get_va(event->bo);
3760
3761         radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3762
3763         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3764
3765         /* TODO: this is overkill. Probably should figure something out from
3766          * the stage mask. */
3767
3768         si_cs_emit_write_event_eop(cs,
3769                                    cmd_buffer->state.predicating,
3770                                    cmd_buffer->device->physical_device->rad_info.chip_class,
3771                                    radv_cmd_buffer_uses_mec(cmd_buffer),
3772                                    V_028A90_BOTTOM_OF_PIPE_TS, 0,
3773                                    1, va, 2, value);
3774
3775         assert(cmd_buffer->cs->cdw <= cdw_max);
3776 }
3777
3778 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3779                       VkEvent _event,
3780                       VkPipelineStageFlags stageMask)
3781 {
3782         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3783         RADV_FROM_HANDLE(radv_event, event, _event);
3784
3785         write_event(cmd_buffer, event, stageMask, 1);
3786 }
3787
3788 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3789                         VkEvent _event,
3790                         VkPipelineStageFlags stageMask)
3791 {
3792         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3793         RADV_FROM_HANDLE(radv_event, event, _event);
3794
3795         write_event(cmd_buffer, event, stageMask, 0);
3796 }
3797
3798 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3799                         uint32_t eventCount,
3800                         const VkEvent* pEvents,
3801                         VkPipelineStageFlags srcStageMask,
3802                         VkPipelineStageFlags dstStageMask,
3803                         uint32_t memoryBarrierCount,
3804                         const VkMemoryBarrier* pMemoryBarriers,
3805                         uint32_t bufferMemoryBarrierCount,
3806                         const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3807                         uint32_t imageMemoryBarrierCount,
3808                         const VkImageMemoryBarrier* pImageMemoryBarriers)
3809 {
3810         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3811         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3812
3813         for (unsigned i = 0; i < eventCount; ++i) {
3814                 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3815                 uint64_t va = radv_buffer_get_va(event->bo);
3816
3817                 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3818
3819                 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3820
3821                 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3822                 assert(cmd_buffer->cs->cdw <= cdw_max);
3823         }
3824
3825
3826         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3827                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3828
3829                 radv_handle_image_transition(cmd_buffer, image,
3830                                              pImageMemoryBarriers[i].oldLayout,
3831                                              pImageMemoryBarriers[i].newLayout,
3832                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
3833                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
3834                                              &pImageMemoryBarriers[i].subresourceRange,
3835                                              0);
3836         }
3837
3838         /* TODO: figure out how to do memory barriers without waiting */
3839         cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3840                                         RADV_CMD_FLAG_INV_GLOBAL_L2 |
3841                                         RADV_CMD_FLAG_INV_VMEM_L1 |
3842                                         RADV_CMD_FLAG_INV_SMEM_L1;
3843 }
3844
3845
3846 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
3847                            uint32_t deviceMask)
3848 {
3849    /* No-op */
3850 }