2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_radeon_winsys.h"
30 #include "radv_shader.h"
34 #include "vk_format.h"
35 #include "radv_debug.h"
36 #include "radv_meta.h"
40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
41 struct radv_image *image,
42 VkImageLayout src_layout,
43 VkImageLayout dst_layout,
46 const VkImageSubresourceRange *range,
47 VkImageAspectFlags pending_clears);
49 const struct radv_dynamic_state default_dynamic_state = {
62 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
67 .stencil_compare_mask = {
71 .stencil_write_mask = {
75 .stencil_reference = {
82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
83 const struct radv_dynamic_state *src)
85 struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
86 uint32_t copy_mask = src->mask;
87 uint32_t dest_mask = 0;
89 /* Make sure to copy the number of viewports/scissors because they can
90 * only be specified at pipeline creation time.
92 dest->viewport.count = src->viewport.count;
93 dest->scissor.count = src->scissor.count;
94 dest->discard_rectangle.count = src->discard_rectangle.count;
96 if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
97 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
98 src->viewport.count * sizeof(VkViewport))) {
99 typed_memcpy(dest->viewport.viewports,
100 src->viewport.viewports,
101 src->viewport.count);
102 dest_mask |= RADV_DYNAMIC_VIEWPORT;
106 if (copy_mask & RADV_DYNAMIC_SCISSOR) {
107 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
108 src->scissor.count * sizeof(VkRect2D))) {
109 typed_memcpy(dest->scissor.scissors,
110 src->scissor.scissors, src->scissor.count);
111 dest_mask |= RADV_DYNAMIC_SCISSOR;
115 if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
116 if (dest->line_width != src->line_width) {
117 dest->line_width = src->line_width;
118 dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
122 if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
123 if (memcmp(&dest->depth_bias, &src->depth_bias,
124 sizeof(src->depth_bias))) {
125 dest->depth_bias = src->depth_bias;
126 dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
130 if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
131 if (memcmp(&dest->blend_constants, &src->blend_constants,
132 sizeof(src->blend_constants))) {
133 typed_memcpy(dest->blend_constants,
134 src->blend_constants, 4);
135 dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
139 if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
140 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
141 sizeof(src->depth_bounds))) {
142 dest->depth_bounds = src->depth_bounds;
143 dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
147 if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
148 if (memcmp(&dest->stencil_compare_mask,
149 &src->stencil_compare_mask,
150 sizeof(src->stencil_compare_mask))) {
151 dest->stencil_compare_mask = src->stencil_compare_mask;
152 dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
156 if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
157 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
158 sizeof(src->stencil_write_mask))) {
159 dest->stencil_write_mask = src->stencil_write_mask;
160 dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
164 if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
165 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
166 sizeof(src->stencil_reference))) {
167 dest->stencil_reference = src->stencil_reference;
168 dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
172 if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
173 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
174 src->discard_rectangle.count * sizeof(VkRect2D))) {
175 typed_memcpy(dest->discard_rectangle.rectangles,
176 src->discard_rectangle.rectangles,
177 src->discard_rectangle.count);
178 dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
182 cmd_buffer->state.dirty |= dest_mask;
185 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
187 return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
188 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
191 enum ring_type radv_queue_family_to_ring(int f) {
193 case RADV_QUEUE_GENERAL:
195 case RADV_QUEUE_COMPUTE:
197 case RADV_QUEUE_TRANSFER:
200 unreachable("Unknown queue family");
204 static VkResult radv_create_cmd_buffer(
205 struct radv_device * device,
206 struct radv_cmd_pool * pool,
207 VkCommandBufferLevel level,
208 VkCommandBuffer* pCommandBuffer)
210 struct radv_cmd_buffer *cmd_buffer;
212 cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
213 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
214 if (cmd_buffer == NULL)
215 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
217 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
218 cmd_buffer->device = device;
219 cmd_buffer->pool = pool;
220 cmd_buffer->level = level;
223 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
224 cmd_buffer->queue_family_index = pool->queue_family_index;
227 /* Init the pool_link so we can safefly call list_del when we destroy
230 list_inithead(&cmd_buffer->pool_link);
231 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
234 ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
236 cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
237 if (!cmd_buffer->cs) {
238 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
239 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
242 *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
244 list_inithead(&cmd_buffer->upload.list);
250 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
252 list_del(&cmd_buffer->pool_link);
254 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
255 &cmd_buffer->upload.list, list) {
256 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
261 if (cmd_buffer->upload.upload_bo)
262 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
263 cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
264 free(cmd_buffer->push_descriptors.set.mapped_ptr);
265 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
269 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
272 cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
274 list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
275 &cmd_buffer->upload.list, list) {
276 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
281 cmd_buffer->push_constant_stages = 0;
282 cmd_buffer->scratch_size_needed = 0;
283 cmd_buffer->compute_scratch_size_needed = 0;
284 cmd_buffer->esgs_ring_size_needed = 0;
285 cmd_buffer->gsvs_ring_size_needed = 0;
286 cmd_buffer->tess_rings_needed = false;
287 cmd_buffer->sample_positions_needed = false;
289 if (cmd_buffer->upload.upload_bo)
290 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
291 cmd_buffer->upload.upload_bo, 8);
292 cmd_buffer->upload.offset = 0;
294 cmd_buffer->record_result = VK_SUCCESS;
296 cmd_buffer->ring_offsets_idx = -1;
298 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
300 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
301 &cmd_buffer->gfx9_fence_offset,
303 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
306 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
308 return cmd_buffer->record_result;
312 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
316 struct radeon_winsys_bo *bo;
317 struct radv_cmd_buffer_upload *upload;
318 struct radv_device *device = cmd_buffer->device;
320 new_size = MAX2(min_needed, 16 * 1024);
321 new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
323 bo = device->ws->buffer_create(device->ws,
326 RADEON_FLAG_CPU_ACCESS|
327 RADEON_FLAG_NO_INTERPROCESS_SHARING);
330 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
334 radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
335 if (cmd_buffer->upload.upload_bo) {
336 upload = malloc(sizeof(*upload));
339 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
340 device->ws->buffer_destroy(bo);
344 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
345 list_add(&upload->list, &cmd_buffer->upload.list);
348 cmd_buffer->upload.upload_bo = bo;
349 cmd_buffer->upload.size = new_size;
350 cmd_buffer->upload.offset = 0;
351 cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
353 if (!cmd_buffer->upload.map) {
354 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
362 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
365 unsigned *out_offset,
368 uint64_t offset = align(cmd_buffer->upload.offset, alignment);
369 if (offset + size > cmd_buffer->upload.size) {
370 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
375 *out_offset = offset;
376 *ptr = cmd_buffer->upload.map + offset;
378 cmd_buffer->upload.offset = offset + size;
383 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
384 unsigned size, unsigned alignment,
385 const void *data, unsigned *out_offset)
389 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
390 out_offset, (void **)&ptr))
394 memcpy(ptr, data, size);
400 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
401 unsigned count, const uint32_t *data)
403 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
404 radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
405 S_370_WR_CONFIRM(1) |
406 S_370_ENGINE_SEL(V_370_ME));
408 radeon_emit(cs, va >> 32);
409 radeon_emit_array(cs, data, count);
412 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
414 struct radv_device *device = cmd_buffer->device;
415 struct radeon_winsys_cs *cs = cmd_buffer->cs;
418 va = radv_buffer_get_va(device->trace_bo);
419 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
422 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
424 ++cmd_buffer->state.trace_id;
425 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
426 radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
427 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
428 radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
432 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
433 enum radv_cmd_flush_bits flags)
435 if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
436 uint32_t *ptr = NULL;
439 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
440 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
442 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
443 va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
444 cmd_buffer->gfx9_fence_offset;
445 ptr = &cmd_buffer->gfx9_fence_idx;
448 /* Force wait for graphics or compute engines to be idle. */
449 si_cs_emit_cache_flush(cmd_buffer->cs, false,
450 cmd_buffer->device->physical_device->rad_info.chip_class,
452 radv_cmd_buffer_uses_mec(cmd_buffer),
456 if (unlikely(cmd_buffer->device->trace_bo))
457 radv_cmd_buffer_trace_emit(cmd_buffer);
461 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
462 struct radv_pipeline *pipeline, enum ring_type ring)
464 struct radv_device *device = cmd_buffer->device;
465 struct radeon_winsys_cs *cs = cmd_buffer->cs;
469 va = radv_buffer_get_va(device->trace_bo);
479 assert(!"invalid ring type");
482 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
485 data[0] = (uintptr_t)pipeline;
486 data[1] = (uintptr_t)pipeline >> 32;
488 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
489 radv_emit_write_data_packet(cs, va, 2, data);
492 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
493 struct radv_descriptor_set *set,
496 cmd_buffer->descriptors[idx] = set;
498 cmd_buffer->state.valid_descriptors |= (1u << idx);
500 cmd_buffer->state.valid_descriptors &= ~(1u << idx);
501 cmd_buffer->state.descriptors_dirty |= (1u << idx);
506 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
508 struct radv_device *device = cmd_buffer->device;
509 struct radeon_winsys_cs *cs = cmd_buffer->cs;
510 uint32_t data[MAX_SETS * 2] = {};
513 va = radv_buffer_get_va(device->trace_bo) + 24;
515 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
516 cmd_buffer->cs, 4 + MAX_SETS * 2);
518 for_each_bit(i, cmd_buffer->state.valid_descriptors) {
519 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
520 data[i * 2] = (uintptr_t)set;
521 data[i * 2 + 1] = (uintptr_t)set >> 32;
524 radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
525 radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
528 struct ac_userdata_info *
529 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
530 gl_shader_stage stage,
533 if (stage == MESA_SHADER_VERTEX) {
534 if (pipeline->shaders[MESA_SHADER_VERTEX])
535 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
536 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
537 return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
538 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
539 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
540 } else if (stage == MESA_SHADER_TESS_EVAL) {
541 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
542 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
543 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
544 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
546 return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
550 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
551 struct radv_pipeline *pipeline,
552 gl_shader_stage stage,
553 int idx, uint64_t va)
555 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
556 uint32_t base_reg = pipeline->user_data_0[stage];
557 if (loc->sgpr_idx == -1)
559 assert(loc->num_sgprs == 2);
560 assert(!loc->indirect);
561 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
562 radeon_emit(cmd_buffer->cs, va);
563 radeon_emit(cmd_buffer->cs, va >> 32);
567 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
568 struct radv_pipeline *pipeline)
570 int num_samples = pipeline->graphics.ms.num_samples;
571 struct radv_multisample_state *ms = &pipeline->graphics.ms;
572 struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
574 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
575 cmd_buffer->sample_positions_needed = true;
577 if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
580 radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
581 radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
582 radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
584 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
586 radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
588 /* GFX9: Flush DFSM when the AA mode changes. */
589 if (cmd_buffer->device->dfsm_allowed) {
590 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
591 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
598 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
601 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
602 si_cp_dma_prefetch(cmd_buffer, va, size);
606 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
608 if (cmd_buffer->state.vb_prefetch_dirty) {
609 radv_emit_prefetch_TC_L2_async(cmd_buffer,
610 cmd_buffer->state.vb_va,
611 cmd_buffer->state.vb_size);
612 cmd_buffer->state.vb_prefetch_dirty = false;
617 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
618 struct radv_shader_variant *shader)
620 struct radeon_winsys *ws = cmd_buffer->device->ws;
621 struct radeon_winsys_cs *cs = cmd_buffer->cs;
627 va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
629 radv_cs_add_buffer(ws, cs, shader->bo, 8);
630 radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
634 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
635 struct radv_pipeline *pipeline)
637 radv_emit_shader_prefetch(cmd_buffer,
638 pipeline->shaders[MESA_SHADER_VERTEX]);
639 radv_emit_VBO_descriptors_prefetch(cmd_buffer);
640 radv_emit_shader_prefetch(cmd_buffer,
641 pipeline->shaders[MESA_SHADER_TESS_CTRL]);
642 radv_emit_shader_prefetch(cmd_buffer,
643 pipeline->shaders[MESA_SHADER_TESS_EVAL]);
644 radv_emit_shader_prefetch(cmd_buffer,
645 pipeline->shaders[MESA_SHADER_GEOMETRY]);
646 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
647 radv_emit_shader_prefetch(cmd_buffer,
648 pipeline->shaders[MESA_SHADER_FRAGMENT]);
652 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
654 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
656 if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
659 radv_update_multisample_state(cmd_buffer, pipeline);
661 cmd_buffer->scratch_size_needed =
662 MAX2(cmd_buffer->scratch_size_needed,
663 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
665 if (!cmd_buffer->state.emitted_pipeline ||
666 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
667 pipeline->graphics.can_use_guardband)
668 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
670 radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
672 if (unlikely(cmd_buffer->device->trace_bo))
673 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
675 cmd_buffer->state.emitted_pipeline = pipeline;
677 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
681 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
683 si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
684 cmd_buffer->state.dynamic.viewport.viewports);
688 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
690 uint32_t count = cmd_buffer->state.dynamic.scissor.count;
692 /* Vega10/Raven scissor bug workaround. This must be done before VPORT
693 * scissor registers are changed. There is also a more efficient but
694 * more involved alternative workaround.
696 if (cmd_buffer->device->physical_device->has_scissor_bug) {
697 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
698 si_emit_cache_flush(cmd_buffer);
700 si_write_scissors(cmd_buffer->cs, 0, count,
701 cmd_buffer->state.dynamic.scissor.scissors,
702 cmd_buffer->state.dynamic.viewport.viewports,
703 cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
707 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
709 if (!cmd_buffer->state.dynamic.discard_rectangle.count)
712 radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
713 cmd_buffer->state.dynamic.discard_rectangle.count * 2);
714 for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
715 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
716 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
717 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
718 S_028214_BR_Y(rect.offset.y + rect.extent.height));
723 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
725 unsigned width = cmd_buffer->state.dynamic.line_width * 8;
727 radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
728 S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
732 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
734 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
736 radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
737 radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
741 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
743 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
745 radeon_set_context_reg_seq(cmd_buffer->cs,
746 R_028430_DB_STENCILREFMASK, 2);
747 radeon_emit(cmd_buffer->cs,
748 S_028430_STENCILTESTVAL(d->stencil_reference.front) |
749 S_028430_STENCILMASK(d->stencil_compare_mask.front) |
750 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
751 S_028430_STENCILOPVAL(1));
752 radeon_emit(cmd_buffer->cs,
753 S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
754 S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
755 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
756 S_028434_STENCILOPVAL_BF(1));
760 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
762 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
764 radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
765 fui(d->depth_bounds.min));
766 radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
767 fui(d->depth_bounds.max));
771 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
773 struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
774 unsigned slope = fui(d->depth_bias.slope * 16.0f);
775 unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
778 radeon_set_context_reg_seq(cmd_buffer->cs,
779 R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
780 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
781 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
782 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
783 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
784 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
788 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
790 struct radv_attachment_info *att,
791 struct radv_image *image,
792 VkImageLayout layout)
794 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
795 struct radv_color_buffer_info *cb = &att->cb;
796 uint32_t cb_color_info = cb->cb_color_info;
798 if (!radv_layout_dcc_compressed(image, layout,
799 radv_image_queue_family_mask(image,
800 cmd_buffer->queue_family_index,
801 cmd_buffer->queue_family_index))) {
802 cb_color_info &= C_028C70_DCC_ENABLE;
805 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
806 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
807 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
808 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
809 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
810 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
811 radeon_emit(cmd_buffer->cs, cb_color_info);
812 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
813 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
814 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
815 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
816 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
817 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
819 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
820 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
821 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
823 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
824 S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
826 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
827 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
828 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
829 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
830 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
831 radeon_emit(cmd_buffer->cs, cb_color_info);
832 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
833 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
834 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
835 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
836 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
837 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
839 if (is_vi) { /* DCC BASE */
840 radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
846 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
847 struct radv_ds_buffer_info *ds,
848 struct radv_image *image,
849 VkImageLayout layout)
851 uint32_t db_z_info = ds->db_z_info;
852 uint32_t db_stencil_info = ds->db_stencil_info;
854 if (!radv_layout_has_htile(image, layout,
855 radv_image_queue_family_mask(image,
856 cmd_buffer->queue_family_index,
857 cmd_buffer->queue_family_index))) {
858 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
859 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
862 radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
863 radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
866 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
867 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
868 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
869 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
870 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
872 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
873 radeon_emit(cmd_buffer->cs, db_z_info); /* DB_Z_INFO */
874 radeon_emit(cmd_buffer->cs, db_stencil_info); /* DB_STENCIL_INFO */
875 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */
876 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32); /* DB_Z_READ_BASE_HI */
877 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* DB_STENCIL_READ_BASE */
878 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
879 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* DB_Z_WRITE_BASE */
880 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
881 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
882 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
884 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
885 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
886 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
888 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
890 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
891 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
892 radeon_emit(cmd_buffer->cs, db_z_info); /* R_028040_DB_Z_INFO */
893 radeon_emit(cmd_buffer->cs, db_stencil_info); /* R_028044_DB_STENCIL_INFO */
894 radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* R_028048_DB_Z_READ_BASE */
895 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base); /* R_02804C_DB_STENCIL_READ_BASE */
896 radeon_emit(cmd_buffer->cs, ds->db_z_write_base); /* R_028050_DB_Z_WRITE_BASE */
897 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
898 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
899 radeon_emit(cmd_buffer->cs, ds->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
903 radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
904 ds->pa_su_poly_offset_db_fmt_cntl);
908 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
909 struct radv_image *image,
910 VkClearDepthStencilValue ds_clear_value,
911 VkImageAspectFlags aspects)
913 uint64_t va = radv_buffer_get_va(image->bo);
914 va += image->offset + image->clear_value_offset;
915 unsigned reg_offset = 0, reg_count = 0;
917 assert(image->surface.htile_size);
919 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
925 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
928 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
929 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
930 S_370_WR_CONFIRM(1) |
931 S_370_ENGINE_SEL(V_370_PFP));
932 radeon_emit(cmd_buffer->cs, va);
933 radeon_emit(cmd_buffer->cs, va >> 32);
934 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
935 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
936 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
937 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
939 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
940 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
941 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
942 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
943 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
947 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
948 struct radv_image *image)
950 VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
951 uint64_t va = radv_buffer_get_va(image->bo);
952 va += image->offset + image->clear_value_offset;
953 unsigned reg_offset = 0, reg_count = 0;
955 if (!image->surface.htile_size)
958 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
964 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
967 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
968 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
969 COPY_DATA_DST_SEL(COPY_DATA_REG) |
970 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
971 radeon_emit(cmd_buffer->cs, va);
972 radeon_emit(cmd_buffer->cs, va >> 32);
973 radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
974 radeon_emit(cmd_buffer->cs, 0);
976 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
977 radeon_emit(cmd_buffer->cs, 0);
981 *with DCC some colors don't require CMASK elimiation before being
982 * used as a texture. This sets a predicate value to determine if the
983 * cmask eliminate is required.
986 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
987 struct radv_image *image,
990 uint64_t pred_val = value;
991 uint64_t va = radv_buffer_get_va(image->bo);
992 va += image->offset + image->dcc_pred_offset;
994 assert(image->surface.dcc_size);
996 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
997 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
998 S_370_WR_CONFIRM(1) |
999 S_370_ENGINE_SEL(V_370_PFP));
1000 radeon_emit(cmd_buffer->cs, va);
1001 radeon_emit(cmd_buffer->cs, va >> 32);
1002 radeon_emit(cmd_buffer->cs, pred_val);
1003 radeon_emit(cmd_buffer->cs, pred_val >> 32);
1007 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1008 struct radv_image *image,
1010 uint32_t color_values[2])
1012 uint64_t va = radv_buffer_get_va(image->bo);
1013 va += image->offset + image->clear_value_offset;
1015 assert(image->cmask.size || image->surface.dcc_size);
1017 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1018 radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1019 S_370_WR_CONFIRM(1) |
1020 S_370_ENGINE_SEL(V_370_PFP));
1021 radeon_emit(cmd_buffer->cs, va);
1022 radeon_emit(cmd_buffer->cs, va >> 32);
1023 radeon_emit(cmd_buffer->cs, color_values[0]);
1024 radeon_emit(cmd_buffer->cs, color_values[1]);
1026 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1027 radeon_emit(cmd_buffer->cs, color_values[0]);
1028 radeon_emit(cmd_buffer->cs, color_values[1]);
1032 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1033 struct radv_image *image,
1036 uint64_t va = radv_buffer_get_va(image->bo);
1037 va += image->offset + image->clear_value_offset;
1039 if (!image->cmask.size && !image->surface.dcc_size)
1042 uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1044 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1045 radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1046 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1047 COPY_DATA_COUNT_SEL);
1048 radeon_emit(cmd_buffer->cs, va);
1049 radeon_emit(cmd_buffer->cs, va >> 32);
1050 radeon_emit(cmd_buffer->cs, reg >> 2);
1051 radeon_emit(cmd_buffer->cs, 0);
1053 radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1054 radeon_emit(cmd_buffer->cs, 0);
1058 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1061 struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1062 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1064 /* this may happen for inherited secondary recording */
1068 for (i = 0; i < 8; ++i) {
1069 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1070 radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1071 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1075 int idx = subpass->color_attachments[i].attachment;
1076 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1077 struct radv_image *image = att->attachment->image;
1078 VkImageLayout layout = subpass->color_attachments[i].layout;
1080 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1082 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1083 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1085 radv_load_color_clear_regs(cmd_buffer, image, i);
1088 if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1089 int idx = subpass->depth_stencil_attachment.attachment;
1090 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1091 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1092 struct radv_image *image = att->attachment->image;
1093 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1094 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1095 cmd_buffer->queue_family_index,
1096 cmd_buffer->queue_family_index);
1097 /* We currently don't support writing decompressed HTILE */
1098 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1099 radv_layout_is_htile_compressed(image, layout, queue_mask));
1101 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1103 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1104 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1105 cmd_buffer->state.offset_scale = att->ds.offset_scale;
1107 radv_load_depth_clear_regs(cmd_buffer, image);
1109 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1110 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1112 radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1114 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1115 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1117 radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1118 S_028208_BR_X(framebuffer->width) |
1119 S_028208_BR_Y(framebuffer->height));
1121 if (cmd_buffer->device->dfsm_allowed) {
1122 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1123 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1126 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1130 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1132 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1133 struct radv_cmd_state *state = &cmd_buffer->state;
1135 if (state->index_type != state->last_index_type) {
1136 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1137 radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1138 2, state->index_type);
1140 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1141 radeon_emit(cs, state->index_type);
1144 state->last_index_type = state->index_type;
1147 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1148 radeon_emit(cs, state->index_va);
1149 radeon_emit(cs, state->index_va >> 32);
1151 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1152 radeon_emit(cs, state->max_index_count);
1154 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1157 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1159 uint32_t db_count_control;
1161 if(!cmd_buffer->state.active_occlusion_queries) {
1162 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1163 db_count_control = 0;
1165 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1168 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1169 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1170 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1171 S_028004_ZPASS_ENABLE(1) |
1172 S_028004_SLICE_EVEN_ENABLE(1) |
1173 S_028004_SLICE_ODD_ENABLE(1);
1175 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1176 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1180 radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1184 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1186 uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1188 if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1189 radv_emit_viewport(cmd_buffer);
1191 if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1192 radv_emit_scissor(cmd_buffer);
1194 if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1195 radv_emit_line_width(cmd_buffer);
1197 if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1198 radv_emit_blend_constants(cmd_buffer);
1200 if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1201 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1202 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1203 radv_emit_stencil(cmd_buffer);
1205 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1206 radv_emit_depth_bounds(cmd_buffer);
1208 if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1209 radv_emit_depth_bias(cmd_buffer);
1211 if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1212 radv_emit_discard_rectangle(cmd_buffer);
1214 cmd_buffer->state.dirty &= ~states;
1218 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1219 struct radv_pipeline *pipeline,
1222 gl_shader_stage stage)
1224 struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1225 uint32_t base_reg = pipeline->user_data_0[stage];
1227 if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1230 assert(!desc_set_loc->indirect);
1231 assert(desc_set_loc->num_sgprs == 2);
1232 radeon_set_sh_reg_seq(cmd_buffer->cs,
1233 base_reg + desc_set_loc->sgpr_idx * 4, 2);
1234 radeon_emit(cmd_buffer->cs, va);
1235 radeon_emit(cmd_buffer->cs, va >> 32);
1239 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1240 VkShaderStageFlags stages,
1241 struct radv_descriptor_set *set,
1244 if (cmd_buffer->state.pipeline) {
1245 radv_foreach_stage(stage, stages) {
1246 if (cmd_buffer->state.pipeline->shaders[stage])
1247 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1253 if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1254 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1256 MESA_SHADER_COMPUTE);
1260 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1262 struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1265 if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1270 set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1271 set->va += bo_offset;
1275 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1277 uint32_t size = MAX_SETS * 2 * 4;
1281 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1282 256, &offset, &ptr))
1285 for (unsigned i = 0; i < MAX_SETS; i++) {
1286 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1287 uint64_t set_va = 0;
1288 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1289 if (cmd_buffer->state.valid_descriptors & (1u << i))
1291 uptr[0] = set_va & 0xffffffff;
1292 uptr[1] = set_va >> 32;
1295 uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1298 if (cmd_buffer->state.pipeline) {
1299 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1300 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1301 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1303 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1304 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1305 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1307 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1308 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1309 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1311 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1312 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1313 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1315 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1316 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1317 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1320 if (cmd_buffer->state.compute_pipeline)
1321 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1322 AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1326 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1327 VkShaderStageFlags stages)
1331 if (!cmd_buffer->state.descriptors_dirty)
1334 if (cmd_buffer->state.push_descriptors_dirty)
1335 radv_flush_push_descriptors(cmd_buffer);
1337 if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1338 (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1339 radv_flush_indirect_descriptor_sets(cmd_buffer);
1342 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1344 MAX_SETS * MESA_SHADER_STAGES * 4);
1346 for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1347 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1348 if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
1351 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1353 cmd_buffer->state.descriptors_dirty = 0;
1354 cmd_buffer->state.push_descriptors_dirty = false;
1356 if (unlikely(cmd_buffer->device->trace_bo))
1357 radv_save_descriptors(cmd_buffer);
1359 assert(cmd_buffer->cs->cdw <= cdw_max);
1363 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1364 struct radv_pipeline *pipeline,
1365 VkShaderStageFlags stages)
1367 struct radv_pipeline_layout *layout = pipeline->layout;
1372 stages &= cmd_buffer->push_constant_stages;
1374 (!layout->push_constant_size && !layout->dynamic_offset_count))
1377 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1378 16 * layout->dynamic_offset_count,
1379 256, &offset, &ptr))
1382 memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1383 memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1384 16 * layout->dynamic_offset_count);
1386 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1389 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1390 cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1392 radv_foreach_stage(stage, stages) {
1393 if (pipeline->shaders[stage]) {
1394 radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1395 AC_UD_PUSH_CONSTANTS, va);
1399 cmd_buffer->push_constant_stages &= ~stages;
1400 assert(cmd_buffer->cs->cdw <= cdw_max);
1404 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1406 if ((pipeline_is_dirty ||
1407 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1408 cmd_buffer->state.pipeline->vertex_elements.count &&
1409 radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1410 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1414 uint32_t count = velems->count;
1417 /* allocate some descriptor state for vertex buffers */
1418 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1419 &vb_offset, &vb_ptr))
1422 for (i = 0; i < count; i++) {
1423 uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1425 int vb = velems->binding[i];
1426 struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1427 uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1429 va = radv_buffer_get_va(buffer->bo);
1431 offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1432 va += offset + buffer->offset;
1434 desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1435 if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1436 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1438 desc[2] = buffer->size - offset;
1439 desc[3] = velems->rsrc_word3[i];
1442 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1445 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1446 AC_UD_VS_VERTEX_BUFFERS, va);
1448 cmd_buffer->state.vb_va = va;
1449 cmd_buffer->state.vb_size = count * 16;
1450 cmd_buffer->state.vb_prefetch_dirty = true;
1452 cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1458 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1460 if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1463 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1464 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1465 VK_SHADER_STAGE_ALL_GRAPHICS);
1471 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1472 bool instanced_draw, bool indirect_draw,
1473 uint32_t draw_vertex_count)
1475 struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1476 struct radv_cmd_state *state = &cmd_buffer->state;
1477 struct radeon_winsys_cs *cs = cmd_buffer->cs;
1478 uint32_t ia_multi_vgt_param;
1479 int32_t primitive_reset_en;
1482 ia_multi_vgt_param =
1483 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1484 indirect_draw, draw_vertex_count);
1486 if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1487 if (info->chip_class >= GFX9) {
1488 radeon_set_uconfig_reg_idx(cs,
1489 R_030960_IA_MULTI_VGT_PARAM,
1490 4, ia_multi_vgt_param);
1491 } else if (info->chip_class >= CIK) {
1492 radeon_set_context_reg_idx(cs,
1493 R_028AA8_IA_MULTI_VGT_PARAM,
1494 1, ia_multi_vgt_param);
1496 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1497 ia_multi_vgt_param);
1499 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1502 /* Primitive restart. */
1503 primitive_reset_en =
1504 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1506 if (primitive_reset_en != state->last_primitive_reset_en) {
1507 state->last_primitive_reset_en = primitive_reset_en;
1508 if (info->chip_class >= GFX9) {
1509 radeon_set_uconfig_reg(cs,
1510 R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1511 primitive_reset_en);
1513 radeon_set_context_reg(cs,
1514 R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1515 primitive_reset_en);
1519 if (primitive_reset_en) {
1520 uint32_t primitive_reset_index =
1521 state->index_type ? 0xffffffffu : 0xffffu;
1523 if (primitive_reset_index != state->last_primitive_reset_index) {
1524 radeon_set_context_reg(cs,
1525 R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1526 primitive_reset_index);
1527 state->last_primitive_reset_index = primitive_reset_index;
1532 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1533 VkPipelineStageFlags src_stage_mask)
1535 if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1536 VK_PIPELINE_STAGE_TRANSFER_BIT |
1537 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1538 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1539 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1542 if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1543 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1544 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1545 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1546 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1547 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1548 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1549 VK_PIPELINE_STAGE_TRANSFER_BIT |
1550 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1551 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1552 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1553 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1554 } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1555 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1556 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1557 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1561 static enum radv_cmd_flush_bits
1562 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1563 VkAccessFlags src_flags)
1565 enum radv_cmd_flush_bits flush_bits = 0;
1567 for_each_bit(b, src_flags) {
1568 switch ((VkAccessFlagBits)(1 << b)) {
1569 case VK_ACCESS_SHADER_WRITE_BIT:
1570 flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1572 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1573 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1574 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1576 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1577 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1578 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1580 case VK_ACCESS_TRANSFER_WRITE_BIT:
1581 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1582 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1583 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1584 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1585 RADV_CMD_FLAG_INV_GLOBAL_L2;
1594 static enum radv_cmd_flush_bits
1595 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1596 VkAccessFlags dst_flags,
1597 struct radv_image *image)
1599 enum radv_cmd_flush_bits flush_bits = 0;
1601 for_each_bit(b, dst_flags) {
1602 switch ((VkAccessFlagBits)(1 << b)) {
1603 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1604 case VK_ACCESS_INDEX_READ_BIT:
1606 case VK_ACCESS_UNIFORM_READ_BIT:
1607 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1609 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1610 case VK_ACCESS_SHADER_READ_BIT:
1611 case VK_ACCESS_TRANSFER_READ_BIT:
1612 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1613 flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1614 RADV_CMD_FLAG_INV_GLOBAL_L2;
1616 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1617 /* TODO: change to image && when the image gets passed
1618 * through from the subpass. */
1619 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1620 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1621 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1623 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1624 if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1625 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1626 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1635 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1637 cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1638 radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1639 cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1643 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1644 VkAttachmentReference att)
1646 unsigned idx = att.attachment;
1647 struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1648 VkImageSubresourceRange range;
1649 range.aspectMask = 0;
1650 range.baseMipLevel = view->base_mip;
1651 range.levelCount = 1;
1652 range.baseArrayLayer = view->base_layer;
1653 range.layerCount = cmd_buffer->state.framebuffer->layers;
1655 radv_handle_image_transition(cmd_buffer,
1657 cmd_buffer->state.attachments[idx].current_layout,
1658 att.layout, 0, 0, &range,
1659 cmd_buffer->state.attachments[idx].pending_clear_aspects);
1661 cmd_buffer->state.attachments[idx].current_layout = att.layout;
1667 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1668 const struct radv_subpass *subpass, bool transitions)
1671 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1673 for (unsigned i = 0; i < subpass->color_count; ++i) {
1674 if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1675 radv_handle_subpass_image_transition(cmd_buffer,
1676 subpass->color_attachments[i]);
1679 for (unsigned i = 0; i < subpass->input_count; ++i) {
1680 radv_handle_subpass_image_transition(cmd_buffer,
1681 subpass->input_attachments[i]);
1684 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1685 radv_handle_subpass_image_transition(cmd_buffer,
1686 subpass->depth_stencil_attachment);
1690 cmd_buffer->state.subpass = subpass;
1692 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
1696 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1697 struct radv_render_pass *pass,
1698 const VkRenderPassBeginInfo *info)
1700 struct radv_cmd_state *state = &cmd_buffer->state;
1702 if (pass->attachment_count == 0) {
1703 state->attachments = NULL;
1707 state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1708 pass->attachment_count *
1709 sizeof(state->attachments[0]),
1710 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1711 if (state->attachments == NULL) {
1712 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1713 return cmd_buffer->record_result;
1716 for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1717 struct radv_render_pass_attachment *att = &pass->attachments[i];
1718 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1719 VkImageAspectFlags clear_aspects = 0;
1721 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1722 /* color attachment */
1723 if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1724 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1727 /* depthstencil attachment */
1728 if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1729 att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1730 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1731 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1732 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1733 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1735 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1736 att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1737 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1741 state->attachments[i].pending_clear_aspects = clear_aspects;
1742 state->attachments[i].cleared_views = 0;
1743 if (clear_aspects && info) {
1744 assert(info->clearValueCount > i);
1745 state->attachments[i].clear_value = info->pClearValues[i];
1748 state->attachments[i].current_layout = att->initial_layout;
1754 VkResult radv_AllocateCommandBuffers(
1756 const VkCommandBufferAllocateInfo *pAllocateInfo,
1757 VkCommandBuffer *pCommandBuffers)
1759 RADV_FROM_HANDLE(radv_device, device, _device);
1760 RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1762 VkResult result = VK_SUCCESS;
1765 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1767 if (!list_empty(&pool->free_cmd_buffers)) {
1768 struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1770 list_del(&cmd_buffer->pool_link);
1771 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1773 result = radv_reset_cmd_buffer(cmd_buffer);
1774 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1775 cmd_buffer->level = pAllocateInfo->level;
1777 pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1779 result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1780 &pCommandBuffers[i]);
1782 if (result != VK_SUCCESS)
1786 if (result != VK_SUCCESS) {
1787 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1788 i, pCommandBuffers);
1790 /* From the Vulkan 1.0.66 spec:
1792 * "vkAllocateCommandBuffers can be used to create multiple
1793 * command buffers. If the creation of any of those command
1794 * buffers fails, the implementation must destroy all
1795 * successfully created command buffer objects from this
1796 * command, set all entries of the pCommandBuffers array to
1797 * NULL and return the error."
1799 memset(pCommandBuffers, 0,
1800 sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1806 void radv_FreeCommandBuffers(
1808 VkCommandPool commandPool,
1809 uint32_t commandBufferCount,
1810 const VkCommandBuffer *pCommandBuffers)
1812 for (uint32_t i = 0; i < commandBufferCount; i++) {
1813 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1816 if (cmd_buffer->pool) {
1817 list_del(&cmd_buffer->pool_link);
1818 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1820 radv_cmd_buffer_destroy(cmd_buffer);
1826 VkResult radv_ResetCommandBuffer(
1827 VkCommandBuffer commandBuffer,
1828 VkCommandBufferResetFlags flags)
1830 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1831 return radv_reset_cmd_buffer(cmd_buffer);
1834 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1836 struct radv_device *device = cmd_buffer->device;
1837 if (device->gfx_init) {
1838 uint64_t va = radv_buffer_get_va(device->gfx_init);
1839 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
1840 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1841 radeon_emit(cmd_buffer->cs, va);
1842 radeon_emit(cmd_buffer->cs, va >> 32);
1843 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1845 si_init_config(cmd_buffer);
1848 VkResult radv_BeginCommandBuffer(
1849 VkCommandBuffer commandBuffer,
1850 const VkCommandBufferBeginInfo *pBeginInfo)
1852 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1853 VkResult result = VK_SUCCESS;
1855 if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
1856 /* If the command buffer has already been resetted with
1857 * vkResetCommandBuffer, no need to do it again.
1859 result = radv_reset_cmd_buffer(cmd_buffer);
1860 if (result != VK_SUCCESS)
1864 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1865 cmd_buffer->state.last_primitive_reset_en = -1;
1866 cmd_buffer->state.last_index_type = -1;
1867 cmd_buffer->state.last_num_instances = -1;
1868 cmd_buffer->state.last_vertex_offset = -1;
1869 cmd_buffer->state.last_first_instance = -1;
1870 cmd_buffer->usage_flags = pBeginInfo->flags;
1872 /* setup initial configuration into command buffer */
1873 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1874 switch (cmd_buffer->queue_family_index) {
1875 case RADV_QUEUE_GENERAL:
1876 emit_gfx_buffer_state(cmd_buffer);
1878 case RADV_QUEUE_COMPUTE:
1879 si_init_compute(cmd_buffer);
1881 case RADV_QUEUE_TRANSFER:
1887 if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1888 assert(pBeginInfo->pInheritanceInfo);
1889 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1890 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1892 struct radv_subpass *subpass =
1893 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1895 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1896 if (result != VK_SUCCESS)
1899 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1902 if (unlikely(cmd_buffer->device->trace_bo))
1903 radv_cmd_buffer_trace_emit(cmd_buffer);
1905 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
1910 void radv_CmdBindVertexBuffers(
1911 VkCommandBuffer commandBuffer,
1912 uint32_t firstBinding,
1913 uint32_t bindingCount,
1914 const VkBuffer* pBuffers,
1915 const VkDeviceSize* pOffsets)
1917 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1918 struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
1919 bool changed = false;
1921 /* We have to defer setting up vertex buffer since we need the buffer
1922 * stride from the pipeline. */
1924 assert(firstBinding + bindingCount <= MAX_VBS);
1925 for (uint32_t i = 0; i < bindingCount; i++) {
1926 uint32_t idx = firstBinding + i;
1929 (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
1930 vb[idx].offset != pOffsets[i])) {
1934 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
1935 vb[idx].offset = pOffsets[i];
1937 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
1938 vb[idx].buffer->bo, 8);
1942 /* No state changes. */
1946 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
1949 void radv_CmdBindIndexBuffer(
1950 VkCommandBuffer commandBuffer,
1952 VkDeviceSize offset,
1953 VkIndexType indexType)
1955 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1956 RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
1958 if (cmd_buffer->state.index_buffer == index_buffer &&
1959 cmd_buffer->state.index_offset == offset &&
1960 cmd_buffer->state.index_type == indexType) {
1961 /* No state changes. */
1965 cmd_buffer->state.index_buffer = index_buffer;
1966 cmd_buffer->state.index_offset = offset;
1967 cmd_buffer->state.index_type = indexType; /* vk matches hw */
1968 cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
1969 cmd_buffer->state.index_va += index_buffer->offset + offset;
1971 int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
1972 cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
1973 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
1974 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
1979 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1980 struct radv_descriptor_set *set, unsigned idx)
1982 struct radeon_winsys *ws = cmd_buffer->device->ws;
1984 radv_set_descriptor_set(cmd_buffer, set, idx);
1988 assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
1990 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
1991 if (set->descriptors[j])
1992 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
1995 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
1998 void radv_CmdBindDescriptorSets(
1999 VkCommandBuffer commandBuffer,
2000 VkPipelineBindPoint pipelineBindPoint,
2001 VkPipelineLayout _layout,
2003 uint32_t descriptorSetCount,
2004 const VkDescriptorSet* pDescriptorSets,
2005 uint32_t dynamicOffsetCount,
2006 const uint32_t* pDynamicOffsets)
2008 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2009 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2010 unsigned dyn_idx = 0;
2012 for (unsigned i = 0; i < descriptorSetCount; ++i) {
2013 unsigned idx = i + firstSet;
2014 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2015 radv_bind_descriptor_set(cmd_buffer, set, idx);
2017 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2018 unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2019 uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2020 assert(dyn_idx < dynamicOffsetCount);
2022 struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2023 uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2025 dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2026 dst[2] = range->size;
2027 dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2028 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2029 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2030 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2031 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2032 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2033 cmd_buffer->push_constant_stages |=
2034 set->layout->dynamic_shader_stages;
2039 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2040 struct radv_descriptor_set *set,
2041 struct radv_descriptor_set_layout *layout)
2043 set->size = layout->size;
2044 set->layout = layout;
2046 if (cmd_buffer->push_descriptors.capacity < set->size) {
2047 size_t new_size = MAX2(set->size, 1024);
2048 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2049 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2051 free(set->mapped_ptr);
2052 set->mapped_ptr = malloc(new_size);
2054 if (!set->mapped_ptr) {
2055 cmd_buffer->push_descriptors.capacity = 0;
2056 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2060 cmd_buffer->push_descriptors.capacity = new_size;
2066 void radv_meta_push_descriptor_set(
2067 struct radv_cmd_buffer* cmd_buffer,
2068 VkPipelineBindPoint pipelineBindPoint,
2069 VkPipelineLayout _layout,
2071 uint32_t descriptorWriteCount,
2072 const VkWriteDescriptorSet* pDescriptorWrites)
2074 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2075 struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2079 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2081 push_set->size = layout->set[set].layout->size;
2082 push_set->layout = layout->set[set].layout;
2084 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2086 (void**) &push_set->mapped_ptr))
2089 push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2090 push_set->va += bo_offset;
2092 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2093 radv_descriptor_set_to_handle(push_set),
2094 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2096 radv_set_descriptor_set(cmd_buffer, push_set, set);
2099 void radv_CmdPushDescriptorSetKHR(
2100 VkCommandBuffer commandBuffer,
2101 VkPipelineBindPoint pipelineBindPoint,
2102 VkPipelineLayout _layout,
2104 uint32_t descriptorWriteCount,
2105 const VkWriteDescriptorSet* pDescriptorWrites)
2107 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2108 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2109 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2111 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2113 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2116 radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2117 radv_descriptor_set_to_handle(push_set),
2118 descriptorWriteCount, pDescriptorWrites, 0, NULL);
2120 radv_set_descriptor_set(cmd_buffer, push_set, set);
2121 cmd_buffer->state.push_descriptors_dirty = true;
2124 void radv_CmdPushDescriptorSetWithTemplateKHR(
2125 VkCommandBuffer commandBuffer,
2126 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
2127 VkPipelineLayout _layout,
2131 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2132 RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2133 struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2135 assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2137 if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2140 radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2141 descriptorUpdateTemplate, pData);
2143 radv_set_descriptor_set(cmd_buffer, push_set, set);
2144 cmd_buffer->state.push_descriptors_dirty = true;
2147 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2148 VkPipelineLayout layout,
2149 VkShaderStageFlags stageFlags,
2152 const void* pValues)
2154 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2155 memcpy(cmd_buffer->push_constants + offset, pValues, size);
2156 cmd_buffer->push_constant_stages |= stageFlags;
2159 VkResult radv_EndCommandBuffer(
2160 VkCommandBuffer commandBuffer)
2162 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2164 if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2165 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2166 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2167 si_emit_cache_flush(cmd_buffer);
2170 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2172 if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2173 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2175 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2177 return cmd_buffer->record_result;
2181 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2183 struct radv_shader_variant *compute_shader;
2184 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2185 struct radv_device *device = cmd_buffer->device;
2186 unsigned compute_resource_limits;
2187 unsigned waves_per_threadgroup;
2190 if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2193 cmd_buffer->state.emitted_compute_pipeline = pipeline;
2195 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2196 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2198 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2199 cmd_buffer->cs, 19);
2201 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2202 radeon_emit(cmd_buffer->cs, va >> 8);
2203 radeon_emit(cmd_buffer->cs, va >> 40);
2205 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2206 radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2207 radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2210 cmd_buffer->compute_scratch_size_needed =
2211 MAX2(cmd_buffer->compute_scratch_size_needed,
2212 pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2214 /* change these once we have scratch support */
2215 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2216 S_00B860_WAVES(pipeline->max_waves) |
2217 S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2219 /* Calculate best compute resource limits. */
2220 waves_per_threadgroup =
2221 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
2222 compute_shader->info.cs.block_size[1] *
2223 compute_shader->info.cs.block_size[2], 64);
2224 compute_resource_limits =
2225 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
2227 if (device->physical_device->rad_info.chip_class >= CIK) {
2228 unsigned num_cu_per_se =
2229 device->physical_device->rad_info.num_good_compute_units /
2230 device->physical_device->rad_info.max_se;
2232 /* Force even distribution on all SIMDs in CU if the workgroup
2233 * size is 64. This has shown some good improvements if # of
2234 * CUs per SE is not a multiple of 4.
2236 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
2237 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
2240 radeon_set_sh_reg(cmd_buffer->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
2241 compute_resource_limits);
2243 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2244 radeon_emit(cmd_buffer->cs,
2245 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2246 radeon_emit(cmd_buffer->cs,
2247 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2248 radeon_emit(cmd_buffer->cs,
2249 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2251 assert(cmd_buffer->cs->cdw <= cdw_max);
2253 if (unlikely(cmd_buffer->device->trace_bo))
2254 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2257 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2259 cmd_buffer->state.descriptors_dirty |= cmd_buffer->state.valid_descriptors;
2262 void radv_CmdBindPipeline(
2263 VkCommandBuffer commandBuffer,
2264 VkPipelineBindPoint pipelineBindPoint,
2265 VkPipeline _pipeline)
2267 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2268 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2270 switch (pipelineBindPoint) {
2271 case VK_PIPELINE_BIND_POINT_COMPUTE:
2272 if (cmd_buffer->state.compute_pipeline == pipeline)
2274 radv_mark_descriptor_sets_dirty(cmd_buffer);
2276 cmd_buffer->state.compute_pipeline = pipeline;
2277 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2279 case VK_PIPELINE_BIND_POINT_GRAPHICS:
2280 if (cmd_buffer->state.pipeline == pipeline)
2282 radv_mark_descriptor_sets_dirty(cmd_buffer);
2284 cmd_buffer->state.pipeline = pipeline;
2288 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2289 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2291 /* the new vertex shader might not have the same user regs */
2292 cmd_buffer->state.last_first_instance = -1;
2293 cmd_buffer->state.last_vertex_offset = -1;
2295 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2297 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2298 cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2299 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2300 cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2302 if (radv_pipeline_has_tess(pipeline))
2303 cmd_buffer->tess_rings_needed = true;
2305 if (radv_pipeline_has_gs(pipeline)) {
2306 struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2307 AC_UD_SCRATCH_RING_OFFSETS);
2308 if (cmd_buffer->ring_offsets_idx == -1)
2309 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2310 else if (loc->sgpr_idx != -1)
2311 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2315 assert(!"invalid bind point");
2320 void radv_CmdSetViewport(
2321 VkCommandBuffer commandBuffer,
2322 uint32_t firstViewport,
2323 uint32_t viewportCount,
2324 const VkViewport* pViewports)
2326 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2327 struct radv_cmd_state *state = &cmd_buffer->state;
2328 MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2330 assert(firstViewport < MAX_VIEWPORTS);
2331 assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2333 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2334 /* Try to skip unnecessary PS partial flushes when the viewports
2337 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2338 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2339 !memcmp(state->dynamic.viewport.viewports + firstViewport,
2340 pViewports, viewportCount * sizeof(*pViewports))) {
2345 memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2346 viewportCount * sizeof(*pViewports));
2348 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2351 void radv_CmdSetScissor(
2352 VkCommandBuffer commandBuffer,
2353 uint32_t firstScissor,
2354 uint32_t scissorCount,
2355 const VkRect2D* pScissors)
2357 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2358 struct radv_cmd_state *state = &cmd_buffer->state;
2359 MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2361 assert(firstScissor < MAX_SCISSORS);
2362 assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2364 if (cmd_buffer->device->physical_device->has_scissor_bug) {
2365 /* Try to skip unnecessary PS partial flushes when the scissors
2368 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2369 RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2370 !memcmp(state->dynamic.scissor.scissors + firstScissor,
2371 pScissors, scissorCount * sizeof(*pScissors))) {
2376 memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2377 scissorCount * sizeof(*pScissors));
2379 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2382 void radv_CmdSetLineWidth(
2383 VkCommandBuffer commandBuffer,
2386 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2387 cmd_buffer->state.dynamic.line_width = lineWidth;
2388 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2391 void radv_CmdSetDepthBias(
2392 VkCommandBuffer commandBuffer,
2393 float depthBiasConstantFactor,
2394 float depthBiasClamp,
2395 float depthBiasSlopeFactor)
2397 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2399 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2400 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2401 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2403 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2406 void radv_CmdSetBlendConstants(
2407 VkCommandBuffer commandBuffer,
2408 const float blendConstants[4])
2410 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2412 memcpy(cmd_buffer->state.dynamic.blend_constants,
2413 blendConstants, sizeof(float) * 4);
2415 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2418 void radv_CmdSetDepthBounds(
2419 VkCommandBuffer commandBuffer,
2420 float minDepthBounds,
2421 float maxDepthBounds)
2423 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2425 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2426 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2428 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2431 void radv_CmdSetStencilCompareMask(
2432 VkCommandBuffer commandBuffer,
2433 VkStencilFaceFlags faceMask,
2434 uint32_t compareMask)
2436 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2438 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2439 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2440 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2441 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2443 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2446 void radv_CmdSetStencilWriteMask(
2447 VkCommandBuffer commandBuffer,
2448 VkStencilFaceFlags faceMask,
2451 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2453 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2454 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2455 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2456 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2458 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2461 void radv_CmdSetStencilReference(
2462 VkCommandBuffer commandBuffer,
2463 VkStencilFaceFlags faceMask,
2466 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2468 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2469 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2470 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2471 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2473 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2476 void radv_CmdSetDiscardRectangleEXT(
2477 VkCommandBuffer commandBuffer,
2478 uint32_t firstDiscardRectangle,
2479 uint32_t discardRectangleCount,
2480 const VkRect2D* pDiscardRectangles)
2482 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2483 struct radv_cmd_state *state = &cmd_buffer->state;
2484 MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2486 assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2487 assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2489 typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2490 pDiscardRectangles, discardRectangleCount);
2492 state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2495 void radv_CmdExecuteCommands(
2496 VkCommandBuffer commandBuffer,
2497 uint32_t commandBufferCount,
2498 const VkCommandBuffer* pCmdBuffers)
2500 RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2502 assert(commandBufferCount > 0);
2504 /* Emit pending flushes on primary prior to executing secondary */
2505 si_emit_cache_flush(primary);
2507 for (uint32_t i = 0; i < commandBufferCount; i++) {
2508 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2510 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2511 secondary->scratch_size_needed);
2512 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2513 secondary->compute_scratch_size_needed);
2515 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2516 primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2517 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2518 primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2519 if (secondary->tess_rings_needed)
2520 primary->tess_rings_needed = true;
2521 if (secondary->sample_positions_needed)
2522 primary->sample_positions_needed = true;
2524 if (secondary->ring_offsets_idx != -1) {
2525 if (primary->ring_offsets_idx == -1)
2526 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2528 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2530 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2533 /* When the secondary command buffer is compute only we don't
2534 * need to re-emit the current graphics pipeline.
2536 if (secondary->state.emitted_pipeline) {
2537 primary->state.emitted_pipeline =
2538 secondary->state.emitted_pipeline;
2541 /* When the secondary command buffer is graphics only we don't
2542 * need to re-emit the current compute pipeline.
2544 if (secondary->state.emitted_compute_pipeline) {
2545 primary->state.emitted_compute_pipeline =
2546 secondary->state.emitted_compute_pipeline;
2549 /* Only re-emit the draw packets when needed. */
2550 if (secondary->state.last_primitive_reset_en != -1) {
2551 primary->state.last_primitive_reset_en =
2552 secondary->state.last_primitive_reset_en;
2555 if (secondary->state.last_primitive_reset_index) {
2556 primary->state.last_primitive_reset_index =
2557 secondary->state.last_primitive_reset_index;
2560 if (secondary->state.last_ia_multi_vgt_param) {
2561 primary->state.last_ia_multi_vgt_param =
2562 secondary->state.last_ia_multi_vgt_param;
2565 if (secondary->state.last_first_instance != -1) {
2566 primary->state.last_first_instance =
2567 secondary->state.last_first_instance;
2570 if (secondary->state.last_num_instances != -1) {
2571 primary->state.last_num_instances =
2572 secondary->state.last_num_instances;
2575 if (secondary->state.last_vertex_offset != -1) {
2576 primary->state.last_vertex_offset =
2577 secondary->state.last_vertex_offset;
2580 if (secondary->state.last_index_type != -1) {
2581 primary->state.last_index_type =
2582 secondary->state.last_index_type;
2586 /* After executing commands from secondary buffers we have to dirty
2589 primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2590 RADV_CMD_DIRTY_INDEX_BUFFER |
2591 RADV_CMD_DIRTY_DYNAMIC_ALL;
2592 radv_mark_descriptor_sets_dirty(primary);
2595 VkResult radv_CreateCommandPool(
2597 const VkCommandPoolCreateInfo* pCreateInfo,
2598 const VkAllocationCallbacks* pAllocator,
2599 VkCommandPool* pCmdPool)
2601 RADV_FROM_HANDLE(radv_device, device, _device);
2602 struct radv_cmd_pool *pool;
2604 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2605 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2607 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2610 pool->alloc = *pAllocator;
2612 pool->alloc = device->alloc;
2614 list_inithead(&pool->cmd_buffers);
2615 list_inithead(&pool->free_cmd_buffers);
2617 pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2619 *pCmdPool = radv_cmd_pool_to_handle(pool);
2625 void radv_DestroyCommandPool(
2627 VkCommandPool commandPool,
2628 const VkAllocationCallbacks* pAllocator)
2630 RADV_FROM_HANDLE(radv_device, device, _device);
2631 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2636 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2637 &pool->cmd_buffers, pool_link) {
2638 radv_cmd_buffer_destroy(cmd_buffer);
2641 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2642 &pool->free_cmd_buffers, pool_link) {
2643 radv_cmd_buffer_destroy(cmd_buffer);
2646 vk_free2(&device->alloc, pAllocator, pool);
2649 VkResult radv_ResetCommandPool(
2651 VkCommandPool commandPool,
2652 VkCommandPoolResetFlags flags)
2654 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2657 list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2658 &pool->cmd_buffers, pool_link) {
2659 result = radv_reset_cmd_buffer(cmd_buffer);
2660 if (result != VK_SUCCESS)
2667 void radv_TrimCommandPoolKHR(
2669 VkCommandPool commandPool,
2670 VkCommandPoolTrimFlagsKHR flags)
2672 RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2677 list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2678 &pool->free_cmd_buffers, pool_link) {
2679 radv_cmd_buffer_destroy(cmd_buffer);
2683 void radv_CmdBeginRenderPass(
2684 VkCommandBuffer commandBuffer,
2685 const VkRenderPassBeginInfo* pRenderPassBegin,
2686 VkSubpassContents contents)
2688 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2689 RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2690 RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2692 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2693 cmd_buffer->cs, 2048);
2694 MAYBE_UNUSED VkResult result;
2696 cmd_buffer->state.framebuffer = framebuffer;
2697 cmd_buffer->state.pass = pass;
2698 cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2700 result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2701 if (result != VK_SUCCESS)
2704 radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2705 assert(cmd_buffer->cs->cdw <= cdw_max);
2707 radv_cmd_buffer_clear_subpass(cmd_buffer);
2710 void radv_CmdNextSubpass(
2711 VkCommandBuffer commandBuffer,
2712 VkSubpassContents contents)
2714 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2716 radv_cmd_buffer_resolve_subpass(cmd_buffer);
2718 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2721 radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2722 radv_cmd_buffer_clear_subpass(cmd_buffer);
2725 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2727 struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2728 for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2729 if (!pipeline->shaders[stage])
2731 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2732 if (loc->sgpr_idx == -1)
2734 uint32_t base_reg = pipeline->user_data_0[stage];
2735 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2738 if (pipeline->gs_copy_shader) {
2739 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2740 if (loc->sgpr_idx != -1) {
2741 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2742 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2748 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2749 uint32_t vertex_count)
2751 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2752 radeon_emit(cmd_buffer->cs, vertex_count);
2753 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2754 S_0287F0_USE_OPAQUE(0));
2758 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2760 uint32_t index_count)
2762 radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2763 radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2764 radeon_emit(cmd_buffer->cs, index_va);
2765 radeon_emit(cmd_buffer->cs, index_va >> 32);
2766 radeon_emit(cmd_buffer->cs, index_count);
2767 radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2771 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2773 uint32_t draw_count,
2777 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2778 unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2779 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2780 bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
2781 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2784 /* just reset draw state for vertex data */
2785 cmd_buffer->state.last_first_instance = -1;
2786 cmd_buffer->state.last_num_instances = -1;
2787 cmd_buffer->state.last_vertex_offset = -1;
2789 if (draw_count == 1 && !count_va && !draw_id_enable) {
2790 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2791 PKT3_DRAW_INDIRECT, 3, false));
2793 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2794 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2795 radeon_emit(cs, di_src_sel);
2797 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2798 PKT3_DRAW_INDIRECT_MULTI,
2801 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2802 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2803 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2804 S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2805 S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2806 radeon_emit(cs, draw_count); /* count */
2807 radeon_emit(cs, count_va); /* count_addr */
2808 radeon_emit(cs, count_va >> 32);
2809 radeon_emit(cs, stride); /* stride */
2810 radeon_emit(cs, di_src_sel);
2814 struct radv_draw_info {
2816 * Number of vertices.
2821 * Index of the first vertex.
2823 int32_t vertex_offset;
2826 * First instance id.
2828 uint32_t first_instance;
2831 * Number of instances.
2833 uint32_t instance_count;
2836 * First index (indexed draws only).
2838 uint32_t first_index;
2841 * Whether it's an indexed draw.
2846 * Indirect draw parameters resource.
2848 struct radv_buffer *indirect;
2849 uint64_t indirect_offset;
2853 * Draw count parameters resource.
2855 struct radv_buffer *count_buffer;
2856 uint64_t count_buffer_offset;
2860 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
2861 const struct radv_draw_info *info)
2863 struct radv_cmd_state *state = &cmd_buffer->state;
2864 struct radeon_winsys *ws = cmd_buffer->device->ws;
2865 struct radeon_winsys_cs *cs = cmd_buffer->cs;
2867 if (info->indirect) {
2868 uint64_t va = radv_buffer_get_va(info->indirect->bo);
2869 uint64_t count_va = 0;
2871 va += info->indirect->offset + info->indirect_offset;
2873 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
2875 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2877 radeon_emit(cs, va);
2878 radeon_emit(cs, va >> 32);
2880 if (info->count_buffer) {
2881 count_va = radv_buffer_get_va(info->count_buffer->bo);
2882 count_va += info->count_buffer->offset +
2883 info->count_buffer_offset;
2885 radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
2888 if (!state->subpass->view_mask) {
2889 radv_cs_emit_indirect_draw_packet(cmd_buffer,
2896 for_each_bit(i, state->subpass->view_mask) {
2897 radv_emit_view_index(cmd_buffer, i);
2899 radv_cs_emit_indirect_draw_packet(cmd_buffer,
2907 assert(state->pipeline->graphics.vtx_base_sgpr);
2909 if (info->vertex_offset != state->last_vertex_offset ||
2910 info->first_instance != state->last_first_instance) {
2911 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
2912 state->pipeline->graphics.vtx_emit_num);
2914 radeon_emit(cs, info->vertex_offset);
2915 radeon_emit(cs, info->first_instance);
2916 if (state->pipeline->graphics.vtx_emit_num == 3)
2918 state->last_first_instance = info->first_instance;
2919 state->last_vertex_offset = info->vertex_offset;
2922 if (state->last_num_instances != info->instance_count) {
2923 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
2924 radeon_emit(cs, info->instance_count);
2925 state->last_num_instances = info->instance_count;
2928 if (info->indexed) {
2929 int index_size = state->index_type ? 4 : 2;
2932 index_va = state->index_va;
2933 index_va += info->first_index * index_size;
2935 if (!state->subpass->view_mask) {
2936 radv_cs_emit_draw_indexed_packet(cmd_buffer,
2941 for_each_bit(i, state->subpass->view_mask) {
2942 radv_emit_view_index(cmd_buffer, i);
2944 radv_cs_emit_draw_indexed_packet(cmd_buffer,
2950 if (!state->subpass->view_mask) {
2951 radv_cs_emit_draw_packet(cmd_buffer, info->count);
2954 for_each_bit(i, state->subpass->view_mask) {
2955 radv_emit_view_index(cmd_buffer, i);
2957 radv_cs_emit_draw_packet(cmd_buffer,
2966 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
2967 const struct radv_draw_info *info)
2969 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
2970 radv_emit_graphics_pipeline(cmd_buffer);
2972 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
2973 radv_emit_framebuffer_state(cmd_buffer);
2975 if (info->indexed) {
2976 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
2977 radv_emit_index_buffer(cmd_buffer);
2979 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
2980 * so the state must be re-emitted before the next indexed
2983 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
2984 cmd_buffer->state.last_index_type = -1;
2985 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2989 radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
2991 radv_emit_draw_registers(cmd_buffer, info->indexed,
2992 info->instance_count > 1, info->indirect,
2993 info->indirect ? 0 : info->count);
2997 radv_draw(struct radv_cmd_buffer *cmd_buffer,
2998 const struct radv_draw_info *info)
3000 bool pipeline_is_dirty =
3001 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3002 cmd_buffer->state.pipeline &&
3003 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3005 MAYBE_UNUSED unsigned cdw_max =
3006 radeon_check_space(cmd_buffer->device->ws,
3007 cmd_buffer->cs, 4096);
3009 /* Use optimal packet order based on whether we need to sync the
3012 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3013 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3014 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3015 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3016 /* If we have to wait for idle, set all states first, so that
3017 * all SET packets are processed in parallel with previous draw
3018 * calls. Then upload descriptors, set shader pointers, and
3019 * draw, and prefetch at the end. This ensures that the time
3020 * the CUs are idle is very short. (there are only SET_SH
3021 * packets between the wait and the draw)
3023 radv_emit_all_graphics_states(cmd_buffer, info);
3024 si_emit_cache_flush(cmd_buffer);
3025 /* <-- CUs are idle here --> */
3027 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3030 radv_emit_draw_packets(cmd_buffer, info);
3031 /* <-- CUs are busy here --> */
3033 /* Start prefetches after the draw has been started. Both will
3034 * run in parallel, but starting the draw first is more
3037 if (pipeline_is_dirty) {
3038 radv_emit_prefetch(cmd_buffer,
3039 cmd_buffer->state.pipeline);
3042 /* If we don't wait for idle, start prefetches first, then set
3043 * states, and draw at the end.
3045 si_emit_cache_flush(cmd_buffer);
3047 if (pipeline_is_dirty) {
3048 radv_emit_prefetch(cmd_buffer,
3049 cmd_buffer->state.pipeline);
3052 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3055 radv_emit_all_graphics_states(cmd_buffer, info);
3056 radv_emit_draw_packets(cmd_buffer, info);
3059 assert(cmd_buffer->cs->cdw <= cdw_max);
3060 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3064 VkCommandBuffer commandBuffer,
3065 uint32_t vertexCount,
3066 uint32_t instanceCount,
3067 uint32_t firstVertex,
3068 uint32_t firstInstance)
3070 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3071 struct radv_draw_info info = {};
3073 info.count = vertexCount;
3074 info.instance_count = instanceCount;
3075 info.first_instance = firstInstance;
3076 info.vertex_offset = firstVertex;
3078 radv_draw(cmd_buffer, &info);
3081 void radv_CmdDrawIndexed(
3082 VkCommandBuffer commandBuffer,
3083 uint32_t indexCount,
3084 uint32_t instanceCount,
3085 uint32_t firstIndex,
3086 int32_t vertexOffset,
3087 uint32_t firstInstance)
3089 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3090 struct radv_draw_info info = {};
3092 info.indexed = true;
3093 info.count = indexCount;
3094 info.instance_count = instanceCount;
3095 info.first_index = firstIndex;
3096 info.vertex_offset = vertexOffset;
3097 info.first_instance = firstInstance;
3099 radv_draw(cmd_buffer, &info);
3102 void radv_CmdDrawIndirect(
3103 VkCommandBuffer commandBuffer,
3105 VkDeviceSize offset,
3109 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3110 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3111 struct radv_draw_info info = {};
3113 info.count = drawCount;
3114 info.indirect = buffer;
3115 info.indirect_offset = offset;
3116 info.stride = stride;
3118 radv_draw(cmd_buffer, &info);
3121 void radv_CmdDrawIndexedIndirect(
3122 VkCommandBuffer commandBuffer,
3124 VkDeviceSize offset,
3128 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3129 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3130 struct radv_draw_info info = {};
3132 info.indexed = true;
3133 info.count = drawCount;
3134 info.indirect = buffer;
3135 info.indirect_offset = offset;
3136 info.stride = stride;
3138 radv_draw(cmd_buffer, &info);
3141 void radv_CmdDrawIndirectCountAMD(
3142 VkCommandBuffer commandBuffer,
3144 VkDeviceSize offset,
3145 VkBuffer _countBuffer,
3146 VkDeviceSize countBufferOffset,
3147 uint32_t maxDrawCount,
3150 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3151 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3152 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3153 struct radv_draw_info info = {};
3155 info.count = maxDrawCount;
3156 info.indirect = buffer;
3157 info.indirect_offset = offset;
3158 info.count_buffer = count_buffer;
3159 info.count_buffer_offset = countBufferOffset;
3160 info.stride = stride;
3162 radv_draw(cmd_buffer, &info);
3165 void radv_CmdDrawIndexedIndirectCountAMD(
3166 VkCommandBuffer commandBuffer,
3168 VkDeviceSize offset,
3169 VkBuffer _countBuffer,
3170 VkDeviceSize countBufferOffset,
3171 uint32_t maxDrawCount,
3174 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3175 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3176 RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3177 struct radv_draw_info info = {};
3179 info.indexed = true;
3180 info.count = maxDrawCount;
3181 info.indirect = buffer;
3182 info.indirect_offset = offset;
3183 info.count_buffer = count_buffer;
3184 info.count_buffer_offset = countBufferOffset;
3185 info.stride = stride;
3187 radv_draw(cmd_buffer, &info);
3190 struct radv_dispatch_info {
3192 * Determine the layout of the grid (in block units) to be used.
3197 * Whether it's an unaligned compute dispatch.
3202 * Indirect compute parameters resource.
3204 struct radv_buffer *indirect;
3205 uint64_t indirect_offset;
3209 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3210 const struct radv_dispatch_info *info)
3212 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3213 struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3214 unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3215 struct radeon_winsys *ws = cmd_buffer->device->ws;
3216 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3217 struct ac_userdata_info *loc;
3219 loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3220 AC_UD_CS_GRID_SIZE);
3222 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3224 if (info->indirect) {
3225 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3227 va += info->indirect->offset + info->indirect_offset;
3229 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3231 if (loc->sgpr_idx != -1) {
3232 for (unsigned i = 0; i < 3; ++i) {
3233 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3234 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3235 COPY_DATA_DST_SEL(COPY_DATA_REG));
3236 radeon_emit(cs, (va + 4 * i));
3237 radeon_emit(cs, (va + 4 * i) >> 32);
3238 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3239 + loc->sgpr_idx * 4) >> 2) + i);
3244 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3245 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3246 PKT3_SHADER_TYPE_S(1));
3247 radeon_emit(cs, va);
3248 radeon_emit(cs, va >> 32);
3249 radeon_emit(cs, dispatch_initiator);
3251 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3252 PKT3_SHADER_TYPE_S(1));
3254 radeon_emit(cs, va);
3255 radeon_emit(cs, va >> 32);
3257 radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3258 PKT3_SHADER_TYPE_S(1));
3260 radeon_emit(cs, dispatch_initiator);
3263 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3265 if (info->unaligned) {
3266 unsigned *cs_block_size = compute_shader->info.cs.block_size;
3267 unsigned remainder[3];
3269 /* If aligned, these should be an entire block size,
3272 remainder[0] = blocks[0] + cs_block_size[0] -
3273 align_u32_npot(blocks[0], cs_block_size[0]);
3274 remainder[1] = blocks[1] + cs_block_size[1] -
3275 align_u32_npot(blocks[1], cs_block_size[1]);
3276 remainder[2] = blocks[2] + cs_block_size[2] -
3277 align_u32_npot(blocks[2], cs_block_size[2]);
3279 blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3280 blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3281 blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3283 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3285 S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3286 S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3288 S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3289 S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3291 S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3292 S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3294 dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3297 if (loc->sgpr_idx != -1) {
3298 assert(!loc->indirect);
3299 assert(loc->num_sgprs == 3);
3301 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3302 loc->sgpr_idx * 4, 3);
3303 radeon_emit(cs, blocks[0]);
3304 radeon_emit(cs, blocks[1]);
3305 radeon_emit(cs, blocks[2]);
3308 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3309 PKT3_SHADER_TYPE_S(1));
3310 radeon_emit(cs, blocks[0]);
3311 radeon_emit(cs, blocks[1]);
3312 radeon_emit(cs, blocks[2]);
3313 radeon_emit(cs, dispatch_initiator);
3316 assert(cmd_buffer->cs->cdw <= cdw_max);
3320 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3322 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3323 radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3324 VK_SHADER_STAGE_COMPUTE_BIT);
3328 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3329 const struct radv_dispatch_info *info)
3331 struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3332 bool pipeline_is_dirty = pipeline &&
3333 pipeline != cmd_buffer->state.emitted_compute_pipeline;
3335 if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3336 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3337 RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3338 RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3339 /* If we have to wait for idle, set all states first, so that
3340 * all SET packets are processed in parallel with previous draw
3341 * calls. Then upload descriptors, set shader pointers, and
3342 * dispatch, and prefetch at the end. This ensures that the
3343 * time the CUs are idle is very short. (there are only SET_SH
3344 * packets between the wait and the draw)
3346 radv_emit_compute_pipeline(cmd_buffer);
3347 si_emit_cache_flush(cmd_buffer);
3348 /* <-- CUs are idle here --> */
3350 radv_upload_compute_shader_descriptors(cmd_buffer);
3352 radv_emit_dispatch_packets(cmd_buffer, info);
3353 /* <-- CUs are busy here --> */
3355 /* Start prefetches after the dispatch has been started. Both
3356 * will run in parallel, but starting the dispatch first is
3359 if (pipeline_is_dirty) {
3360 radv_emit_shader_prefetch(cmd_buffer,
3361 pipeline->shaders[MESA_SHADER_COMPUTE]);
3364 /* If we don't wait for idle, start prefetches first, then set
3365 * states, and dispatch at the end.
3367 si_emit_cache_flush(cmd_buffer);
3369 if (pipeline_is_dirty) {
3370 radv_emit_shader_prefetch(cmd_buffer,
3371 pipeline->shaders[MESA_SHADER_COMPUTE]);
3374 radv_upload_compute_shader_descriptors(cmd_buffer);
3376 radv_emit_compute_pipeline(cmd_buffer);
3377 radv_emit_dispatch_packets(cmd_buffer, info);
3380 radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3383 void radv_CmdDispatch(
3384 VkCommandBuffer commandBuffer,
3389 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3390 struct radv_dispatch_info info = {};
3396 radv_dispatch(cmd_buffer, &info);
3399 void radv_CmdDispatchIndirect(
3400 VkCommandBuffer commandBuffer,
3402 VkDeviceSize offset)
3404 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3405 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3406 struct radv_dispatch_info info = {};
3408 info.indirect = buffer;
3409 info.indirect_offset = offset;
3411 radv_dispatch(cmd_buffer, &info);
3414 void radv_unaligned_dispatch(
3415 struct radv_cmd_buffer *cmd_buffer,
3420 struct radv_dispatch_info info = {};
3427 radv_dispatch(cmd_buffer, &info);
3430 void radv_CmdEndRenderPass(
3431 VkCommandBuffer commandBuffer)
3433 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3435 radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3437 radv_cmd_buffer_resolve_subpass(cmd_buffer);
3439 for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3440 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3441 radv_handle_subpass_image_transition(cmd_buffer,
3442 (VkAttachmentReference){i, layout});
3445 vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3447 cmd_buffer->state.pass = NULL;
3448 cmd_buffer->state.subpass = NULL;
3449 cmd_buffer->state.attachments = NULL;
3450 cmd_buffer->state.framebuffer = NULL;
3454 * For HTILE we have the following interesting clear words:
3455 * 0x0000030f: Uncompressed for depth+stencil HTILE.
3456 * 0x0000000f: Uncompressed for depth only HTILE.
3457 * 0xfffffff0: Clear depth to 1.0
3458 * 0x00000000: Clear depth to 0.0
3460 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3461 struct radv_image *image,
3462 const VkImageSubresourceRange *range,
3463 uint32_t clear_word)
3465 assert(range->baseMipLevel == 0);
3466 assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3467 unsigned layer_count = radv_get_layerCount(image, range);
3468 uint64_t size = image->surface.htile_slice_size * layer_count;
3469 uint64_t offset = image->offset + image->htile_offset +
3470 image->surface.htile_slice_size * range->baseArrayLayer;
3471 struct radv_cmd_state *state = &cmd_buffer->state;
3473 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3474 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3476 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3479 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3482 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3483 struct radv_image *image,
3484 VkImageLayout src_layout,
3485 VkImageLayout dst_layout,
3486 unsigned src_queue_mask,
3487 unsigned dst_queue_mask,
3488 const VkImageSubresourceRange *range,
3489 VkImageAspectFlags pending_clears)
3491 if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3492 (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3493 cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3494 cmd_buffer->state.render_area.extent.width == image->info.width &&
3495 cmd_buffer->state.render_area.extent.height == image->info.height) {
3496 /* The clear will initialize htile. */
3498 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3499 radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3500 /* TODO: merge with the clear if applicable */
3501 radv_initialize_htile(cmd_buffer, image, range, 0);
3502 } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3503 radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3504 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0x30f : 0xf;
3505 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3506 } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3507 !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3508 VkImageSubresourceRange local_range = *range;
3509 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3510 local_range.baseMipLevel = 0;
3511 local_range.levelCount = 1;
3513 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3514 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3516 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3518 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3519 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3523 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3524 struct radv_image *image, uint32_t value)
3526 struct radv_cmd_state *state = &cmd_buffer->state;
3528 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3529 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3531 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3532 image->offset + image->cmask.offset,
3533 image->cmask.size, value);
3535 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3538 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3539 struct radv_image *image,
3540 VkImageLayout src_layout,
3541 VkImageLayout dst_layout,
3542 unsigned src_queue_mask,
3543 unsigned dst_queue_mask,
3544 const VkImageSubresourceRange *range)
3546 if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3547 if (image->fmask.size)
3548 radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3550 radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3551 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3552 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3553 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3557 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3558 struct radv_image *image, uint32_t value)
3560 struct radv_cmd_state *state = &cmd_buffer->state;
3562 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3563 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3565 state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3566 image->offset + image->dcc_offset,
3567 image->surface.dcc_size, value);
3569 state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3570 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3573 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3574 struct radv_image *image,
3575 VkImageLayout src_layout,
3576 VkImageLayout dst_layout,
3577 unsigned src_queue_mask,
3578 unsigned dst_queue_mask,
3579 const VkImageSubresourceRange *range)
3581 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
3582 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
3583 } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3584 radv_initialize_dcc(cmd_buffer, image,
3585 radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask) ?
3586 0x20202020u : 0xffffffffu);
3587 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
3588 !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
3589 radv_decompress_dcc(cmd_buffer, image, range);
3590 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3591 !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3592 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3596 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3597 struct radv_image *image,
3598 VkImageLayout src_layout,
3599 VkImageLayout dst_layout,
3600 uint32_t src_family,
3601 uint32_t dst_family,
3602 const VkImageSubresourceRange *range,
3603 VkImageAspectFlags pending_clears)
3605 if (image->exclusive && src_family != dst_family) {
3606 /* This is an acquire or a release operation and there will be
3607 * a corresponding release/acquire. Do the transition in the
3608 * most flexible queue. */
3610 assert(src_family == cmd_buffer->queue_family_index ||
3611 dst_family == cmd_buffer->queue_family_index);
3613 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3616 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3617 (src_family == RADV_QUEUE_GENERAL ||
3618 dst_family == RADV_QUEUE_GENERAL))
3622 unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3623 unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3625 if (image->surface.htile_size)
3626 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3627 dst_layout, src_queue_mask,
3628 dst_queue_mask, range,
3631 if (image->cmask.size || image->fmask.size)
3632 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3633 dst_layout, src_queue_mask,
3634 dst_queue_mask, range);
3636 if (image->surface.dcc_size)
3637 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3638 dst_layout, src_queue_mask,
3639 dst_queue_mask, range);
3642 void radv_CmdPipelineBarrier(
3643 VkCommandBuffer commandBuffer,
3644 VkPipelineStageFlags srcStageMask,
3645 VkPipelineStageFlags destStageMask,
3647 uint32_t memoryBarrierCount,
3648 const VkMemoryBarrier* pMemoryBarriers,
3649 uint32_t bufferMemoryBarrierCount,
3650 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3651 uint32_t imageMemoryBarrierCount,
3652 const VkImageMemoryBarrier* pImageMemoryBarriers)
3654 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3655 enum radv_cmd_flush_bits src_flush_bits = 0;
3656 enum radv_cmd_flush_bits dst_flush_bits = 0;
3658 for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3659 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3660 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3664 for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3665 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3666 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3670 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3671 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3672 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3673 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3677 radv_stage_flush(cmd_buffer, srcStageMask);
3678 cmd_buffer->state.flush_bits |= src_flush_bits;
3680 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3681 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3682 radv_handle_image_transition(cmd_buffer, image,
3683 pImageMemoryBarriers[i].oldLayout,
3684 pImageMemoryBarriers[i].newLayout,
3685 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3686 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3687 &pImageMemoryBarriers[i].subresourceRange,
3691 cmd_buffer->state.flush_bits |= dst_flush_bits;
3695 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3696 struct radv_event *event,
3697 VkPipelineStageFlags stageMask,
3700 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3701 uint64_t va = radv_buffer_get_va(event->bo);
3703 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3705 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3707 /* TODO: this is overkill. Probably should figure something out from
3708 * the stage mask. */
3710 si_cs_emit_write_event_eop(cs,
3711 cmd_buffer->state.predicating,
3712 cmd_buffer->device->physical_device->rad_info.chip_class,
3713 radv_cmd_buffer_uses_mec(cmd_buffer),
3714 V_028A90_BOTTOM_OF_PIPE_TS, 0,
3717 assert(cmd_buffer->cs->cdw <= cdw_max);
3720 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3722 VkPipelineStageFlags stageMask)
3724 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3725 RADV_FROM_HANDLE(radv_event, event, _event);
3727 write_event(cmd_buffer, event, stageMask, 1);
3730 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3732 VkPipelineStageFlags stageMask)
3734 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3735 RADV_FROM_HANDLE(radv_event, event, _event);
3737 write_event(cmd_buffer, event, stageMask, 0);
3740 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3741 uint32_t eventCount,
3742 const VkEvent* pEvents,
3743 VkPipelineStageFlags srcStageMask,
3744 VkPipelineStageFlags dstStageMask,
3745 uint32_t memoryBarrierCount,
3746 const VkMemoryBarrier* pMemoryBarriers,
3747 uint32_t bufferMemoryBarrierCount,
3748 const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3749 uint32_t imageMemoryBarrierCount,
3750 const VkImageMemoryBarrier* pImageMemoryBarriers)
3752 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3753 struct radeon_winsys_cs *cs = cmd_buffer->cs;
3755 for (unsigned i = 0; i < eventCount; ++i) {
3756 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3757 uint64_t va = radv_buffer_get_va(event->bo);
3759 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3761 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3763 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3764 assert(cmd_buffer->cs->cdw <= cdw_max);
3768 for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3769 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3771 radv_handle_image_transition(cmd_buffer, image,
3772 pImageMemoryBarriers[i].oldLayout,
3773 pImageMemoryBarriers[i].newLayout,
3774 pImageMemoryBarriers[i].srcQueueFamilyIndex,
3775 pImageMemoryBarriers[i].dstQueueFamilyIndex,
3776 &pImageMemoryBarriers[i].subresourceRange,
3780 /* TODO: figure out how to do memory barriers without waiting */
3781 cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3782 RADV_CMD_FLAG_INV_GLOBAL_L2 |
3783 RADV_CMD_FLAG_INV_VMEM_L1 |
3784 RADV_CMD_FLAG_INV_SMEM_L1;