src/amd/vulkan/radv_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "radv_private.h"
  29 #include "radv_radeon_winsys.h"
  30 #include "radv_shader.h"
  31 #include "radv_cs.h"
  32 #include "sid.h"
  33 #include "gfx9d.h"
  34 #include "vk_format.h"
  35 #include "radv_debug.h"
  36 #include "radv_meta.h"
  37
  38 #include "ac_debug.h"
  39
  40 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
  41                                          struct radv_image *image,
  42                                          VkImageLayout src_layout,
  43                                          VkImageLayout dst_layout,
  44                                          uint32_t src_family,
  45                                          uint32_t dst_family,
  46                                          const VkImageSubresourceRange *range,
  47                                          VkImageAspectFlags pending_clears);
  48
  49 const struct radv_dynamic_state default_dynamic_state = {
  50         .viewport = {
  51                 .count = 0,
  52         },
  53         .scissor = {
  54                 .count = 0,
  55         },
  56         .line_width = 1.0f,
  57         .depth_bias = {
  58                 .bias = 0.0f,
  59                 .clamp = 0.0f,
  60                 .slope = 0.0f,
  61         },
  62         .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
  63         .depth_bounds = {
  64                 .min = 0.0f,
  65                 .max = 1.0f,
  66         },
  67         .stencil_compare_mask = {
  68                 .front = ~0u,
  69                 .back = ~0u,
  70         },
  71         .stencil_write_mask = {
  72                 .front = ~0u,
  73                 .back = ~0u,
  74         },
  75         .stencil_reference = {
  76                 .front = 0u,
  77                 .back = 0u,
  78         },
  79 };
  80
  81 static void
  82 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
  83                         const struct radv_dynamic_state *src)
  84 {
  85         struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
  86         uint32_t copy_mask = src->mask;
  87         uint32_t dest_mask = 0;
  88
  89         /* Make sure to copy the number of viewports/scissors because they can
  90          * only be specified at pipeline creation time.
  91          */
  92         dest->viewport.count = src->viewport.count;
  93         dest->scissor.count = src->scissor.count;
  94         dest->discard_rectangle.count = src->discard_rectangle.count;
  95
  96         if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
  97                 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
  98                            src->viewport.count * sizeof(VkViewport))) {
  99                         typed_memcpy(dest->viewport.viewports,
 100                                      src->viewport.viewports,
 101                                      src->viewport.count);
 102                         dest_mask |= RADV_DYNAMIC_VIEWPORT;
 103                 }
 104         }
 105
 106         if (copy_mask & RADV_DYNAMIC_SCISSOR) {
 107                 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
 108                            src->scissor.count * sizeof(VkRect2D))) {
 109                         typed_memcpy(dest->scissor.scissors,
 110                                      src->scissor.scissors, src->scissor.count);
 111                         dest_mask |= RADV_DYNAMIC_SCISSOR;
 112                 }
 113         }
 114
 115         if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
 116                 if (dest->line_width != src->line_width) {
 117                         dest->line_width = src->line_width;
 118                         dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
 119                 }
 120         }
 121
 122         if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
 123                 if (memcmp(&dest->depth_bias, &src->depth_bias,
 124                            sizeof(src->depth_bias))) {
 125                         dest->depth_bias = src->depth_bias;
 126                         dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
 127                 }
 128         }
 129
 130         if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
 131                 if (memcmp(&dest->blend_constants, &src->blend_constants,
 132                            sizeof(src->blend_constants))) {
 133                         typed_memcpy(dest->blend_constants,
 134                                      src->blend_constants, 4);
 135                         dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
 136                 }
 137         }
 138
 139         if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
 140                 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
 141                            sizeof(src->depth_bounds))) {
 142                         dest->depth_bounds = src->depth_bounds;
 143                         dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
 144                 }
 145         }
 146
 147         if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
 148                 if (memcmp(&dest->stencil_compare_mask,
 149                            &src->stencil_compare_mask,
 150                            sizeof(src->stencil_compare_mask))) {
 151                         dest->stencil_compare_mask = src->stencil_compare_mask;
 152                         dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
 153                 }
 154         }
 155
 156         if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
 157                 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
 158                            sizeof(src->stencil_write_mask))) {
 159                         dest->stencil_write_mask = src->stencil_write_mask;
 160                         dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
 161                 }
 162         }
 163
 164         if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
 165                 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
 166                            sizeof(src->stencil_reference))) {
 167                         dest->stencil_reference = src->stencil_reference;
 168                         dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
 169                 }
 170         }
 171
 172         if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
 173                 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
 174                            src->discard_rectangle.count * sizeof(VkRect2D))) {
 175                         typed_memcpy(dest->discard_rectangle.rectangles,
 176                                      src->discard_rectangle.rectangles,
 177                                      src->discard_rectangle.count);
 178                         dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
 179                 }
 180         }
 181
 182         cmd_buffer->state.dirty |= dest_mask;
 183 }
 184
 185 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
 186 {
 187         return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
 188                cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
 189 }
 190
 191 enum ring_type radv_queue_family_to_ring(int f) {
 192         switch (f) {
 193         case RADV_QUEUE_GENERAL:
 194                 return RING_GFX;
 195         case RADV_QUEUE_COMPUTE:
 196                 return RING_COMPUTE;
 197         case RADV_QUEUE_TRANSFER:
 198                 return RING_DMA;
 199         default:
 200                 unreachable("Unknown queue family");
 201         }
 202 }
 203
 204 static VkResult radv_create_cmd_buffer(
 205         struct radv_device *                         device,
 206         struct radv_cmd_pool *                       pool,
 207         VkCommandBufferLevel                        level,
 208         VkCommandBuffer*                            pCommandBuffer)
 209 {
 210         struct radv_cmd_buffer *cmd_buffer;
 211         unsigned ring;
 212         cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
 213                                VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 214         if (cmd_buffer == NULL)
 215                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 216
 217         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
 218         cmd_buffer->device = device;
 219         cmd_buffer->pool = pool;
 220         cmd_buffer->level = level;
 221
 222         if (pool) {
 223                 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
 224                 cmd_buffer->queue_family_index = pool->queue_family_index;
 225
 226         } else {
 227                 /* Init the pool_link so we can safefly call list_del when we destroy
 228                  * the command buffer
 229                  */
 230                 list_inithead(&cmd_buffer->pool_link);
 231                 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
 232         }
 233
 234         ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
 235
 236         cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
 237         if (!cmd_buffer->cs) {
 238                 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 239                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 240         }
 241
 242         *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
 243
 244         list_inithead(&cmd_buffer->upload.list);
 245
 246         return VK_SUCCESS;
 247 }
 248
 249 static void
 250 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
 251 {
 252         list_del(&cmd_buffer->pool_link);
 253
 254         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 255                                  &cmd_buffer->upload.list, list) {
 256                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 257                 list_del(&up->list);
 258                 free(up);
 259         }
 260
 261         if (cmd_buffer->upload.upload_bo)
 262                 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
 263         cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
 264         free(cmd_buffer->push_descriptors.set.mapped_ptr);
 265         vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 266 }
 267
 268 static VkResult
 269 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 270 {
 271
 272         cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
 273
 274         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 275                                  &cmd_buffer->upload.list, list) {
 276                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 277                 list_del(&up->list);
 278                 free(up);
 279         }
 280
 281         cmd_buffer->push_constant_stages = 0;
 282         cmd_buffer->scratch_size_needed = 0;
 283         cmd_buffer->compute_scratch_size_needed = 0;
 284         cmd_buffer->esgs_ring_size_needed = 0;
 285         cmd_buffer->gsvs_ring_size_needed = 0;
 286         cmd_buffer->tess_rings_needed = false;
 287         cmd_buffer->sample_positions_needed = false;
 288
 289         if (cmd_buffer->upload.upload_bo)
 290                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 291                                    cmd_buffer->upload.upload_bo, 8);
 292         cmd_buffer->upload.offset = 0;
 293
 294         cmd_buffer->record_result = VK_SUCCESS;
 295
 296         cmd_buffer->ring_offsets_idx = -1;
 297
 298         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 299                 void *fence_ptr;
 300                 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
 301                                              &cmd_buffer->gfx9_fence_offset,
 302                                              &fence_ptr);
 303                 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
 304         }
 305
 306         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
 307
 308         return cmd_buffer->record_result;
 309 }
 310
 311 static bool
 312 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
 313                                   uint64_t min_needed)
 314 {
 315         uint64_t new_size;
 316         struct radeon_winsys_bo *bo;
 317         struct radv_cmd_buffer_upload *upload;
 318         struct radv_device *device = cmd_buffer->device;
 319
 320         new_size = MAX2(min_needed, 16 * 1024);
 321         new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
 322
 323         bo = device->ws->buffer_create(device->ws,
 324                                        new_size, 4096,
 325                                        RADEON_DOMAIN_GTT,
 326                                        RADEON_FLAG_CPU_ACCESS|
 327                                        RADEON_FLAG_NO_INTERPROCESS_SHARING);
 328
 329         if (!bo) {
 330                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 331                 return false;
 332         }
 333
 334         radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
 335         if (cmd_buffer->upload.upload_bo) {
 336                 upload = malloc(sizeof(*upload));
 337
 338                 if (!upload) {
 339                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
 340                         device->ws->buffer_destroy(bo);
 341                         return false;
 342                 }
 343
 344                 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
 345                 list_add(&upload->list, &cmd_buffer->upload.list);
 346         }
 347
 348         cmd_buffer->upload.upload_bo = bo;
 349         cmd_buffer->upload.size = new_size;
 350         cmd_buffer->upload.offset = 0;
 351         cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
 352
 353         if (!cmd_buffer->upload.map) {
 354                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 355                 return false;
 356         }
 357
 358         return true;
 359 }
 360
 361 bool
 362 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
 363                              unsigned size,
 364                              unsigned alignment,
 365                              unsigned *out_offset,
 366                              void **ptr)
 367 {
 368         uint64_t offset = align(cmd_buffer->upload.offset, alignment);
 369         if (offset + size > cmd_buffer->upload.size) {
 370                 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
 371                         return false;
 372                 offset = 0;
 373         }
 374
 375         *out_offset = offset;
 376         *ptr = cmd_buffer->upload.map + offset;
 377
 378         cmd_buffer->upload.offset = offset + size;
 379         return true;
 380 }
 381
 382 bool
 383 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
 384                             unsigned size, unsigned alignment,
 385                             const void *data, unsigned *out_offset)
 386 {
 387         uint8_t *ptr;
 388
 389         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
 390                                           out_offset, (void **)&ptr))
 391                 return false;
 392
 393         if (ptr)
 394                 memcpy(ptr, data, size);
 395
 396         return true;
 397 }
 398
 399 static void
 400 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
 401                             unsigned count, const uint32_t *data)
 402 {
 403         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
 404         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
 405                     S_370_WR_CONFIRM(1) |
 406                     S_370_ENGINE_SEL(V_370_ME));
 407         radeon_emit(cs, va);
 408         radeon_emit(cs, va >> 32);
 409         radeon_emit_array(cs, data, count);
 410 }
 411
 412 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
 413 {
 414         struct radv_device *device = cmd_buffer->device;
 415         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 416         uint64_t va;
 417
 418         va = radv_buffer_get_va(device->trace_bo);
 419         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
 420                 va += 4;
 421
 422         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
 423
 424         ++cmd_buffer->state.trace_id;
 425         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 426         radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
 427         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
 428         radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
 429 }
 430
 431 static void
 432 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
 433 {
 434         if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
 435                 enum radv_cmd_flush_bits flags;
 436
 437                 /* Force wait for graphics/compute engines to be idle. */
 438                 flags = RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
 439                         RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
 440
 441                 si_cs_emit_cache_flush(cmd_buffer->cs, false,
 442                                        cmd_buffer->device->physical_device->rad_info.chip_class,
 443                                        NULL, 0,
 444                                        radv_cmd_buffer_uses_mec(cmd_buffer),
 445                                        flags);
 446         }
 447
 448         if (unlikely(cmd_buffer->device->trace_bo))
 449                 radv_cmd_buffer_trace_emit(cmd_buffer);
 450 }
 451
 452 static void
 453 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
 454                    struct radv_pipeline *pipeline, enum ring_type ring)
 455 {
 456         struct radv_device *device = cmd_buffer->device;
 457         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 458         uint32_t data[2];
 459         uint64_t va;
 460
 461         va = radv_buffer_get_va(device->trace_bo);
 462
 463         switch (ring) {
 464         case RING_GFX:
 465                 va += 8;
 466                 break;
 467         case RING_COMPUTE:
 468                 va += 16;
 469                 break;
 470         default:
 471                 assert(!"invalid ring type");
 472         }
 473
 474         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 475                                                            cmd_buffer->cs, 6);
 476
 477         data[0] = (uintptr_t)pipeline;
 478         data[1] = (uintptr_t)pipeline >> 32;
 479
 480         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 481         radv_emit_write_data_packet(cs, va, 2, data);
 482 }
 483
 484 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 485                              struct radv_descriptor_set *set,
 486                              unsigned idx)
 487 {
 488         cmd_buffer->descriptors[idx] = set;
 489         if (set)
 490                 cmd_buffer->state.valid_descriptors |= (1u << idx);
 491         else
 492                 cmd_buffer->state.valid_descriptors &= ~(1u << idx);
 493         cmd_buffer->state.descriptors_dirty |= (1u << idx);
 494
 495 }
 496
 497 static void
 498 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer)
 499 {
 500         struct radv_device *device = cmd_buffer->device;
 501         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 502         uint32_t data[MAX_SETS * 2] = {};
 503         uint64_t va;
 504         unsigned i;
 505         va = radv_buffer_get_va(device->trace_bo) + 24;
 506
 507         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 508                                                            cmd_buffer->cs, 4 + MAX_SETS * 2);
 509
 510         for_each_bit(i, cmd_buffer->state.valid_descriptors) {
 511                 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
 512                 data[i * 2] = (uintptr_t)set;
 513                 data[i * 2 + 1] = (uintptr_t)set >> 32;
 514         }
 515
 516         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 517         radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
 518 }
 519
 520 static void
 521 radv_emit_graphics_blend_state(struct radv_cmd_buffer *cmd_buffer,
 522                                struct radv_pipeline *pipeline)
 523 {
 524         radeon_set_context_reg_seq(cmd_buffer->cs, R_028780_CB_BLEND0_CONTROL, 8);
 525         radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.cb_blend_control,
 526                           8);
 527         radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_color_control);
 528         radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alpha_to_mask);
 529
 530         if (cmd_buffer->device->physical_device->has_rbplus) {
 531
 532                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028760_SX_MRT0_BLEND_OPT, 8);
 533                 radeon_emit_array(cmd_buffer->cs, pipeline->graphics.blend.sx_mrt_blend_opt, 8);
 534
 535                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
 536                 radeon_emit(cmd_buffer->cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
 537                 radeon_emit(cmd_buffer->cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
 538                 radeon_emit(cmd_buffer->cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
 539         }
 540 }
 541
 542 static void
 543 radv_emit_graphics_depth_stencil_state(struct radv_cmd_buffer *cmd_buffer,
 544                                        struct radv_pipeline *pipeline)
 545 {
 546         struct radv_depth_stencil_state *ds = &pipeline->graphics.ds;
 547         radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control);
 548         radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control);
 549
 550         radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control);
 551         radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2);
 552 }
 553
 554 struct ac_userdata_info *
 555 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
 556                       gl_shader_stage stage,
 557                       int idx)
 558 {
 559         if (stage == MESA_SHADER_VERTEX) {
 560                 if (pipeline->shaders[MESA_SHADER_VERTEX])
 561                         return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
 562                 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
 563                         return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
 564                 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
 565                         return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
 566         } else if (stage == MESA_SHADER_TESS_EVAL) {
 567                 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
 568                         return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
 569                 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
 570                         return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
 571         }
 572         return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
 573 }
 574
 575 static void
 576 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
 577                            struct radv_pipeline *pipeline,
 578                            gl_shader_stage stage,
 579                            int idx, uint64_t va)
 580 {
 581         struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
 582         uint32_t base_reg = pipeline->user_data_0[stage];
 583         if (loc->sgpr_idx == -1)
 584                 return;
 585         assert(loc->num_sgprs == 2);
 586         assert(!loc->indirect);
 587         radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
 588         radeon_emit(cmd_buffer->cs, va);
 589         radeon_emit(cmd_buffer->cs, va >> 32);
 590 }
 591
 592 static void
 593 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
 594                               struct radv_pipeline *pipeline)
 595 {
 596         int num_samples = pipeline->graphics.ms.num_samples;
 597         struct radv_multisample_state *ms = &pipeline->graphics.ms;
 598         struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
 599
 600         radeon_set_context_reg_seq(cmd_buffer->cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
 601         radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
 602         radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
 603
 604         radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
 605         radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
 606
 607         if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples &&
 608             old_pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions == pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
 609                 return;
 610
 611         radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
 612         radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
 613         radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
 614
 615         radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
 616
 617         radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
 618
 619         /* GFX9: Flush DFSM when the AA mode changes. */
 620         if (cmd_buffer->device->dfsm_allowed) {
 621                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 622                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
 623         }
 624         if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions) {
 625                 uint32_t offset;
 626                 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_FRAGMENT, AC_UD_PS_SAMPLE_POS_OFFSET);
 627                 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_FRAGMENT];
 628                 if (loc->sgpr_idx == -1)
 629                         return;
 630                 assert(loc->num_sgprs == 1);
 631                 assert(!loc->indirect);
 632                 switch (num_samples) {
 633                 default:
 634                         offset = 0;
 635                         break;
 636                 case 2:
 637                         offset = 1;
 638                         break;
 639                 case 4:
 640                         offset = 3;
 641                         break;
 642                 case 8:
 643                         offset = 7;
 644                         break;
 645                 case 16:
 646                         offset = 15;
 647                         break;
 648                 }
 649
 650                 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset);
 651                 cmd_buffer->sample_positions_needed = true;
 652         }
 653 }
 654
 655 static void
 656 radv_emit_graphics_raster_state(struct radv_cmd_buffer *cmd_buffer,
 657                                 struct radv_pipeline *pipeline)
 658 {
 659         struct radv_raster_state *raster = &pipeline->graphics.raster;
 660
 661         radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL,
 662                                raster->pa_cl_clip_cntl);
 663         radeon_set_context_reg(cmd_buffer->cs, R_0286D4_SPI_INTERP_CONTROL_0,
 664                                raster->spi_interp_control);
 665         radeon_set_context_reg(cmd_buffer->cs, R_028BE4_PA_SU_VTX_CNTL,
 666                                raster->pa_su_vtx_cntl);
 667         radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL,
 668                                raster->pa_su_sc_mode_cntl);
 669 }
 670
 671 static inline void
 672 radv_emit_prefetch_TC_L2_async(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
 673                                unsigned size)
 674 {
 675         if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
 676                 si_cp_dma_prefetch(cmd_buffer, va, size);
 677 }
 678
 679 static void
 680 radv_emit_VBO_descriptors_prefetch(struct radv_cmd_buffer *cmd_buffer)
 681 {
 682         if (cmd_buffer->state.vb_prefetch_dirty) {
 683                 radv_emit_prefetch_TC_L2_async(cmd_buffer,
 684                                                cmd_buffer->state.vb_va,
 685                                                cmd_buffer->state.vb_size);
 686                 cmd_buffer->state.vb_prefetch_dirty = false;
 687         }
 688 }
 689
 690 static void
 691 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
 692                           struct radv_shader_variant *shader)
 693 {
 694         struct radeon_winsys *ws = cmd_buffer->device->ws;
 695         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 696         uint64_t va;
 697
 698         if (!shader)
 699                 return;
 700
 701         va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 702
 703         radv_cs_add_buffer(ws, cs, shader->bo, 8);
 704         radv_emit_prefetch_TC_L2_async(cmd_buffer, va, shader->code_size);
 705 }
 706
 707 static void
 708 radv_emit_prefetch(struct radv_cmd_buffer *cmd_buffer,
 709                    struct radv_pipeline *pipeline)
 710 {
 711         radv_emit_shader_prefetch(cmd_buffer,
 712                                   pipeline->shaders[MESA_SHADER_VERTEX]);
 713         radv_emit_VBO_descriptors_prefetch(cmd_buffer);
 714         radv_emit_shader_prefetch(cmd_buffer,
 715                                   pipeline->shaders[MESA_SHADER_TESS_CTRL]);
 716         radv_emit_shader_prefetch(cmd_buffer,
 717                                   pipeline->shaders[MESA_SHADER_TESS_EVAL]);
 718         radv_emit_shader_prefetch(cmd_buffer,
 719                                   pipeline->shaders[MESA_SHADER_GEOMETRY]);
 720         radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
 721         radv_emit_shader_prefetch(cmd_buffer,
 722                                   pipeline->shaders[MESA_SHADER_FRAGMENT]);
 723 }
 724
 725 static void
 726 radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer,
 727                 struct radv_pipeline *pipeline,
 728                 struct radv_shader_variant *shader)
 729 {
 730         uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 731
 732         radeon_set_context_reg(cmd_buffer->cs, R_0286C4_SPI_VS_OUT_CONFIG,
 733                                pipeline->graphics.vs.spi_vs_out_config);
 734
 735         radeon_set_context_reg(cmd_buffer->cs, R_02870C_SPI_SHADER_POS_FORMAT,
 736                                pipeline->graphics.vs.spi_shader_pos_format);
 737
 738         radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
 739         radeon_emit(cmd_buffer->cs, va >> 8);
 740         radeon_emit(cmd_buffer->cs, va >> 40);
 741         radeon_emit(cmd_buffer->cs, shader->rsrc1);
 742         radeon_emit(cmd_buffer->cs, shader->rsrc2);
 743
 744         radeon_set_context_reg(cmd_buffer->cs, R_028818_PA_CL_VTE_CNTL,
 745                                S_028818_VTX_W0_FMT(1) |
 746                                S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
 747                                S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
 748                                S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
 749
 750
 751         radeon_set_context_reg(cmd_buffer->cs, R_02881C_PA_CL_VS_OUT_CNTL,
 752                                pipeline->graphics.vs.pa_cl_vs_out_cntl);
 753
 754         if (cmd_buffer->device->physical_device->rad_info.chip_class <= VI)
 755                 radeon_set_context_reg(cmd_buffer->cs, R_028AB4_VGT_REUSE_OFF,
 756                                        pipeline->graphics.vs.vgt_reuse_off);
 757 }
 758
 759 static void
 760 radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer,
 761                 struct radv_pipeline *pipeline,
 762                 struct radv_shader_variant *shader)
 763 {
 764         uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 765
 766         radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
 767         radeon_emit(cmd_buffer->cs, va >> 8);
 768         radeon_emit(cmd_buffer->cs, va >> 40);
 769         radeon_emit(cmd_buffer->cs, shader->rsrc1);
 770         radeon_emit(cmd_buffer->cs, shader->rsrc2);
 771 }
 772
 773 static void
 774 radv_emit_hw_ls(struct radv_cmd_buffer *cmd_buffer,
 775                 struct radv_shader_variant *shader)
 776 {
 777         uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 778         uint32_t rsrc2 = shader->rsrc2;
 779
 780         radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
 781         radeon_emit(cmd_buffer->cs, va >> 8);
 782         radeon_emit(cmd_buffer->cs, va >> 40);
 783
 784         rsrc2 |= S_00B52C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size);
 785         if (cmd_buffer->device->physical_device->rad_info.chip_class == CIK &&
 786             cmd_buffer->device->physical_device->rad_info.family != CHIP_HAWAII)
 787                 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
 788
 789         radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
 790         radeon_emit(cmd_buffer->cs, shader->rsrc1);
 791         radeon_emit(cmd_buffer->cs, rsrc2);
 792 }
 793
 794 static void
 795 radv_emit_hw_hs(struct radv_cmd_buffer *cmd_buffer,
 796                 struct radv_shader_variant *shader)
 797 {
 798         uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 799
 800         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 801                 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
 802                 radeon_emit(cmd_buffer->cs, va >> 8);
 803                 radeon_emit(cmd_buffer->cs, va >> 40);
 804
 805                 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
 806                 radeon_emit(cmd_buffer->cs, shader->rsrc1);
 807                 radeon_emit(cmd_buffer->cs, shader->rsrc2 |
 808                                             S_00B42C_LDS_SIZE(cmd_buffer->state.pipeline->graphics.tess.lds_size));
 809         } else {
 810                 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
 811                 radeon_emit(cmd_buffer->cs, va >> 8);
 812                 radeon_emit(cmd_buffer->cs, va >> 40);
 813                 radeon_emit(cmd_buffer->cs, shader->rsrc1);
 814                 radeon_emit(cmd_buffer->cs, shader->rsrc2);
 815         }
 816 }
 817
 818 static void
 819 radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer,
 820                         struct radv_pipeline *pipeline)
 821 {
 822         struct radv_shader_variant *vs;
 823
 824         radeon_set_context_reg(cmd_buffer->cs, R_028A84_VGT_PRIMITIVEID_EN, pipeline->graphics.vgt_primitiveid_en);
 825
 826         /* Skip shaders merged into HS/GS */
 827         vs = pipeline->shaders[MESA_SHADER_VERTEX];
 828         if (!vs)
 829                 return;
 830
 831         if (vs->info.vs.as_ls)
 832                 radv_emit_hw_ls(cmd_buffer, vs);
 833         else if (vs->info.vs.as_es)
 834                 radv_emit_hw_es(cmd_buffer, pipeline, vs);
 835         else
 836                 radv_emit_hw_vs(cmd_buffer, pipeline, vs);
 837 }
 838
 839
 840 static void
 841 radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer,
 842                        struct radv_pipeline *pipeline)
 843 {
 844         if (!radv_pipeline_has_tess(pipeline))
 845                 return;
 846
 847         struct radv_shader_variant *tes, *tcs;
 848
 849         tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
 850         tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
 851
 852         if (tes) {
 853                 if (tes->info.tes.as_es)
 854                         radv_emit_hw_es(cmd_buffer, pipeline, tes);
 855                 else
 856                         radv_emit_hw_vs(cmd_buffer, pipeline, tes);
 857         }
 858
 859         radv_emit_hw_hs(cmd_buffer, tcs);
 860
 861         radeon_set_context_reg(cmd_buffer->cs, R_028B6C_VGT_TF_PARAM,
 862                                pipeline->graphics.tess.tf_param);
 863
 864         if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK)
 865                 radeon_set_context_reg_idx(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG, 2,
 866                                            pipeline->graphics.tess.ls_hs_config);
 867         else
 868                 radeon_set_context_reg(cmd_buffer->cs, R_028B58_VGT_LS_HS_CONFIG,
 869                                        pipeline->graphics.tess.ls_hs_config);
 870
 871         struct ac_userdata_info *loc;
 872
 873         loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_CTRL, AC_UD_TCS_OFFCHIP_LAYOUT);
 874         if (loc->sgpr_idx != -1) {
 875                 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_CTRL];
 876                 assert(loc->num_sgprs == 4);
 877                 assert(!loc->indirect);
 878                 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4);
 879                 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.offchip_layout);
 880                 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_offsets);
 881                 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_out_layout |
 882                             pipeline->graphics.tess.num_tcs_input_cp << 26);
 883                 radeon_emit(cmd_buffer->cs, pipeline->graphics.tess.tcs_in_layout);
 884         }
 885
 886         loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_TESS_EVAL, AC_UD_TES_OFFCHIP_LAYOUT);
 887         if (loc->sgpr_idx != -1) {
 888                 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_TESS_EVAL];
 889                 assert(loc->num_sgprs == 1);
 890                 assert(!loc->indirect);
 891
 892                 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
 893                                   pipeline->graphics.tess.offchip_layout);
 894         }
 895
 896         loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT);
 897         if (loc->sgpr_idx != -1) {
 898                 uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX];
 899                 assert(loc->num_sgprs == 1);
 900                 assert(!loc->indirect);
 901
 902                 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
 903                                   pipeline->graphics.tess.tcs_in_layout);
 904         }
 905 }
 906
 907 static void
 908 radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer,
 909                           struct radv_pipeline *pipeline)
 910 {
 911         struct radv_shader_variant *gs;
 912         uint64_t va;
 913
 914         radeon_set_context_reg(cmd_buffer->cs, R_028A40_VGT_GS_MODE, pipeline->graphics.vgt_gs_mode);
 915
 916         gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
 917         if (!gs)
 918                 return;
 919
 920         uint32_t gsvs_itemsize = gs->info.gs.max_gsvs_emit_size >> 2;
 921
 922         radeon_set_context_reg_seq(cmd_buffer->cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
 923         radeon_emit(cmd_buffer->cs, gsvs_itemsize);
 924         radeon_emit(cmd_buffer->cs, gsvs_itemsize);
 925         radeon_emit(cmd_buffer->cs, gsvs_itemsize);
 926
 927         radeon_set_context_reg(cmd_buffer->cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
 928
 929         radeon_set_context_reg(cmd_buffer->cs, R_028B38_VGT_GS_MAX_VERT_OUT, gs->info.gs.vertices_out);
 930
 931         uint32_t gs_vert_itemsize = gs->info.gs.gsvs_vertex_size;
 932         radeon_set_context_reg_seq(cmd_buffer->cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
 933         radeon_emit(cmd_buffer->cs, gs_vert_itemsize >> 2);
 934         radeon_emit(cmd_buffer->cs, 0);
 935         radeon_emit(cmd_buffer->cs, 0);
 936         radeon_emit(cmd_buffer->cs, 0);
 937
 938         uint32_t gs_num_invocations = gs->info.gs.invocations;
 939         radeon_set_context_reg(cmd_buffer->cs, R_028B90_VGT_GS_INSTANCE_CNT,
 940                                S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
 941                                S_028B90_ENABLE(gs_num_invocations > 0));
 942
 943         radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
 944                                pipeline->graphics.gs.vgt_esgs_ring_itemsize);
 945
 946         va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
 947
 948         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 949                 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
 950                 radeon_emit(cmd_buffer->cs, va >> 8);
 951                 radeon_emit(cmd_buffer->cs, va >> 40);
 952
 953                 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
 954                 radeon_emit(cmd_buffer->cs, gs->rsrc1);
 955                 radeon_emit(cmd_buffer->cs, gs->rsrc2 |
 956                                             S_00B22C_LDS_SIZE(pipeline->graphics.gs.lds_size));
 957
 958                 radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl);
 959                 radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup);
 960         } else {
 961                 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
 962                 radeon_emit(cmd_buffer->cs, va >> 8);
 963                 radeon_emit(cmd_buffer->cs, va >> 40);
 964                 radeon_emit(cmd_buffer->cs, gs->rsrc1);
 965                 radeon_emit(cmd_buffer->cs, gs->rsrc2);
 966         }
 967
 968         radv_emit_hw_vs(cmd_buffer, pipeline, pipeline->gs_copy_shader);
 969
 970         struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
 971                                                              AC_UD_GS_VS_RING_STRIDE_ENTRIES);
 972         if (loc->sgpr_idx != -1) {
 973                 uint32_t stride = gs->info.gs.max_gsvs_emit_size;
 974                 uint32_t num_entries = 64;
 975                 bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
 976
 977                 if (is_vi)
 978                         num_entries *= stride;
 979
 980                 stride = S_008F04_STRIDE(stride);
 981                 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B230_SPI_SHADER_USER_DATA_GS_0 + loc->sgpr_idx * 4, 2);
 982                 radeon_emit(cmd_buffer->cs, stride);
 983                 radeon_emit(cmd_buffer->cs, num_entries);
 984         }
 985 }
 986
 987 static void
 988 radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
 989                           struct radv_pipeline *pipeline)
 990 {
 991         struct radv_shader_variant *ps;
 992         uint64_t va;
 993         unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
 994         struct radv_blend_state *blend = &pipeline->graphics.blend;
 995         assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
 996
 997         ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
 998         va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
 999
1000         radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
1001         radeon_emit(cmd_buffer->cs, va >> 8);
1002         radeon_emit(cmd_buffer->cs, va >> 40);
1003         radeon_emit(cmd_buffer->cs, ps->rsrc1);
1004         radeon_emit(cmd_buffer->cs, ps->rsrc2);
1005
1006         radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL,
1007                                pipeline->graphics.db_shader_control);
1008
1009         radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA,
1010                                ps->config.spi_ps_input_ena);
1011
1012         radeon_set_context_reg(cmd_buffer->cs, R_0286D0_SPI_PS_INPUT_ADDR,
1013                                ps->config.spi_ps_input_addr);
1014
1015         if (ps->info.info.ps.force_persample)
1016                 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1017
1018         radeon_set_context_reg(cmd_buffer->cs, R_0286D8_SPI_PS_IN_CONTROL,
1019                                S_0286D8_NUM_INTERP(ps->info.fs.num_interp));
1020
1021         radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1022
1023         radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
1024                                pipeline->graphics.shader_z_format);
1025
1026         radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
1027
1028         radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
1029         radeon_set_context_reg(cmd_buffer->cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
1030
1031         if (cmd_buffer->device->dfsm_allowed) {
1032                 /* optimise this? */
1033                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1034                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
1035         }
1036
1037         if (pipeline->graphics.ps_input_cntl_num) {
1038                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028644_SPI_PS_INPUT_CNTL_0, pipeline->graphics.ps_input_cntl_num);
1039                 for (unsigned i = 0; i < pipeline->graphics.ps_input_cntl_num; i++) {
1040                         radeon_emit(cmd_buffer->cs, pipeline->graphics.ps_input_cntl[i]);
1041                 }
1042         }
1043 }
1044
1045 static void
1046 radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
1047                            struct radv_pipeline *pipeline)
1048 {
1049         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1050
1051         if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
1052                 return;
1053
1054         radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1055                                pipeline->graphics.vtx_reuse_depth);
1056 }
1057
1058 static void
1059 radv_emit_binning_state(struct radv_cmd_buffer *cmd_buffer,
1060                            struct radv_pipeline *pipeline)
1061 {
1062         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1063
1064         if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9)
1065                 return;
1066
1067         radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
1068                                pipeline->graphics.bin.pa_sc_binner_cntl_0);
1069         radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
1070                                pipeline->graphics.bin.db_dfsm_control);
1071 }
1072
1073 static void
1074 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
1075 {
1076         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1077
1078         if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
1079                 return;
1080
1081         radv_emit_graphics_depth_stencil_state(cmd_buffer, pipeline);
1082         radv_emit_graphics_blend_state(cmd_buffer, pipeline);
1083         radv_emit_graphics_raster_state(cmd_buffer, pipeline);
1084         radv_update_multisample_state(cmd_buffer, pipeline);
1085         radv_emit_vertex_shader(cmd_buffer, pipeline);
1086         radv_emit_tess_shaders(cmd_buffer, pipeline);
1087         radv_emit_geometry_shader(cmd_buffer, pipeline);
1088         radv_emit_fragment_shader(cmd_buffer, pipeline);
1089         radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
1090         radv_emit_binning_state(cmd_buffer, pipeline);
1091
1092         cmd_buffer->scratch_size_needed =
1093                                   MAX2(cmd_buffer->scratch_size_needed,
1094                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
1095
1096         radeon_set_context_reg(cmd_buffer->cs, R_0286E8_SPI_TMPRING_SIZE,
1097                                S_0286E8_WAVES(pipeline->max_waves) |
1098                                S_0286E8_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
1099
1100         if (!cmd_buffer->state.emitted_pipeline ||
1101             cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
1102              pipeline->graphics.can_use_guardband)
1103                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
1104
1105         radeon_set_context_reg(cmd_buffer->cs, R_028B54_VGT_SHADER_STAGES_EN, pipeline->graphics.vgt_shader_stages_en);
1106
1107         if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1108                 radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_030908_VGT_PRIMITIVE_TYPE, 1, pipeline->graphics.prim);
1109         } else {
1110                 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, pipeline->graphics.prim);
1111         }
1112         radeon_set_context_reg(cmd_buffer->cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, pipeline->graphics.gs_out);
1113
1114         radeon_set_context_reg(cmd_buffer->cs, R_02820C_PA_SC_CLIPRECT_RULE, pipeline->graphics.pa_sc_cliprect_rule);
1115
1116         if (unlikely(cmd_buffer->device->trace_bo))
1117                 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
1118
1119         cmd_buffer->state.emitted_pipeline = pipeline;
1120
1121         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
1122 }
1123
1124 static void
1125 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
1126 {
1127         si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
1128                           cmd_buffer->state.dynamic.viewport.viewports);
1129 }
1130
1131 static void
1132 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
1133 {
1134         uint32_t count = cmd_buffer->state.dynamic.scissor.count;
1135
1136         /* Vega10/Raven scissor bug workaround. This must be done before VPORT
1137          * scissor registers are changed. There is also a more efficient but
1138          * more involved alternative workaround.
1139          */
1140         if (cmd_buffer->device->physical_device->has_scissor_bug) {
1141                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1142                 si_emit_cache_flush(cmd_buffer);
1143         }
1144         si_write_scissors(cmd_buffer->cs, 0, count,
1145                           cmd_buffer->state.dynamic.scissor.scissors,
1146                           cmd_buffer->state.dynamic.viewport.viewports,
1147                           cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
1148 }
1149
1150 static void
1151 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
1152 {
1153         if (!cmd_buffer->state.dynamic.discard_rectangle.count)
1154                 return;
1155
1156         radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
1157                                    cmd_buffer->state.dynamic.discard_rectangle.count * 2);
1158         for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
1159                 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
1160                 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
1161                 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
1162                                             S_028214_BR_Y(rect.offset.y + rect.extent.height));
1163         }
1164 }
1165
1166 static void
1167 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
1168 {
1169         unsigned width = cmd_buffer->state.dynamic.line_width * 8;
1170
1171         radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
1172                                S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
1173 }
1174
1175 static void
1176 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
1177 {
1178         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1179
1180         radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
1181         radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
1182 }
1183
1184 static void
1185 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
1186 {
1187         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1188
1189         radeon_set_context_reg_seq(cmd_buffer->cs,
1190                                    R_028430_DB_STENCILREFMASK, 2);
1191         radeon_emit(cmd_buffer->cs,
1192                     S_028430_STENCILTESTVAL(d->stencil_reference.front) |
1193                     S_028430_STENCILMASK(d->stencil_compare_mask.front) |
1194                     S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
1195                     S_028430_STENCILOPVAL(1));
1196         radeon_emit(cmd_buffer->cs,
1197                     S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
1198                     S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
1199                     S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
1200                     S_028434_STENCILOPVAL_BF(1));
1201 }
1202
1203 static void
1204 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
1205 {
1206         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1207
1208         radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
1209                                fui(d->depth_bounds.min));
1210         radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
1211                                fui(d->depth_bounds.max));
1212 }
1213
1214 static void
1215 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1216 {
1217         struct radv_raster_state *raster = &cmd_buffer->state.pipeline->graphics.raster;
1218         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1219         unsigned slope = fui(d->depth_bias.slope * 16.0f);
1220         unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1221
1222         if (G_028814_POLY_OFFSET_FRONT_ENABLE(raster->pa_su_sc_mode_cntl)) {
1223                 radeon_set_context_reg_seq(cmd_buffer->cs,
1224                                            R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1225                 radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1226                 radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1227                 radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1228                 radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1229                 radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1230         }
1231 }
1232
1233 static void
1234 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1235                          int index,
1236                          struct radv_attachment_info *att,
1237                          struct radv_image *image,
1238                          VkImageLayout layout)
1239 {
1240         bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1241         struct radv_color_buffer_info *cb = &att->cb;
1242         uint32_t cb_color_info = cb->cb_color_info;
1243
1244         if (!radv_layout_dcc_compressed(image, layout,
1245                                         radv_image_queue_family_mask(image,
1246                                                                      cmd_buffer->queue_family_index,
1247                                                                      cmd_buffer->queue_family_index))) {
1248                 cb_color_info &= C_028C70_DCC_ENABLE;
1249         }
1250
1251         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1252                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1253                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1254                 radeon_emit(cmd_buffer->cs, cb->cb_color_base >> 32);
1255                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1256                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1257                 radeon_emit(cmd_buffer->cs, cb_color_info);
1258                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1259                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1260                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1261                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask >> 32);
1262                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1263                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask >> 32);
1264
1265                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1266                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1267                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base >> 32);
1268
1269                 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1270                                        S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1271         } else {
1272                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1273                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1274                 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1275                 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1276                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1277                 radeon_emit(cmd_buffer->cs, cb_color_info);
1278                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1279                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1280                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1281                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1282                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1283                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1284
1285                 if (is_vi) { /* DCC BASE */
1286                         radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1287                 }
1288         }
1289 }
1290
1291 static void
1292 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1293                       struct radv_ds_buffer_info *ds,
1294                       struct radv_image *image,
1295                       VkImageLayout layout)
1296 {
1297         uint32_t db_z_info = ds->db_z_info;
1298         uint32_t db_stencil_info = ds->db_stencil_info;
1299
1300         if (!radv_layout_has_htile(image, layout,
1301                                    radv_image_queue_family_mask(image,
1302                                                                 cmd_buffer->queue_family_index,
1303                                                                 cmd_buffer->queue_family_index))) {
1304                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1305                 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1306         }
1307
1308         radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1309         radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1310
1311
1312         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1313                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1314                 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1315                 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
1316                 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1317
1318                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1319                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* DB_Z_INFO */
1320                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* DB_STENCIL_INFO */
1321                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* DB_Z_READ_BASE */
1322                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);  /* DB_Z_READ_BASE_HI */
1323                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* DB_STENCIL_READ_BASE */
1324                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32); /* DB_STENCIL_READ_BASE_HI */
1325                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* DB_Z_WRITE_BASE */
1326                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base >> 32); /* DB_Z_WRITE_BASE_HI */
1327                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1328                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
1329
1330                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1331                 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1332                 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1333         } else {
1334                 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1335
1336                 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1337                 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1338                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* R_028040_DB_Z_INFO */
1339                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* R_028044_DB_STENCIL_INFO */
1340                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* R_028048_DB_Z_READ_BASE */
1341                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* R_02804C_DB_STENCIL_READ_BASE */
1342                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* R_028050_DB_Z_WRITE_BASE */
1343                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1344                 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1345                 radeon_emit(cmd_buffer->cs, ds->db_depth_slice);        /* R_02805C_DB_DEPTH_SLICE */
1346
1347         }
1348
1349         radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1350                                ds->pa_su_poly_offset_db_fmt_cntl);
1351 }
1352
1353 void
1354 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1355                           struct radv_image *image,
1356                           VkClearDepthStencilValue ds_clear_value,
1357                           VkImageAspectFlags aspects)
1358 {
1359         uint64_t va = radv_buffer_get_va(image->bo);
1360         va += image->offset + image->clear_value_offset;
1361         unsigned reg_offset = 0, reg_count = 0;
1362
1363         assert(image->surface.htile_size);
1364
1365         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1366                 ++reg_count;
1367         } else {
1368                 ++reg_offset;
1369                 va += 4;
1370         }
1371         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1372                 ++reg_count;
1373
1374         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1375         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1376                                     S_370_WR_CONFIRM(1) |
1377                                     S_370_ENGINE_SEL(V_370_PFP));
1378         radeon_emit(cmd_buffer->cs, va);
1379         radeon_emit(cmd_buffer->cs, va >> 32);
1380         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1381                 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1382         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1383                 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1384
1385         radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1386         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1387                 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1388         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1389                 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1390 }
1391
1392 static void
1393 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1394                            struct radv_image *image)
1395 {
1396         VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1397         uint64_t va = radv_buffer_get_va(image->bo);
1398         va += image->offset + image->clear_value_offset;
1399         unsigned reg_offset = 0, reg_count = 0;
1400
1401         if (!image->surface.htile_size)
1402                 return;
1403
1404         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1405                 ++reg_count;
1406         } else {
1407                 ++reg_offset;
1408                 va += 4;
1409         }
1410         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1411                 ++reg_count;
1412
1413         radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1414         radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1415                                     COPY_DATA_DST_SEL(COPY_DATA_REG) |
1416                                     (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1417         radeon_emit(cmd_buffer->cs, va);
1418         radeon_emit(cmd_buffer->cs, va >> 32);
1419         radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1420         radeon_emit(cmd_buffer->cs, 0);
1421
1422         radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1423         radeon_emit(cmd_buffer->cs, 0);
1424 }
1425
1426 /*
1427  *with DCC some colors don't require CMASK elimiation before being
1428  * used as a texture. This sets a predicate value to determine if the
1429  * cmask eliminate is required.
1430  */
1431 void
1432 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1433                                   struct radv_image *image,
1434                                   bool value)
1435 {
1436         uint64_t pred_val = value;
1437         uint64_t va = radv_buffer_get_va(image->bo);
1438         va += image->offset + image->dcc_pred_offset;
1439
1440         assert(image->surface.dcc_size);
1441
1442         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1443         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1444                                     S_370_WR_CONFIRM(1) |
1445                                     S_370_ENGINE_SEL(V_370_PFP));
1446         radeon_emit(cmd_buffer->cs, va);
1447         radeon_emit(cmd_buffer->cs, va >> 32);
1448         radeon_emit(cmd_buffer->cs, pred_val);
1449         radeon_emit(cmd_buffer->cs, pred_val >> 32);
1450 }
1451
1452 void
1453 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1454                           struct radv_image *image,
1455                           int idx,
1456                           uint32_t color_values[2])
1457 {
1458         uint64_t va = radv_buffer_get_va(image->bo);
1459         va += image->offset + image->clear_value_offset;
1460
1461         assert(image->cmask.size || image->surface.dcc_size);
1462
1463         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1464         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1465                                     S_370_WR_CONFIRM(1) |
1466                                     S_370_ENGINE_SEL(V_370_PFP));
1467         radeon_emit(cmd_buffer->cs, va);
1468         radeon_emit(cmd_buffer->cs, va >> 32);
1469         radeon_emit(cmd_buffer->cs, color_values[0]);
1470         radeon_emit(cmd_buffer->cs, color_values[1]);
1471
1472         radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1473         radeon_emit(cmd_buffer->cs, color_values[0]);
1474         radeon_emit(cmd_buffer->cs, color_values[1]);
1475 }
1476
1477 static void
1478 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1479                            struct radv_image *image,
1480                            int idx)
1481 {
1482         uint64_t va = radv_buffer_get_va(image->bo);
1483         va += image->offset + image->clear_value_offset;
1484
1485         if (!image->cmask.size && !image->surface.dcc_size)
1486                 return;
1487
1488         uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1489
1490         radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1491         radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1492                                     COPY_DATA_DST_SEL(COPY_DATA_REG) |
1493                                     COPY_DATA_COUNT_SEL);
1494         radeon_emit(cmd_buffer->cs, va);
1495         radeon_emit(cmd_buffer->cs, va >> 32);
1496         radeon_emit(cmd_buffer->cs, reg >> 2);
1497         radeon_emit(cmd_buffer->cs, 0);
1498
1499         radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1500         radeon_emit(cmd_buffer->cs, 0);
1501 }
1502
1503 static void
1504 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1505 {
1506         int i;
1507         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1508         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1509
1510         /* this may happen for inherited secondary recording */
1511         if (!framebuffer)
1512                 return;
1513
1514         for (i = 0; i < 8; ++i) {
1515                 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1516                         radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1517                                        S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1518                         continue;
1519                 }
1520
1521                 int idx = subpass->color_attachments[i].attachment;
1522                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1523                 struct radv_image *image = att->attachment->image;
1524                 VkImageLayout layout = subpass->color_attachments[i].layout;
1525
1526                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1527
1528                 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1529                 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1530
1531                 radv_load_color_clear_regs(cmd_buffer, image, i);
1532         }
1533
1534         if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1535                 int idx = subpass->depth_stencil_attachment.attachment;
1536                 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1537                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1538                 struct radv_image *image = att->attachment->image;
1539                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1540                 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1541                                                                                 cmd_buffer->queue_family_index,
1542                                                                                 cmd_buffer->queue_family_index);
1543                 /* We currently don't support writing decompressed HTILE */
1544                 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1545                        radv_layout_is_htile_compressed(image, layout, queue_mask));
1546
1547                 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1548
1549                 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1550                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1551                         cmd_buffer->state.offset_scale = att->ds.offset_scale;
1552                 }
1553                 radv_load_depth_clear_regs(cmd_buffer, image);
1554         } else {
1555                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1556                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1557                 else
1558                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1559
1560                 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1561                 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1562         }
1563         radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1564                                S_028208_BR_X(framebuffer->width) |
1565                                S_028208_BR_Y(framebuffer->height));
1566
1567         if (cmd_buffer->device->dfsm_allowed) {
1568                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1569                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1570         }
1571
1572         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1573 }
1574
1575 static void
1576 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1577 {
1578         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1579         struct radv_cmd_state *state = &cmd_buffer->state;
1580
1581         if (state->index_type != state->last_index_type) {
1582                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1583                         radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1584                                                    2, state->index_type);
1585                 } else {
1586                         radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1587                         radeon_emit(cs, state->index_type);
1588                 }
1589
1590                 state->last_index_type = state->index_type;
1591         }
1592
1593         radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1594         radeon_emit(cs, state->index_va);
1595         radeon_emit(cs, state->index_va >> 32);
1596
1597         radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1598         radeon_emit(cs, state->max_index_count);
1599
1600         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1601 }
1602
1603 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1604 {
1605         uint32_t db_count_control;
1606
1607         if(!cmd_buffer->state.active_occlusion_queries) {
1608                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1609                         db_count_control = 0;
1610                 } else {
1611                         db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1612                 }
1613         } else {
1614                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1615                         db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1616                                 S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
1617                                 S_028004_ZPASS_ENABLE(1) |
1618                                 S_028004_SLICE_EVEN_ENABLE(1) |
1619                                 S_028004_SLICE_ODD_ENABLE(1);
1620                 } else {
1621                         db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1622                                 S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
1623                 }
1624         }
1625
1626         radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1627 }
1628
1629 static void
1630 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1631 {
1632         if (G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.raster.pa_cl_clip_cntl))
1633                 return;
1634
1635         if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1636                 radv_emit_viewport(cmd_buffer);
1637
1638         if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1639                 radv_emit_scissor(cmd_buffer);
1640
1641         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1642                 radv_emit_line_width(cmd_buffer);
1643
1644         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1645                 radv_emit_blend_constants(cmd_buffer);
1646
1647         if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1648                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1649                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1650                 radv_emit_stencil(cmd_buffer);
1651
1652         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1653                 radv_emit_depth_bounds(cmd_buffer);
1654
1655         if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_PIPELINE |
1656                                        RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS))
1657                 radv_emit_depth_bias(cmd_buffer);
1658
1659         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1660                 radv_emit_discard_rectangle(cmd_buffer);
1661
1662         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_ALL;
1663 }
1664
1665 static void
1666 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1667                                    struct radv_pipeline *pipeline,
1668                                    int idx,
1669                                    uint64_t va,
1670                                    gl_shader_stage stage)
1671 {
1672         struct ac_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1673         uint32_t base_reg = pipeline->user_data_0[stage];
1674
1675         if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1676                 return;
1677
1678         assert(!desc_set_loc->indirect);
1679         assert(desc_set_loc->num_sgprs == 2);
1680         radeon_set_sh_reg_seq(cmd_buffer->cs,
1681                               base_reg + desc_set_loc->sgpr_idx * 4, 2);
1682         radeon_emit(cmd_buffer->cs, va);
1683         radeon_emit(cmd_buffer->cs, va >> 32);
1684 }
1685
1686 static void
1687 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1688                                   VkShaderStageFlags stages,
1689                                   struct radv_descriptor_set *set,
1690                                   unsigned idx)
1691 {
1692         if (cmd_buffer->state.pipeline) {
1693                 radv_foreach_stage(stage, stages) {
1694                         if (cmd_buffer->state.pipeline->shaders[stage])
1695                                 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1696                                                                    idx, set->va,
1697                                                                    stage);
1698                 }
1699         }
1700
1701         if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1702                 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1703                                                    idx, set->va,
1704                                                    MESA_SHADER_COMPUTE);
1705 }
1706
1707 static void
1708 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer)
1709 {
1710         struct radv_descriptor_set *set = &cmd_buffer->push_descriptors.set;
1711         unsigned bo_offset;
1712
1713         if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1714                                          set->mapped_ptr,
1715                                          &bo_offset))
1716                 return;
1717
1718         set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1719         set->va += bo_offset;
1720 }
1721
1722 static void
1723 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer)
1724 {
1725         uint32_t size = MAX_SETS * 2 * 4;
1726         uint32_t offset;
1727         void *ptr;
1728
1729         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1730                                           256, &offset, &ptr))
1731                 return;
1732
1733         for (unsigned i = 0; i < MAX_SETS; i++) {
1734                 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1735                 uint64_t set_va = 0;
1736                 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1737                 if (cmd_buffer->state.valid_descriptors & (1u << i))
1738                         set_va = set->va;
1739                 uptr[0] = set_va & 0xffffffff;
1740                 uptr[1] = set_va >> 32;
1741         }
1742
1743         uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1744         va += offset;
1745
1746         if (cmd_buffer->state.pipeline) {
1747                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1748                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1749                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1750
1751                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1752                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1753                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1754
1755                 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1756                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1757                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1758
1759                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1760                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1761                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1762
1763                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1764                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1765                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1766         }
1767
1768         if (cmd_buffer->state.compute_pipeline)
1769                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1770                                            AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1771 }
1772
1773 static void
1774 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1775                        VkShaderStageFlags stages)
1776 {
1777         unsigned i;
1778
1779         if (!cmd_buffer->state.descriptors_dirty)
1780                 return;
1781
1782         if (cmd_buffer->state.push_descriptors_dirty)
1783                 radv_flush_push_descriptors(cmd_buffer);
1784
1785         if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1786             (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1787                 radv_flush_indirect_descriptor_sets(cmd_buffer);
1788         }
1789
1790         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1791                                                            cmd_buffer->cs,
1792                                                            MAX_SETS * MESA_SHADER_STAGES * 4);
1793
1794         for_each_bit(i, cmd_buffer->state.descriptors_dirty) {
1795                 struct radv_descriptor_set *set = cmd_buffer->descriptors[i];
1796                 if (!(cmd_buffer->state.valid_descriptors & (1u << i)))
1797                         continue;
1798
1799                 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1800         }
1801         cmd_buffer->state.descriptors_dirty = 0;
1802         cmd_buffer->state.push_descriptors_dirty = false;
1803
1804         if (unlikely(cmd_buffer->device->trace_bo))
1805                 radv_save_descriptors(cmd_buffer);
1806
1807         assert(cmd_buffer->cs->cdw <= cdw_max);
1808 }
1809
1810 static void
1811 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1812                      struct radv_pipeline *pipeline,
1813                      VkShaderStageFlags stages)
1814 {
1815         struct radv_pipeline_layout *layout = pipeline->layout;
1816         unsigned offset;
1817         void *ptr;
1818         uint64_t va;
1819
1820         stages &= cmd_buffer->push_constant_stages;
1821         if (!stages ||
1822             (!layout->push_constant_size && !layout->dynamic_offset_count))
1823                 return;
1824
1825         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1826                                           16 * layout->dynamic_offset_count,
1827                                           256, &offset, &ptr))
1828                 return;
1829
1830         memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1831         memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1832                16 * layout->dynamic_offset_count);
1833
1834         va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1835         va += offset;
1836
1837         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1838                                                            cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1839
1840         radv_foreach_stage(stage, stages) {
1841                 if (pipeline->shaders[stage]) {
1842                         radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1843                                                    AC_UD_PUSH_CONSTANTS, va);
1844                 }
1845         }
1846
1847         cmd_buffer->push_constant_stages &= ~stages;
1848         assert(cmd_buffer->cs->cdw <= cdw_max);
1849 }
1850
1851 static bool
1852 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1853 {
1854         if ((pipeline_is_dirty ||
1855             (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1856             cmd_buffer->state.pipeline->vertex_elements.count &&
1857             radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1858                 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1859                 unsigned vb_offset;
1860                 void *vb_ptr;
1861                 uint32_t i = 0;
1862                 uint32_t count = velems->count;
1863                 uint64_t va;
1864
1865                 /* allocate some descriptor state for vertex buffers */
1866                 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1867                                                   &vb_offset, &vb_ptr))
1868                         return false;
1869
1870                 for (i = 0; i < count; i++) {
1871                         uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1872                         uint32_t offset;
1873                         int vb = velems->binding[i];
1874                         struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1875                         uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1876
1877                         va = radv_buffer_get_va(buffer->bo);
1878
1879                         offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1880                         va += offset + buffer->offset;
1881                         desc[0] = va;
1882                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1883                         if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1884                                 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1885                         else
1886                                 desc[2] = buffer->size - offset;
1887                         desc[3] = velems->rsrc_word3[i];
1888                 }
1889
1890                 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1891                 va += vb_offset;
1892
1893                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1894                                            AC_UD_VS_VERTEX_BUFFERS, va);
1895
1896                 cmd_buffer->state.vb_va = va;
1897                 cmd_buffer->state.vb_size = count * 16;
1898                 cmd_buffer->state.vb_prefetch_dirty = true;
1899         }
1900         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1901
1902         return true;
1903 }
1904
1905 static bool
1906 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1907 {
1908         if (!radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty))
1909                 return false;
1910
1911         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1912         radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1913                              VK_SHADER_STAGE_ALL_GRAPHICS);
1914
1915         return true;
1916 }
1917
1918 static void
1919 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1920                          bool instanced_draw, bool indirect_draw,
1921                          uint32_t draw_vertex_count)
1922 {
1923         struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1924         struct radv_cmd_state *state = &cmd_buffer->state;
1925         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1926         uint32_t ia_multi_vgt_param;
1927         int32_t primitive_reset_en;
1928
1929         /* Draw state. */
1930         ia_multi_vgt_param =
1931                 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1932                                           indirect_draw, draw_vertex_count);
1933
1934         if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1935                 if (info->chip_class >= GFX9) {
1936                         radeon_set_uconfig_reg_idx(cs,
1937                                                    R_030960_IA_MULTI_VGT_PARAM,
1938                                                    4, ia_multi_vgt_param);
1939                 } else if (info->chip_class >= CIK) {
1940                         radeon_set_context_reg_idx(cs,
1941                                                    R_028AA8_IA_MULTI_VGT_PARAM,
1942                                                    1, ia_multi_vgt_param);
1943                 } else {
1944                         radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1945                                                ia_multi_vgt_param);
1946                 }
1947                 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1948         }
1949
1950         /* Primitive restart. */
1951         primitive_reset_en =
1952                 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1953
1954         if (primitive_reset_en != state->last_primitive_reset_en) {
1955                 state->last_primitive_reset_en = primitive_reset_en;
1956                 if (info->chip_class >= GFX9) {
1957                         radeon_set_uconfig_reg(cs,
1958                                                R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1959                                                primitive_reset_en);
1960                 } else {
1961                         radeon_set_context_reg(cs,
1962                                                R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1963                                                primitive_reset_en);
1964                 }
1965         }
1966
1967         if (primitive_reset_en) {
1968                 uint32_t primitive_reset_index =
1969                         state->index_type ? 0xffffffffu : 0xffffu;
1970
1971                 if (primitive_reset_index != state->last_primitive_reset_index) {
1972                         radeon_set_context_reg(cs,
1973                                                R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1974                                                primitive_reset_index);
1975                         state->last_primitive_reset_index = primitive_reset_index;
1976                 }
1977         }
1978 }
1979
1980 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1981                              VkPipelineStageFlags src_stage_mask)
1982 {
1983         if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1984                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1985                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1986                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1987                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1988         }
1989
1990         if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1991                               VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1992                               VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1993                               VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1994                               VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1995                               VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1996                               VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1997                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1998                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1999                               VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2000                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2001                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2002         } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2003                                      VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2004                                      VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
2005                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2006         }
2007 }
2008
2009 static enum radv_cmd_flush_bits
2010 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2011                                   VkAccessFlags src_flags)
2012 {
2013         enum radv_cmd_flush_bits flush_bits = 0;
2014         uint32_t b;
2015         for_each_bit(b, src_flags) {
2016                 switch ((VkAccessFlagBits)(1 << b)) {
2017                 case VK_ACCESS_SHADER_WRITE_BIT:
2018                         flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2019                         break;
2020                 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2021                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2022                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2023                         break;
2024                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2025                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2026                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2027                         break;
2028                 case VK_ACCESS_TRANSFER_WRITE_BIT:
2029                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2030                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
2031                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2032                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
2033                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
2034                         break;
2035                 default:
2036                         break;
2037                 }
2038         }
2039         return flush_bits;
2040 }
2041
2042 static enum radv_cmd_flush_bits
2043 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2044                       VkAccessFlags dst_flags,
2045                       struct radv_image *image)
2046 {
2047         enum radv_cmd_flush_bits flush_bits = 0;
2048         uint32_t b;
2049         for_each_bit(b, dst_flags) {
2050                 switch ((VkAccessFlagBits)(1 << b)) {
2051                 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2052                 case VK_ACCESS_INDEX_READ_BIT:
2053                         break;
2054                 case VK_ACCESS_UNIFORM_READ_BIT:
2055                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2056                         break;
2057                 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2058                 case VK_ACCESS_SHADER_READ_BIT:
2059                 case VK_ACCESS_TRANSFER_READ_BIT:
2060                 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2061                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2062                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
2063                         break;
2064                 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2065                         /* TODO: change to image && when the image gets passed
2066                          * through from the subpass. */
2067                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2068                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2069                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2070                         break;
2071                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2072                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2073                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2074                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2075                         break;
2076                 default:
2077                         break;
2078                 }
2079         }
2080         return flush_bits;
2081 }
2082
2083 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2084 {
2085         cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2086         radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2087         cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2088                                                               NULL);
2089 }
2090
2091 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2092                                                  VkAttachmentReference att)
2093 {
2094         unsigned idx = att.attachment;
2095         struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2096         VkImageSubresourceRange range;
2097         range.aspectMask = 0;
2098         range.baseMipLevel = view->base_mip;
2099         range.levelCount = 1;
2100         range.baseArrayLayer = view->base_layer;
2101         range.layerCount = cmd_buffer->state.framebuffer->layers;
2102
2103         radv_handle_image_transition(cmd_buffer,
2104                                      view->image,
2105                                      cmd_buffer->state.attachments[idx].current_layout,
2106                                      att.layout, 0, 0, &range,
2107                                      cmd_buffer->state.attachments[idx].pending_clear_aspects);
2108
2109         cmd_buffer->state.attachments[idx].current_layout = att.layout;
2110
2111
2112 }
2113
2114 void
2115 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2116                             const struct radv_subpass *subpass, bool transitions)
2117 {
2118         if (transitions) {
2119                 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2120
2121                 for (unsigned i = 0; i < subpass->color_count; ++i) {
2122                         if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2123                                 radv_handle_subpass_image_transition(cmd_buffer,
2124                                                                      subpass->color_attachments[i]);
2125                 }
2126
2127                 for (unsigned i = 0; i < subpass->input_count; ++i) {
2128                         radv_handle_subpass_image_transition(cmd_buffer,
2129                                                         subpass->input_attachments[i]);
2130                 }
2131
2132                 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2133                         radv_handle_subpass_image_transition(cmd_buffer,
2134                                                         subpass->depth_stencil_attachment);
2135                 }
2136         }
2137
2138         cmd_buffer->state.subpass = subpass;
2139
2140         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2141 }
2142
2143 static VkResult
2144 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2145                                  struct radv_render_pass *pass,
2146                                  const VkRenderPassBeginInfo *info)
2147 {
2148         struct radv_cmd_state *state = &cmd_buffer->state;
2149
2150         if (pass->attachment_count == 0) {
2151                 state->attachments = NULL;
2152                 return VK_SUCCESS;
2153         }
2154
2155         state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2156                                         pass->attachment_count *
2157                                         sizeof(state->attachments[0]),
2158                                         8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2159         if (state->attachments == NULL) {
2160                 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2161                 return cmd_buffer->record_result;
2162         }
2163
2164         for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2165                 struct radv_render_pass_attachment *att = &pass->attachments[i];
2166                 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2167                 VkImageAspectFlags clear_aspects = 0;
2168
2169                 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2170                         /* color attachment */
2171                         if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2172                                 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2173                         }
2174                 } else {
2175                         /* depthstencil attachment */
2176                         if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2177                             att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2178                                 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2179                                 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2180                                     att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2181                                         clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2182                         }
2183                         if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2184                             att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2185                                 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2186                         }
2187                 }
2188
2189                 state->attachments[i].pending_clear_aspects = clear_aspects;
2190                 state->attachments[i].cleared_views = 0;
2191                 if (clear_aspects && info) {
2192                         assert(info->clearValueCount > i);
2193                         state->attachments[i].clear_value = info->pClearValues[i];
2194                 }
2195
2196                 state->attachments[i].current_layout = att->initial_layout;
2197         }
2198
2199         return VK_SUCCESS;
2200 }
2201
2202 VkResult radv_AllocateCommandBuffers(
2203         VkDevice _device,
2204         const VkCommandBufferAllocateInfo *pAllocateInfo,
2205         VkCommandBuffer *pCommandBuffers)
2206 {
2207         RADV_FROM_HANDLE(radv_device, device, _device);
2208         RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2209
2210         VkResult result = VK_SUCCESS;
2211         uint32_t i;
2212
2213         for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2214
2215                 if (!list_empty(&pool->free_cmd_buffers)) {
2216                         struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2217
2218                         list_del(&cmd_buffer->pool_link);
2219                         list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2220
2221                         result = radv_reset_cmd_buffer(cmd_buffer);
2222                         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2223                         cmd_buffer->level = pAllocateInfo->level;
2224
2225                         pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2226                 } else {
2227                         result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2228                                                         &pCommandBuffers[i]);
2229                 }
2230                 if (result != VK_SUCCESS)
2231                         break;
2232         }
2233
2234         if (result != VK_SUCCESS) {
2235                 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2236                                         i, pCommandBuffers);
2237
2238                 /* From the Vulkan 1.0.66 spec:
2239                  *
2240                  * "vkAllocateCommandBuffers can be used to create multiple
2241                  *  command buffers. If the creation of any of those command
2242                  *  buffers fails, the implementation must destroy all
2243                  *  successfully created command buffer objects from this
2244                  *  command, set all entries of the pCommandBuffers array to
2245                  *  NULL and return the error."
2246                  */
2247                 memset(pCommandBuffers, 0,
2248                        sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2249         }
2250
2251         return result;
2252 }
2253
2254 void radv_FreeCommandBuffers(
2255         VkDevice device,
2256         VkCommandPool commandPool,
2257         uint32_t commandBufferCount,
2258         const VkCommandBuffer *pCommandBuffers)
2259 {
2260         for (uint32_t i = 0; i < commandBufferCount; i++) {
2261                 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2262
2263                 if (cmd_buffer) {
2264                         if (cmd_buffer->pool) {
2265                                 list_del(&cmd_buffer->pool_link);
2266                                 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2267                         } else
2268                                 radv_cmd_buffer_destroy(cmd_buffer);
2269
2270                 }
2271         }
2272 }
2273
2274 VkResult radv_ResetCommandBuffer(
2275         VkCommandBuffer commandBuffer,
2276         VkCommandBufferResetFlags flags)
2277 {
2278         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2279         return radv_reset_cmd_buffer(cmd_buffer);
2280 }
2281
2282 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2283 {
2284         struct radv_device *device = cmd_buffer->device;
2285         if (device->gfx_init) {
2286                 uint64_t va = radv_buffer_get_va(device->gfx_init);
2287                 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2288                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2289                 radeon_emit(cmd_buffer->cs, va);
2290                 radeon_emit(cmd_buffer->cs, va >> 32);
2291                 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2292         } else
2293                 si_init_config(cmd_buffer);
2294 }
2295
2296 VkResult radv_BeginCommandBuffer(
2297         VkCommandBuffer commandBuffer,
2298         const VkCommandBufferBeginInfo *pBeginInfo)
2299 {
2300         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2301         VkResult result = VK_SUCCESS;
2302
2303         if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2304                 /* If the command buffer has already been resetted with
2305                  * vkResetCommandBuffer, no need to do it again.
2306                  */
2307                 result = radv_reset_cmd_buffer(cmd_buffer);
2308                 if (result != VK_SUCCESS)
2309                         return result;
2310         }
2311
2312         memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2313         cmd_buffer->state.last_primitive_reset_en = -1;
2314         cmd_buffer->state.last_index_type = -1;
2315         cmd_buffer->state.last_num_instances = -1;
2316         cmd_buffer->state.last_vertex_offset = -1;
2317         cmd_buffer->state.last_first_instance = -1;
2318         cmd_buffer->usage_flags = pBeginInfo->flags;
2319
2320         /* setup initial configuration into command buffer */
2321         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2322                 switch (cmd_buffer->queue_family_index) {
2323                 case RADV_QUEUE_GENERAL:
2324                         emit_gfx_buffer_state(cmd_buffer);
2325                         break;
2326                 case RADV_QUEUE_COMPUTE:
2327                         si_init_compute(cmd_buffer);
2328                         break;
2329                 case RADV_QUEUE_TRANSFER:
2330                 default:
2331                         break;
2332                 }
2333         }
2334
2335         if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2336                 assert(pBeginInfo->pInheritanceInfo);
2337                 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2338                 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2339
2340                 struct radv_subpass *subpass =
2341                         &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2342
2343                 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2344                 if (result != VK_SUCCESS)
2345                         return result;
2346
2347                 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2348         }
2349
2350         if (unlikely(cmd_buffer->device->trace_bo))
2351                 radv_cmd_buffer_trace_emit(cmd_buffer);
2352
2353         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2354
2355         return result;
2356 }
2357
2358 void radv_CmdBindVertexBuffers(
2359         VkCommandBuffer                             commandBuffer,
2360         uint32_t                                    firstBinding,
2361         uint32_t                                    bindingCount,
2362         const VkBuffer*                             pBuffers,
2363         const VkDeviceSize*                         pOffsets)
2364 {
2365         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2366         struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2367         bool changed = false;
2368
2369         /* We have to defer setting up vertex buffer since we need the buffer
2370          * stride from the pipeline. */
2371
2372         assert(firstBinding + bindingCount <= MAX_VBS);
2373         for (uint32_t i = 0; i < bindingCount; i++) {
2374                 uint32_t idx = firstBinding + i;
2375
2376                 if (!changed &&
2377                     (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2378                      vb[idx].offset != pOffsets[i])) {
2379                         changed = true;
2380                 }
2381
2382                 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2383                 vb[idx].offset = pOffsets[i];
2384
2385                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2386                                    vb[idx].buffer->bo, 8);
2387         }
2388
2389         if (!changed) {
2390                 /* No state changes. */
2391                 return;
2392         }
2393
2394         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2395 }
2396
2397 void radv_CmdBindIndexBuffer(
2398         VkCommandBuffer                             commandBuffer,
2399         VkBuffer buffer,
2400         VkDeviceSize offset,
2401         VkIndexType indexType)
2402 {
2403         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2404         RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2405
2406         if (cmd_buffer->state.index_buffer == index_buffer &&
2407             cmd_buffer->state.index_offset == offset &&
2408             cmd_buffer->state.index_type == indexType) {
2409                 /* No state changes. */
2410                 return;
2411         }
2412
2413         cmd_buffer->state.index_buffer = index_buffer;
2414         cmd_buffer->state.index_offset = offset;
2415         cmd_buffer->state.index_type = indexType; /* vk matches hw */
2416         cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2417         cmd_buffer->state.index_va += index_buffer->offset + offset;
2418
2419         int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2420         cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2421         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2422         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2423 }
2424
2425
2426 static void
2427 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2428                          struct radv_descriptor_set *set, unsigned idx)
2429 {
2430         struct radeon_winsys *ws = cmd_buffer->device->ws;
2431
2432         radv_set_descriptor_set(cmd_buffer, set, idx);
2433         if (!set)
2434                 return;
2435
2436         assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2437
2438         for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2439                 if (set->descriptors[j])
2440                         radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2441
2442         if(set->bo)
2443                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2444 }
2445
2446 void radv_CmdBindDescriptorSets(
2447         VkCommandBuffer                             commandBuffer,
2448         VkPipelineBindPoint                         pipelineBindPoint,
2449         VkPipelineLayout                            _layout,
2450         uint32_t                                    firstSet,
2451         uint32_t                                    descriptorSetCount,
2452         const VkDescriptorSet*                      pDescriptorSets,
2453         uint32_t                                    dynamicOffsetCount,
2454         const uint32_t*                             pDynamicOffsets)
2455 {
2456         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2457         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2458         unsigned dyn_idx = 0;
2459
2460         for (unsigned i = 0; i < descriptorSetCount; ++i) {
2461                 unsigned idx = i + firstSet;
2462                 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2463                 radv_bind_descriptor_set(cmd_buffer, set, idx);
2464
2465                 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2466                         unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2467                         uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2468                         assert(dyn_idx < dynamicOffsetCount);
2469
2470                         struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2471                         uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2472                         dst[0] = va;
2473                         dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2474                         dst[2] = range->size;
2475                         dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2476                                  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2477                                  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2478                                  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2479                                  S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2480                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2481                         cmd_buffer->push_constant_stages |=
2482                                              set->layout->dynamic_shader_stages;
2483                 }
2484         }
2485 }
2486
2487 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2488                                           struct radv_descriptor_set *set,
2489                                           struct radv_descriptor_set_layout *layout)
2490 {
2491         set->size = layout->size;
2492         set->layout = layout;
2493
2494         if (cmd_buffer->push_descriptors.capacity < set->size) {
2495                 size_t new_size = MAX2(set->size, 1024);
2496                 new_size = MAX2(new_size, 2 * cmd_buffer->push_descriptors.capacity);
2497                 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2498
2499                 free(set->mapped_ptr);
2500                 set->mapped_ptr = malloc(new_size);
2501
2502                 if (!set->mapped_ptr) {
2503                         cmd_buffer->push_descriptors.capacity = 0;
2504                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2505                         return false;
2506                 }
2507
2508                 cmd_buffer->push_descriptors.capacity = new_size;
2509         }
2510
2511         return true;
2512 }
2513
2514 void radv_meta_push_descriptor_set(
2515         struct radv_cmd_buffer*              cmd_buffer,
2516         VkPipelineBindPoint                  pipelineBindPoint,
2517         VkPipelineLayout                     _layout,
2518         uint32_t                             set,
2519         uint32_t                             descriptorWriteCount,
2520         const VkWriteDescriptorSet*          pDescriptorWrites)
2521 {
2522         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2523         struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2524         unsigned bo_offset;
2525
2526         assert(set == 0);
2527         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2528
2529         push_set->size = layout->set[set].layout->size;
2530         push_set->layout = layout->set[set].layout;
2531
2532         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2533                                           &bo_offset,
2534                                           (void**) &push_set->mapped_ptr))
2535                 return;
2536
2537         push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2538         push_set->va += bo_offset;
2539
2540         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2541                                     radv_descriptor_set_to_handle(push_set),
2542                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2543
2544         radv_set_descriptor_set(cmd_buffer, push_set, set);
2545 }
2546
2547 void radv_CmdPushDescriptorSetKHR(
2548         VkCommandBuffer                             commandBuffer,
2549         VkPipelineBindPoint                         pipelineBindPoint,
2550         VkPipelineLayout                            _layout,
2551         uint32_t                                    set,
2552         uint32_t                                    descriptorWriteCount,
2553         const VkWriteDescriptorSet*                 pDescriptorWrites)
2554 {
2555         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2556         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2557         struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2558
2559         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2560
2561         if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2562                 return;
2563
2564         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2565                                     radv_descriptor_set_to_handle(push_set),
2566                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2567
2568         radv_set_descriptor_set(cmd_buffer, push_set, set);
2569         cmd_buffer->state.push_descriptors_dirty = true;
2570 }
2571
2572 void radv_CmdPushDescriptorSetWithTemplateKHR(
2573         VkCommandBuffer                             commandBuffer,
2574         VkDescriptorUpdateTemplateKHR               descriptorUpdateTemplate,
2575         VkPipelineLayout                            _layout,
2576         uint32_t                                    set,
2577         const void*                                 pData)
2578 {
2579         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2580         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2581         struct radv_descriptor_set *push_set = &cmd_buffer->push_descriptors.set;
2582
2583         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2584
2585         if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout))
2586                 return;
2587
2588         radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2589                                                  descriptorUpdateTemplate, pData);
2590
2591         radv_set_descriptor_set(cmd_buffer, push_set, set);
2592         cmd_buffer->state.push_descriptors_dirty = true;
2593 }
2594
2595 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2596                            VkPipelineLayout layout,
2597                            VkShaderStageFlags stageFlags,
2598                            uint32_t offset,
2599                            uint32_t size,
2600                            const void* pValues)
2601 {
2602         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2603         memcpy(cmd_buffer->push_constants + offset, pValues, size);
2604         cmd_buffer->push_constant_stages |= stageFlags;
2605 }
2606
2607 VkResult radv_EndCommandBuffer(
2608         VkCommandBuffer                             commandBuffer)
2609 {
2610         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2611
2612         if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2613                 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2614                         cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2615                 si_emit_cache_flush(cmd_buffer);
2616         }
2617
2618         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2619
2620         if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2621                 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2622
2623         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2624
2625         return cmd_buffer->record_result;
2626 }
2627
2628 static void
2629 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2630 {
2631         struct radv_shader_variant *compute_shader;
2632         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2633         struct radv_device *device = cmd_buffer->device;
2634         unsigned compute_resource_limits;
2635         unsigned waves_per_threadgroup;
2636         uint64_t va;
2637
2638         if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2639                 return;
2640
2641         cmd_buffer->state.emitted_compute_pipeline = pipeline;
2642
2643         compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
2644         va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
2645
2646         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2647                                                            cmd_buffer->cs, 19);
2648
2649         radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B830_COMPUTE_PGM_LO, 2);
2650         radeon_emit(cmd_buffer->cs, va >> 8);
2651         radeon_emit(cmd_buffer->cs, va >> 40);
2652
2653         radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
2654         radeon_emit(cmd_buffer->cs, compute_shader->rsrc1);
2655         radeon_emit(cmd_buffer->cs, compute_shader->rsrc2);
2656
2657
2658         cmd_buffer->compute_scratch_size_needed =
2659                                   MAX2(cmd_buffer->compute_scratch_size_needed,
2660                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2661
2662         /* change these once we have scratch support */
2663         radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE,
2664                           S_00B860_WAVES(pipeline->max_waves) |
2665                           S_00B860_WAVESIZE(pipeline->scratch_bytes_per_wave >> 10));
2666
2667         /* Calculate best compute resource limits. */
2668         waves_per_threadgroup =
2669                 DIV_ROUND_UP(compute_shader->info.cs.block_size[0] *
2670                              compute_shader->info.cs.block_size[1] *
2671                              compute_shader->info.cs.block_size[2], 64);
2672         compute_resource_limits =
2673                 S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
2674
2675         if (device->physical_device->rad_info.chip_class >= CIK) {
2676                 unsigned num_cu_per_se =
2677                         device->physical_device->rad_info.num_good_compute_units /
2678                         device->physical_device->rad_info.max_se;
2679
2680                 /* Force even distribution on all SIMDs in CU if the workgroup
2681                  * size is 64. This has shown some good improvements if # of
2682                  * CUs per SE is not a multiple of 4.
2683                  */
2684                 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
2685                         compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
2686         }
2687
2688         radeon_set_sh_reg(cmd_buffer->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
2689                           compute_resource_limits);
2690
2691         radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
2692         radeon_emit(cmd_buffer->cs,
2693                     S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
2694         radeon_emit(cmd_buffer->cs,
2695                     S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
2696         radeon_emit(cmd_buffer->cs,
2697                     S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
2698
2699         assert(cmd_buffer->cs->cdw <= cdw_max);
2700
2701         if (unlikely(cmd_buffer->device->trace_bo))
2702                 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2703 }
2704
2705 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer)
2706 {
2707         cmd_buffer->state.descriptors_dirty |= cmd_buffer->state.valid_descriptors;
2708 }
2709
2710 void radv_CmdBindPipeline(
2711         VkCommandBuffer                             commandBuffer,
2712         VkPipelineBindPoint                         pipelineBindPoint,
2713         VkPipeline                                  _pipeline)
2714 {
2715         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2716         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2717
2718         switch (pipelineBindPoint) {
2719         case VK_PIPELINE_BIND_POINT_COMPUTE:
2720                 if (cmd_buffer->state.compute_pipeline == pipeline)
2721                         return;
2722                 radv_mark_descriptor_sets_dirty(cmd_buffer);
2723
2724                 cmd_buffer->state.compute_pipeline = pipeline;
2725                 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2726                 break;
2727         case VK_PIPELINE_BIND_POINT_GRAPHICS:
2728                 if (cmd_buffer->state.pipeline == pipeline)
2729                         return;
2730                 radv_mark_descriptor_sets_dirty(cmd_buffer);
2731
2732                 cmd_buffer->state.pipeline = pipeline;
2733                 if (!pipeline)
2734                         break;
2735
2736                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2737                 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2738
2739                 /* the new vertex shader might not have the same user regs */
2740                 cmd_buffer->state.last_first_instance = -1;
2741                 cmd_buffer->state.last_vertex_offset = -1;
2742
2743                 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2744
2745                 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2746                         cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2747                 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2748                         cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2749
2750                 if (radv_pipeline_has_tess(pipeline))
2751                         cmd_buffer->tess_rings_needed = true;
2752
2753                 if (radv_pipeline_has_gs(pipeline)) {
2754                         struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2755                                                                              AC_UD_SCRATCH_RING_OFFSETS);
2756                         if (cmd_buffer->ring_offsets_idx == -1)
2757                                 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2758                         else if (loc->sgpr_idx != -1)
2759                                 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2760                 }
2761                 break;
2762         default:
2763                 assert(!"invalid bind point");
2764                 break;
2765         }
2766 }
2767
2768 void radv_CmdSetViewport(
2769         VkCommandBuffer                             commandBuffer,
2770         uint32_t                                    firstViewport,
2771         uint32_t                                    viewportCount,
2772         const VkViewport*                           pViewports)
2773 {
2774         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2775         struct radv_cmd_state *state = &cmd_buffer->state;
2776         MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2777
2778         assert(firstViewport < MAX_VIEWPORTS);
2779         assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2780
2781         if (cmd_buffer->device->physical_device->has_scissor_bug) {
2782                 /* Try to skip unnecessary PS partial flushes when the viewports
2783                  * don't change.
2784                  */
2785                 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2786                                       RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2787                     !memcmp(state->dynamic.viewport.viewports + firstViewport,
2788                             pViewports, viewportCount * sizeof(*pViewports))) {
2789                         return;
2790                 }
2791         }
2792
2793         memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2794                viewportCount * sizeof(*pViewports));
2795
2796         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2797 }
2798
2799 void radv_CmdSetScissor(
2800         VkCommandBuffer                             commandBuffer,
2801         uint32_t                                    firstScissor,
2802         uint32_t                                    scissorCount,
2803         const VkRect2D*                             pScissors)
2804 {
2805         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2806         struct radv_cmd_state *state = &cmd_buffer->state;
2807         MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2808
2809         assert(firstScissor < MAX_SCISSORS);
2810         assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2811
2812         if (cmd_buffer->device->physical_device->has_scissor_bug) {
2813                 /* Try to skip unnecessary PS partial flushes when the scissors
2814                  * don't change.
2815                  */
2816                 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2817                                       RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2818                     !memcmp(state->dynamic.scissor.scissors + firstScissor,
2819                             pScissors, scissorCount * sizeof(*pScissors))) {
2820                         return;
2821                 }
2822         }
2823
2824         memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2825                scissorCount * sizeof(*pScissors));
2826
2827         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2828 }
2829
2830 void radv_CmdSetLineWidth(
2831         VkCommandBuffer                             commandBuffer,
2832         float                                       lineWidth)
2833 {
2834         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2835         cmd_buffer->state.dynamic.line_width = lineWidth;
2836         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2837 }
2838
2839 void radv_CmdSetDepthBias(
2840         VkCommandBuffer                             commandBuffer,
2841         float                                       depthBiasConstantFactor,
2842         float                                       depthBiasClamp,
2843         float                                       depthBiasSlopeFactor)
2844 {
2845         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2846
2847         cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2848         cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2849         cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2850
2851         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2852 }
2853
2854 void radv_CmdSetBlendConstants(
2855         VkCommandBuffer                             commandBuffer,
2856         const float                                 blendConstants[4])
2857 {
2858         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2859
2860         memcpy(cmd_buffer->state.dynamic.blend_constants,
2861                blendConstants, sizeof(float) * 4);
2862
2863         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2864 }
2865
2866 void radv_CmdSetDepthBounds(
2867         VkCommandBuffer                             commandBuffer,
2868         float                                       minDepthBounds,
2869         float                                       maxDepthBounds)
2870 {
2871         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2872
2873         cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2874         cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2875
2876         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2877 }
2878
2879 void radv_CmdSetStencilCompareMask(
2880         VkCommandBuffer                             commandBuffer,
2881         VkStencilFaceFlags                          faceMask,
2882         uint32_t                                    compareMask)
2883 {
2884         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2885
2886         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2887                 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2888         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2889                 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2890
2891         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2892 }
2893
2894 void radv_CmdSetStencilWriteMask(
2895         VkCommandBuffer                             commandBuffer,
2896         VkStencilFaceFlags                          faceMask,
2897         uint32_t                                    writeMask)
2898 {
2899         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2900
2901         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2902                 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2903         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2904                 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2905
2906         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2907 }
2908
2909 void radv_CmdSetStencilReference(
2910         VkCommandBuffer                             commandBuffer,
2911         VkStencilFaceFlags                          faceMask,
2912         uint32_t                                    reference)
2913 {
2914         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2915
2916         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2917                 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2918         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2919                 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2920
2921         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2922 }
2923
2924 void radv_CmdSetDiscardRectangleEXT(
2925         VkCommandBuffer                             commandBuffer,
2926         uint32_t                                    firstDiscardRectangle,
2927         uint32_t                                    discardRectangleCount,
2928         const VkRect2D*                             pDiscardRectangles)
2929 {
2930         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2931         struct radv_cmd_state *state = &cmd_buffer->state;
2932         MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2933
2934         assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2935         assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2936
2937         typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2938                      pDiscardRectangles, discardRectangleCount);
2939
2940         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2941 }
2942
2943 void radv_CmdExecuteCommands(
2944         VkCommandBuffer                             commandBuffer,
2945         uint32_t                                    commandBufferCount,
2946         const VkCommandBuffer*                      pCmdBuffers)
2947 {
2948         RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2949
2950         assert(commandBufferCount > 0);
2951
2952         /* Emit pending flushes on primary prior to executing secondary */
2953         si_emit_cache_flush(primary);
2954
2955         for (uint32_t i = 0; i < commandBufferCount; i++) {
2956                 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2957
2958                 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2959                                                     secondary->scratch_size_needed);
2960                 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2961                                                             secondary->compute_scratch_size_needed);
2962
2963                 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2964                         primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2965                 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2966                         primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2967                 if (secondary->tess_rings_needed)
2968                         primary->tess_rings_needed = true;
2969                 if (secondary->sample_positions_needed)
2970                         primary->sample_positions_needed = true;
2971
2972                 if (secondary->ring_offsets_idx != -1) {
2973                         if (primary->ring_offsets_idx == -1)
2974                                 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2975                         else
2976                                 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2977                 }
2978                 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2979
2980
2981                 /* When the secondary command buffer is compute only we don't
2982                  * need to re-emit the current graphics pipeline.
2983                  */
2984                 if (secondary->state.emitted_pipeline) {
2985                         primary->state.emitted_pipeline =
2986                                 secondary->state.emitted_pipeline;
2987                 }
2988
2989                 /* When the secondary command buffer is graphics only we don't
2990                  * need to re-emit the current compute pipeline.
2991                  */
2992                 if (secondary->state.emitted_compute_pipeline) {
2993                         primary->state.emitted_compute_pipeline =
2994                                 secondary->state.emitted_compute_pipeline;
2995                 }
2996
2997                 /* Only re-emit the draw packets when needed. */
2998                 if (secondary->state.last_primitive_reset_en != -1) {
2999                         primary->state.last_primitive_reset_en =
3000                                 secondary->state.last_primitive_reset_en;
3001                 }
3002
3003                 if (secondary->state.last_primitive_reset_index) {
3004                         primary->state.last_primitive_reset_index =
3005                                 secondary->state.last_primitive_reset_index;
3006                 }
3007
3008                 if (secondary->state.last_ia_multi_vgt_param) {
3009                         primary->state.last_ia_multi_vgt_param =
3010                                 secondary->state.last_ia_multi_vgt_param;
3011                 }
3012
3013                 if (secondary->state.last_first_instance != -1) {
3014                         primary->state.last_first_instance =
3015                                 secondary->state.last_first_instance;
3016                 }
3017
3018                 if (secondary->state.last_num_instances != -1) {
3019                         primary->state.last_num_instances =
3020                                 secondary->state.last_num_instances;
3021                 }
3022
3023                 if (secondary->state.last_vertex_offset != -1) {
3024                         primary->state.last_vertex_offset =
3025                                 secondary->state.last_vertex_offset;
3026                 }
3027
3028                 if (secondary->state.last_index_type != -1) {
3029                         primary->state.last_index_type =
3030                                 secondary->state.last_index_type;
3031                 }
3032         }
3033
3034         /* After executing commands from secondary buffers we have to dirty
3035          * some states.
3036          */
3037         primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3038                                 RADV_CMD_DIRTY_INDEX_BUFFER |
3039                                 RADV_CMD_DIRTY_DYNAMIC_ALL;
3040         radv_mark_descriptor_sets_dirty(primary);
3041 }
3042
3043 VkResult radv_CreateCommandPool(
3044         VkDevice                                    _device,
3045         const VkCommandPoolCreateInfo*              pCreateInfo,
3046         const VkAllocationCallbacks*                pAllocator,
3047         VkCommandPool*                              pCmdPool)
3048 {
3049         RADV_FROM_HANDLE(radv_device, device, _device);
3050         struct radv_cmd_pool *pool;
3051
3052         pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3053                            VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3054         if (pool == NULL)
3055                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3056
3057         if (pAllocator)
3058                 pool->alloc = *pAllocator;
3059         else
3060                 pool->alloc = device->alloc;
3061
3062         list_inithead(&pool->cmd_buffers);
3063         list_inithead(&pool->free_cmd_buffers);
3064
3065         pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3066
3067         *pCmdPool = radv_cmd_pool_to_handle(pool);
3068
3069         return VK_SUCCESS;
3070
3071 }
3072
3073 void radv_DestroyCommandPool(
3074         VkDevice                                    _device,
3075         VkCommandPool                               commandPool,
3076         const VkAllocationCallbacks*                pAllocator)
3077 {
3078         RADV_FROM_HANDLE(radv_device, device, _device);
3079         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3080
3081         if (!pool)
3082                 return;
3083
3084         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3085                                  &pool->cmd_buffers, pool_link) {
3086                 radv_cmd_buffer_destroy(cmd_buffer);
3087         }
3088
3089         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3090                                  &pool->free_cmd_buffers, pool_link) {
3091                 radv_cmd_buffer_destroy(cmd_buffer);
3092         }
3093
3094         vk_free2(&device->alloc, pAllocator, pool);
3095 }
3096
3097 VkResult radv_ResetCommandPool(
3098         VkDevice                                    device,
3099         VkCommandPool                               commandPool,
3100         VkCommandPoolResetFlags                     flags)
3101 {
3102         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3103         VkResult result;
3104
3105         list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3106                             &pool->cmd_buffers, pool_link) {
3107                 result = radv_reset_cmd_buffer(cmd_buffer);
3108                 if (result != VK_SUCCESS)
3109                         return result;
3110         }
3111
3112         return VK_SUCCESS;
3113 }
3114
3115 void radv_TrimCommandPoolKHR(
3116     VkDevice                                    device,
3117     VkCommandPool                               commandPool,
3118     VkCommandPoolTrimFlagsKHR                   flags)
3119 {
3120         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3121
3122         if (!pool)
3123                 return;
3124
3125         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3126                                  &pool->free_cmd_buffers, pool_link) {
3127                 radv_cmd_buffer_destroy(cmd_buffer);
3128         }
3129 }
3130
3131 void radv_CmdBeginRenderPass(
3132         VkCommandBuffer                             commandBuffer,
3133         const VkRenderPassBeginInfo*                pRenderPassBegin,
3134         VkSubpassContents                           contents)
3135 {
3136         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3137         RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3138         RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3139
3140         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3141                                                            cmd_buffer->cs, 2048);
3142         MAYBE_UNUSED VkResult result;
3143
3144         cmd_buffer->state.framebuffer = framebuffer;
3145         cmd_buffer->state.pass = pass;
3146         cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3147
3148         result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3149         if (result != VK_SUCCESS)
3150                 return;
3151
3152         radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3153         assert(cmd_buffer->cs->cdw <= cdw_max);
3154
3155         radv_cmd_buffer_clear_subpass(cmd_buffer);
3156 }
3157
3158 void radv_CmdNextSubpass(
3159     VkCommandBuffer                             commandBuffer,
3160     VkSubpassContents                           contents)
3161 {
3162         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3163
3164         radv_cmd_buffer_resolve_subpass(cmd_buffer);
3165
3166         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3167                                               2048);
3168
3169         radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3170         radv_cmd_buffer_clear_subpass(cmd_buffer);
3171 }
3172
3173 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3174 {
3175         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3176         for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3177                 if (!pipeline->shaders[stage])
3178                         continue;
3179                 struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3180                 if (loc->sgpr_idx == -1)
3181                         continue;
3182                 uint32_t base_reg = pipeline->user_data_0[stage];
3183                 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3184
3185         }
3186         if (pipeline->gs_copy_shader) {
3187                 struct ac_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3188                 if (loc->sgpr_idx != -1) {
3189                         uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3190                         radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3191                 }
3192         }
3193 }
3194
3195 static void
3196 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3197                          uint32_t vertex_count)
3198 {
3199         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3200         radeon_emit(cmd_buffer->cs, vertex_count);
3201         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3202                                     S_0287F0_USE_OPAQUE(0));
3203 }
3204
3205 static void
3206 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3207                                  uint64_t index_va,
3208                                  uint32_t index_count)
3209 {
3210         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3211         radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3212         radeon_emit(cmd_buffer->cs, index_va);
3213         radeon_emit(cmd_buffer->cs, index_va >> 32);
3214         radeon_emit(cmd_buffer->cs, index_count);
3215         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3216 }
3217
3218 static void
3219 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3220                                   bool indexed,
3221                                   uint32_t draw_count,
3222                                   uint64_t count_va,
3223                                   uint32_t stride)
3224 {
3225         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3226         unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3227                                       : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3228         bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
3229         uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3230         assert(base_reg);
3231
3232         /* just reset draw state for vertex data */
3233         cmd_buffer->state.last_first_instance = -1;
3234         cmd_buffer->state.last_num_instances = -1;
3235         cmd_buffer->state.last_vertex_offset = -1;
3236
3237         if (draw_count == 1 && !count_va && !draw_id_enable) {
3238                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3239                                      PKT3_DRAW_INDIRECT, 3, false));
3240                 radeon_emit(cs, 0);
3241                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3242                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3243                 radeon_emit(cs, di_src_sel);
3244         } else {
3245                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3246                                      PKT3_DRAW_INDIRECT_MULTI,
3247                                      8, false));
3248                 radeon_emit(cs, 0);
3249                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3250                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3251                 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3252                             S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3253                             S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3254                 radeon_emit(cs, draw_count); /* count */
3255                 radeon_emit(cs, count_va); /* count_addr */
3256                 radeon_emit(cs, count_va >> 32);
3257                 radeon_emit(cs, stride); /* stride */
3258                 radeon_emit(cs, di_src_sel);
3259         }
3260 }
3261
3262 struct radv_draw_info {
3263         /**
3264          * Number of vertices.
3265          */
3266         uint32_t count;
3267
3268         /**
3269          * Index of the first vertex.
3270          */
3271         int32_t vertex_offset;
3272
3273         /**
3274          * First instance id.
3275          */
3276         uint32_t first_instance;
3277
3278         /**
3279          * Number of instances.
3280          */
3281         uint32_t instance_count;
3282
3283         /**
3284          * First index (indexed draws only).
3285          */
3286         uint32_t first_index;
3287
3288         /**
3289          * Whether it's an indexed draw.
3290          */
3291         bool indexed;
3292
3293         /**
3294          * Indirect draw parameters resource.
3295          */
3296         struct radv_buffer *indirect;
3297         uint64_t indirect_offset;
3298         uint32_t stride;
3299
3300         /**
3301          * Draw count parameters resource.
3302          */
3303         struct radv_buffer *count_buffer;
3304         uint64_t count_buffer_offset;
3305 };
3306
3307 static void
3308 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3309                        const struct radv_draw_info *info)
3310 {
3311         struct radv_cmd_state *state = &cmd_buffer->state;
3312         struct radeon_winsys *ws = cmd_buffer->device->ws;
3313         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3314
3315         if (info->indirect) {
3316                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3317                 uint64_t count_va = 0;
3318
3319                 va += info->indirect->offset + info->indirect_offset;
3320
3321                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3322
3323                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3324                 radeon_emit(cs, 1);
3325                 radeon_emit(cs, va);
3326                 radeon_emit(cs, va >> 32);
3327
3328                 if (info->count_buffer) {
3329                         count_va = radv_buffer_get_va(info->count_buffer->bo);
3330                         count_va += info->count_buffer->offset +
3331                                     info->count_buffer_offset;
3332
3333                         radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3334                 }
3335
3336                 if (!state->subpass->view_mask) {
3337                         radv_cs_emit_indirect_draw_packet(cmd_buffer,
3338                                                           info->indexed,
3339                                                           info->count,
3340                                                           count_va,
3341                                                           info->stride);
3342                 } else {
3343                         unsigned i;
3344                         for_each_bit(i, state->subpass->view_mask) {
3345                                 radv_emit_view_index(cmd_buffer, i);
3346
3347                                 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3348                                                                   info->indexed,
3349                                                                   info->count,
3350                                                                   count_va,
3351                                                                   info->stride);
3352                         }
3353                 }
3354         } else {
3355                 assert(state->pipeline->graphics.vtx_base_sgpr);
3356
3357                 if (info->vertex_offset != state->last_vertex_offset ||
3358                     info->first_instance != state->last_first_instance) {
3359                         radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3360                                               state->pipeline->graphics.vtx_emit_num);
3361
3362                         radeon_emit(cs, info->vertex_offset);
3363                         radeon_emit(cs, info->first_instance);
3364                         if (state->pipeline->graphics.vtx_emit_num == 3)
3365                                 radeon_emit(cs, 0);
3366                         state->last_first_instance = info->first_instance;
3367                         state->last_vertex_offset = info->vertex_offset;
3368                 }
3369
3370                 if (state->last_num_instances != info->instance_count) {
3371                         radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
3372                         radeon_emit(cs, info->instance_count);
3373                         state->last_num_instances = info->instance_count;
3374                 }
3375
3376                 if (info->indexed) {
3377                         int index_size = state->index_type ? 4 : 2;
3378                         uint64_t index_va;
3379
3380                         index_va = state->index_va;
3381                         index_va += info->first_index * index_size;
3382
3383                         if (!state->subpass->view_mask) {
3384                                 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3385                                                                  index_va,
3386                                                                  info->count);
3387                         } else {
3388                                 unsigned i;
3389                                 for_each_bit(i, state->subpass->view_mask) {
3390                                         radv_emit_view_index(cmd_buffer, i);
3391
3392                                         radv_cs_emit_draw_indexed_packet(cmd_buffer,
3393                                                                          index_va,
3394                                                                          info->count);
3395                                 }
3396                         }
3397                 } else {
3398                         if (!state->subpass->view_mask) {
3399                                 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3400                         } else {
3401                                 unsigned i;
3402                                 for_each_bit(i, state->subpass->view_mask) {
3403                                         radv_emit_view_index(cmd_buffer, i);
3404
3405                                         radv_cs_emit_draw_packet(cmd_buffer,
3406                                                                  info->count);
3407                                 }
3408                         }
3409                 }
3410         }
3411 }
3412
3413 static void
3414 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3415                               const struct radv_draw_info *info)
3416 {
3417         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3418                 radv_emit_graphics_pipeline(cmd_buffer);
3419
3420         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3421                 radv_emit_framebuffer_state(cmd_buffer);
3422
3423         if (info->indexed) {
3424                 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3425                         radv_emit_index_buffer(cmd_buffer);
3426         } else {
3427                 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3428                  * so the state must be re-emitted before the next indexed
3429                  * draw.
3430                  */
3431                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3432                         cmd_buffer->state.last_index_type = -1;
3433                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3434                 }
3435         }
3436
3437         radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3438
3439         radv_emit_draw_registers(cmd_buffer, info->indexed,
3440                                  info->instance_count > 1, info->indirect,
3441                                  info->indirect ? 0 : info->count);
3442 }
3443
3444 static void
3445 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3446           const struct radv_draw_info *info)
3447 {
3448         bool pipeline_is_dirty =
3449                 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3450                 cmd_buffer->state.pipeline &&
3451                 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3452
3453         MAYBE_UNUSED unsigned cdw_max =
3454                 radeon_check_space(cmd_buffer->device->ws,
3455                                    cmd_buffer->cs, 4096);
3456
3457         /* Use optimal packet order based on whether we need to sync the
3458          * pipeline.
3459          */
3460         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3461                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3462                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3463                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3464                 /* If we have to wait for idle, set all states first, so that
3465                  * all SET packets are processed in parallel with previous draw
3466                  * calls. Then upload descriptors, set shader pointers, and
3467                  * draw, and prefetch at the end. This ensures that the time
3468                  * the CUs are idle is very short. (there are only SET_SH
3469                  * packets between the wait and the draw)
3470                  */
3471                 radv_emit_all_graphics_states(cmd_buffer, info);
3472                 si_emit_cache_flush(cmd_buffer);
3473                 /* <-- CUs are idle here --> */
3474
3475                 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3476                         return;
3477
3478                 radv_emit_draw_packets(cmd_buffer, info);
3479                 /* <-- CUs are busy here --> */
3480
3481                 /* Start prefetches after the draw has been started. Both will
3482                  * run in parallel, but starting the draw first is more
3483                  * important.
3484                  */
3485                 if (pipeline_is_dirty) {
3486                         radv_emit_prefetch(cmd_buffer,
3487                                            cmd_buffer->state.pipeline);
3488                 }
3489         } else {
3490                 /* If we don't wait for idle, start prefetches first, then set
3491                  * states, and draw at the end.
3492                  */
3493                 si_emit_cache_flush(cmd_buffer);
3494
3495                 if (pipeline_is_dirty) {
3496                         radv_emit_prefetch(cmd_buffer,
3497                                            cmd_buffer->state.pipeline);
3498                 }
3499
3500                 if (!radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty))
3501                         return;
3502
3503                 radv_emit_all_graphics_states(cmd_buffer, info);
3504                 radv_emit_draw_packets(cmd_buffer, info);
3505         }
3506
3507         assert(cmd_buffer->cs->cdw <= cdw_max);
3508         radv_cmd_buffer_after_draw(cmd_buffer);
3509 }
3510
3511 void radv_CmdDraw(
3512         VkCommandBuffer                             commandBuffer,
3513         uint32_t                                    vertexCount,
3514         uint32_t                                    instanceCount,
3515         uint32_t                                    firstVertex,
3516         uint32_t                                    firstInstance)
3517 {
3518         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3519         struct radv_draw_info info = {};
3520
3521         info.count = vertexCount;
3522         info.instance_count = instanceCount;
3523         info.first_instance = firstInstance;
3524         info.vertex_offset = firstVertex;
3525
3526         radv_draw(cmd_buffer, &info);
3527 }
3528
3529 void radv_CmdDrawIndexed(
3530         VkCommandBuffer                             commandBuffer,
3531         uint32_t                                    indexCount,
3532         uint32_t                                    instanceCount,
3533         uint32_t                                    firstIndex,
3534         int32_t                                     vertexOffset,
3535         uint32_t                                    firstInstance)
3536 {
3537         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3538         struct radv_draw_info info = {};
3539
3540         info.indexed = true;
3541         info.count = indexCount;
3542         info.instance_count = instanceCount;
3543         info.first_index = firstIndex;
3544         info.vertex_offset = vertexOffset;
3545         info.first_instance = firstInstance;
3546
3547         radv_draw(cmd_buffer, &info);
3548 }
3549
3550 void radv_CmdDrawIndirect(
3551         VkCommandBuffer                             commandBuffer,
3552         VkBuffer                                    _buffer,
3553         VkDeviceSize                                offset,
3554         uint32_t                                    drawCount,
3555         uint32_t                                    stride)
3556 {
3557         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3558         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3559         struct radv_draw_info info = {};
3560
3561         info.count = drawCount;
3562         info.indirect = buffer;
3563         info.indirect_offset = offset;
3564         info.stride = stride;
3565
3566         radv_draw(cmd_buffer, &info);
3567 }
3568
3569 void radv_CmdDrawIndexedIndirect(
3570         VkCommandBuffer                             commandBuffer,
3571         VkBuffer                                    _buffer,
3572         VkDeviceSize                                offset,
3573         uint32_t                                    drawCount,
3574         uint32_t                                    stride)
3575 {
3576         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3577         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3578         struct radv_draw_info info = {};
3579
3580         info.indexed = true;
3581         info.count = drawCount;
3582         info.indirect = buffer;
3583         info.indirect_offset = offset;
3584         info.stride = stride;
3585
3586         radv_draw(cmd_buffer, &info);
3587 }
3588
3589 void radv_CmdDrawIndirectCountAMD(
3590         VkCommandBuffer                             commandBuffer,
3591         VkBuffer                                    _buffer,
3592         VkDeviceSize                                offset,
3593         VkBuffer                                    _countBuffer,
3594         VkDeviceSize                                countBufferOffset,
3595         uint32_t                                    maxDrawCount,
3596         uint32_t                                    stride)
3597 {
3598         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3599         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3600         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3601         struct radv_draw_info info = {};
3602
3603         info.count = maxDrawCount;
3604         info.indirect = buffer;
3605         info.indirect_offset = offset;
3606         info.count_buffer = count_buffer;
3607         info.count_buffer_offset = countBufferOffset;
3608         info.stride = stride;
3609
3610         radv_draw(cmd_buffer, &info);
3611 }
3612
3613 void radv_CmdDrawIndexedIndirectCountAMD(
3614         VkCommandBuffer                             commandBuffer,
3615         VkBuffer                                    _buffer,
3616         VkDeviceSize                                offset,
3617         VkBuffer                                    _countBuffer,
3618         VkDeviceSize                                countBufferOffset,
3619         uint32_t                                    maxDrawCount,
3620         uint32_t                                    stride)
3621 {
3622         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3623         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3624         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3625         struct radv_draw_info info = {};
3626
3627         info.indexed = true;
3628         info.count = maxDrawCount;
3629         info.indirect = buffer;
3630         info.indirect_offset = offset;
3631         info.count_buffer = count_buffer;
3632         info.count_buffer_offset = countBufferOffset;
3633         info.stride = stride;
3634
3635         radv_draw(cmd_buffer, &info);
3636 }
3637
3638 struct radv_dispatch_info {
3639         /**
3640          * Determine the layout of the grid (in block units) to be used.
3641          */
3642         uint32_t blocks[3];
3643
3644         /**
3645          * Whether it's an unaligned compute dispatch.
3646          */
3647         bool unaligned;
3648
3649         /**
3650          * Indirect compute parameters resource.
3651          */
3652         struct radv_buffer *indirect;
3653         uint64_t indirect_offset;
3654 };
3655
3656 static void
3657 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3658                            const struct radv_dispatch_info *info)
3659 {
3660         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3661         struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3662         unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3663         struct radeon_winsys *ws = cmd_buffer->device->ws;
3664         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3665         struct ac_userdata_info *loc;
3666
3667         loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3668                                     AC_UD_CS_GRID_SIZE);
3669
3670         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3671
3672         if (info->indirect) {
3673                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3674
3675                 va += info->indirect->offset + info->indirect_offset;
3676
3677                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3678
3679                 if (loc->sgpr_idx != -1) {
3680                         for (unsigned i = 0; i < 3; ++i) {
3681                                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3682                                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3683                                                 COPY_DATA_DST_SEL(COPY_DATA_REG));
3684                                 radeon_emit(cs, (va +  4 * i));
3685                                 radeon_emit(cs, (va + 4 * i) >> 32);
3686                                 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3687                                                  + loc->sgpr_idx * 4) >> 2) + i);
3688                                 radeon_emit(cs, 0);
3689                         }
3690                 }
3691
3692                 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3693                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3694                                         PKT3_SHADER_TYPE_S(1));
3695                         radeon_emit(cs, va);
3696                         radeon_emit(cs, va >> 32);
3697                         radeon_emit(cs, dispatch_initiator);
3698                 } else {
3699                         radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3700                                         PKT3_SHADER_TYPE_S(1));
3701                         radeon_emit(cs, 1);
3702                         radeon_emit(cs, va);
3703                         radeon_emit(cs, va >> 32);
3704
3705                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3706                                         PKT3_SHADER_TYPE_S(1));
3707                         radeon_emit(cs, 0);
3708                         radeon_emit(cs, dispatch_initiator);
3709                 }
3710         } else {
3711                 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3712
3713                 if (info->unaligned) {
3714                         unsigned *cs_block_size = compute_shader->info.cs.block_size;
3715                         unsigned remainder[3];
3716
3717                         /* If aligned, these should be an entire block size,
3718                          * not 0.
3719                          */
3720                         remainder[0] = blocks[0] + cs_block_size[0] -
3721                                        align_u32_npot(blocks[0], cs_block_size[0]);
3722                         remainder[1] = blocks[1] + cs_block_size[1] -
3723                                        align_u32_npot(blocks[1], cs_block_size[1]);
3724                         remainder[2] = blocks[2] + cs_block_size[2] -
3725                                        align_u32_npot(blocks[2], cs_block_size[2]);
3726
3727                         blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3728                         blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3729                         blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3730
3731                         radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3732                         radeon_emit(cs,
3733                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3734                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3735                         radeon_emit(cs,
3736                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3737                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3738                         radeon_emit(cs,
3739                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3740                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3741
3742                         dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3743                 }
3744
3745                 if (loc->sgpr_idx != -1) {
3746                         assert(!loc->indirect);
3747                         assert(loc->num_sgprs == 3);
3748
3749                         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3750                                                   loc->sgpr_idx * 4, 3);
3751                         radeon_emit(cs, blocks[0]);
3752                         radeon_emit(cs, blocks[1]);
3753                         radeon_emit(cs, blocks[2]);
3754                 }
3755
3756                 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3757                                 PKT3_SHADER_TYPE_S(1));
3758                 radeon_emit(cs, blocks[0]);
3759                 radeon_emit(cs, blocks[1]);
3760                 radeon_emit(cs, blocks[2]);
3761                 radeon_emit(cs, dispatch_initiator);
3762         }
3763
3764         assert(cmd_buffer->cs->cdw <= cdw_max);
3765 }
3766
3767 static void
3768 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3769 {
3770         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3771         radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3772                              VK_SHADER_STAGE_COMPUTE_BIT);
3773 }
3774
3775 static void
3776 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3777               const struct radv_dispatch_info *info)
3778 {
3779         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3780         bool pipeline_is_dirty = pipeline &&
3781                                  pipeline != cmd_buffer->state.emitted_compute_pipeline;
3782
3783         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3784                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3785                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3786                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3787                 /* If we have to wait for idle, set all states first, so that
3788                  * all SET packets are processed in parallel with previous draw
3789                  * calls. Then upload descriptors, set shader pointers, and
3790                  * dispatch, and prefetch at the end. This ensures that the
3791                  * time the CUs are idle is very short. (there are only SET_SH
3792                  * packets between the wait and the draw)
3793                  */
3794                 radv_emit_compute_pipeline(cmd_buffer);
3795                 si_emit_cache_flush(cmd_buffer);
3796                 /* <-- CUs are idle here --> */
3797
3798                 radv_upload_compute_shader_descriptors(cmd_buffer);
3799
3800                 radv_emit_dispatch_packets(cmd_buffer, info);
3801                 /* <-- CUs are busy here --> */
3802
3803                 /* Start prefetches after the dispatch has been started. Both
3804                  * will run in parallel, but starting the dispatch first is
3805                  * more important.
3806                  */
3807                 if (pipeline_is_dirty) {
3808                         radv_emit_shader_prefetch(cmd_buffer,
3809                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3810                 }
3811         } else {
3812                 /* If we don't wait for idle, start prefetches first, then set
3813                  * states, and dispatch at the end.
3814                  */
3815                 si_emit_cache_flush(cmd_buffer);
3816
3817                 if (pipeline_is_dirty) {
3818                         radv_emit_shader_prefetch(cmd_buffer,
3819                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3820                 }
3821
3822                 radv_upload_compute_shader_descriptors(cmd_buffer);
3823
3824                 radv_emit_compute_pipeline(cmd_buffer);
3825                 radv_emit_dispatch_packets(cmd_buffer, info);
3826         }
3827
3828         radv_cmd_buffer_after_draw(cmd_buffer);
3829 }
3830
3831 void radv_CmdDispatch(
3832         VkCommandBuffer                             commandBuffer,
3833         uint32_t                                    x,
3834         uint32_t                                    y,
3835         uint32_t                                    z)
3836 {
3837         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3838         struct radv_dispatch_info info = {};
3839
3840         info.blocks[0] = x;
3841         info.blocks[1] = y;
3842         info.blocks[2] = z;
3843
3844         radv_dispatch(cmd_buffer, &info);
3845 }
3846
3847 void radv_CmdDispatchIndirect(
3848         VkCommandBuffer                             commandBuffer,
3849         VkBuffer                                    _buffer,
3850         VkDeviceSize                                offset)
3851 {
3852         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3853         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3854         struct radv_dispatch_info info = {};
3855
3856         info.indirect = buffer;
3857         info.indirect_offset = offset;
3858
3859         radv_dispatch(cmd_buffer, &info);
3860 }
3861
3862 void radv_unaligned_dispatch(
3863         struct radv_cmd_buffer                      *cmd_buffer,
3864         uint32_t                                    x,
3865         uint32_t                                    y,
3866         uint32_t                                    z)
3867 {
3868         struct radv_dispatch_info info = {};
3869
3870         info.blocks[0] = x;
3871         info.blocks[1] = y;
3872         info.blocks[2] = z;
3873         info.unaligned = 1;
3874
3875         radv_dispatch(cmd_buffer, &info);
3876 }
3877
3878 void radv_CmdEndRenderPass(
3879         VkCommandBuffer                             commandBuffer)
3880 {
3881         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3882
3883         radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3884
3885         radv_cmd_buffer_resolve_subpass(cmd_buffer);
3886
3887         for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3888                 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3889                 radv_handle_subpass_image_transition(cmd_buffer,
3890                                       (VkAttachmentReference){i, layout});
3891         }
3892
3893         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3894
3895         cmd_buffer->state.pass = NULL;
3896         cmd_buffer->state.subpass = NULL;
3897         cmd_buffer->state.attachments = NULL;
3898         cmd_buffer->state.framebuffer = NULL;
3899 }
3900
3901 /*
3902  * For HTILE we have the following interesting clear words:
3903  *   0x0000030f: Uncompressed for depth+stencil HTILE.
3904  *   0x0000000f: Uncompressed for depth only HTILE.
3905  *   0xfffffff0: Clear depth to 1.0
3906  *   0x00000000: Clear depth to 0.0
3907  */
3908 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3909                                   struct radv_image *image,
3910                                   const VkImageSubresourceRange *range,
3911                                   uint32_t clear_word)
3912 {
3913         assert(range->baseMipLevel == 0);
3914         assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3915         unsigned layer_count = radv_get_layerCount(image, range);
3916         uint64_t size = image->surface.htile_slice_size * layer_count;
3917         uint64_t offset = image->offset + image->htile_offset +
3918                           image->surface.htile_slice_size * range->baseArrayLayer;
3919         struct radv_cmd_state *state = &cmd_buffer->state;
3920
3921         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3922                              RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3923
3924         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3925                                               size, clear_word);
3926
3927         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3928 }
3929
3930 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3931                                                struct radv_image *image,
3932                                                VkImageLayout src_layout,
3933                                                VkImageLayout dst_layout,
3934                                                unsigned src_queue_mask,
3935                                                unsigned dst_queue_mask,
3936                                                const VkImageSubresourceRange *range,
3937                                                VkImageAspectFlags pending_clears)
3938 {
3939         if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3940             (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3941             cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3942             cmd_buffer->state.render_area.extent.width == image->info.width &&
3943             cmd_buffer->state.render_area.extent.height == image->info.height) {
3944                 /* The clear will initialize htile. */
3945                 return;
3946         } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3947                    radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3948                 /* TODO: merge with the clear if applicable */
3949                 radv_initialize_htile(cmd_buffer, image, range, 0);
3950         } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3951                    radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3952                 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0x30f : 0xf;
3953                 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3954         } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3955                    !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3956                 VkImageSubresourceRange local_range = *range;
3957                 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3958                 local_range.baseMipLevel = 0;
3959                 local_range.levelCount = 1;
3960
3961                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3962                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3963
3964                 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3965
3966                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3967                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3968         }
3969 }
3970
3971 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3972                            struct radv_image *image, uint32_t value)
3973 {
3974         struct radv_cmd_state *state = &cmd_buffer->state;
3975
3976         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3977                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3978
3979         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3980                                               image->offset + image->cmask.offset,
3981                                               image->cmask.size, value);
3982
3983         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3984 }
3985
3986 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3987                                                struct radv_image *image,
3988                                                VkImageLayout src_layout,
3989                                                VkImageLayout dst_layout,
3990                                                unsigned src_queue_mask,
3991                                                unsigned dst_queue_mask,
3992                                                const VkImageSubresourceRange *range)
3993 {
3994         if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3995                 if (image->fmask.size)
3996                         radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3997                 else
3998                         radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3999         } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4000                    !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4001                 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4002         }
4003 }
4004
4005 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4006                          struct radv_image *image, uint32_t value)
4007 {
4008         struct radv_cmd_state *state = &cmd_buffer->state;
4009
4010         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4011                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4012
4013         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
4014                                               image->offset + image->dcc_offset,
4015                                               image->surface.dcc_size, value);
4016
4017         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4018                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4019 }
4020
4021 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
4022                                              struct radv_image *image,
4023                                              VkImageLayout src_layout,
4024                                              VkImageLayout dst_layout,
4025                                              unsigned src_queue_mask,
4026                                              unsigned dst_queue_mask,
4027                                              const VkImageSubresourceRange *range)
4028 {
4029         if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4030                 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4031         } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4032                 radv_initialize_dcc(cmd_buffer, image,
4033                                     radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask) ?
4034                                          0x20202020u : 0xffffffffu);
4035         } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4036                    !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4037                 radv_decompress_dcc(cmd_buffer, image, range);
4038         } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4039                    !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4040                 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4041         }
4042 }
4043
4044 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4045                                          struct radv_image *image,
4046                                          VkImageLayout src_layout,
4047                                          VkImageLayout dst_layout,
4048                                          uint32_t src_family,
4049                                          uint32_t dst_family,
4050                                          const VkImageSubresourceRange *range,
4051                                          VkImageAspectFlags pending_clears)
4052 {
4053         if (image->exclusive && src_family != dst_family) {
4054                 /* This is an acquire or a release operation and there will be
4055                  * a corresponding release/acquire. Do the transition in the
4056                  * most flexible queue. */
4057
4058                 assert(src_family == cmd_buffer->queue_family_index ||
4059                        dst_family == cmd_buffer->queue_family_index);
4060
4061                 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4062                         return;
4063
4064                 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4065                     (src_family == RADV_QUEUE_GENERAL ||
4066                      dst_family == RADV_QUEUE_GENERAL))
4067                         return;
4068         }
4069
4070         unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
4071         unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
4072
4073         if (image->surface.htile_size)
4074                 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
4075                                                    dst_layout, src_queue_mask,
4076                                                    dst_queue_mask, range,
4077                                                    pending_clears);
4078
4079         if (image->cmask.size || image->fmask.size)
4080                 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
4081                                                    dst_layout, src_queue_mask,
4082                                                    dst_queue_mask, range);
4083
4084         if (image->surface.dcc_size)
4085                 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
4086                                                  dst_layout, src_queue_mask,
4087                                                  dst_queue_mask, range);
4088 }
4089
4090 void radv_CmdPipelineBarrier(
4091         VkCommandBuffer                             commandBuffer,
4092         VkPipelineStageFlags                        srcStageMask,
4093         VkPipelineStageFlags                        destStageMask,
4094         VkBool32                                    byRegion,
4095         uint32_t                                    memoryBarrierCount,
4096         const VkMemoryBarrier*                      pMemoryBarriers,
4097         uint32_t                                    bufferMemoryBarrierCount,
4098         const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
4099         uint32_t                                    imageMemoryBarrierCount,
4100         const VkImageMemoryBarrier*                 pImageMemoryBarriers)
4101 {
4102         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4103         enum radv_cmd_flush_bits src_flush_bits = 0;
4104         enum radv_cmd_flush_bits dst_flush_bits = 0;
4105
4106         for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4107                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
4108                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4109                                                         NULL);
4110         }
4111
4112         for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4113                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
4114                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4115                                                         NULL);
4116         }
4117
4118         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4119                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4120                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
4121                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4122                                                         image);
4123         }
4124
4125         radv_stage_flush(cmd_buffer, srcStageMask);
4126         cmd_buffer->state.flush_bits |= src_flush_bits;
4127
4128         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4129                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4130                 radv_handle_image_transition(cmd_buffer, image,
4131                                              pImageMemoryBarriers[i].oldLayout,
4132                                              pImageMemoryBarriers[i].newLayout,
4133                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
4134                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
4135                                              &pImageMemoryBarriers[i].subresourceRange,
4136                                              0);
4137         }
4138
4139         cmd_buffer->state.flush_bits |= dst_flush_bits;
4140 }
4141
4142
4143 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4144                         struct radv_event *event,
4145                         VkPipelineStageFlags stageMask,
4146                         unsigned value)
4147 {
4148         struct radeon_winsys_cs *cs = cmd_buffer->cs;
4149         uint64_t va = radv_buffer_get_va(event->bo);
4150
4151         radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4152
4153         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4154
4155         /* TODO: this is overkill. Probably should figure something out from
4156          * the stage mask. */
4157
4158         si_cs_emit_write_event_eop(cs,
4159                                    cmd_buffer->state.predicating,
4160                                    cmd_buffer->device->physical_device->rad_info.chip_class,
4161                                    radv_cmd_buffer_uses_mec(cmd_buffer),
4162                                    V_028A90_BOTTOM_OF_PIPE_TS, 0,
4163                                    1, va, 2, value);
4164
4165         assert(cmd_buffer->cs->cdw <= cdw_max);
4166 }
4167
4168 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4169                       VkEvent _event,
4170                       VkPipelineStageFlags stageMask)
4171 {
4172         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4173         RADV_FROM_HANDLE(radv_event, event, _event);
4174
4175         write_event(cmd_buffer, event, stageMask, 1);
4176 }
4177
4178 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4179                         VkEvent _event,
4180                         VkPipelineStageFlags stageMask)
4181 {
4182         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4183         RADV_FROM_HANDLE(radv_event, event, _event);
4184
4185         write_event(cmd_buffer, event, stageMask, 0);
4186 }
4187
4188 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4189                         uint32_t eventCount,
4190                         const VkEvent* pEvents,
4191                         VkPipelineStageFlags srcStageMask,
4192                         VkPipelineStageFlags dstStageMask,
4193                         uint32_t memoryBarrierCount,
4194                         const VkMemoryBarrier* pMemoryBarriers,
4195                         uint32_t bufferMemoryBarrierCount,
4196                         const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4197                         uint32_t imageMemoryBarrierCount,
4198                         const VkImageMemoryBarrier* pImageMemoryBarriers)
4199 {
4200         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4201         struct radeon_winsys_cs *cs = cmd_buffer->cs;
4202
4203         for (unsigned i = 0; i < eventCount; ++i) {
4204                 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4205                 uint64_t va = radv_buffer_get_va(event->bo);
4206
4207                 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4208
4209                 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4210
4211                 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4212                 assert(cmd_buffer->cs->cdw <= cdw_max);
4213         }
4214
4215
4216         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4217                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4218
4219                 radv_handle_image_transition(cmd_buffer, image,
4220                                              pImageMemoryBarriers[i].oldLayout,
4221                                              pImageMemoryBarriers[i].newLayout,
4222                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
4223                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
4224                                              &pImageMemoryBarriers[i].subresourceRange,
4225                                              0);
4226         }
4227
4228         /* TODO: figure out how to do memory barriers without waiting */
4229         cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4230                                         RADV_CMD_FLAG_INV_GLOBAL_L2 |
4231                                         RADV_CMD_FLAG_INV_VMEM_L1 |
4232                                         RADV_CMD_FLAG_INV_SMEM_L1;
4233 }