src/amd/vulkan/radv_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "radv_private.h"
  29 #include "radv_radeon_winsys.h"
  30 #include "radv_shader.h"
  31 #include "radv_cs.h"
  32 #include "sid.h"
  33 #include "gfx9d.h"
  34 #include "vk_format.h"
  35 #include "radv_debug.h"
  36 #include "radv_meta.h"
  37
  38 #include "ac_debug.h"
  39
  40 enum {
  41         RADV_PREFETCH_VBO_DESCRIPTORS   = (1 << 0),
  42         RADV_PREFETCH_VS                = (1 << 1),
  43         RADV_PREFETCH_TCS               = (1 << 2),
  44         RADV_PREFETCH_TES               = (1 << 3),
  45         RADV_PREFETCH_GS                = (1 << 4),
  46         RADV_PREFETCH_PS                = (1 << 5),
  47         RADV_PREFETCH_SHADERS           = (RADV_PREFETCH_VS  |
  48                                            RADV_PREFETCH_TCS |
  49                                            RADV_PREFETCH_TES |
  50                                            RADV_PREFETCH_GS  |
  51                                            RADV_PREFETCH_PS)
  52 };
  53
  54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
  55                                          struct radv_image *image,
  56                                          VkImageLayout src_layout,
  57                                          VkImageLayout dst_layout,
  58                                          uint32_t src_family,
  59                                          uint32_t dst_family,
  60                                          const VkImageSubresourceRange *range,
  61                                          VkImageAspectFlags pending_clears);
  62
  63 const struct radv_dynamic_state default_dynamic_state = {
  64         .viewport = {
  65                 .count = 0,
  66         },
  67         .scissor = {
  68                 .count = 0,
  69         },
  70         .line_width = 1.0f,
  71         .depth_bias = {
  72                 .bias = 0.0f,
  73                 .clamp = 0.0f,
  74                 .slope = 0.0f,
  75         },
  76         .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
  77         .depth_bounds = {
  78                 .min = 0.0f,
  79                 .max = 1.0f,
  80         },
  81         .stencil_compare_mask = {
  82                 .front = ~0u,
  83                 .back = ~0u,
  84         },
  85         .stencil_write_mask = {
  86                 .front = ~0u,
  87                 .back = ~0u,
  88         },
  89         .stencil_reference = {
  90                 .front = 0u,
  91                 .back = 0u,
  92         },
  93 };
  94
  95 static void
  96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
  97                         const struct radv_dynamic_state *src)
  98 {
  99         struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
 100         uint32_t copy_mask = src->mask;
 101         uint32_t dest_mask = 0;
 102
 103         /* Make sure to copy the number of viewports/scissors because they can
 104          * only be specified at pipeline creation time.
 105          */
 106         dest->viewport.count = src->viewport.count;
 107         dest->scissor.count = src->scissor.count;
 108         dest->discard_rectangle.count = src->discard_rectangle.count;
 109
 110         if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
 111                 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
 112                            src->viewport.count * sizeof(VkViewport))) {
 113                         typed_memcpy(dest->viewport.viewports,
 114                                      src->viewport.viewports,
 115                                      src->viewport.count);
 116                         dest_mask |= RADV_DYNAMIC_VIEWPORT;
 117                 }
 118         }
 119
 120         if (copy_mask & RADV_DYNAMIC_SCISSOR) {
 121                 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
 122                            src->scissor.count * sizeof(VkRect2D))) {
 123                         typed_memcpy(dest->scissor.scissors,
 124                                      src->scissor.scissors, src->scissor.count);
 125                         dest_mask |= RADV_DYNAMIC_SCISSOR;
 126                 }
 127         }
 128
 129         if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
 130                 if (dest->line_width != src->line_width) {
 131                         dest->line_width = src->line_width;
 132                         dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
 133                 }
 134         }
 135
 136         if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
 137                 if (memcmp(&dest->depth_bias, &src->depth_bias,
 138                            sizeof(src->depth_bias))) {
 139                         dest->depth_bias = src->depth_bias;
 140                         dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
 141                 }
 142         }
 143
 144         if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
 145                 if (memcmp(&dest->blend_constants, &src->blend_constants,
 146                            sizeof(src->blend_constants))) {
 147                         typed_memcpy(dest->blend_constants,
 148                                      src->blend_constants, 4);
 149                         dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
 150                 }
 151         }
 152
 153         if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
 154                 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
 155                            sizeof(src->depth_bounds))) {
 156                         dest->depth_bounds = src->depth_bounds;
 157                         dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
 158                 }
 159         }
 160
 161         if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
 162                 if (memcmp(&dest->stencil_compare_mask,
 163                            &src->stencil_compare_mask,
 164                            sizeof(src->stencil_compare_mask))) {
 165                         dest->stencil_compare_mask = src->stencil_compare_mask;
 166                         dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
 167                 }
 168         }
 169
 170         if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
 171                 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
 172                            sizeof(src->stencil_write_mask))) {
 173                         dest->stencil_write_mask = src->stencil_write_mask;
 174                         dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
 175                 }
 176         }
 177
 178         if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
 179                 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
 180                            sizeof(src->stencil_reference))) {
 181                         dest->stencil_reference = src->stencil_reference;
 182                         dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
 183                 }
 184         }
 185
 186         if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
 187                 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
 188                            src->discard_rectangle.count * sizeof(VkRect2D))) {
 189                         typed_memcpy(dest->discard_rectangle.rectangles,
 190                                      src->discard_rectangle.rectangles,
 191                                      src->discard_rectangle.count);
 192                         dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
 193                 }
 194         }
 195
 196         cmd_buffer->state.dirty |= dest_mask;
 197 }
 198
 199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
 200 {
 201         return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
 202                cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
 203 }
 204
 205 enum ring_type radv_queue_family_to_ring(int f) {
 206         switch (f) {
 207         case RADV_QUEUE_GENERAL:
 208                 return RING_GFX;
 209         case RADV_QUEUE_COMPUTE:
 210                 return RING_COMPUTE;
 211         case RADV_QUEUE_TRANSFER:
 212                 return RING_DMA;
 213         default:
 214                 unreachable("Unknown queue family");
 215         }
 216 }
 217
 218 static VkResult radv_create_cmd_buffer(
 219         struct radv_device *                         device,
 220         struct radv_cmd_pool *                       pool,
 221         VkCommandBufferLevel                        level,
 222         VkCommandBuffer*                            pCommandBuffer)
 223 {
 224         struct radv_cmd_buffer *cmd_buffer;
 225         unsigned ring;
 226         cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
 227                                VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 228         if (cmd_buffer == NULL)
 229                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 230
 231         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
 232         cmd_buffer->device = device;
 233         cmd_buffer->pool = pool;
 234         cmd_buffer->level = level;
 235
 236         if (pool) {
 237                 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
 238                 cmd_buffer->queue_family_index = pool->queue_family_index;
 239
 240         } else {
 241                 /* Init the pool_link so we can safely call list_del when we destroy
 242                  * the command buffer
 243                  */
 244                 list_inithead(&cmd_buffer->pool_link);
 245                 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
 246         }
 247
 248         ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
 249
 250         cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
 251         if (!cmd_buffer->cs) {
 252                 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 253                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 254         }
 255
 256         *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
 257
 258         list_inithead(&cmd_buffer->upload.list);
 259
 260         return VK_SUCCESS;
 261 }
 262
 263 static void
 264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
 265 {
 266         list_del(&cmd_buffer->pool_link);
 267
 268         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 269                                  &cmd_buffer->upload.list, list) {
 270                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 271                 list_del(&up->list);
 272                 free(up);
 273         }
 274
 275         if (cmd_buffer->upload.upload_bo)
 276                 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
 277         cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
 278
 279         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
 280                 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
 281
 282         vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 283 }
 284
 285 static VkResult
 286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 287 {
 288
 289         cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
 290
 291         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 292                                  &cmd_buffer->upload.list, list) {
 293                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 294                 list_del(&up->list);
 295                 free(up);
 296         }
 297
 298         cmd_buffer->push_constant_stages = 0;
 299         cmd_buffer->scratch_size_needed = 0;
 300         cmd_buffer->compute_scratch_size_needed = 0;
 301         cmd_buffer->esgs_ring_size_needed = 0;
 302         cmd_buffer->gsvs_ring_size_needed = 0;
 303         cmd_buffer->tess_rings_needed = false;
 304         cmd_buffer->sample_positions_needed = false;
 305
 306         if (cmd_buffer->upload.upload_bo)
 307                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 308                                    cmd_buffer->upload.upload_bo, 8);
 309         cmd_buffer->upload.offset = 0;
 310
 311         cmd_buffer->record_result = VK_SUCCESS;
 312
 313         cmd_buffer->ring_offsets_idx = -1;
 314
 315         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
 316                 cmd_buffer->descriptors[i].dirty = 0;
 317                 cmd_buffer->descriptors[i].valid = 0;
 318                 cmd_buffer->descriptors[i].push_dirty = false;
 319         }
 320
 321         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 322                 void *fence_ptr;
 323                 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
 324                                              &cmd_buffer->gfx9_fence_offset,
 325                                              &fence_ptr);
 326                 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
 327         }
 328
 329         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
 330
 331         return cmd_buffer->record_result;
 332 }
 333
 334 static bool
 335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
 336                                   uint64_t min_needed)
 337 {
 338         uint64_t new_size;
 339         struct radeon_winsys_bo *bo;
 340         struct radv_cmd_buffer_upload *upload;
 341         struct radv_device *device = cmd_buffer->device;
 342
 343         new_size = MAX2(min_needed, 16 * 1024);
 344         new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
 345
 346         bo = device->ws->buffer_create(device->ws,
 347                                        new_size, 4096,
 348                                        RADEON_DOMAIN_GTT,
 349                                        RADEON_FLAG_CPU_ACCESS|
 350                                        RADEON_FLAG_NO_INTERPROCESS_SHARING |
 351                                        RADEON_FLAG_32BIT);
 352
 353         if (!bo) {
 354                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 355                 return false;
 356         }
 357
 358         radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
 359         if (cmd_buffer->upload.upload_bo) {
 360                 upload = malloc(sizeof(*upload));
 361
 362                 if (!upload) {
 363                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
 364                         device->ws->buffer_destroy(bo);
 365                         return false;
 366                 }
 367
 368                 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
 369                 list_add(&upload->list, &cmd_buffer->upload.list);
 370         }
 371
 372         cmd_buffer->upload.upload_bo = bo;
 373         cmd_buffer->upload.size = new_size;
 374         cmd_buffer->upload.offset = 0;
 375         cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
 376
 377         if (!cmd_buffer->upload.map) {
 378                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 379                 return false;
 380         }
 381
 382         return true;
 383 }
 384
 385 bool
 386 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
 387                              unsigned size,
 388                              unsigned alignment,
 389                              unsigned *out_offset,
 390                              void **ptr)
 391 {
 392         uint64_t offset = align(cmd_buffer->upload.offset, alignment);
 393         if (offset + size > cmd_buffer->upload.size) {
 394                 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
 395                         return false;
 396                 offset = 0;
 397         }
 398
 399         *out_offset = offset;
 400         *ptr = cmd_buffer->upload.map + offset;
 401
 402         cmd_buffer->upload.offset = offset + size;
 403         return true;
 404 }
 405
 406 bool
 407 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
 408                             unsigned size, unsigned alignment,
 409                             const void *data, unsigned *out_offset)
 410 {
 411         uint8_t *ptr;
 412
 413         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
 414                                           out_offset, (void **)&ptr))
 415                 return false;
 416
 417         if (ptr)
 418                 memcpy(ptr, data, size);
 419
 420         return true;
 421 }
 422
 423 static void
 424 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
 425                             unsigned count, const uint32_t *data)
 426 {
 427         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
 428         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
 429                     S_370_WR_CONFIRM(1) |
 430                     S_370_ENGINE_SEL(V_370_ME));
 431         radeon_emit(cs, va);
 432         radeon_emit(cs, va >> 32);
 433         radeon_emit_array(cs, data, count);
 434 }
 435
 436 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
 437 {
 438         struct radv_device *device = cmd_buffer->device;
 439         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 440         uint64_t va;
 441
 442         va = radv_buffer_get_va(device->trace_bo);
 443         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
 444                 va += 4;
 445
 446         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
 447
 448         ++cmd_buffer->state.trace_id;
 449         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 450         radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
 451         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
 452         radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
 453 }
 454
 455 static void
 456 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
 457                            enum radv_cmd_flush_bits flags)
 458 {
 459         if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
 460                 uint32_t *ptr = NULL;
 461                 uint64_t va = 0;
 462
 463                 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
 464                                 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
 465
 466                 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
 467                         va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
 468                              cmd_buffer->gfx9_fence_offset;
 469                         ptr = &cmd_buffer->gfx9_fence_idx;
 470                 }
 471
 472                 /* Force wait for graphics or compute engines to be idle. */
 473                 si_cs_emit_cache_flush(cmd_buffer->cs,
 474                                        cmd_buffer->device->physical_device->rad_info.chip_class,
 475                                        ptr, va,
 476                                        radv_cmd_buffer_uses_mec(cmd_buffer),
 477                                        flags);
 478         }
 479
 480         if (unlikely(cmd_buffer->device->trace_bo))
 481                 radv_cmd_buffer_trace_emit(cmd_buffer);
 482 }
 483
 484 static void
 485 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
 486                    struct radv_pipeline *pipeline, enum ring_type ring)
 487 {
 488         struct radv_device *device = cmd_buffer->device;
 489         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 490         uint32_t data[2];
 491         uint64_t va;
 492
 493         va = radv_buffer_get_va(device->trace_bo);
 494
 495         switch (ring) {
 496         case RING_GFX:
 497                 va += 8;
 498                 break;
 499         case RING_COMPUTE:
 500                 va += 16;
 501                 break;
 502         default:
 503                 assert(!"invalid ring type");
 504         }
 505
 506         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 507                                                            cmd_buffer->cs, 6);
 508
 509         data[0] = (uintptr_t)pipeline;
 510         data[1] = (uintptr_t)pipeline >> 32;
 511
 512         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 513         radv_emit_write_data_packet(cs, va, 2, data);
 514 }
 515
 516 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 517                              VkPipelineBindPoint bind_point,
 518                              struct radv_descriptor_set *set,
 519                              unsigned idx)
 520 {
 521         struct radv_descriptor_state *descriptors_state =
 522                 radv_get_descriptors_state(cmd_buffer, bind_point);
 523
 524         descriptors_state->sets[idx] = set;
 525         if (set)
 526                 descriptors_state->valid |= (1u << idx);
 527         else
 528                 descriptors_state->valid &= ~(1u << idx);
 529         descriptors_state->dirty |= (1u << idx);
 530 }
 531
 532 static void
 533 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
 534                       VkPipelineBindPoint bind_point)
 535 {
 536         struct radv_descriptor_state *descriptors_state =
 537                 radv_get_descriptors_state(cmd_buffer, bind_point);
 538         struct radv_device *device = cmd_buffer->device;
 539         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 540         uint32_t data[MAX_SETS * 2] = {};
 541         uint64_t va;
 542         unsigned i;
 543         va = radv_buffer_get_va(device->trace_bo) + 24;
 544
 545         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 546                                                            cmd_buffer->cs, 4 + MAX_SETS * 2);
 547
 548         for_each_bit(i, descriptors_state->valid) {
 549                 struct radv_descriptor_set *set = descriptors_state->sets[i];
 550                 data[i * 2] = (uintptr_t)set;
 551                 data[i * 2 + 1] = (uintptr_t)set >> 32;
 552         }
 553
 554         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 555         radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
 556 }
 557
 558 struct radv_userdata_info *
 559 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
 560                       gl_shader_stage stage,
 561                       int idx)
 562 {
 563         struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
 564         return &shader->info.user_sgprs_locs.shader_data[idx];
 565 }
 566
 567 static void
 568 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
 569                            struct radv_pipeline *pipeline,
 570                            gl_shader_stage stage,
 571                            int idx, uint64_t va)
 572 {
 573         struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
 574         uint32_t base_reg = pipeline->user_data_0[stage];
 575         if (loc->sgpr_idx == -1)
 576                 return;
 577
 578         assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
 579         assert(!loc->indirect);
 580
 581         radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
 582                                  base_reg + loc->sgpr_idx * 4, va, false);
 583 }
 584
 585 static void
 586 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
 587                               struct radv_pipeline *pipeline,
 588                               struct radv_descriptor_state *descriptors_state,
 589                               gl_shader_stage stage)
 590 {
 591         struct radv_device *device = cmd_buffer->device;
 592         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 593         uint32_t sh_base = pipeline->user_data_0[stage];
 594         struct radv_userdata_locations *locs =
 595                 &pipeline->shaders[stage]->info.user_sgprs_locs;
 596         unsigned mask;
 597
 598         mask = descriptors_state->dirty & descriptors_state->valid;
 599
 600         for (int i = 0; i < MAX_SETS; i++) {
 601                 struct radv_userdata_info *loc = &locs->descriptor_sets[i];
 602                 if (loc->sgpr_idx != -1 && !loc->indirect)
 603                         continue;
 604                 mask &= ~(1 << i);
 605         }
 606
 607         while (mask) {
 608                 int start, count;
 609
 610                 u_bit_scan_consecutive_range(&mask, &start, &count);
 611
 612                 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
 613                 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
 614
 615                 radv_emit_shader_pointer_head(cs, sh_offset, count,
 616                                               HAVE_32BIT_POINTERS);
 617                 for (int i = 0; i < count; i++) {
 618                         struct radv_descriptor_set *set =
 619                                 descriptors_state->sets[start + i];
 620
 621                         radv_emit_shader_pointer_body(device, cs, set->va,
 622                                                       HAVE_32BIT_POINTERS);
 623                 }
 624         }
 625 }
 626
 627 static void
 628 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
 629                               struct radv_pipeline *pipeline)
 630 {
 631         int num_samples = pipeline->graphics.ms.num_samples;
 632         struct radv_multisample_state *ms = &pipeline->graphics.ms;
 633         struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
 634
 635         if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
 636                 cmd_buffer->sample_positions_needed = true;
 637
 638         if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
 639                 return;
 640
 641         radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
 642         radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
 643         radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
 644
 645         radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
 646
 647         radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
 648
 649         /* GFX9: Flush DFSM when the AA mode changes. */
 650         if (cmd_buffer->device->dfsm_allowed) {
 651                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 652                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
 653         }
 654 }
 655
 656 static void
 657 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
 658                           struct radv_shader_variant *shader)
 659 {
 660         uint64_t va;
 661
 662         if (!shader)
 663                 return;
 664
 665         va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 666
 667         si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
 668 }
 669
 670 static void
 671 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
 672                       struct radv_pipeline *pipeline,
 673                       bool vertex_stage_only)
 674 {
 675         struct radv_cmd_state *state = &cmd_buffer->state;
 676         uint32_t mask = state->prefetch_L2_mask;
 677
 678         if (vertex_stage_only) {
 679                 /* Fast prefetch path for starting draws as soon as possible.
 680                  */
 681                 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
 682                                                   RADV_PREFETCH_VBO_DESCRIPTORS);
 683         }
 684
 685         if (mask & RADV_PREFETCH_VS)
 686                 radv_emit_shader_prefetch(cmd_buffer,
 687                                           pipeline->shaders[MESA_SHADER_VERTEX]);
 688
 689         if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
 690                 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
 691
 692         if (mask & RADV_PREFETCH_TCS)
 693                 radv_emit_shader_prefetch(cmd_buffer,
 694                                           pipeline->shaders[MESA_SHADER_TESS_CTRL]);
 695
 696         if (mask & RADV_PREFETCH_TES)
 697                 radv_emit_shader_prefetch(cmd_buffer,
 698                                           pipeline->shaders[MESA_SHADER_TESS_EVAL]);
 699
 700         if (mask & RADV_PREFETCH_GS) {
 701                 radv_emit_shader_prefetch(cmd_buffer,
 702                                           pipeline->shaders[MESA_SHADER_GEOMETRY]);
 703                 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
 704         }
 705
 706         if (mask & RADV_PREFETCH_PS)
 707                 radv_emit_shader_prefetch(cmd_buffer,
 708                                           pipeline->shaders[MESA_SHADER_FRAGMENT]);
 709
 710         state->prefetch_L2_mask &= ~mask;
 711 }
 712
 713 static void
 714 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
 715 {
 716         if (!cmd_buffer->device->physical_device->rbplus_allowed)
 717                 return;
 718
 719         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 720         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
 721         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 722
 723         unsigned sx_ps_downconvert = 0;
 724         unsigned sx_blend_opt_epsilon = 0;
 725         unsigned sx_blend_opt_control = 0;
 726
 727         for (unsigned i = 0; i < subpass->color_count; ++i) {
 728                 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
 729                         continue;
 730
 731                 int idx = subpass->color_attachments[i].attachment;
 732                 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
 733
 734                 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
 735                 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
 736                 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
 737                 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
 738
 739                 bool has_alpha, has_rgb;
 740
 741                 /* Set if RGB and A are present. */
 742                 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
 743
 744                 if (format == V_028C70_COLOR_8 ||
 745                     format == V_028C70_COLOR_16 ||
 746                     format == V_028C70_COLOR_32)
 747                         has_rgb = !has_alpha;
 748                 else
 749                         has_rgb = true;
 750
 751                 /* Check the colormask and export format. */
 752                 if (!(colormask & 0x7))
 753                         has_rgb = false;
 754                 if (!(colormask & 0x8))
 755                         has_alpha = false;
 756
 757                 if (spi_format == V_028714_SPI_SHADER_ZERO) {
 758                         has_rgb = false;
 759                         has_alpha = false;
 760                 }
 761
 762                 /* Disable value checking for disabled channels. */
 763                 if (!has_rgb)
 764                         sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 765                 if (!has_alpha)
 766                         sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 767
 768                 /* Enable down-conversion for 32bpp and smaller formats. */
 769                 switch (format) {
 770                 case V_028C70_COLOR_8:
 771                 case V_028C70_COLOR_8_8:
 772                 case V_028C70_COLOR_8_8_8_8:
 773                         /* For 1 and 2-channel formats, use the superset thereof. */
 774                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
 775                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 776                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 777                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
 778                                 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
 779                         }
 780                         break;
 781
 782                 case V_028C70_COLOR_5_6_5:
 783                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 784                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
 785                                 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
 786                         }
 787                         break;
 788
 789                 case V_028C70_COLOR_1_5_5_5:
 790                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 791                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
 792                                 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
 793                         }
 794                         break;
 795
 796                 case V_028C70_COLOR_4_4_4_4:
 797                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 798                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
 799                                 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
 800                         }
 801                         break;
 802
 803                 case V_028C70_COLOR_32:
 804                         if (swap == V_028C70_SWAP_STD &&
 805                             spi_format == V_028714_SPI_SHADER_32_R)
 806                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
 807                         else if (swap == V_028C70_SWAP_ALT_REV &&
 808                                  spi_format == V_028714_SPI_SHADER_32_AR)
 809                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
 810                         break;
 811
 812                 case V_028C70_COLOR_16:
 813                 case V_028C70_COLOR_16_16:
 814                         /* For 1-channel formats, use the superset thereof. */
 815                         if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
 816                             spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
 817                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 818                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 819                                 if (swap == V_028C70_SWAP_STD ||
 820                                     swap == V_028C70_SWAP_STD_REV)
 821                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
 822                                 else
 823                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
 824                         }
 825                         break;
 826
 827                 case V_028C70_COLOR_10_11_11:
 828                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 829                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
 830                                 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
 831                         }
 832                         break;
 833
 834                 case V_028C70_COLOR_2_10_10_10:
 835                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 836                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
 837                                 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
 838                         }
 839                         break;
 840                 }
 841         }
 842
 843         radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
 844         radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
 845         radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
 846         radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
 847 }
 848
 849 static void
 850 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
 851 {
 852         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 853
 854         if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
 855                 return;
 856
 857         radv_update_multisample_state(cmd_buffer, pipeline);
 858
 859         cmd_buffer->scratch_size_needed =
 860                                   MAX2(cmd_buffer->scratch_size_needed,
 861                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
 862
 863         if (!cmd_buffer->state.emitted_pipeline ||
 864             cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
 865              pipeline->graphics.can_use_guardband)
 866                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
 867
 868         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
 869
 870         for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
 871                 if (!pipeline->shaders[i])
 872                         continue;
 873
 874                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 875                                    pipeline->shaders[i]->bo, 8);
 876         }
 877
 878         if (radv_pipeline_has_gs(pipeline))
 879                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 880                                    pipeline->gs_copy_shader->bo, 8);
 881
 882         if (unlikely(cmd_buffer->device->trace_bo))
 883                 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
 884
 885         cmd_buffer->state.emitted_pipeline = pipeline;
 886
 887         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
 888 }
 889
 890 static void
 891 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
 892 {
 893         si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
 894                           cmd_buffer->state.dynamic.viewport.viewports);
 895 }
 896
 897 static void
 898 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
 899 {
 900         uint32_t count = cmd_buffer->state.dynamic.scissor.count;
 901
 902         si_write_scissors(cmd_buffer->cs, 0, count,
 903                           cmd_buffer->state.dynamic.scissor.scissors,
 904                           cmd_buffer->state.dynamic.viewport.viewports,
 905                           cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
 906 }
 907
 908 static void
 909 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
 910 {
 911         if (!cmd_buffer->state.dynamic.discard_rectangle.count)
 912                 return;
 913
 914         radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
 915                                    cmd_buffer->state.dynamic.discard_rectangle.count * 2);
 916         for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
 917                 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
 918                 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
 919                 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
 920                                             S_028214_BR_Y(rect.offset.y + rect.extent.height));
 921         }
 922 }
 923
 924 static void
 925 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
 926 {
 927         unsigned width = cmd_buffer->state.dynamic.line_width * 8;
 928
 929         radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
 930                                S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
 931 }
 932
 933 static void
 934 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
 935 {
 936         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 937
 938         radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
 939         radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
 940 }
 941
 942 static void
 943 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
 944 {
 945         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 946
 947         radeon_set_context_reg_seq(cmd_buffer->cs,
 948                                    R_028430_DB_STENCILREFMASK, 2);
 949         radeon_emit(cmd_buffer->cs,
 950                     S_028430_STENCILTESTVAL(d->stencil_reference.front) |
 951                     S_028430_STENCILMASK(d->stencil_compare_mask.front) |
 952                     S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
 953                     S_028430_STENCILOPVAL(1));
 954         radeon_emit(cmd_buffer->cs,
 955                     S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
 956                     S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
 957                     S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
 958                     S_028434_STENCILOPVAL_BF(1));
 959 }
 960
 961 static void
 962 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
 963 {
 964         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 965
 966         radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
 967                                fui(d->depth_bounds.min));
 968         radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
 969                                fui(d->depth_bounds.max));
 970 }
 971
 972 static void
 973 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
 974 {
 975         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 976         unsigned slope = fui(d->depth_bias.slope * 16.0f);
 977         unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
 978
 979
 980         radeon_set_context_reg_seq(cmd_buffer->cs,
 981                                    R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
 982         radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
 983         radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
 984         radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
 985         radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
 986         radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
 987 }
 988
 989 static void
 990 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
 991                          int index,
 992                          struct radv_attachment_info *att,
 993                          struct radv_image *image,
 994                          VkImageLayout layout)
 995 {
 996         bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
 997         struct radv_color_buffer_info *cb = &att->cb;
 998         uint32_t cb_color_info = cb->cb_color_info;
 999
1000         if (!radv_layout_dcc_compressed(image, layout,
1001                                         radv_image_queue_family_mask(image,
1002                                                                      cmd_buffer->queue_family_index,
1003                                                                      cmd_buffer->queue_family_index))) {
1004                 cb_color_info &= C_028C70_DCC_ENABLE;
1005         }
1006
1007         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1008                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1009                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1010                 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1011                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1012                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1013                 radeon_emit(cmd_buffer->cs, cb_color_info);
1014                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1015                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1016                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1017                 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1018                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1019                 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1020
1021                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1022                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1023                 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1024
1025                 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1026                                        S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1027         } else {
1028                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1029                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1030                 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1031                 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1032                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1033                 radeon_emit(cmd_buffer->cs, cb_color_info);
1034                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1035                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1036                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1037                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1038                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1039                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1040
1041                 if (is_vi) { /* DCC BASE */
1042                         radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1043                 }
1044         }
1045 }
1046
1047 static void
1048 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1049                       struct radv_ds_buffer_info *ds,
1050                       struct radv_image *image,
1051                       VkImageLayout layout)
1052 {
1053         uint32_t db_z_info = ds->db_z_info;
1054         uint32_t db_stencil_info = ds->db_stencil_info;
1055
1056         if (!radv_layout_has_htile(image, layout,
1057                                    radv_image_queue_family_mask(image,
1058                                                                 cmd_buffer->queue_family_index,
1059                                                                 cmd_buffer->queue_family_index))) {
1060                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1061                 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1062         }
1063
1064         radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1065         radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1066
1067
1068         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1069                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1070                 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1071                 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1072                 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1073
1074                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1075                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* DB_Z_INFO */
1076                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* DB_STENCIL_INFO */
1077                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* DB_Z_READ_BASE */
1078                 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32));        /* DB_Z_READ_BASE_HI */
1079                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* DB_STENCIL_READ_BASE */
1080                 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1081                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* DB_Z_WRITE_BASE */
1082                 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32));       /* DB_Z_WRITE_BASE_HI */
1083                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1084                 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1085
1086                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1087                 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1088                 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1089         } else {
1090                 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1091
1092                 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1093                 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1094                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* R_028040_DB_Z_INFO */
1095                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* R_028044_DB_STENCIL_INFO */
1096                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* R_028048_DB_Z_READ_BASE */
1097                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* R_02804C_DB_STENCIL_READ_BASE */
1098                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* R_028050_DB_Z_WRITE_BASE */
1099                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1100                 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1101                 radeon_emit(cmd_buffer->cs, ds->db_depth_slice);        /* R_02805C_DB_DEPTH_SLICE */
1102
1103         }
1104
1105         radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1106                                ds->pa_su_poly_offset_db_fmt_cntl);
1107 }
1108
1109 void
1110 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1111                           struct radv_image *image,
1112                           VkClearDepthStencilValue ds_clear_value,
1113                           VkImageAspectFlags aspects)
1114 {
1115         uint64_t va = radv_buffer_get_va(image->bo);
1116         va += image->offset + image->clear_value_offset;
1117         unsigned reg_offset = 0, reg_count = 0;
1118
1119         assert(radv_image_has_htile(image));
1120
1121         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1122                 ++reg_count;
1123         } else {
1124                 ++reg_offset;
1125                 va += 4;
1126         }
1127         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1128                 ++reg_count;
1129
1130         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1131         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1132                                     S_370_WR_CONFIRM(1) |
1133                                     S_370_ENGINE_SEL(V_370_PFP));
1134         radeon_emit(cmd_buffer->cs, va);
1135         radeon_emit(cmd_buffer->cs, va >> 32);
1136         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1137                 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1138         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1139                 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1140
1141         radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1142         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1143                 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1144         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1145                 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1146 }
1147
1148 static void
1149 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1150                            struct radv_image *image)
1151 {
1152         VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1153         uint64_t va = radv_buffer_get_va(image->bo);
1154         va += image->offset + image->clear_value_offset;
1155         unsigned reg_offset = 0, reg_count = 0;
1156
1157         if (!radv_image_has_htile(image))
1158                 return;
1159
1160         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1161                 ++reg_count;
1162         } else {
1163                 ++reg_offset;
1164                 va += 4;
1165         }
1166         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1167                 ++reg_count;
1168
1169         radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1170         radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1171                                     COPY_DATA_DST_SEL(COPY_DATA_REG) |
1172                                     (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1173         radeon_emit(cmd_buffer->cs, va);
1174         radeon_emit(cmd_buffer->cs, va >> 32);
1175         radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1176         radeon_emit(cmd_buffer->cs, 0);
1177
1178         radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1179         radeon_emit(cmd_buffer->cs, 0);
1180 }
1181
1182 /*
1183  * With DCC some colors don't require CMASK elimination before being
1184  * used as a texture. This sets a predicate value to determine if the
1185  * cmask eliminate is required.
1186  */
1187 void
1188 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1189                                   struct radv_image *image,
1190                                   bool value)
1191 {
1192         uint64_t pred_val = value;
1193         uint64_t va = radv_buffer_get_va(image->bo);
1194         va += image->offset + image->dcc_pred_offset;
1195
1196         assert(radv_image_has_dcc(image));
1197
1198         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1199         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1200                                     S_370_WR_CONFIRM(1) |
1201                                     S_370_ENGINE_SEL(V_370_PFP));
1202         radeon_emit(cmd_buffer->cs, va);
1203         radeon_emit(cmd_buffer->cs, va >> 32);
1204         radeon_emit(cmd_buffer->cs, pred_val);
1205         radeon_emit(cmd_buffer->cs, pred_val >> 32);
1206 }
1207
1208 void
1209 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1210                           struct radv_image *image,
1211                           int idx,
1212                           uint32_t color_values[2])
1213 {
1214         uint64_t va = radv_buffer_get_va(image->bo);
1215         va += image->offset + image->clear_value_offset;
1216
1217         assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1218
1219         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1220         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1221                                     S_370_WR_CONFIRM(1) |
1222                                     S_370_ENGINE_SEL(V_370_PFP));
1223         radeon_emit(cmd_buffer->cs, va);
1224         radeon_emit(cmd_buffer->cs, va >> 32);
1225         radeon_emit(cmd_buffer->cs, color_values[0]);
1226         radeon_emit(cmd_buffer->cs, color_values[1]);
1227
1228         radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1229         radeon_emit(cmd_buffer->cs, color_values[0]);
1230         radeon_emit(cmd_buffer->cs, color_values[1]);
1231 }
1232
1233 static void
1234 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1235                            struct radv_image *image,
1236                            int idx)
1237 {
1238         uint64_t va = radv_buffer_get_va(image->bo);
1239         va += image->offset + image->clear_value_offset;
1240
1241         if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1242                 return;
1243
1244         uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1245
1246         radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1247         radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1248                                     COPY_DATA_DST_SEL(COPY_DATA_REG) |
1249                                     COPY_DATA_COUNT_SEL);
1250         radeon_emit(cmd_buffer->cs, va);
1251         radeon_emit(cmd_buffer->cs, va >> 32);
1252         radeon_emit(cmd_buffer->cs, reg >> 2);
1253         radeon_emit(cmd_buffer->cs, 0);
1254
1255         radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1256         radeon_emit(cmd_buffer->cs, 0);
1257 }
1258
1259 static void
1260 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1261 {
1262         int i;
1263         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1264         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1265
1266         /* this may happen for inherited secondary recording */
1267         if (!framebuffer)
1268                 return;
1269
1270         for (i = 0; i < 8; ++i) {
1271                 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1272                         radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1273                                        S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1274                         continue;
1275                 }
1276
1277                 int idx = subpass->color_attachments[i].attachment;
1278                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1279                 struct radv_image *image = att->attachment->image;
1280                 VkImageLayout layout = subpass->color_attachments[i].layout;
1281
1282                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1283
1284                 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1285                 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1286
1287                 radv_load_color_clear_regs(cmd_buffer, image, i);
1288         }
1289
1290         if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1291                 int idx = subpass->depth_stencil_attachment.attachment;
1292                 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1293                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1294                 struct radv_image *image = att->attachment->image;
1295                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1296                 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1297                                                                                 cmd_buffer->queue_family_index,
1298                                                                                 cmd_buffer->queue_family_index);
1299                 /* We currently don't support writing decompressed HTILE */
1300                 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1301                        radv_layout_is_htile_compressed(image, layout, queue_mask));
1302
1303                 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1304
1305                 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1306                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1307                         cmd_buffer->state.offset_scale = att->ds.offset_scale;
1308                 }
1309                 radv_load_depth_clear_regs(cmd_buffer, image);
1310         } else {
1311                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1312                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1313                 else
1314                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1315
1316                 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1317                 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1318         }
1319         radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1320                                S_028208_BR_X(framebuffer->width) |
1321                                S_028208_BR_Y(framebuffer->height));
1322
1323         if (cmd_buffer->device->dfsm_allowed) {
1324                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1325                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1326         }
1327
1328         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1329 }
1330
1331 static void
1332 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1333 {
1334         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1335         struct radv_cmd_state *state = &cmd_buffer->state;
1336
1337         if (state->index_type != state->last_index_type) {
1338                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1339                         radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1340                                                    2, state->index_type);
1341                 } else {
1342                         radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1343                         radeon_emit(cs, state->index_type);
1344                 }
1345
1346                 state->last_index_type = state->index_type;
1347         }
1348
1349         radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1350         radeon_emit(cs, state->index_va);
1351         radeon_emit(cs, state->index_va >> 32);
1352
1353         radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1354         radeon_emit(cs, state->max_index_count);
1355
1356         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1357 }
1358
1359 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1360 {
1361         bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1362         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1363         uint32_t pa_sc_mode_cntl_1 =
1364                 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1365         uint32_t db_count_control;
1366
1367         if(!cmd_buffer->state.active_occlusion_queries) {
1368                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1369                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1370                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1371                             has_perfect_queries) {
1372                                 /* Re-enable out-of-order rasterization if the
1373                                  * bound pipeline supports it and if it's has
1374                                  * been disabled before starting any perfect
1375                                  * occlusion queries.
1376                                  */
1377                                 radeon_set_context_reg(cmd_buffer->cs,
1378                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1379                                                        pa_sc_mode_cntl_1);
1380                         }
1381                         db_count_control = 0;
1382                 } else {
1383                         db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1384                 }
1385         } else {
1386                 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1387                 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1388
1389                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1390                         db_count_control =
1391                                 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1392                                 S_028004_SAMPLE_RATE(sample_rate) |
1393                                 S_028004_ZPASS_ENABLE(1) |
1394                                 S_028004_SLICE_EVEN_ENABLE(1) |
1395                                 S_028004_SLICE_ODD_ENABLE(1);
1396
1397                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1398                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1399                             has_perfect_queries) {
1400                                 /* If the bound pipeline has enabled
1401                                  * out-of-order rasterization, we should
1402                                  * disable it before starting any perfect
1403                                  * occlusion queries.
1404                                  */
1405                                 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1406
1407                                 radeon_set_context_reg(cmd_buffer->cs,
1408                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1409                                                        pa_sc_mode_cntl_1);
1410                         }
1411                 } else {
1412                         db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1413                                 S_028004_SAMPLE_RATE(sample_rate);
1414                 }
1415         }
1416
1417         radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1418 }
1419
1420 static void
1421 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1422 {
1423         uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1424
1425         if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1426                 radv_emit_viewport(cmd_buffer);
1427
1428         if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1429             !cmd_buffer->device->physical_device->has_scissor_bug)
1430                 radv_emit_scissor(cmd_buffer);
1431
1432         if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1433                 radv_emit_line_width(cmd_buffer);
1434
1435         if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1436                 radv_emit_blend_constants(cmd_buffer);
1437
1438         if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1439                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1440                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1441                 radv_emit_stencil(cmd_buffer);
1442
1443         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1444                 radv_emit_depth_bounds(cmd_buffer);
1445
1446         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1447                 radv_emit_depth_bias(cmd_buffer);
1448
1449         if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1450                 radv_emit_discard_rectangle(cmd_buffer);
1451
1452         cmd_buffer->state.dirty &= ~states;
1453 }
1454
1455 static void
1456 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1457                             VkPipelineBindPoint bind_point)
1458 {
1459         struct radv_descriptor_state *descriptors_state =
1460                 radv_get_descriptors_state(cmd_buffer, bind_point);
1461         struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1462         unsigned bo_offset;
1463
1464         if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1465                                          set->mapped_ptr,
1466                                          &bo_offset))
1467                 return;
1468
1469         set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1470         set->va += bo_offset;
1471 }
1472
1473 static void
1474 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1475                                     VkPipelineBindPoint bind_point)
1476 {
1477         struct radv_descriptor_state *descriptors_state =
1478                 radv_get_descriptors_state(cmd_buffer, bind_point);
1479         uint32_t size = MAX_SETS * 2 * 4;
1480         uint32_t offset;
1481         void *ptr;
1482
1483         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1484                                           256, &offset, &ptr))
1485                 return;
1486
1487         for (unsigned i = 0; i < MAX_SETS; i++) {
1488                 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1489                 uint64_t set_va = 0;
1490                 struct radv_descriptor_set *set = descriptors_state->sets[i];
1491                 if (descriptors_state->valid & (1u << i))
1492                         set_va = set->va;
1493                 uptr[0] = set_va & 0xffffffff;
1494                 uptr[1] = set_va >> 32;
1495         }
1496
1497         uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1498         va += offset;
1499
1500         if (cmd_buffer->state.pipeline) {
1501                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1502                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1503                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1504
1505                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1506                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1507                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1508
1509                 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1510                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1511                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1512
1513                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1514                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1515                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1516
1517                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1518                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1519                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1520         }
1521
1522         if (cmd_buffer->state.compute_pipeline)
1523                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1524                                            AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1525 }
1526
1527 static void
1528 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1529                        VkShaderStageFlags stages)
1530 {
1531         VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1532                                          VK_PIPELINE_BIND_POINT_COMPUTE :
1533                                          VK_PIPELINE_BIND_POINT_GRAPHICS;
1534         struct radv_descriptor_state *descriptors_state =
1535                 radv_get_descriptors_state(cmd_buffer, bind_point);
1536
1537         if (!descriptors_state->dirty)
1538                 return;
1539
1540         if (descriptors_state->push_dirty)
1541                 radv_flush_push_descriptors(cmd_buffer, bind_point);
1542
1543         if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1544             (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1545                 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1546         }
1547
1548         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1549                                                            cmd_buffer->cs,
1550                                                            MAX_SETS * MESA_SHADER_STAGES * 4);
1551
1552         if (cmd_buffer->state.pipeline) {
1553                 radv_foreach_stage(stage, stages) {
1554                         if (!cmd_buffer->state.pipeline->shaders[stage])
1555                                 continue;
1556
1557                         radv_emit_descriptor_pointers(cmd_buffer,
1558                                                       cmd_buffer->state.pipeline,
1559                                                       descriptors_state, stage);
1560                 }
1561         }
1562
1563         if (cmd_buffer->state.compute_pipeline &&
1564             (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1565                 radv_emit_descriptor_pointers(cmd_buffer,
1566                                               cmd_buffer->state.compute_pipeline,
1567                                               descriptors_state,
1568                                               MESA_SHADER_COMPUTE);
1569         }
1570
1571         descriptors_state->dirty = 0;
1572         descriptors_state->push_dirty = false;
1573
1574         if (unlikely(cmd_buffer->device->trace_bo))
1575                 radv_save_descriptors(cmd_buffer, bind_point);
1576
1577         assert(cmd_buffer->cs->cdw <= cdw_max);
1578 }
1579
1580 static void
1581 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1582                      VkShaderStageFlags stages)
1583 {
1584         struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1585                                          ? cmd_buffer->state.compute_pipeline
1586                                          : cmd_buffer->state.pipeline;
1587         struct radv_pipeline_layout *layout = pipeline->layout;
1588         struct radv_shader_variant *shader, *prev_shader;
1589         unsigned offset;
1590         void *ptr;
1591         uint64_t va;
1592
1593         stages &= cmd_buffer->push_constant_stages;
1594         if (!stages ||
1595             (!layout->push_constant_size && !layout->dynamic_offset_count))
1596                 return;
1597
1598         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1599                                           16 * layout->dynamic_offset_count,
1600                                           256, &offset, &ptr))
1601                 return;
1602
1603         memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1604         memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1605                16 * layout->dynamic_offset_count);
1606
1607         va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1608         va += offset;
1609
1610         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1611                                                            cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1612
1613         prev_shader = NULL;
1614         radv_foreach_stage(stage, stages) {
1615                 shader = radv_get_shader(pipeline, stage);
1616
1617                 /* Avoid redundantly emitting the address for merged stages. */
1618                 if (shader && shader != prev_shader) {
1619                         radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1620                                                    AC_UD_PUSH_CONSTANTS, va);
1621
1622                         prev_shader = shader;
1623                 }
1624         }
1625
1626         cmd_buffer->push_constant_stages &= ~stages;
1627         assert(cmd_buffer->cs->cdw <= cdw_max);
1628 }
1629
1630 static void
1631 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1632                               bool pipeline_is_dirty)
1633 {
1634         if ((pipeline_is_dirty ||
1635             (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1636             cmd_buffer->state.pipeline->vertex_elements.count &&
1637             radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1638                 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1639                 unsigned vb_offset;
1640                 void *vb_ptr;
1641                 uint32_t i = 0;
1642                 uint32_t count = velems->count;
1643                 uint64_t va;
1644
1645                 /* allocate some descriptor state for vertex buffers */
1646                 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1647                                                   &vb_offset, &vb_ptr))
1648                         return;
1649
1650                 for (i = 0; i < count; i++) {
1651                         uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1652                         uint32_t offset;
1653                         int vb = velems->binding[i];
1654                         struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1655                         uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1656
1657                         va = radv_buffer_get_va(buffer->bo);
1658
1659                         offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1660                         va += offset + buffer->offset;
1661                         desc[0] = va;
1662                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1663                         if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1664                                 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1665                         else
1666                                 desc[2] = buffer->size - offset;
1667                         desc[3] = velems->rsrc_word3[i];
1668                 }
1669
1670                 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1671                 va += vb_offset;
1672
1673                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1674                                            AC_UD_VS_VERTEX_BUFFERS, va);
1675
1676                 cmd_buffer->state.vb_va = va;
1677                 cmd_buffer->state.vb_size = count * 16;
1678                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1679         }
1680         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1681 }
1682
1683 static void
1684 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1685 {
1686         radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1687         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1688         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1689 }
1690
1691 static void
1692 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1693                          bool instanced_draw, bool indirect_draw,
1694                          uint32_t draw_vertex_count)
1695 {
1696         struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1697         struct radv_cmd_state *state = &cmd_buffer->state;
1698         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1699         uint32_t ia_multi_vgt_param;
1700         int32_t primitive_reset_en;
1701
1702         /* Draw state. */
1703         ia_multi_vgt_param =
1704                 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1705                                           indirect_draw, draw_vertex_count);
1706
1707         if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1708                 if (info->chip_class >= GFX9) {
1709                         radeon_set_uconfig_reg_idx(cs,
1710                                                    R_030960_IA_MULTI_VGT_PARAM,
1711                                                    4, ia_multi_vgt_param);
1712                 } else if (info->chip_class >= CIK) {
1713                         radeon_set_context_reg_idx(cs,
1714                                                    R_028AA8_IA_MULTI_VGT_PARAM,
1715                                                    1, ia_multi_vgt_param);
1716                 } else {
1717                         radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1718                                                ia_multi_vgt_param);
1719                 }
1720                 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1721         }
1722
1723         /* Primitive restart. */
1724         primitive_reset_en =
1725                 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1726
1727         if (primitive_reset_en != state->last_primitive_reset_en) {
1728                 state->last_primitive_reset_en = primitive_reset_en;
1729                 if (info->chip_class >= GFX9) {
1730                         radeon_set_uconfig_reg(cs,
1731                                                R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1732                                                primitive_reset_en);
1733                 } else {
1734                         radeon_set_context_reg(cs,
1735                                                R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1736                                                primitive_reset_en);
1737                 }
1738         }
1739
1740         if (primitive_reset_en) {
1741                 uint32_t primitive_reset_index =
1742                         state->index_type ? 0xffffffffu : 0xffffu;
1743
1744                 if (primitive_reset_index != state->last_primitive_reset_index) {
1745                         radeon_set_context_reg(cs,
1746                                                R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1747                                                primitive_reset_index);
1748                         state->last_primitive_reset_index = primitive_reset_index;
1749                 }
1750         }
1751 }
1752
1753 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1754                              VkPipelineStageFlags src_stage_mask)
1755 {
1756         if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1757                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1758                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1759                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1760                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1761         }
1762
1763         if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1764                               VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1765                               VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1766                               VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1767                               VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1768                               VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1769                               VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1770                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1771                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1772                               VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1773                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1774                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1775         } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1776                                      VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1777                                      VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1778                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1779         }
1780 }
1781
1782 static enum radv_cmd_flush_bits
1783 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1784                                   VkAccessFlags src_flags)
1785 {
1786         enum radv_cmd_flush_bits flush_bits = 0;
1787         uint32_t b;
1788         for_each_bit(b, src_flags) {
1789                 switch ((VkAccessFlagBits)(1 << b)) {
1790                 case VK_ACCESS_SHADER_WRITE_BIT:
1791                         flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1792                         break;
1793                 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1794                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1795                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1796                         break;
1797                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1798                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1799                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1800                         break;
1801                 case VK_ACCESS_TRANSFER_WRITE_BIT:
1802                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1803                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1804                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1805                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1806                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
1807                         break;
1808                 default:
1809                         break;
1810                 }
1811         }
1812         return flush_bits;
1813 }
1814
1815 static enum radv_cmd_flush_bits
1816 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1817                       VkAccessFlags dst_flags,
1818                       struct radv_image *image)
1819 {
1820         enum radv_cmd_flush_bits flush_bits = 0;
1821         uint32_t b;
1822         for_each_bit(b, dst_flags) {
1823                 switch ((VkAccessFlagBits)(1 << b)) {
1824                 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1825                 case VK_ACCESS_INDEX_READ_BIT:
1826                         break;
1827                 case VK_ACCESS_UNIFORM_READ_BIT:
1828                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1829                         break;
1830                 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1831                 case VK_ACCESS_SHADER_READ_BIT:
1832                 case VK_ACCESS_TRANSFER_READ_BIT:
1833                 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1834                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1835                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
1836                         break;
1837                 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1838                         /* TODO: change to image && when the image gets passed
1839                          * through from the subpass. */
1840                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1841                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1842                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1843                         break;
1844                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1845                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1846                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1847                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1848                         break;
1849                 default:
1850                         break;
1851                 }
1852         }
1853         return flush_bits;
1854 }
1855
1856 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1857 {
1858         cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1859         radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1860         cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1861                                                               NULL);
1862 }
1863
1864 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1865                                                  VkAttachmentReference att)
1866 {
1867         unsigned idx = att.attachment;
1868         struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1869         VkImageSubresourceRange range;
1870         range.aspectMask = 0;
1871         range.baseMipLevel = view->base_mip;
1872         range.levelCount = 1;
1873         range.baseArrayLayer = view->base_layer;
1874         range.layerCount = cmd_buffer->state.framebuffer->layers;
1875
1876         radv_handle_image_transition(cmd_buffer,
1877                                      view->image,
1878                                      cmd_buffer->state.attachments[idx].current_layout,
1879                                      att.layout, 0, 0, &range,
1880                                      cmd_buffer->state.attachments[idx].pending_clear_aspects);
1881
1882         cmd_buffer->state.attachments[idx].current_layout = att.layout;
1883
1884
1885 }
1886
1887 void
1888 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1889                             const struct radv_subpass *subpass, bool transitions)
1890 {
1891         if (transitions) {
1892                 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1893
1894                 for (unsigned i = 0; i < subpass->color_count; ++i) {
1895                         if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1896                                 radv_handle_subpass_image_transition(cmd_buffer,
1897                                                                      subpass->color_attachments[i]);
1898                 }
1899
1900                 for (unsigned i = 0; i < subpass->input_count; ++i) {
1901                         radv_handle_subpass_image_transition(cmd_buffer,
1902                                                         subpass->input_attachments[i]);
1903                 }
1904
1905                 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1906                         radv_handle_subpass_image_transition(cmd_buffer,
1907                                                         subpass->depth_stencil_attachment);
1908                 }
1909         }
1910
1911         cmd_buffer->state.subpass = subpass;
1912
1913         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
1914 }
1915
1916 static VkResult
1917 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1918                                  struct radv_render_pass *pass,
1919                                  const VkRenderPassBeginInfo *info)
1920 {
1921         struct radv_cmd_state *state = &cmd_buffer->state;
1922
1923         if (pass->attachment_count == 0) {
1924                 state->attachments = NULL;
1925                 return VK_SUCCESS;
1926         }
1927
1928         state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1929                                         pass->attachment_count *
1930                                         sizeof(state->attachments[0]),
1931                                         8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1932         if (state->attachments == NULL) {
1933                 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1934                 return cmd_buffer->record_result;
1935         }
1936
1937         for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1938                 struct radv_render_pass_attachment *att = &pass->attachments[i];
1939                 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1940                 VkImageAspectFlags clear_aspects = 0;
1941
1942                 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1943                         /* color attachment */
1944                         if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1945                                 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1946                         }
1947                 } else {
1948                         /* depthstencil attachment */
1949                         if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1950                             att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1951                                 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1952                                 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1953                                     att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1954                                         clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1955                         }
1956                         if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1957                             att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1958                                 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1959                         }
1960                 }
1961
1962                 state->attachments[i].pending_clear_aspects = clear_aspects;
1963                 state->attachments[i].cleared_views = 0;
1964                 if (clear_aspects && info) {
1965                         assert(info->clearValueCount > i);
1966                         state->attachments[i].clear_value = info->pClearValues[i];
1967                 }
1968
1969                 state->attachments[i].current_layout = att->initial_layout;
1970         }
1971
1972         return VK_SUCCESS;
1973 }
1974
1975 VkResult radv_AllocateCommandBuffers(
1976         VkDevice _device,
1977         const VkCommandBufferAllocateInfo *pAllocateInfo,
1978         VkCommandBuffer *pCommandBuffers)
1979 {
1980         RADV_FROM_HANDLE(radv_device, device, _device);
1981         RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1982
1983         VkResult result = VK_SUCCESS;
1984         uint32_t i;
1985
1986         for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1987
1988                 if (!list_empty(&pool->free_cmd_buffers)) {
1989                         struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1990
1991                         list_del(&cmd_buffer->pool_link);
1992                         list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1993
1994                         result = radv_reset_cmd_buffer(cmd_buffer);
1995                         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1996                         cmd_buffer->level = pAllocateInfo->level;
1997
1998                         pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1999                 } else {
2000                         result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2001                                                         &pCommandBuffers[i]);
2002                 }
2003                 if (result != VK_SUCCESS)
2004                         break;
2005         }
2006
2007         if (result != VK_SUCCESS) {
2008                 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2009                                         i, pCommandBuffers);
2010
2011                 /* From the Vulkan 1.0.66 spec:
2012                  *
2013                  * "vkAllocateCommandBuffers can be used to create multiple
2014                  *  command buffers. If the creation of any of those command
2015                  *  buffers fails, the implementation must destroy all
2016                  *  successfully created command buffer objects from this
2017                  *  command, set all entries of the pCommandBuffers array to
2018                  *  NULL and return the error."
2019                  */
2020                 memset(pCommandBuffers, 0,
2021                        sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2022         }
2023
2024         return result;
2025 }
2026
2027 void radv_FreeCommandBuffers(
2028         VkDevice device,
2029         VkCommandPool commandPool,
2030         uint32_t commandBufferCount,
2031         const VkCommandBuffer *pCommandBuffers)
2032 {
2033         for (uint32_t i = 0; i < commandBufferCount; i++) {
2034                 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2035
2036                 if (cmd_buffer) {
2037                         if (cmd_buffer->pool) {
2038                                 list_del(&cmd_buffer->pool_link);
2039                                 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2040                         } else
2041                                 radv_cmd_buffer_destroy(cmd_buffer);
2042
2043                 }
2044         }
2045 }
2046
2047 VkResult radv_ResetCommandBuffer(
2048         VkCommandBuffer commandBuffer,
2049         VkCommandBufferResetFlags flags)
2050 {
2051         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2052         return radv_reset_cmd_buffer(cmd_buffer);
2053 }
2054
2055 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2056 {
2057         struct radv_device *device = cmd_buffer->device;
2058         if (device->gfx_init) {
2059                 uint64_t va = radv_buffer_get_va(device->gfx_init);
2060                 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2061                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2062                 radeon_emit(cmd_buffer->cs, va);
2063                 radeon_emit(cmd_buffer->cs, va >> 32);
2064                 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2065         } else
2066                 si_init_config(cmd_buffer);
2067 }
2068
2069 VkResult radv_BeginCommandBuffer(
2070         VkCommandBuffer commandBuffer,
2071         const VkCommandBufferBeginInfo *pBeginInfo)
2072 {
2073         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2074         VkResult result = VK_SUCCESS;
2075
2076         if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2077                 /* If the command buffer has already been resetted with
2078                  * vkResetCommandBuffer, no need to do it again.
2079                  */
2080                 result = radv_reset_cmd_buffer(cmd_buffer);
2081                 if (result != VK_SUCCESS)
2082                         return result;
2083         }
2084
2085         memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2086         cmd_buffer->state.last_primitive_reset_en = -1;
2087         cmd_buffer->state.last_index_type = -1;
2088         cmd_buffer->state.last_num_instances = -1;
2089         cmd_buffer->state.last_vertex_offset = -1;
2090         cmd_buffer->state.last_first_instance = -1;
2091         cmd_buffer->usage_flags = pBeginInfo->flags;
2092
2093         /* setup initial configuration into command buffer */
2094         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2095                 switch (cmd_buffer->queue_family_index) {
2096                 case RADV_QUEUE_GENERAL:
2097                         emit_gfx_buffer_state(cmd_buffer);
2098                         break;
2099                 case RADV_QUEUE_COMPUTE:
2100                         si_init_compute(cmd_buffer);
2101                         break;
2102                 case RADV_QUEUE_TRANSFER:
2103                 default:
2104                         break;
2105                 }
2106         }
2107
2108         if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2109                 assert(pBeginInfo->pInheritanceInfo);
2110                 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2111                 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2112
2113                 struct radv_subpass *subpass =
2114                         &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2115
2116                 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2117                 if (result != VK_SUCCESS)
2118                         return result;
2119
2120                 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2121         }
2122
2123         if (unlikely(cmd_buffer->device->trace_bo))
2124                 radv_cmd_buffer_trace_emit(cmd_buffer);
2125
2126         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2127
2128         return result;
2129 }
2130
2131 void radv_CmdBindVertexBuffers(
2132         VkCommandBuffer                             commandBuffer,
2133         uint32_t                                    firstBinding,
2134         uint32_t                                    bindingCount,
2135         const VkBuffer*                             pBuffers,
2136         const VkDeviceSize*                         pOffsets)
2137 {
2138         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2139         struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2140         bool changed = false;
2141
2142         /* We have to defer setting up vertex buffer since we need the buffer
2143          * stride from the pipeline. */
2144
2145         assert(firstBinding + bindingCount <= MAX_VBS);
2146         for (uint32_t i = 0; i < bindingCount; i++) {
2147                 uint32_t idx = firstBinding + i;
2148
2149                 if (!changed &&
2150                     (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2151                      vb[idx].offset != pOffsets[i])) {
2152                         changed = true;
2153                 }
2154
2155                 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2156                 vb[idx].offset = pOffsets[i];
2157
2158                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2159                                    vb[idx].buffer->bo, 8);
2160         }
2161
2162         if (!changed) {
2163                 /* No state changes. */
2164                 return;
2165         }
2166
2167         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2168 }
2169
2170 void radv_CmdBindIndexBuffer(
2171         VkCommandBuffer                             commandBuffer,
2172         VkBuffer buffer,
2173         VkDeviceSize offset,
2174         VkIndexType indexType)
2175 {
2176         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2177         RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2178
2179         if (cmd_buffer->state.index_buffer == index_buffer &&
2180             cmd_buffer->state.index_offset == offset &&
2181             cmd_buffer->state.index_type == indexType) {
2182                 /* No state changes. */
2183                 return;
2184         }
2185
2186         cmd_buffer->state.index_buffer = index_buffer;
2187         cmd_buffer->state.index_offset = offset;
2188         cmd_buffer->state.index_type = indexType; /* vk matches hw */
2189         cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2190         cmd_buffer->state.index_va += index_buffer->offset + offset;
2191
2192         int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2193         cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2194         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2195         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2196 }
2197
2198
2199 static void
2200 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2201                          VkPipelineBindPoint bind_point,
2202                          struct radv_descriptor_set *set, unsigned idx)
2203 {
2204         struct radeon_winsys *ws = cmd_buffer->device->ws;
2205
2206         radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2207         if (!set)
2208                 return;
2209
2210         assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2211
2212         if (!cmd_buffer->device->use_global_bo_list) {
2213                 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2214                         if (set->descriptors[j])
2215                                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2216         }
2217
2218         if(set->bo)
2219                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2220 }
2221
2222 void radv_CmdBindDescriptorSets(
2223         VkCommandBuffer                             commandBuffer,
2224         VkPipelineBindPoint                         pipelineBindPoint,
2225         VkPipelineLayout                            _layout,
2226         uint32_t                                    firstSet,
2227         uint32_t                                    descriptorSetCount,
2228         const VkDescriptorSet*                      pDescriptorSets,
2229         uint32_t                                    dynamicOffsetCount,
2230         const uint32_t*                             pDynamicOffsets)
2231 {
2232         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2233         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2234         unsigned dyn_idx = 0;
2235
2236         const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2237
2238         for (unsigned i = 0; i < descriptorSetCount; ++i) {
2239                 unsigned idx = i + firstSet;
2240                 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2241                 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2242
2243                 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2244                         unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2245                         uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2246                         assert(dyn_idx < dynamicOffsetCount);
2247
2248                         struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2249                         uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2250                         dst[0] = va;
2251                         dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2252                         dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2253                         dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2254                                  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2255                                  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2256                                  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2257                                  S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2258                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2259                         cmd_buffer->push_constant_stages |=
2260                                              set->layout->dynamic_shader_stages;
2261                 }
2262         }
2263 }
2264
2265 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2266                                           struct radv_descriptor_set *set,
2267                                           struct radv_descriptor_set_layout *layout,
2268                                           VkPipelineBindPoint bind_point)
2269 {
2270         struct radv_descriptor_state *descriptors_state =
2271                 radv_get_descriptors_state(cmd_buffer, bind_point);
2272         set->size = layout->size;
2273         set->layout = layout;
2274
2275         if (descriptors_state->push_set.capacity < set->size) {
2276                 size_t new_size = MAX2(set->size, 1024);
2277                 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2278                 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2279
2280                 free(set->mapped_ptr);
2281                 set->mapped_ptr = malloc(new_size);
2282
2283                 if (!set->mapped_ptr) {
2284                         descriptors_state->push_set.capacity = 0;
2285                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2286                         return false;
2287                 }
2288
2289                 descriptors_state->push_set.capacity = new_size;
2290         }
2291
2292         return true;
2293 }
2294
2295 void radv_meta_push_descriptor_set(
2296         struct radv_cmd_buffer*              cmd_buffer,
2297         VkPipelineBindPoint                  pipelineBindPoint,
2298         VkPipelineLayout                     _layout,
2299         uint32_t                             set,
2300         uint32_t                             descriptorWriteCount,
2301         const VkWriteDescriptorSet*          pDescriptorWrites)
2302 {
2303         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2304         struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2305         unsigned bo_offset;
2306
2307         assert(set == 0);
2308         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2309
2310         push_set->size = layout->set[set].layout->size;
2311         push_set->layout = layout->set[set].layout;
2312
2313         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2314                                           &bo_offset,
2315                                           (void**) &push_set->mapped_ptr))
2316                 return;
2317
2318         push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2319         push_set->va += bo_offset;
2320
2321         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2322                                     radv_descriptor_set_to_handle(push_set),
2323                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2324
2325         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2326 }
2327
2328 void radv_CmdPushDescriptorSetKHR(
2329         VkCommandBuffer                             commandBuffer,
2330         VkPipelineBindPoint                         pipelineBindPoint,
2331         VkPipelineLayout                            _layout,
2332         uint32_t                                    set,
2333         uint32_t                                    descriptorWriteCount,
2334         const VkWriteDescriptorSet*                 pDescriptorWrites)
2335 {
2336         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2337         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2338         struct radv_descriptor_state *descriptors_state =
2339                 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2340         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2341
2342         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2343
2344         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2345                                            layout->set[set].layout,
2346                                            pipelineBindPoint))
2347                 return;
2348
2349         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2350                                     radv_descriptor_set_to_handle(push_set),
2351                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2352
2353         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2354         descriptors_state->push_dirty = true;
2355 }
2356
2357 void radv_CmdPushDescriptorSetWithTemplateKHR(
2358         VkCommandBuffer                             commandBuffer,
2359         VkDescriptorUpdateTemplateKHR               descriptorUpdateTemplate,
2360         VkPipelineLayout                            _layout,
2361         uint32_t                                    set,
2362         const void*                                 pData)
2363 {
2364         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2365         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2366         RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2367         struct radv_descriptor_state *descriptors_state =
2368                 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2369         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2370
2371         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2372
2373         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2374                                            layout->set[set].layout,
2375                                            templ->bind_point))
2376                 return;
2377
2378         radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2379                                                  descriptorUpdateTemplate, pData);
2380
2381         radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2382         descriptors_state->push_dirty = true;
2383 }
2384
2385 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2386                            VkPipelineLayout layout,
2387                            VkShaderStageFlags stageFlags,
2388                            uint32_t offset,
2389                            uint32_t size,
2390                            const void* pValues)
2391 {
2392         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2393         memcpy(cmd_buffer->push_constants + offset, pValues, size);
2394         cmd_buffer->push_constant_stages |= stageFlags;
2395 }
2396
2397 VkResult radv_EndCommandBuffer(
2398         VkCommandBuffer                             commandBuffer)
2399 {
2400         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2401
2402         if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2403                 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2404                         cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2405                 si_emit_cache_flush(cmd_buffer);
2406         }
2407
2408         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2409
2410         if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2411                 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2412
2413         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2414
2415         return cmd_buffer->record_result;
2416 }
2417
2418 static void
2419 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2420 {
2421         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2422
2423         if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2424                 return;
2425
2426         cmd_buffer->state.emitted_compute_pipeline = pipeline;
2427
2428         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2429         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2430
2431         cmd_buffer->compute_scratch_size_needed =
2432                                   MAX2(cmd_buffer->compute_scratch_size_needed,
2433                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2434
2435         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2436                            pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
2437
2438         if (unlikely(cmd_buffer->device->trace_bo))
2439                 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2440 }
2441
2442 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2443                                             VkPipelineBindPoint bind_point)
2444 {
2445         struct radv_descriptor_state *descriptors_state =
2446                 radv_get_descriptors_state(cmd_buffer, bind_point);
2447
2448         descriptors_state->dirty |= descriptors_state->valid;
2449 }
2450
2451 void radv_CmdBindPipeline(
2452         VkCommandBuffer                             commandBuffer,
2453         VkPipelineBindPoint                         pipelineBindPoint,
2454         VkPipeline                                  _pipeline)
2455 {
2456         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2457         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2458
2459         switch (pipelineBindPoint) {
2460         case VK_PIPELINE_BIND_POINT_COMPUTE:
2461                 if (cmd_buffer->state.compute_pipeline == pipeline)
2462                         return;
2463                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2464
2465                 cmd_buffer->state.compute_pipeline = pipeline;
2466                 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2467                 break;
2468         case VK_PIPELINE_BIND_POINT_GRAPHICS:
2469                 if (cmd_buffer->state.pipeline == pipeline)
2470                         return;
2471                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2472
2473                 cmd_buffer->state.pipeline = pipeline;
2474                 if (!pipeline)
2475                         break;
2476
2477                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2478                 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2479
2480                 /* the new vertex shader might not have the same user regs */
2481                 cmd_buffer->state.last_first_instance = -1;
2482                 cmd_buffer->state.last_vertex_offset = -1;
2483
2484                 /* Prefetch all pipeline shaders at first draw time. */
2485                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2486
2487                 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2488
2489                 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2490                         cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2491                 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2492                         cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2493
2494                 if (radv_pipeline_has_tess(pipeline))
2495                         cmd_buffer->tess_rings_needed = true;
2496
2497                 if (radv_pipeline_has_gs(pipeline)) {
2498                         struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2499                                                                              AC_UD_SCRATCH_RING_OFFSETS);
2500                         if (cmd_buffer->ring_offsets_idx == -1)
2501                                 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2502                         else if (loc->sgpr_idx != -1)
2503                                 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2504                 }
2505                 break;
2506         default:
2507                 assert(!"invalid bind point");
2508                 break;
2509         }
2510 }
2511
2512 void radv_CmdSetViewport(
2513         VkCommandBuffer                             commandBuffer,
2514         uint32_t                                    firstViewport,
2515         uint32_t                                    viewportCount,
2516         const VkViewport*                           pViewports)
2517 {
2518         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2519         struct radv_cmd_state *state = &cmd_buffer->state;
2520         MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2521
2522         assert(firstViewport < MAX_VIEWPORTS);
2523         assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2524
2525         memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2526                viewportCount * sizeof(*pViewports));
2527
2528         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2529 }
2530
2531 void radv_CmdSetScissor(
2532         VkCommandBuffer                             commandBuffer,
2533         uint32_t                                    firstScissor,
2534         uint32_t                                    scissorCount,
2535         const VkRect2D*                             pScissors)
2536 {
2537         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2538         struct radv_cmd_state *state = &cmd_buffer->state;
2539         MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2540
2541         assert(firstScissor < MAX_SCISSORS);
2542         assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2543
2544         memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2545                scissorCount * sizeof(*pScissors));
2546
2547         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2548 }
2549
2550 void radv_CmdSetLineWidth(
2551         VkCommandBuffer                             commandBuffer,
2552         float                                       lineWidth)
2553 {
2554         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2555         cmd_buffer->state.dynamic.line_width = lineWidth;
2556         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2557 }
2558
2559 void radv_CmdSetDepthBias(
2560         VkCommandBuffer                             commandBuffer,
2561         float                                       depthBiasConstantFactor,
2562         float                                       depthBiasClamp,
2563         float                                       depthBiasSlopeFactor)
2564 {
2565         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2566
2567         cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2568         cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2569         cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2570
2571         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2572 }
2573
2574 void radv_CmdSetBlendConstants(
2575         VkCommandBuffer                             commandBuffer,
2576         const float                                 blendConstants[4])
2577 {
2578         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2579
2580         memcpy(cmd_buffer->state.dynamic.blend_constants,
2581                blendConstants, sizeof(float) * 4);
2582
2583         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2584 }
2585
2586 void radv_CmdSetDepthBounds(
2587         VkCommandBuffer                             commandBuffer,
2588         float                                       minDepthBounds,
2589         float                                       maxDepthBounds)
2590 {
2591         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2592
2593         cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2594         cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2595
2596         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2597 }
2598
2599 void radv_CmdSetStencilCompareMask(
2600         VkCommandBuffer                             commandBuffer,
2601         VkStencilFaceFlags                          faceMask,
2602         uint32_t                                    compareMask)
2603 {
2604         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2605
2606         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2607                 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2608         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2609                 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2610
2611         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2612 }
2613
2614 void radv_CmdSetStencilWriteMask(
2615         VkCommandBuffer                             commandBuffer,
2616         VkStencilFaceFlags                          faceMask,
2617         uint32_t                                    writeMask)
2618 {
2619         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2620
2621         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2622                 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2623         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2624                 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2625
2626         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2627 }
2628
2629 void radv_CmdSetStencilReference(
2630         VkCommandBuffer                             commandBuffer,
2631         VkStencilFaceFlags                          faceMask,
2632         uint32_t                                    reference)
2633 {
2634         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2635
2636         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2637                 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2638         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2639                 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2640
2641         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2642 }
2643
2644 void radv_CmdSetDiscardRectangleEXT(
2645         VkCommandBuffer                             commandBuffer,
2646         uint32_t                                    firstDiscardRectangle,
2647         uint32_t                                    discardRectangleCount,
2648         const VkRect2D*                             pDiscardRectangles)
2649 {
2650         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2651         struct radv_cmd_state *state = &cmd_buffer->state;
2652         MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2653
2654         assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2655         assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2656
2657         typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2658                      pDiscardRectangles, discardRectangleCount);
2659
2660         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2661 }
2662
2663 void radv_CmdExecuteCommands(
2664         VkCommandBuffer                             commandBuffer,
2665         uint32_t                                    commandBufferCount,
2666         const VkCommandBuffer*                      pCmdBuffers)
2667 {
2668         RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2669
2670         assert(commandBufferCount > 0);
2671
2672         /* Emit pending flushes on primary prior to executing secondary */
2673         si_emit_cache_flush(primary);
2674
2675         for (uint32_t i = 0; i < commandBufferCount; i++) {
2676                 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2677
2678                 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2679                                                     secondary->scratch_size_needed);
2680                 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2681                                                             secondary->compute_scratch_size_needed);
2682
2683                 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2684                         primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2685                 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2686                         primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2687                 if (secondary->tess_rings_needed)
2688                         primary->tess_rings_needed = true;
2689                 if (secondary->sample_positions_needed)
2690                         primary->sample_positions_needed = true;
2691
2692                 if (secondary->ring_offsets_idx != -1) {
2693                         if (primary->ring_offsets_idx == -1)
2694                                 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2695                         else
2696                                 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2697                 }
2698                 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2699
2700
2701                 /* When the secondary command buffer is compute only we don't
2702                  * need to re-emit the current graphics pipeline.
2703                  */
2704                 if (secondary->state.emitted_pipeline) {
2705                         primary->state.emitted_pipeline =
2706                                 secondary->state.emitted_pipeline;
2707                 }
2708
2709                 /* When the secondary command buffer is graphics only we don't
2710                  * need to re-emit the current compute pipeline.
2711                  */
2712                 if (secondary->state.emitted_compute_pipeline) {
2713                         primary->state.emitted_compute_pipeline =
2714                                 secondary->state.emitted_compute_pipeline;
2715                 }
2716
2717                 /* Only re-emit the draw packets when needed. */
2718                 if (secondary->state.last_primitive_reset_en != -1) {
2719                         primary->state.last_primitive_reset_en =
2720                                 secondary->state.last_primitive_reset_en;
2721                 }
2722
2723                 if (secondary->state.last_primitive_reset_index) {
2724                         primary->state.last_primitive_reset_index =
2725                                 secondary->state.last_primitive_reset_index;
2726                 }
2727
2728                 if (secondary->state.last_ia_multi_vgt_param) {
2729                         primary->state.last_ia_multi_vgt_param =
2730                                 secondary->state.last_ia_multi_vgt_param;
2731                 }
2732
2733                 primary->state.last_first_instance = secondary->state.last_first_instance;
2734                 primary->state.last_num_instances = secondary->state.last_num_instances;
2735                 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2736
2737                 if (secondary->state.last_index_type != -1) {
2738                         primary->state.last_index_type =
2739                                 secondary->state.last_index_type;
2740                 }
2741         }
2742
2743         /* After executing commands from secondary buffers we have to dirty
2744          * some states.
2745          */
2746         primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2747                                 RADV_CMD_DIRTY_INDEX_BUFFER |
2748                                 RADV_CMD_DIRTY_DYNAMIC_ALL;
2749         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2750         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2751 }
2752
2753 VkResult radv_CreateCommandPool(
2754         VkDevice                                    _device,
2755         const VkCommandPoolCreateInfo*              pCreateInfo,
2756         const VkAllocationCallbacks*                pAllocator,
2757         VkCommandPool*                              pCmdPool)
2758 {
2759         RADV_FROM_HANDLE(radv_device, device, _device);
2760         struct radv_cmd_pool *pool;
2761
2762         pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2763                            VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2764         if (pool == NULL)
2765                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2766
2767         if (pAllocator)
2768                 pool->alloc = *pAllocator;
2769         else
2770                 pool->alloc = device->alloc;
2771
2772         list_inithead(&pool->cmd_buffers);
2773         list_inithead(&pool->free_cmd_buffers);
2774
2775         pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2776
2777         *pCmdPool = radv_cmd_pool_to_handle(pool);
2778
2779         return VK_SUCCESS;
2780
2781 }
2782
2783 void radv_DestroyCommandPool(
2784         VkDevice                                    _device,
2785         VkCommandPool                               commandPool,
2786         const VkAllocationCallbacks*                pAllocator)
2787 {
2788         RADV_FROM_HANDLE(radv_device, device, _device);
2789         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2790
2791         if (!pool)
2792                 return;
2793
2794         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2795                                  &pool->cmd_buffers, pool_link) {
2796                 radv_cmd_buffer_destroy(cmd_buffer);
2797         }
2798
2799         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2800                                  &pool->free_cmd_buffers, pool_link) {
2801                 radv_cmd_buffer_destroy(cmd_buffer);
2802         }
2803
2804         vk_free2(&device->alloc, pAllocator, pool);
2805 }
2806
2807 VkResult radv_ResetCommandPool(
2808         VkDevice                                    device,
2809         VkCommandPool                               commandPool,
2810         VkCommandPoolResetFlags                     flags)
2811 {
2812         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2813         VkResult result;
2814
2815         list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2816                             &pool->cmd_buffers, pool_link) {
2817                 result = radv_reset_cmd_buffer(cmd_buffer);
2818                 if (result != VK_SUCCESS)
2819                         return result;
2820         }
2821
2822         return VK_SUCCESS;
2823 }
2824
2825 void radv_TrimCommandPool(
2826     VkDevice                                    device,
2827     VkCommandPool                               commandPool,
2828     VkCommandPoolTrimFlagsKHR                   flags)
2829 {
2830         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2831
2832         if (!pool)
2833                 return;
2834
2835         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2836                                  &pool->free_cmd_buffers, pool_link) {
2837                 radv_cmd_buffer_destroy(cmd_buffer);
2838         }
2839 }
2840
2841 void radv_CmdBeginRenderPass(
2842         VkCommandBuffer                             commandBuffer,
2843         const VkRenderPassBeginInfo*                pRenderPassBegin,
2844         VkSubpassContents                           contents)
2845 {
2846         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2847         RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2848         RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2849
2850         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2851                                                            cmd_buffer->cs, 2048);
2852         MAYBE_UNUSED VkResult result;
2853
2854         cmd_buffer->state.framebuffer = framebuffer;
2855         cmd_buffer->state.pass = pass;
2856         cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2857
2858         result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2859         if (result != VK_SUCCESS)
2860                 return;
2861
2862         radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2863         assert(cmd_buffer->cs->cdw <= cdw_max);
2864
2865         radv_cmd_buffer_clear_subpass(cmd_buffer);
2866 }
2867
2868 void radv_CmdNextSubpass(
2869     VkCommandBuffer                             commandBuffer,
2870     VkSubpassContents                           contents)
2871 {
2872         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2873
2874         radv_cmd_buffer_resolve_subpass(cmd_buffer);
2875
2876         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2877                                               2048);
2878
2879         radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2880         radv_cmd_buffer_clear_subpass(cmd_buffer);
2881 }
2882
2883 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2884 {
2885         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2886         for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2887                 if (!pipeline->shaders[stage])
2888                         continue;
2889                 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2890                 if (loc->sgpr_idx == -1)
2891                         continue;
2892                 uint32_t base_reg = pipeline->user_data_0[stage];
2893                 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2894
2895         }
2896         if (pipeline->gs_copy_shader) {
2897                 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2898                 if (loc->sgpr_idx != -1) {
2899                         uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2900                         radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2901                 }
2902         }
2903 }
2904
2905 static void
2906 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2907                          uint32_t vertex_count)
2908 {
2909         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2910         radeon_emit(cmd_buffer->cs, vertex_count);
2911         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2912                                     S_0287F0_USE_OPAQUE(0));
2913 }
2914
2915 static void
2916 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2917                                  uint64_t index_va,
2918                                  uint32_t index_count)
2919 {
2920         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2921         radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2922         radeon_emit(cmd_buffer->cs, index_va);
2923         radeon_emit(cmd_buffer->cs, index_va >> 32);
2924         radeon_emit(cmd_buffer->cs, index_count);
2925         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2926 }
2927
2928 static void
2929 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2930                                   bool indexed,
2931                                   uint32_t draw_count,
2932                                   uint64_t count_va,
2933                                   uint32_t stride)
2934 {
2935         struct radeon_winsys_cs *cs = cmd_buffer->cs;
2936         unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2937                                       : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2938         bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
2939         uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2940         assert(base_reg);
2941
2942         /* just reset draw state for vertex data */
2943         cmd_buffer->state.last_first_instance = -1;
2944         cmd_buffer->state.last_num_instances = -1;
2945         cmd_buffer->state.last_vertex_offset = -1;
2946
2947         if (draw_count == 1 && !count_va && !draw_id_enable) {
2948                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2949                                      PKT3_DRAW_INDIRECT, 3, false));
2950                 radeon_emit(cs, 0);
2951                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2952                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2953                 radeon_emit(cs, di_src_sel);
2954         } else {
2955                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2956                                      PKT3_DRAW_INDIRECT_MULTI,
2957                                      8, false));
2958                 radeon_emit(cs, 0);
2959                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2960                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2961                 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2962                             S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2963                             S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2964                 radeon_emit(cs, draw_count); /* count */
2965                 radeon_emit(cs, count_va); /* count_addr */
2966                 radeon_emit(cs, count_va >> 32);
2967                 radeon_emit(cs, stride); /* stride */
2968                 radeon_emit(cs, di_src_sel);
2969         }
2970 }
2971
2972 struct radv_draw_info {
2973         /**
2974          * Number of vertices.
2975          */
2976         uint32_t count;
2977
2978         /**
2979          * Index of the first vertex.
2980          */
2981         int32_t vertex_offset;
2982
2983         /**
2984          * First instance id.
2985          */
2986         uint32_t first_instance;
2987
2988         /**
2989          * Number of instances.
2990          */
2991         uint32_t instance_count;
2992
2993         /**
2994          * First index (indexed draws only).
2995          */
2996         uint32_t first_index;
2997
2998         /**
2999          * Whether it's an indexed draw.
3000          */
3001         bool indexed;
3002
3003         /**
3004          * Indirect draw parameters resource.
3005          */
3006         struct radv_buffer *indirect;
3007         uint64_t indirect_offset;
3008         uint32_t stride;
3009
3010         /**
3011          * Draw count parameters resource.
3012          */
3013         struct radv_buffer *count_buffer;
3014         uint64_t count_buffer_offset;
3015 };
3016
3017 static void
3018 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3019                        const struct radv_draw_info *info)
3020 {
3021         struct radv_cmd_state *state = &cmd_buffer->state;
3022         struct radeon_winsys *ws = cmd_buffer->device->ws;
3023         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3024
3025         if (info->indirect) {
3026                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3027                 uint64_t count_va = 0;
3028
3029                 va += info->indirect->offset + info->indirect_offset;
3030
3031                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3032
3033                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3034                 radeon_emit(cs, 1);
3035                 radeon_emit(cs, va);
3036                 radeon_emit(cs, va >> 32);
3037
3038                 if (info->count_buffer) {
3039                         count_va = radv_buffer_get_va(info->count_buffer->bo);
3040                         count_va += info->count_buffer->offset +
3041                                     info->count_buffer_offset;
3042
3043                         radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3044                 }
3045
3046                 if (!state->subpass->view_mask) {
3047                         radv_cs_emit_indirect_draw_packet(cmd_buffer,
3048                                                           info->indexed,
3049                                                           info->count,
3050                                                           count_va,
3051                                                           info->stride);
3052                 } else {
3053                         unsigned i;
3054                         for_each_bit(i, state->subpass->view_mask) {
3055                                 radv_emit_view_index(cmd_buffer, i);
3056
3057                                 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3058                                                                   info->indexed,
3059                                                                   info->count,
3060                                                                   count_va,
3061                                                                   info->stride);
3062                         }
3063                 }
3064         } else {
3065                 assert(state->pipeline->graphics.vtx_base_sgpr);
3066
3067                 if (info->vertex_offset != state->last_vertex_offset ||
3068                     info->first_instance != state->last_first_instance) {
3069                         radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3070                                               state->pipeline->graphics.vtx_emit_num);
3071
3072                         radeon_emit(cs, info->vertex_offset);
3073                         radeon_emit(cs, info->first_instance);
3074                         if (state->pipeline->graphics.vtx_emit_num == 3)
3075                                 radeon_emit(cs, 0);
3076                         state->last_first_instance = info->first_instance;
3077                         state->last_vertex_offset = info->vertex_offset;
3078                 }
3079
3080                 if (state->last_num_instances != info->instance_count) {
3081                         radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3082                         radeon_emit(cs, info->instance_count);
3083                         state->last_num_instances = info->instance_count;
3084                 }
3085
3086                 if (info->indexed) {
3087                         int index_size = state->index_type ? 4 : 2;
3088                         uint64_t index_va;
3089
3090                         index_va = state->index_va;
3091                         index_va += info->first_index * index_size;
3092
3093                         if (!state->subpass->view_mask) {
3094                                 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3095                                                                  index_va,
3096                                                                  info->count);
3097                         } else {
3098                                 unsigned i;
3099                                 for_each_bit(i, state->subpass->view_mask) {
3100                                         radv_emit_view_index(cmd_buffer, i);
3101
3102                                         radv_cs_emit_draw_indexed_packet(cmd_buffer,
3103                                                                          index_va,
3104                                                                          info->count);
3105                                 }
3106                         }
3107                 } else {
3108                         if (!state->subpass->view_mask) {
3109                                 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3110                         } else {
3111                                 unsigned i;
3112                                 for_each_bit(i, state->subpass->view_mask) {
3113                                         radv_emit_view_index(cmd_buffer, i);
3114
3115                                         radv_cs_emit_draw_packet(cmd_buffer,
3116                                                                  info->count);
3117                                 }
3118                         }
3119                 }
3120         }
3121 }
3122
3123 /*
3124  * Vega and raven have a bug which triggers if there are multiple context
3125  * register contexts active at the same time with different scissor values.
3126  *
3127  * There are two possible workarounds:
3128  * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3129  *    there is only ever 1 active set of scissor values at the same time.
3130  *
3131  * 2) Whenever the hardware switches contexts we have to set the scissor
3132  *    registers again even if it is a noop. That way the new context gets
3133  *    the correct scissor values.
3134  *
3135  * This implements option 2. radv_need_late_scissor_emission needs to
3136  * return true on affected HW if radv_emit_all_graphics_states sets
3137  * any context registers.
3138  */
3139 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3140                                             bool indexed_draw)
3141 {
3142         struct radv_cmd_state *state = &cmd_buffer->state;
3143
3144         if (!cmd_buffer->device->physical_device->has_scissor_bug)
3145                 return false;
3146
3147         /* Assume all state changes except  these two can imply context rolls. */
3148         if (cmd_buffer->state.dirty & ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3149                                         RADV_CMD_DIRTY_VERTEX_BUFFER |
3150                                         RADV_CMD_DIRTY_PIPELINE))
3151                 return true;
3152
3153         if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3154                 return true;
3155
3156         if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3157             (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3158                 return true;
3159
3160         return false;
3161 }
3162
3163 static void
3164 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3165                               const struct radv_draw_info *info)
3166 {
3167         bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3168
3169         if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3170             cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3171                 radv_emit_rbplus_state(cmd_buffer);
3172
3173         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3174                 radv_emit_graphics_pipeline(cmd_buffer);
3175
3176         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3177                 radv_emit_framebuffer_state(cmd_buffer);
3178
3179         if (info->indexed) {
3180                 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3181                         radv_emit_index_buffer(cmd_buffer);
3182         } else {
3183                 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3184                  * so the state must be re-emitted before the next indexed
3185                  * draw.
3186                  */
3187                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3188                         cmd_buffer->state.last_index_type = -1;
3189                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3190                 }
3191         }
3192
3193         radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3194
3195         radv_emit_draw_registers(cmd_buffer, info->indexed,
3196                                  info->instance_count > 1, info->indirect,
3197                                  info->indirect ? 0 : info->count);
3198
3199         if (late_scissor_emission)
3200                 radv_emit_scissor(cmd_buffer);
3201 }
3202
3203 static void
3204 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3205           const struct radv_draw_info *info)
3206 {
3207         bool has_prefetch =
3208                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3209         bool pipeline_is_dirty =
3210                 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3211                 cmd_buffer->state.pipeline &&
3212                 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3213
3214         MAYBE_UNUSED unsigned cdw_max =
3215                 radeon_check_space(cmd_buffer->device->ws,
3216                                    cmd_buffer->cs, 4096);
3217
3218         /* Use optimal packet order based on whether we need to sync the
3219          * pipeline.
3220          */
3221         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3222                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3223                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3224                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3225                 /* If we have to wait for idle, set all states first, so that
3226                  * all SET packets are processed in parallel with previous draw
3227                  * calls. Then upload descriptors, set shader pointers, and
3228                  * draw, and prefetch at the end. This ensures that the time
3229                  * the CUs are idle is very short. (there are only SET_SH
3230                  * packets between the wait and the draw)
3231                  */
3232                 radv_emit_all_graphics_states(cmd_buffer, info);
3233                 si_emit_cache_flush(cmd_buffer);
3234                 /* <-- CUs are idle here --> */
3235
3236                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3237
3238                 radv_emit_draw_packets(cmd_buffer, info);
3239                 /* <-- CUs are busy here --> */
3240
3241                 /* Start prefetches after the draw has been started. Both will
3242                  * run in parallel, but starting the draw first is more
3243                  * important.
3244                  */
3245                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3246                         radv_emit_prefetch_L2(cmd_buffer,
3247                                               cmd_buffer->state.pipeline, false);
3248                 }
3249         } else {
3250                 /* If we don't wait for idle, start prefetches first, then set
3251                  * states, and draw at the end.
3252                  */
3253                 si_emit_cache_flush(cmd_buffer);
3254
3255                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3256                         /* Only prefetch the vertex shader and VBO descriptors
3257                          * in order to start the draw as soon as possible.
3258                          */
3259                         radv_emit_prefetch_L2(cmd_buffer,
3260                                               cmd_buffer->state.pipeline, true);
3261                 }
3262
3263                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3264
3265                 radv_emit_all_graphics_states(cmd_buffer, info);
3266                 radv_emit_draw_packets(cmd_buffer, info);
3267
3268                 /* Prefetch the remaining shaders after the draw has been
3269                  * started.
3270                  */
3271                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3272                         radv_emit_prefetch_L2(cmd_buffer,
3273                                               cmd_buffer->state.pipeline, false);
3274                 }
3275         }
3276
3277         assert(cmd_buffer->cs->cdw <= cdw_max);
3278         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3279 }
3280
3281 void radv_CmdDraw(
3282         VkCommandBuffer                             commandBuffer,
3283         uint32_t                                    vertexCount,
3284         uint32_t                                    instanceCount,
3285         uint32_t                                    firstVertex,
3286         uint32_t                                    firstInstance)
3287 {
3288         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3289         struct radv_draw_info info = {};
3290
3291         info.count = vertexCount;
3292         info.instance_count = instanceCount;
3293         info.first_instance = firstInstance;
3294         info.vertex_offset = firstVertex;
3295
3296         radv_draw(cmd_buffer, &info);
3297 }
3298
3299 void radv_CmdDrawIndexed(
3300         VkCommandBuffer                             commandBuffer,
3301         uint32_t                                    indexCount,
3302         uint32_t                                    instanceCount,
3303         uint32_t                                    firstIndex,
3304         int32_t                                     vertexOffset,
3305         uint32_t                                    firstInstance)
3306 {
3307         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3308         struct radv_draw_info info = {};
3309
3310         info.indexed = true;
3311         info.count = indexCount;
3312         info.instance_count = instanceCount;
3313         info.first_index = firstIndex;
3314         info.vertex_offset = vertexOffset;
3315         info.first_instance = firstInstance;
3316
3317         radv_draw(cmd_buffer, &info);
3318 }
3319
3320 void radv_CmdDrawIndirect(
3321         VkCommandBuffer                             commandBuffer,
3322         VkBuffer                                    _buffer,
3323         VkDeviceSize                                offset,
3324         uint32_t                                    drawCount,
3325         uint32_t                                    stride)
3326 {
3327         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3328         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3329         struct radv_draw_info info = {};
3330
3331         info.count = drawCount;
3332         info.indirect = buffer;
3333         info.indirect_offset = offset;
3334         info.stride = stride;
3335
3336         radv_draw(cmd_buffer, &info);
3337 }
3338
3339 void radv_CmdDrawIndexedIndirect(
3340         VkCommandBuffer                             commandBuffer,
3341         VkBuffer                                    _buffer,
3342         VkDeviceSize                                offset,
3343         uint32_t                                    drawCount,
3344         uint32_t                                    stride)
3345 {
3346         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3347         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3348         struct radv_draw_info info = {};
3349
3350         info.indexed = true;
3351         info.count = drawCount;
3352         info.indirect = buffer;
3353         info.indirect_offset = offset;
3354         info.stride = stride;
3355
3356         radv_draw(cmd_buffer, &info);
3357 }
3358
3359 void radv_CmdDrawIndirectCountAMD(
3360         VkCommandBuffer                             commandBuffer,
3361         VkBuffer                                    _buffer,
3362         VkDeviceSize                                offset,
3363         VkBuffer                                    _countBuffer,
3364         VkDeviceSize                                countBufferOffset,
3365         uint32_t                                    maxDrawCount,
3366         uint32_t                                    stride)
3367 {
3368         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3369         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3370         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3371         struct radv_draw_info info = {};
3372
3373         info.count = maxDrawCount;
3374         info.indirect = buffer;
3375         info.indirect_offset = offset;
3376         info.count_buffer = count_buffer;
3377         info.count_buffer_offset = countBufferOffset;
3378         info.stride = stride;
3379
3380         radv_draw(cmd_buffer, &info);
3381 }
3382
3383 void radv_CmdDrawIndexedIndirectCountAMD(
3384         VkCommandBuffer                             commandBuffer,
3385         VkBuffer                                    _buffer,
3386         VkDeviceSize                                offset,
3387         VkBuffer                                    _countBuffer,
3388         VkDeviceSize                                countBufferOffset,
3389         uint32_t                                    maxDrawCount,
3390         uint32_t                                    stride)
3391 {
3392         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3393         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3394         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3395         struct radv_draw_info info = {};
3396
3397         info.indexed = true;
3398         info.count = maxDrawCount;
3399         info.indirect = buffer;
3400         info.indirect_offset = offset;
3401         info.count_buffer = count_buffer;
3402         info.count_buffer_offset = countBufferOffset;
3403         info.stride = stride;
3404
3405         radv_draw(cmd_buffer, &info);
3406 }
3407
3408 void radv_CmdDrawIndirectCountKHR(
3409         VkCommandBuffer                             commandBuffer,
3410         VkBuffer                                    _buffer,
3411         VkDeviceSize                                offset,
3412         VkBuffer                                    _countBuffer,
3413         VkDeviceSize                                countBufferOffset,
3414         uint32_t                                    maxDrawCount,
3415         uint32_t                                    stride)
3416 {
3417         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3418         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3419         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3420         struct radv_draw_info info = {};
3421
3422         info.count = maxDrawCount;
3423         info.indirect = buffer;
3424         info.indirect_offset = offset;
3425         info.count_buffer = count_buffer;
3426         info.count_buffer_offset = countBufferOffset;
3427         info.stride = stride;
3428
3429         radv_draw(cmd_buffer, &info);
3430 }
3431
3432 void radv_CmdDrawIndexedIndirectCountKHR(
3433         VkCommandBuffer                             commandBuffer,
3434         VkBuffer                                    _buffer,
3435         VkDeviceSize                                offset,
3436         VkBuffer                                    _countBuffer,
3437         VkDeviceSize                                countBufferOffset,
3438         uint32_t                                    maxDrawCount,
3439         uint32_t                                    stride)
3440 {
3441         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3442         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3443         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3444         struct radv_draw_info info = {};
3445
3446         info.indexed = true;
3447         info.count = maxDrawCount;
3448         info.indirect = buffer;
3449         info.indirect_offset = offset;
3450         info.count_buffer = count_buffer;
3451         info.count_buffer_offset = countBufferOffset;
3452         info.stride = stride;
3453
3454         radv_draw(cmd_buffer, &info);
3455 }
3456
3457 struct radv_dispatch_info {
3458         /**
3459          * Determine the layout of the grid (in block units) to be used.
3460          */
3461         uint32_t blocks[3];
3462
3463         /**
3464          * A starting offset for the grid. If unaligned is set, the offset
3465          * must still be aligned.
3466          */
3467         uint32_t offsets[3];
3468         /**
3469          * Whether it's an unaligned compute dispatch.
3470          */
3471         bool unaligned;
3472
3473         /**
3474          * Indirect compute parameters resource.
3475          */
3476         struct radv_buffer *indirect;
3477         uint64_t indirect_offset;
3478 };
3479
3480 static void
3481 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3482                            const struct radv_dispatch_info *info)
3483 {
3484         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3485         struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3486         unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3487         struct radeon_winsys *ws = cmd_buffer->device->ws;
3488         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3489         struct radv_userdata_info *loc;
3490
3491         loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3492                                     AC_UD_CS_GRID_SIZE);
3493
3494         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3495
3496         if (info->indirect) {
3497                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3498
3499                 va += info->indirect->offset + info->indirect_offset;
3500
3501                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3502
3503                 if (loc->sgpr_idx != -1) {
3504                         for (unsigned i = 0; i < 3; ++i) {
3505                                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3506                                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3507                                                 COPY_DATA_DST_SEL(COPY_DATA_REG));
3508                                 radeon_emit(cs, (va +  4 * i));
3509                                 radeon_emit(cs, (va + 4 * i) >> 32);
3510                                 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3511                                                  + loc->sgpr_idx * 4) >> 2) + i);
3512                                 radeon_emit(cs, 0);
3513                         }
3514                 }
3515
3516                 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3517                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3518                                         PKT3_SHADER_TYPE_S(1));
3519                         radeon_emit(cs, va);
3520                         radeon_emit(cs, va >> 32);
3521                         radeon_emit(cs, dispatch_initiator);
3522                 } else {
3523                         radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3524                                         PKT3_SHADER_TYPE_S(1));
3525                         radeon_emit(cs, 1);
3526                         radeon_emit(cs, va);
3527                         radeon_emit(cs, va >> 32);
3528
3529                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3530                                         PKT3_SHADER_TYPE_S(1));
3531                         radeon_emit(cs, 0);
3532                         radeon_emit(cs, dispatch_initiator);
3533                 }
3534         } else {
3535                 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3536                 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3537
3538                 if (info->unaligned) {
3539                         unsigned *cs_block_size = compute_shader->info.cs.block_size;
3540                         unsigned remainder[3];
3541
3542                         /* If aligned, these should be an entire block size,
3543                          * not 0.
3544                          */
3545                         remainder[0] = blocks[0] + cs_block_size[0] -
3546                                        align_u32_npot(blocks[0], cs_block_size[0]);
3547                         remainder[1] = blocks[1] + cs_block_size[1] -
3548                                        align_u32_npot(blocks[1], cs_block_size[1]);
3549                         remainder[2] = blocks[2] + cs_block_size[2] -
3550                                        align_u32_npot(blocks[2], cs_block_size[2]);
3551
3552                         blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3553                         blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3554                         blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3555
3556                         for(unsigned i = 0; i < 3; ++i) {
3557                                 assert(offsets[i] % cs_block_size[i] == 0);
3558                                 offsets[i] /= cs_block_size[i];
3559                         }
3560
3561                         radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3562                         radeon_emit(cs,
3563                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3564                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3565                         radeon_emit(cs,
3566                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3567                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3568                         radeon_emit(cs,
3569                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3570                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3571
3572                         dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3573                 }
3574
3575                 if (loc->sgpr_idx != -1) {
3576                         assert(!loc->indirect);
3577                         assert(loc->num_sgprs == 3);
3578
3579                         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3580                                                   loc->sgpr_idx * 4, 3);
3581                         radeon_emit(cs, blocks[0]);
3582                         radeon_emit(cs, blocks[1]);
3583                         radeon_emit(cs, blocks[2]);
3584                 }
3585
3586                 if (offsets[0] || offsets[1] || offsets[2]) {
3587                         radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3588                         radeon_emit(cs, offsets[0]);
3589                         radeon_emit(cs, offsets[1]);
3590                         radeon_emit(cs, offsets[2]);
3591
3592                         /* The blocks in the packet are not counts but end values. */
3593                         for (unsigned i = 0; i < 3; ++i)
3594                                 blocks[i] += offsets[i];
3595                 } else {
3596                         dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3597                 }
3598
3599                 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3600                                 PKT3_SHADER_TYPE_S(1));
3601                 radeon_emit(cs, blocks[0]);
3602                 radeon_emit(cs, blocks[1]);
3603                 radeon_emit(cs, blocks[2]);
3604                 radeon_emit(cs, dispatch_initiator);
3605         }
3606
3607         assert(cmd_buffer->cs->cdw <= cdw_max);
3608 }
3609
3610 static void
3611 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3612 {
3613         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3614         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3615 }
3616
3617 static void
3618 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3619               const struct radv_dispatch_info *info)
3620 {
3621         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3622         bool has_prefetch =
3623                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3624         bool pipeline_is_dirty = pipeline &&
3625                                  pipeline != cmd_buffer->state.emitted_compute_pipeline;
3626
3627         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3628                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3629                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3630                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3631                 /* If we have to wait for idle, set all states first, so that
3632                  * all SET packets are processed in parallel with previous draw
3633                  * calls. Then upload descriptors, set shader pointers, and
3634                  * dispatch, and prefetch at the end. This ensures that the
3635                  * time the CUs are idle is very short. (there are only SET_SH
3636                  * packets between the wait and the draw)
3637                  */
3638                 radv_emit_compute_pipeline(cmd_buffer);
3639                 si_emit_cache_flush(cmd_buffer);
3640                 /* <-- CUs are idle here --> */
3641
3642                 radv_upload_compute_shader_descriptors(cmd_buffer);
3643
3644                 radv_emit_dispatch_packets(cmd_buffer, info);
3645                 /* <-- CUs are busy here --> */
3646
3647                 /* Start prefetches after the dispatch has been started. Both
3648                  * will run in parallel, but starting the dispatch first is
3649                  * more important.
3650                  */
3651                 if (has_prefetch && pipeline_is_dirty) {
3652                         radv_emit_shader_prefetch(cmd_buffer,
3653                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3654                 }
3655         } else {
3656                 /* If we don't wait for idle, start prefetches first, then set
3657                  * states, and dispatch at the end.
3658                  */
3659                 si_emit_cache_flush(cmd_buffer);
3660
3661                 if (has_prefetch && pipeline_is_dirty) {
3662                         radv_emit_shader_prefetch(cmd_buffer,
3663                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3664                 }
3665
3666                 radv_upload_compute_shader_descriptors(cmd_buffer);
3667
3668                 radv_emit_compute_pipeline(cmd_buffer);
3669                 radv_emit_dispatch_packets(cmd_buffer, info);
3670         }
3671
3672         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3673 }
3674
3675 void radv_CmdDispatchBase(
3676         VkCommandBuffer                             commandBuffer,
3677         uint32_t                                    base_x,
3678         uint32_t                                    base_y,
3679         uint32_t                                    base_z,
3680         uint32_t                                    x,
3681         uint32_t                                    y,
3682         uint32_t                                    z)
3683 {
3684         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3685         struct radv_dispatch_info info = {};
3686
3687         info.blocks[0] = x;
3688         info.blocks[1] = y;
3689         info.blocks[2] = z;
3690
3691         info.offsets[0] = base_x;
3692         info.offsets[1] = base_y;
3693         info.offsets[2] = base_z;
3694         radv_dispatch(cmd_buffer, &info);
3695 }
3696
3697 void radv_CmdDispatch(
3698         VkCommandBuffer                             commandBuffer,
3699         uint32_t                                    x,
3700         uint32_t                                    y,
3701         uint32_t                                    z)
3702 {
3703         radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3704 }
3705
3706 void radv_CmdDispatchIndirect(
3707         VkCommandBuffer                             commandBuffer,
3708         VkBuffer                                    _buffer,
3709         VkDeviceSize                                offset)
3710 {
3711         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3712         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3713         struct radv_dispatch_info info = {};
3714
3715         info.indirect = buffer;
3716         info.indirect_offset = offset;
3717
3718         radv_dispatch(cmd_buffer, &info);
3719 }
3720
3721 void radv_unaligned_dispatch(
3722         struct radv_cmd_buffer                      *cmd_buffer,
3723         uint32_t                                    x,
3724         uint32_t                                    y,
3725         uint32_t                                    z)
3726 {
3727         struct radv_dispatch_info info = {};
3728
3729         info.blocks[0] = x;
3730         info.blocks[1] = y;
3731         info.blocks[2] = z;
3732         info.unaligned = 1;
3733
3734         radv_dispatch(cmd_buffer, &info);
3735 }
3736
3737 void radv_CmdEndRenderPass(
3738         VkCommandBuffer                             commandBuffer)
3739 {
3740         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3741
3742         radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3743
3744         radv_cmd_buffer_resolve_subpass(cmd_buffer);
3745
3746         for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3747                 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3748                 radv_handle_subpass_image_transition(cmd_buffer,
3749                                       (VkAttachmentReference){i, layout});
3750         }
3751
3752         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3753
3754         cmd_buffer->state.pass = NULL;
3755         cmd_buffer->state.subpass = NULL;
3756         cmd_buffer->state.attachments = NULL;
3757         cmd_buffer->state.framebuffer = NULL;
3758 }
3759
3760 /*
3761  * For HTILE we have the following interesting clear words:
3762  *   0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3763  *   0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3764  *   0xfffffff0: Clear depth to 1.0
3765  *   0x00000000: Clear depth to 0.0
3766  */
3767 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3768                                   struct radv_image *image,
3769                                   const VkImageSubresourceRange *range,
3770                                   uint32_t clear_word)
3771 {
3772         assert(range->baseMipLevel == 0);
3773         assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3774         unsigned layer_count = radv_get_layerCount(image, range);
3775         uint64_t size = image->surface.htile_slice_size * layer_count;
3776         uint64_t offset = image->offset + image->htile_offset +
3777                           image->surface.htile_slice_size * range->baseArrayLayer;
3778         struct radv_cmd_state *state = &cmd_buffer->state;
3779
3780         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3781                              RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3782
3783         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3784                                               size, clear_word);
3785
3786         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3787 }
3788
3789 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3790                                                struct radv_image *image,
3791                                                VkImageLayout src_layout,
3792                                                VkImageLayout dst_layout,
3793                                                unsigned src_queue_mask,
3794                                                unsigned dst_queue_mask,
3795                                                const VkImageSubresourceRange *range,
3796                                                VkImageAspectFlags pending_clears)
3797 {
3798         if (!radv_image_has_htile(image))
3799                 return;
3800
3801         if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3802             (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3803             cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3804             cmd_buffer->state.render_area.extent.width == image->info.width &&
3805             cmd_buffer->state.render_area.extent.height == image->info.height) {
3806                 /* The clear will initialize htile. */
3807                 return;
3808         } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3809                    radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3810                 /* TODO: merge with the clear if applicable */
3811                 radv_initialize_htile(cmd_buffer, image, range, 0);
3812         } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3813                    radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3814                 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3815                 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3816         } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3817                    !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3818                 VkImageSubresourceRange local_range = *range;
3819                 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3820                 local_range.baseMipLevel = 0;
3821                 local_range.levelCount = 1;
3822
3823                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3824                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3825
3826                 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3827
3828                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3829                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3830         }
3831 }
3832
3833 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3834                                   struct radv_image *image, uint32_t value)
3835 {
3836         struct radv_cmd_state *state = &cmd_buffer->state;
3837
3838         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3839                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3840
3841         state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
3842
3843         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3844 }
3845
3846 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3847                          struct radv_image *image, uint32_t value)
3848 {
3849         struct radv_cmd_state *state = &cmd_buffer->state;
3850
3851         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3852                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3853
3854         state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
3855
3856         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3857                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3858 }
3859
3860 /**
3861  * Initialize DCC/FMASK/CMASK metadata for a color image.
3862  */
3863 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
3864                                            struct radv_image *image,
3865                                            VkImageLayout src_layout,
3866                                            VkImageLayout dst_layout,
3867                                            unsigned src_queue_mask,
3868                                            unsigned dst_queue_mask)
3869 {
3870         if (radv_image_has_cmask(image)) {
3871                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
3872
3873                 /*  TODO: clarify this. */
3874                 if (radv_image_has_fmask(image)) {
3875                         value = 0xccccccccu;
3876                 }
3877
3878                 radv_initialise_cmask(cmd_buffer, image, value);
3879         }
3880
3881         if (radv_image_has_dcc(image)) {
3882                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
3883
3884                 if (radv_layout_dcc_compressed(image, dst_layout,
3885                                                dst_queue_mask)) {
3886                         value = 0x20202020u;
3887                 }
3888
3889                 radv_initialize_dcc(cmd_buffer, image, value);
3890         }
3891 }
3892
3893 /**
3894  * Handle color image transitions for DCC/FMASK/CMASK.
3895  */
3896 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
3897                                                struct radv_image *image,
3898                                                VkImageLayout src_layout,
3899                                                VkImageLayout dst_layout,
3900                                                unsigned src_queue_mask,
3901                                                unsigned dst_queue_mask,
3902                                                const VkImageSubresourceRange *range)
3903 {
3904         if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3905                 radv_init_color_image_metadata(cmd_buffer, image,
3906                                                src_layout, dst_layout,
3907                                                src_queue_mask, dst_queue_mask);
3908                 return;
3909         }
3910
3911         if (radv_image_has_dcc(image)) {
3912                 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
3913                         radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
3914                 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
3915                            !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
3916                         radv_decompress_dcc(cmd_buffer, image, range);
3917                 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3918                            !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3919                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3920                 }
3921         } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
3922                 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3923                     !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3924                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3925                 }
3926         }
3927 }
3928
3929 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3930                                          struct radv_image *image,
3931                                          VkImageLayout src_layout,
3932                                          VkImageLayout dst_layout,
3933                                          uint32_t src_family,
3934                                          uint32_t dst_family,
3935                                          const VkImageSubresourceRange *range,
3936                                          VkImageAspectFlags pending_clears)
3937 {
3938         if (image->exclusive && src_family != dst_family) {
3939                 /* This is an acquire or a release operation and there will be
3940                  * a corresponding release/acquire. Do the transition in the
3941                  * most flexible queue. */
3942
3943                 assert(src_family == cmd_buffer->queue_family_index ||
3944                        dst_family == cmd_buffer->queue_family_index);
3945
3946                 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3947                         return;
3948
3949                 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3950                     (src_family == RADV_QUEUE_GENERAL ||
3951                      dst_family == RADV_QUEUE_GENERAL))
3952                         return;
3953         }
3954
3955         unsigned src_queue_mask =
3956                 radv_image_queue_family_mask(image, src_family,
3957                                              cmd_buffer->queue_family_index);
3958         unsigned dst_queue_mask =
3959                 radv_image_queue_family_mask(image, dst_family,
3960                                              cmd_buffer->queue_family_index);
3961
3962         if (vk_format_is_depth(image->vk_format)) {
3963                 radv_handle_depth_image_transition(cmd_buffer, image,
3964                                                    src_layout, dst_layout,
3965                                                    src_queue_mask, dst_queue_mask,
3966                                                    range, pending_clears);
3967         } else {
3968                 radv_handle_color_image_transition(cmd_buffer, image,
3969                                                    src_layout, dst_layout,
3970                                                    src_queue_mask, dst_queue_mask,
3971                                                    range);
3972         }
3973 }
3974
3975 void radv_CmdPipelineBarrier(
3976         VkCommandBuffer                             commandBuffer,
3977         VkPipelineStageFlags                        srcStageMask,
3978         VkPipelineStageFlags                        destStageMask,
3979         VkBool32                                    byRegion,
3980         uint32_t                                    memoryBarrierCount,
3981         const VkMemoryBarrier*                      pMemoryBarriers,
3982         uint32_t                                    bufferMemoryBarrierCount,
3983         const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
3984         uint32_t                                    imageMemoryBarrierCount,
3985         const VkImageMemoryBarrier*                 pImageMemoryBarriers)
3986 {
3987         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3988         enum radv_cmd_flush_bits src_flush_bits = 0;
3989         enum radv_cmd_flush_bits dst_flush_bits = 0;
3990
3991         for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3992                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3993                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3994                                                         NULL);
3995         }
3996
3997         for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3998                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3999                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4000                                                         NULL);
4001         }
4002
4003         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4004                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4005                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
4006                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4007                                                         image);
4008         }
4009
4010         radv_stage_flush(cmd_buffer, srcStageMask);
4011         cmd_buffer->state.flush_bits |= src_flush_bits;
4012
4013         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4014                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4015                 radv_handle_image_transition(cmd_buffer, image,
4016                                              pImageMemoryBarriers[i].oldLayout,
4017                                              pImageMemoryBarriers[i].newLayout,
4018                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
4019                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
4020                                              &pImageMemoryBarriers[i].subresourceRange,
4021                                              0);
4022         }
4023
4024         cmd_buffer->state.flush_bits |= dst_flush_bits;
4025 }
4026
4027
4028 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4029                         struct radv_event *event,
4030                         VkPipelineStageFlags stageMask,
4031                         unsigned value)
4032 {
4033         struct radeon_winsys_cs *cs = cmd_buffer->cs;
4034         uint64_t va = radv_buffer_get_va(event->bo);
4035
4036         radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4037
4038         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4039
4040         /* TODO: this is overkill. Probably should figure something out from
4041          * the stage mask. */
4042
4043         si_cs_emit_write_event_eop(cs,
4044                                    cmd_buffer->state.predicating,
4045                                    cmd_buffer->device->physical_device->rad_info.chip_class,
4046                                    radv_cmd_buffer_uses_mec(cmd_buffer),
4047                                    V_028A90_BOTTOM_OF_PIPE_TS, 0,
4048                                    1, va, 2, value);
4049
4050         assert(cmd_buffer->cs->cdw <= cdw_max);
4051 }
4052
4053 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4054                       VkEvent _event,
4055                       VkPipelineStageFlags stageMask)
4056 {
4057         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4058         RADV_FROM_HANDLE(radv_event, event, _event);
4059
4060         write_event(cmd_buffer, event, stageMask, 1);
4061 }
4062
4063 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4064                         VkEvent _event,
4065                         VkPipelineStageFlags stageMask)
4066 {
4067         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4068         RADV_FROM_HANDLE(radv_event, event, _event);
4069
4070         write_event(cmd_buffer, event, stageMask, 0);
4071 }
4072
4073 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4074                         uint32_t eventCount,
4075                         const VkEvent* pEvents,
4076                         VkPipelineStageFlags srcStageMask,
4077                         VkPipelineStageFlags dstStageMask,
4078                         uint32_t memoryBarrierCount,
4079                         const VkMemoryBarrier* pMemoryBarriers,
4080                         uint32_t bufferMemoryBarrierCount,
4081                         const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4082                         uint32_t imageMemoryBarrierCount,
4083                         const VkImageMemoryBarrier* pImageMemoryBarriers)
4084 {
4085         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4086         struct radeon_winsys_cs *cs = cmd_buffer->cs;
4087
4088         for (unsigned i = 0; i < eventCount; ++i) {
4089                 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4090                 uint64_t va = radv_buffer_get_va(event->bo);
4091
4092                 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4093
4094                 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4095
4096                 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4097                 assert(cmd_buffer->cs->cdw <= cdw_max);
4098         }
4099
4100
4101         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4102                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4103
4104                 radv_handle_image_transition(cmd_buffer, image,
4105                                              pImageMemoryBarriers[i].oldLayout,
4106                                              pImageMemoryBarriers[i].newLayout,
4107                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
4108                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
4109                                              &pImageMemoryBarriers[i].subresourceRange,
4110                                              0);
4111         }
4112
4113         /* TODO: figure out how to do memory barriers without waiting */
4114         cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4115                                         RADV_CMD_FLAG_INV_GLOBAL_L2 |
4116                                         RADV_CMD_FLAG_INV_VMEM_L1 |
4117                                         RADV_CMD_FLAG_INV_SMEM_L1;
4118 }
4119
4120
4121 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4122                            uint32_t deviceMask)
4123 {
4124    /* No-op */
4125 }