src/amd/vulkan/radv_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "radv_private.h"
  29 #include "radv_radeon_winsys.h"
  30 #include "radv_shader.h"
  31 #include "radv_cs.h"
  32 #include "sid.h"
  33 #include "gfx9d.h"
  34 #include "vk_format.h"
  35 #include "radv_debug.h"
  36 #include "radv_meta.h"
  37
  38 #include "ac_debug.h"
  39
  40 enum {
  41         RADV_PREFETCH_VBO_DESCRIPTORS   = (1 << 0),
  42         RADV_PREFETCH_VS                = (1 << 1),
  43         RADV_PREFETCH_TCS               = (1 << 2),
  44         RADV_PREFETCH_TES               = (1 << 3),
  45         RADV_PREFETCH_GS                = (1 << 4),
  46         RADV_PREFETCH_PS                = (1 << 5),
  47         RADV_PREFETCH_SHADERS           = (RADV_PREFETCH_VS  |
  48                                            RADV_PREFETCH_TCS |
  49                                            RADV_PREFETCH_TES |
  50                                            RADV_PREFETCH_GS  |
  51                                            RADV_PREFETCH_PS)
  52 };
  53
  54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
  55                                          struct radv_image *image,
  56                                          VkImageLayout src_layout,
  57                                          VkImageLayout dst_layout,
  58                                          uint32_t src_family,
  59                                          uint32_t dst_family,
  60                                          const VkImageSubresourceRange *range);
  61
  62 const struct radv_dynamic_state default_dynamic_state = {
  63         .viewport = {
  64                 .count = 0,
  65         },
  66         .scissor = {
  67                 .count = 0,
  68         },
  69         .line_width = 1.0f,
  70         .depth_bias = {
  71                 .bias = 0.0f,
  72                 .clamp = 0.0f,
  73                 .slope = 0.0f,
  74         },
  75         .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
  76         .depth_bounds = {
  77                 .min = 0.0f,
  78                 .max = 1.0f,
  79         },
  80         .stencil_compare_mask = {
  81                 .front = ~0u,
  82                 .back = ~0u,
  83         },
  84         .stencil_write_mask = {
  85                 .front = ~0u,
  86                 .back = ~0u,
  87         },
  88         .stencil_reference = {
  89                 .front = 0u,
  90                 .back = 0u,
  91         },
  92 };
  93
  94 static void
  95 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
  96                         const struct radv_dynamic_state *src)
  97 {
  98         struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
  99         uint32_t copy_mask = src->mask;
 100         uint32_t dest_mask = 0;
 101
 102         /* Make sure to copy the number of viewports/scissors because they can
 103          * only be specified at pipeline creation time.
 104          */
 105         dest->viewport.count = src->viewport.count;
 106         dest->scissor.count = src->scissor.count;
 107         dest->discard_rectangle.count = src->discard_rectangle.count;
 108
 109         if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
 110                 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
 111                            src->viewport.count * sizeof(VkViewport))) {
 112                         typed_memcpy(dest->viewport.viewports,
 113                                      src->viewport.viewports,
 114                                      src->viewport.count);
 115                         dest_mask |= RADV_DYNAMIC_VIEWPORT;
 116                 }
 117         }
 118
 119         if (copy_mask & RADV_DYNAMIC_SCISSOR) {
 120                 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
 121                            src->scissor.count * sizeof(VkRect2D))) {
 122                         typed_memcpy(dest->scissor.scissors,
 123                                      src->scissor.scissors, src->scissor.count);
 124                         dest_mask |= RADV_DYNAMIC_SCISSOR;
 125                 }
 126         }
 127
 128         if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
 129                 if (dest->line_width != src->line_width) {
 130                         dest->line_width = src->line_width;
 131                         dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
 132                 }
 133         }
 134
 135         if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
 136                 if (memcmp(&dest->depth_bias, &src->depth_bias,
 137                            sizeof(src->depth_bias))) {
 138                         dest->depth_bias = src->depth_bias;
 139                         dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
 140                 }
 141         }
 142
 143         if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
 144                 if (memcmp(&dest->blend_constants, &src->blend_constants,
 145                            sizeof(src->blend_constants))) {
 146                         typed_memcpy(dest->blend_constants,
 147                                      src->blend_constants, 4);
 148                         dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
 149                 }
 150         }
 151
 152         if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
 153                 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
 154                            sizeof(src->depth_bounds))) {
 155                         dest->depth_bounds = src->depth_bounds;
 156                         dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
 157                 }
 158         }
 159
 160         if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
 161                 if (memcmp(&dest->stencil_compare_mask,
 162                            &src->stencil_compare_mask,
 163                            sizeof(src->stencil_compare_mask))) {
 164                         dest->stencil_compare_mask = src->stencil_compare_mask;
 165                         dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
 166                 }
 167         }
 168
 169         if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
 170                 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
 171                            sizeof(src->stencil_write_mask))) {
 172                         dest->stencil_write_mask = src->stencil_write_mask;
 173                         dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
 174                 }
 175         }
 176
 177         if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
 178                 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
 179                            sizeof(src->stencil_reference))) {
 180                         dest->stencil_reference = src->stencil_reference;
 181                         dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
 182                 }
 183         }
 184
 185         if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
 186                 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
 187                            src->discard_rectangle.count * sizeof(VkRect2D))) {
 188                         typed_memcpy(dest->discard_rectangle.rectangles,
 189                                      src->discard_rectangle.rectangles,
 190                                      src->discard_rectangle.count);
 191                         dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
 192                 }
 193         }
 194
 195         cmd_buffer->state.dirty |= dest_mask;
 196 }
 197
 198 static void
 199 radv_bind_streamout_state(struct radv_cmd_buffer *cmd_buffer,
 200                           struct radv_pipeline *pipeline)
 201 {
 202         struct radv_streamout_state *so = &cmd_buffer->state.streamout;
 203         struct radv_shader_info *info;
 204
 205         if (!pipeline->streamout_shader)
 206                 return;
 207
 208         info = &pipeline->streamout_shader->info.info;
 209         for (int i = 0; i < MAX_SO_BUFFERS; i++)
 210                 so->stride_in_dw[i] = info->so.strides[i];
 211
 212         so->enabled_stream_buffers_mask = info->so.enabled_stream_buffers_mask;
 213 }
 214
 215 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
 216 {
 217         return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
 218                cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
 219 }
 220
 221 enum ring_type radv_queue_family_to_ring(int f) {
 222         switch (f) {
 223         case RADV_QUEUE_GENERAL:
 224                 return RING_GFX;
 225         case RADV_QUEUE_COMPUTE:
 226                 return RING_COMPUTE;
 227         case RADV_QUEUE_TRANSFER:
 228                 return RING_DMA;
 229         default:
 230                 unreachable("Unknown queue family");
 231         }
 232 }
 233
 234 static VkResult radv_create_cmd_buffer(
 235         struct radv_device *                         device,
 236         struct radv_cmd_pool *                       pool,
 237         VkCommandBufferLevel                        level,
 238         VkCommandBuffer*                            pCommandBuffer)
 239 {
 240         struct radv_cmd_buffer *cmd_buffer;
 241         unsigned ring;
 242         cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
 243                                VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 244         if (cmd_buffer == NULL)
 245                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 246
 247         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
 248         cmd_buffer->device = device;
 249         cmd_buffer->pool = pool;
 250         cmd_buffer->level = level;
 251
 252         if (pool) {
 253                 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
 254                 cmd_buffer->queue_family_index = pool->queue_family_index;
 255
 256         } else {
 257                 /* Init the pool_link so we can safely call list_del when we destroy
 258                  * the command buffer
 259                  */
 260                 list_inithead(&cmd_buffer->pool_link);
 261                 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
 262         }
 263
 264         ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
 265
 266         cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
 267         if (!cmd_buffer->cs) {
 268                 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 269                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 270         }
 271
 272         *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
 273
 274         list_inithead(&cmd_buffer->upload.list);
 275
 276         return VK_SUCCESS;
 277 }
 278
 279 static void
 280 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
 281 {
 282         list_del(&cmd_buffer->pool_link);
 283
 284         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 285                                  &cmd_buffer->upload.list, list) {
 286                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 287                 list_del(&up->list);
 288                 free(up);
 289         }
 290
 291         if (cmd_buffer->upload.upload_bo)
 292                 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
 293         cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
 294
 295         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
 296                 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
 297
 298         vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 299 }
 300
 301 static VkResult
 302 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 303 {
 304
 305         cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
 306
 307         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 308                                  &cmd_buffer->upload.list, list) {
 309                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 310                 list_del(&up->list);
 311                 free(up);
 312         }
 313
 314         cmd_buffer->push_constant_stages = 0;
 315         cmd_buffer->scratch_size_needed = 0;
 316         cmd_buffer->compute_scratch_size_needed = 0;
 317         cmd_buffer->esgs_ring_size_needed = 0;
 318         cmd_buffer->gsvs_ring_size_needed = 0;
 319         cmd_buffer->tess_rings_needed = false;
 320         cmd_buffer->sample_positions_needed = false;
 321
 322         if (cmd_buffer->upload.upload_bo)
 323                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 324                                    cmd_buffer->upload.upload_bo);
 325         cmd_buffer->upload.offset = 0;
 326
 327         cmd_buffer->record_result = VK_SUCCESS;
 328
 329         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
 330                 cmd_buffer->descriptors[i].dirty = 0;
 331                 cmd_buffer->descriptors[i].valid = 0;
 332                 cmd_buffer->descriptors[i].push_dirty = false;
 333         }
 334
 335         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
 336             cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
 337                 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends;
 338                 unsigned fence_offset, eop_bug_offset;
 339                 void *fence_ptr;
 340
 341                 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0, &fence_offset,
 342                                              &fence_ptr);
 343                 cmd_buffer->gfx9_fence_va =
 344                         radv_buffer_get_va(cmd_buffer->upload.upload_bo);
 345                 cmd_buffer->gfx9_fence_va += fence_offset;
 346
 347                 /* Allocate a buffer for the EOP bug on GFX9. */
 348                 radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 0,
 349                                              &eop_bug_offset, &fence_ptr);
 350                 cmd_buffer->gfx9_eop_bug_va =
 351                         radv_buffer_get_va(cmd_buffer->upload.upload_bo);
 352                 cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
 353         }
 354
 355         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
 356
 357         return cmd_buffer->record_result;
 358 }
 359
 360 static bool
 361 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
 362                                   uint64_t min_needed)
 363 {
 364         uint64_t new_size;
 365         struct radeon_winsys_bo *bo;
 366         struct radv_cmd_buffer_upload *upload;
 367         struct radv_device *device = cmd_buffer->device;
 368
 369         new_size = MAX2(min_needed, 16 * 1024);
 370         new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
 371
 372         bo = device->ws->buffer_create(device->ws,
 373                                        new_size, 4096,
 374                                        RADEON_DOMAIN_GTT,
 375                                        RADEON_FLAG_CPU_ACCESS|
 376                                        RADEON_FLAG_NO_INTERPROCESS_SHARING |
 377                                        RADEON_FLAG_32BIT,
 378                                        RADV_BO_PRIORITY_UPLOAD_BUFFER);
 379
 380         if (!bo) {
 381                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 382                 return false;
 383         }
 384
 385         radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);
 386         if (cmd_buffer->upload.upload_bo) {
 387                 upload = malloc(sizeof(*upload));
 388
 389                 if (!upload) {
 390                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
 391                         device->ws->buffer_destroy(bo);
 392                         return false;
 393                 }
 394
 395                 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
 396                 list_add(&upload->list, &cmd_buffer->upload.list);
 397         }
 398
 399         cmd_buffer->upload.upload_bo = bo;
 400         cmd_buffer->upload.size = new_size;
 401         cmd_buffer->upload.offset = 0;
 402         cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
 403
 404         if (!cmd_buffer->upload.map) {
 405                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 406                 return false;
 407         }
 408
 409         return true;
 410 }
 411
 412 bool
 413 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
 414                              unsigned size,
 415                              unsigned alignment,
 416                              unsigned *out_offset,
 417                              void **ptr)
 418 {
 419         uint64_t offset = align(cmd_buffer->upload.offset, alignment);
 420         if (offset + size > cmd_buffer->upload.size) {
 421                 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
 422                         return false;
 423                 offset = 0;
 424         }
 425
 426         *out_offset = offset;
 427         *ptr = cmd_buffer->upload.map + offset;
 428
 429         cmd_buffer->upload.offset = offset + size;
 430         return true;
 431 }
 432
 433 bool
 434 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
 435                             unsigned size, unsigned alignment,
 436                             const void *data, unsigned *out_offset)
 437 {
 438         uint8_t *ptr;
 439
 440         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
 441                                           out_offset, (void **)&ptr))
 442                 return false;
 443
 444         if (ptr)
 445                 memcpy(ptr, data, size);
 446
 447         return true;
 448 }
 449
 450 static void
 451 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
 452                             unsigned count, const uint32_t *data)
 453 {
 454         struct radeon_cmdbuf *cs = cmd_buffer->cs;
 455
 456         radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);
 457
 458         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
 459         radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
 460                     S_370_WR_CONFIRM(1) |
 461                     S_370_ENGINE_SEL(V_370_ME));
 462         radeon_emit(cs, va);
 463         radeon_emit(cs, va >> 32);
 464         radeon_emit_array(cs, data, count);
 465 }
 466
 467 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
 468 {
 469         struct radv_device *device = cmd_buffer->device;
 470         struct radeon_cmdbuf *cs = cmd_buffer->cs;
 471         uint64_t va;
 472
 473         va = radv_buffer_get_va(device->trace_bo);
 474         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
 475                 va += 4;
 476
 477         ++cmd_buffer->state.trace_id;
 478         radv_emit_write_data_packet(cmd_buffer, va, 1,
 479                                     &cmd_buffer->state.trace_id);
 480
 481         radeon_check_space(cmd_buffer->device->ws, cs, 2);
 482
 483         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
 484         radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
 485 }
 486
 487 static void
 488 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
 489                            enum radv_cmd_flush_bits flags)
 490 {
 491         if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
 492                 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
 493                                 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
 494
 495                 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
 496
 497                 /* Force wait for graphics or compute engines to be idle. */
 498                 si_cs_emit_cache_flush(cmd_buffer->cs,
 499                                        cmd_buffer->device->physical_device->rad_info.chip_class,
 500                                        &cmd_buffer->gfx9_fence_idx,
 501                                        cmd_buffer->gfx9_fence_va,
 502                                        radv_cmd_buffer_uses_mec(cmd_buffer),
 503                                        flags, cmd_buffer->gfx9_eop_bug_va);
 504         }
 505
 506         if (unlikely(cmd_buffer->device->trace_bo))
 507                 radv_cmd_buffer_trace_emit(cmd_buffer);
 508 }
 509
 510 static void
 511 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
 512                    struct radv_pipeline *pipeline, enum ring_type ring)
 513 {
 514         struct radv_device *device = cmd_buffer->device;
 515         uint32_t data[2];
 516         uint64_t va;
 517
 518         va = radv_buffer_get_va(device->trace_bo);
 519
 520         switch (ring) {
 521         case RING_GFX:
 522                 va += 8;
 523                 break;
 524         case RING_COMPUTE:
 525                 va += 16;
 526                 break;
 527         default:
 528                 assert(!"invalid ring type");
 529         }
 530
 531         data[0] = (uintptr_t)pipeline;
 532         data[1] = (uintptr_t)pipeline >> 32;
 533
 534         radv_emit_write_data_packet(cmd_buffer, va, 2, data);
 535 }
 536
 537 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 538                              VkPipelineBindPoint bind_point,
 539                              struct radv_descriptor_set *set,
 540                              unsigned idx)
 541 {
 542         struct radv_descriptor_state *descriptors_state =
 543                 radv_get_descriptors_state(cmd_buffer, bind_point);
 544
 545         descriptors_state->sets[idx] = set;
 546
 547         descriptors_state->valid |= (1u << idx); /* active descriptors */
 548         descriptors_state->dirty |= (1u << idx);
 549 }
 550
 551 static void
 552 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
 553                       VkPipelineBindPoint bind_point)
 554 {
 555         struct radv_descriptor_state *descriptors_state =
 556                 radv_get_descriptors_state(cmd_buffer, bind_point);
 557         struct radv_device *device = cmd_buffer->device;
 558         uint32_t data[MAX_SETS * 2] = {};
 559         uint64_t va;
 560         unsigned i;
 561         va = radv_buffer_get_va(device->trace_bo) + 24;
 562
 563         for_each_bit(i, descriptors_state->valid) {
 564                 struct radv_descriptor_set *set = descriptors_state->sets[i];
 565                 data[i * 2] = (uintptr_t)set;
 566                 data[i * 2 + 1] = (uintptr_t)set >> 32;
 567         }
 568
 569         radv_emit_write_data_packet(cmd_buffer, va, MAX_SETS * 2, data);
 570 }
 571
 572 struct radv_userdata_info *
 573 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
 574                       gl_shader_stage stage,
 575                       int idx)
 576 {
 577         struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
 578         return &shader->info.user_sgprs_locs.shader_data[idx];
 579 }
 580
 581 static void
 582 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
 583                            struct radv_pipeline *pipeline,
 584                            gl_shader_stage stage,
 585                            int idx, uint64_t va)
 586 {
 587         struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
 588         uint32_t base_reg = pipeline->user_data_0[stage];
 589         if (loc->sgpr_idx == -1)
 590                 return;
 591
 592         assert(loc->num_sgprs == 1);
 593
 594         radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
 595                                  base_reg + loc->sgpr_idx * 4, va, false);
 596 }
 597
 598 static void
 599 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
 600                               struct radv_pipeline *pipeline,
 601                               struct radv_descriptor_state *descriptors_state,
 602                               gl_shader_stage stage)
 603 {
 604         struct radv_device *device = cmd_buffer->device;
 605         struct radeon_cmdbuf *cs = cmd_buffer->cs;
 606         uint32_t sh_base = pipeline->user_data_0[stage];
 607         struct radv_userdata_locations *locs =
 608                 &pipeline->shaders[stage]->info.user_sgprs_locs;
 609         unsigned mask = locs->descriptor_sets_enabled;
 610
 611         mask &= descriptors_state->dirty & descriptors_state->valid;
 612
 613         while (mask) {
 614                 int start, count;
 615
 616                 u_bit_scan_consecutive_range(&mask, &start, &count);
 617
 618                 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
 619                 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
 620
 621                 radv_emit_shader_pointer_head(cs, sh_offset, count, true);
 622                 for (int i = 0; i < count; i++) {
 623                         struct radv_descriptor_set *set =
 624                                 descriptors_state->sets[start + i];
 625
 626                         radv_emit_shader_pointer_body(device, cs, set->va, true);
 627                 }
 628         }
 629 }
 630
 631 static void
 632 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
 633                               struct radv_pipeline *pipeline)
 634 {
 635         int num_samples = pipeline->graphics.ms.num_samples;
 636         struct radv_multisample_state *ms = &pipeline->graphics.ms;
 637         struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
 638
 639         if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
 640                 cmd_buffer->sample_positions_needed = true;
 641
 642         if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
 643                 return;
 644
 645         radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
 646         radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
 647         radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
 648
 649         radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
 650
 651         radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
 652
 653         /* GFX9: Flush DFSM when the AA mode changes. */
 654         if (cmd_buffer->device->dfsm_allowed) {
 655                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 656                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
 657         }
 658
 659         cmd_buffer->state.context_roll_without_scissor_emitted = true;
 660 }
 661
 662 static void
 663 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
 664                           struct radv_shader_variant *shader)
 665 {
 666         uint64_t va;
 667
 668         if (!shader)
 669                 return;
 670
 671         va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 672
 673         si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
 674 }
 675
 676 static void
 677 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
 678                       struct radv_pipeline *pipeline,
 679                       bool vertex_stage_only)
 680 {
 681         struct radv_cmd_state *state = &cmd_buffer->state;
 682         uint32_t mask = state->prefetch_L2_mask;
 683
 684         if (vertex_stage_only) {
 685                 /* Fast prefetch path for starting draws as soon as possible.
 686                  */
 687                 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
 688                                                   RADV_PREFETCH_VBO_DESCRIPTORS);
 689         }
 690
 691         if (mask & RADV_PREFETCH_VS)
 692                 radv_emit_shader_prefetch(cmd_buffer,
 693                                           pipeline->shaders[MESA_SHADER_VERTEX]);
 694
 695         if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
 696                 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
 697
 698         if (mask & RADV_PREFETCH_TCS)
 699                 radv_emit_shader_prefetch(cmd_buffer,
 700                                           pipeline->shaders[MESA_SHADER_TESS_CTRL]);
 701
 702         if (mask & RADV_PREFETCH_TES)
 703                 radv_emit_shader_prefetch(cmd_buffer,
 704                                           pipeline->shaders[MESA_SHADER_TESS_EVAL]);
 705
 706         if (mask & RADV_PREFETCH_GS) {
 707                 radv_emit_shader_prefetch(cmd_buffer,
 708                                           pipeline->shaders[MESA_SHADER_GEOMETRY]);
 709                 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
 710         }
 711
 712         if (mask & RADV_PREFETCH_PS)
 713                 radv_emit_shader_prefetch(cmd_buffer,
 714                                           pipeline->shaders[MESA_SHADER_FRAGMENT]);
 715
 716         state->prefetch_L2_mask &= ~mask;
 717 }
 718
 719 static void
 720 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
 721 {
 722         if (!cmd_buffer->device->physical_device->rbplus_allowed)
 723                 return;
 724
 725         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 726         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
 727         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 728
 729         unsigned sx_ps_downconvert = 0;
 730         unsigned sx_blend_opt_epsilon = 0;
 731         unsigned sx_blend_opt_control = 0;
 732
 733         for (unsigned i = 0; i < subpass->color_count; ++i) {
 734                 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
 735                         sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 736                         sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 737                         continue;
 738                 }
 739
 740                 int idx = subpass->color_attachments[i].attachment;
 741                 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
 742
 743                 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
 744                 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
 745                 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
 746                 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
 747
 748                 bool has_alpha, has_rgb;
 749
 750                 /* Set if RGB and A are present. */
 751                 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
 752
 753                 if (format == V_028C70_COLOR_8 ||
 754                     format == V_028C70_COLOR_16 ||
 755                     format == V_028C70_COLOR_32)
 756                         has_rgb = !has_alpha;
 757                 else
 758                         has_rgb = true;
 759
 760                 /* Check the colormask and export format. */
 761                 if (!(colormask & 0x7))
 762                         has_rgb = false;
 763                 if (!(colormask & 0x8))
 764                         has_alpha = false;
 765
 766                 if (spi_format == V_028714_SPI_SHADER_ZERO) {
 767                         has_rgb = false;
 768                         has_alpha = false;
 769                 }
 770
 771                 /* Disable value checking for disabled channels. */
 772                 if (!has_rgb)
 773                         sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 774                 if (!has_alpha)
 775                         sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 776
 777                 /* Enable down-conversion for 32bpp and smaller formats. */
 778                 switch (format) {
 779                 case V_028C70_COLOR_8:
 780                 case V_028C70_COLOR_8_8:
 781                 case V_028C70_COLOR_8_8_8_8:
 782                         /* For 1 and 2-channel formats, use the superset thereof. */
 783                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
 784                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 785                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 786                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
 787                                 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
 788                         }
 789                         break;
 790
 791                 case V_028C70_COLOR_5_6_5:
 792                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 793                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
 794                                 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
 795                         }
 796                         break;
 797
 798                 case V_028C70_COLOR_1_5_5_5:
 799                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 800                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
 801                                 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
 802                         }
 803                         break;
 804
 805                 case V_028C70_COLOR_4_4_4_4:
 806                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 807                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
 808                                 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
 809                         }
 810                         break;
 811
 812                 case V_028C70_COLOR_32:
 813                         if (swap == V_028C70_SWAP_STD &&
 814                             spi_format == V_028714_SPI_SHADER_32_R)
 815                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
 816                         else if (swap == V_028C70_SWAP_ALT_REV &&
 817                                  spi_format == V_028714_SPI_SHADER_32_AR)
 818                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
 819                         break;
 820
 821                 case V_028C70_COLOR_16:
 822                 case V_028C70_COLOR_16_16:
 823                         /* For 1-channel formats, use the superset thereof. */
 824                         if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
 825                             spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
 826                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 827                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 828                                 if (swap == V_028C70_SWAP_STD ||
 829                                     swap == V_028C70_SWAP_STD_REV)
 830                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
 831                                 else
 832                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
 833                         }
 834                         break;
 835
 836                 case V_028C70_COLOR_10_11_11:
 837                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 838                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
 839                                 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
 840                         }
 841                         break;
 842
 843                 case V_028C70_COLOR_2_10_10_10:
 844                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 845                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
 846                                 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
 847                         }
 848                         break;
 849                 }
 850         }
 851
 852         for (unsigned i = subpass->color_count; i < 8; ++i) {
 853                 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 854                 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 855         }
 856         /* TODO: avoid redundantly setting context registers */
 857         radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
 858         radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
 859         radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
 860         radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
 861
 862         cmd_buffer->state.context_roll_without_scissor_emitted = true;
 863 }
 864
 865 static void
 866 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
 867 {
 868         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 869
 870         if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
 871                 return;
 872
 873         radv_update_multisample_state(cmd_buffer, pipeline);
 874
 875         cmd_buffer->scratch_size_needed =
 876                                   MAX2(cmd_buffer->scratch_size_needed,
 877                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
 878
 879         if (!cmd_buffer->state.emitted_pipeline ||
 880             cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
 881              pipeline->graphics.can_use_guardband)
 882                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
 883
 884         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
 885
 886         if (!cmd_buffer->state.emitted_pipeline ||
 887             cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||
 888             cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||
 889             memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf,
 890                    pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw * 4)) {
 891                 radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);
 892                 cmd_buffer->state.context_roll_without_scissor_emitted = true;
 893         }
 894
 895         for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
 896                 if (!pipeline->shaders[i])
 897                         continue;
 898
 899                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 900                                    pipeline->shaders[i]->bo);
 901         }
 902
 903         if (radv_pipeline_has_gs(pipeline))
 904                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 905                                    pipeline->gs_copy_shader->bo);
 906
 907         if (unlikely(cmd_buffer->device->trace_bo))
 908                 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
 909
 910         cmd_buffer->state.emitted_pipeline = pipeline;
 911
 912         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
 913 }
 914
 915 static void
 916 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
 917 {
 918         si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
 919                           cmd_buffer->state.dynamic.viewport.viewports);
 920 }
 921
 922 static void
 923 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
 924 {
 925         uint32_t count = cmd_buffer->state.dynamic.scissor.count;
 926
 927         si_write_scissors(cmd_buffer->cs, 0, count,
 928                           cmd_buffer->state.dynamic.scissor.scissors,
 929                           cmd_buffer->state.dynamic.viewport.viewports,
 930                           cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
 931
 932         cmd_buffer->state.context_roll_without_scissor_emitted = false;
 933 }
 934
 935 static void
 936 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
 937 {
 938         if (!cmd_buffer->state.dynamic.discard_rectangle.count)
 939                 return;
 940
 941         radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
 942                                    cmd_buffer->state.dynamic.discard_rectangle.count * 2);
 943         for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
 944                 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
 945                 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
 946                 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
 947                                             S_028214_BR_Y(rect.offset.y + rect.extent.height));
 948         }
 949 }
 950
 951 static void
 952 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
 953 {
 954         unsigned width = cmd_buffer->state.dynamic.line_width * 8;
 955
 956         radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
 957                                S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
 958 }
 959
 960 static void
 961 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
 962 {
 963         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 964
 965         radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
 966         radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
 967 }
 968
 969 static void
 970 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
 971 {
 972         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 973
 974         radeon_set_context_reg_seq(cmd_buffer->cs,
 975                                    R_028430_DB_STENCILREFMASK, 2);
 976         radeon_emit(cmd_buffer->cs,
 977                     S_028430_STENCILTESTVAL(d->stencil_reference.front) |
 978                     S_028430_STENCILMASK(d->stencil_compare_mask.front) |
 979                     S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
 980                     S_028430_STENCILOPVAL(1));
 981         radeon_emit(cmd_buffer->cs,
 982                     S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
 983                     S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
 984                     S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
 985                     S_028434_STENCILOPVAL_BF(1));
 986 }
 987
 988 static void
 989 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
 990 {
 991         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 992
 993         radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
 994                                fui(d->depth_bounds.min));
 995         radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
 996                                fui(d->depth_bounds.max));
 997 }
 998
 999 static void
1000 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
1001 {
1002         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
1003         unsigned slope = fui(d->depth_bias.slope * 16.0f);
1004         unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
1005
1006
1007         radeon_set_context_reg_seq(cmd_buffer->cs,
1008                                    R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
1009         radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
1010         radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
1011         radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
1012         radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
1013         radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
1014 }
1015
1016 static void
1017 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
1018                          int index,
1019                          struct radv_attachment_info *att,
1020                          struct radv_image *image,
1021                          VkImageLayout layout)
1022 {
1023         bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
1024         struct radv_color_buffer_info *cb = &att->cb;
1025         uint32_t cb_color_info = cb->cb_color_info;
1026
1027         if (!radv_layout_dcc_compressed(image, layout,
1028                                         radv_image_queue_family_mask(image,
1029                                                                      cmd_buffer->queue_family_index,
1030                                                                      cmd_buffer->queue_family_index))) {
1031                 cb_color_info &= C_028C70_DCC_ENABLE;
1032         }
1033
1034         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1035                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1036                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1037                 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1038                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1039                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1040                 radeon_emit(cmd_buffer->cs, cb_color_info);
1041                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1042                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1043                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1044                 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1045                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1046                 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1047
1048                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1049                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1050                 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1051
1052                 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1053                                        S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1054         } else {
1055                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1056                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1057                 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1058                 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1059                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1060                 radeon_emit(cmd_buffer->cs, cb_color_info);
1061                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1062                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1063                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1064                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1065                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1066                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1067
1068                 if (is_vi) { /* DCC BASE */
1069                         radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1070                 }
1071         }
1072
1073         if (radv_image_has_dcc(image)) {
1074                 /* Drawing with DCC enabled also compresses colorbuffers. */
1075                 radv_update_dcc_metadata(cmd_buffer, image, true);
1076         }
1077 }
1078
1079 static void
1080 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1081                              struct radv_ds_buffer_info *ds,
1082                              struct radv_image *image, VkImageLayout layout,
1083                              bool requires_cond_exec)
1084 {
1085         uint32_t db_z_info = ds->db_z_info;
1086         uint32_t db_z_info_reg;
1087
1088         if (!radv_image_is_tc_compat_htile(image))
1089                 return;
1090
1091         if (!radv_layout_has_htile(image, layout,
1092                                    radv_image_queue_family_mask(image,
1093                                                                 cmd_buffer->queue_family_index,
1094                                                                 cmd_buffer->queue_family_index))) {
1095                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1096         }
1097
1098         db_z_info &= C_028040_ZRANGE_PRECISION;
1099
1100         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1101                 db_z_info_reg = R_028038_DB_Z_INFO;
1102         } else {
1103                 db_z_info_reg = R_028040_DB_Z_INFO;
1104         }
1105
1106         /* When we don't know the last fast clear value we need to emit a
1107          * conditional packet that will eventually skip the following
1108          * SET_CONTEXT_REG packet.
1109          */
1110         if (requires_cond_exec) {
1111                 uint64_t va = radv_buffer_get_va(image->bo);
1112                 va += image->offset + image->tc_compat_zrange_offset;
1113
1114                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));
1115                 radeon_emit(cmd_buffer->cs, va);
1116                 radeon_emit(cmd_buffer->cs, va >> 32);
1117                 radeon_emit(cmd_buffer->cs, 0);
1118                 radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */
1119         }
1120
1121         radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1122 }
1123
1124 static void
1125 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1126                       struct radv_ds_buffer_info *ds,
1127                       struct radv_image *image,
1128                       VkImageLayout layout)
1129 {
1130         uint32_t db_z_info = ds->db_z_info;
1131         uint32_t db_stencil_info = ds->db_stencil_info;
1132
1133         if (!radv_layout_has_htile(image, layout,
1134                                    radv_image_queue_family_mask(image,
1135                                                                 cmd_buffer->queue_family_index,
1136                                                                 cmd_buffer->queue_family_index))) {
1137                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1138                 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1139         }
1140
1141         radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1142         radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1143
1144
1145         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1146                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1147                 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1148                 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1149                 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1150
1151                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1152                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* DB_Z_INFO */
1153                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* DB_STENCIL_INFO */
1154                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* DB_Z_READ_BASE */
1155                 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32));        /* DB_Z_READ_BASE_HI */
1156                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* DB_STENCIL_READ_BASE */
1157                 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1158                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* DB_Z_WRITE_BASE */
1159                 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32));       /* DB_Z_WRITE_BASE_HI */
1160                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1161                 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1162
1163                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1164                 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1165                 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1166         } else {
1167                 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1168
1169                 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1170                 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1171                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* R_028040_DB_Z_INFO */
1172                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* R_028044_DB_STENCIL_INFO */
1173                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* R_028048_DB_Z_READ_BASE */
1174                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* R_02804C_DB_STENCIL_READ_BASE */
1175                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* R_028050_DB_Z_WRITE_BASE */
1176                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1177                 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1178                 radeon_emit(cmd_buffer->cs, ds->db_depth_slice);        /* R_02805C_DB_DEPTH_SLICE */
1179
1180         }
1181
1182         /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1183         radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1184
1185         radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1186                                ds->pa_su_poly_offset_db_fmt_cntl);
1187 }
1188
1189 /**
1190  * Update the fast clear depth/stencil values if the image is bound as a
1191  * depth/stencil buffer.
1192  */
1193 static void
1194 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1195                                 struct radv_image *image,
1196                                 VkClearDepthStencilValue ds_clear_value,
1197                                 VkImageAspectFlags aspects)
1198 {
1199         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1200         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1201         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1202         struct radv_attachment_info *att;
1203         uint32_t att_idx;
1204
1205         if (!framebuffer || !subpass)
1206                 return;
1207
1208         if (!subpass->depth_stencil_attachment)
1209                 return;
1210
1211         att_idx = subpass->depth_stencil_attachment->attachment;
1212         att = &framebuffer->attachments[att_idx];
1213         if (att->attachment->image != image)
1214                 return;
1215
1216         radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1217         radeon_emit(cs, ds_clear_value.stencil);
1218         radeon_emit(cs, fui(ds_clear_value.depth));
1219
1220         /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1221          * only needed when clearing Z to 0.0.
1222          */
1223         if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1224             ds_clear_value.depth == 0.0) {
1225                 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1226
1227                 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1228                                              layout, false);
1229         }
1230
1231         cmd_buffer->state.context_roll_without_scissor_emitted = true;
1232 }
1233
1234 /**
1235  * Set the clear depth/stencil values to the image's metadata.
1236  */
1237 static void
1238 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1239                            struct radv_image *image,
1240                            VkClearDepthStencilValue ds_clear_value,
1241                            VkImageAspectFlags aspects)
1242 {
1243         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1244         uint64_t va = radv_buffer_get_va(image->bo);
1245         unsigned reg_offset = 0, reg_count = 0;
1246
1247         va += image->offset + image->clear_value_offset;
1248
1249         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1250                 ++reg_count;
1251         } else {
1252                 ++reg_offset;
1253                 va += 4;
1254         }
1255         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1256                 ++reg_count;
1257
1258         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1259         radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1260                         S_370_WR_CONFIRM(1) |
1261                         S_370_ENGINE_SEL(V_370_PFP));
1262         radeon_emit(cs, va);
1263         radeon_emit(cs, va >> 32);
1264         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1265                 radeon_emit(cs, ds_clear_value.stencil);
1266         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1267                 radeon_emit(cs, fui(ds_clear_value.depth));
1268 }
1269
1270 /**
1271  * Update the TC-compat metadata value for this image.
1272  */
1273 static void
1274 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1275                                    struct radv_image *image,
1276                                    uint32_t value)
1277 {
1278         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1279         uint64_t va = radv_buffer_get_va(image->bo);
1280         va += image->offset + image->tc_compat_zrange_offset;
1281
1282         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1283         radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1284                         S_370_WR_CONFIRM(1) |
1285                         S_370_ENGINE_SEL(V_370_PFP));
1286         radeon_emit(cs, va);
1287         radeon_emit(cs, va >> 32);
1288         radeon_emit(cs, value);
1289 }
1290
1291 static void
1292 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,
1293                                       struct radv_image *image,
1294                                       VkClearDepthStencilValue ds_clear_value)
1295 {
1296         uint64_t va = radv_buffer_get_va(image->bo);
1297         va += image->offset + image->tc_compat_zrange_offset;
1298         uint32_t cond_val;
1299
1300         /* Conditionally set DB_Z_INFO.ZRANGE_PRECISION to 0 when the last
1301          * depth clear value is 0.0f.
1302          */
1303         cond_val = ds_clear_value.depth == 0.0f ? UINT_MAX : 0;
1304
1305         radv_set_tc_compat_zrange_metadata(cmd_buffer, image, cond_val);
1306 }
1307
1308 /**
1309  * Update the clear depth/stencil values for this image.
1310  */
1311 void
1312 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1313                               struct radv_image *image,
1314                               VkClearDepthStencilValue ds_clear_value,
1315                               VkImageAspectFlags aspects)
1316 {
1317         assert(radv_image_has_htile(image));
1318
1319         radv_set_ds_clear_metadata(cmd_buffer, image, ds_clear_value, aspects);
1320
1321         if (radv_image_is_tc_compat_htile(image) &&
1322             (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
1323                 radv_update_tc_compat_zrange_metadata(cmd_buffer, image,
1324                                                       ds_clear_value);
1325         }
1326
1327         radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1328                                         aspects);
1329 }
1330
1331 /**
1332  * Load the clear depth/stencil values from the image's metadata.
1333  */
1334 static void
1335 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1336                             struct radv_image *image)
1337 {
1338         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1339         VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1340         uint64_t va = radv_buffer_get_va(image->bo);
1341         unsigned reg_offset = 0, reg_count = 0;
1342
1343         va += image->offset + image->clear_value_offset;
1344
1345         if (!radv_image_has_htile(image))
1346                 return;
1347
1348         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1349                 ++reg_count;
1350         } else {
1351                 ++reg_offset;
1352                 va += 4;
1353         }
1354         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1355                 ++reg_count;
1356
1357         uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
1358
1359         if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1360                 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
1361                 radeon_emit(cs, va);
1362                 radeon_emit(cs, va >> 32);
1363                 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1364                 radeon_emit(cs, reg_count);
1365         } else {
1366                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1367                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1368                                 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1369                                 (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1370                 radeon_emit(cs, va);
1371                 radeon_emit(cs, va >> 32);
1372                 radeon_emit(cs, reg >> 2);
1373                 radeon_emit(cs, 0);
1374
1375                 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1376                 radeon_emit(cs, 0);
1377         }
1378 }
1379
1380 /*
1381  * With DCC some colors don't require CMASK elimination before being
1382  * used as a texture. This sets a predicate value to determine if the
1383  * cmask eliminate is required.
1384  */
1385 void
1386 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer,
1387                          struct radv_image *image, bool value)
1388 {
1389         uint64_t pred_val = value;
1390         uint64_t va = radv_buffer_get_va(image->bo);
1391         va += image->offset + image->fce_pred_offset;
1392
1393         assert(radv_image_has_dcc(image));
1394
1395         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1396         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1397                                     S_370_WR_CONFIRM(1) |
1398                                     S_370_ENGINE_SEL(V_370_PFP));
1399         radeon_emit(cmd_buffer->cs, va);
1400         radeon_emit(cmd_buffer->cs, va >> 32);
1401         radeon_emit(cmd_buffer->cs, pred_val);
1402         radeon_emit(cmd_buffer->cs, pred_val >> 32);
1403 }
1404
1405 /**
1406  * Update the DCC predicate to reflect the compression state.
1407  */
1408 void
1409 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer,
1410                          struct radv_image *image, bool value)
1411 {
1412         uint64_t pred_val = value;
1413         uint64_t va = radv_buffer_get_va(image->bo);
1414         va += image->offset + image->dcc_pred_offset;
1415
1416         assert(radv_image_has_dcc(image));
1417
1418         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1419         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM) |
1420                                     S_370_WR_CONFIRM(1) |
1421                                     S_370_ENGINE_SEL(V_370_PFP));
1422         radeon_emit(cmd_buffer->cs, va);
1423         radeon_emit(cmd_buffer->cs, va >> 32);
1424         radeon_emit(cmd_buffer->cs, pred_val);
1425         radeon_emit(cmd_buffer->cs, pred_val >> 32);
1426 }
1427
1428 /**
1429  * Update the fast clear color values if the image is bound as a color buffer.
1430  */
1431 static void
1432 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1433                                    struct radv_image *image,
1434                                    int cb_idx,
1435                                    uint32_t color_values[2])
1436 {
1437         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1438         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1439         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1440         struct radv_attachment_info *att;
1441         uint32_t att_idx;
1442
1443         if (!framebuffer || !subpass)
1444                 return;
1445
1446         att_idx = subpass->color_attachments[cb_idx].attachment;
1447         if (att_idx == VK_ATTACHMENT_UNUSED)
1448                 return;
1449
1450         att = &framebuffer->attachments[att_idx];
1451         if (att->attachment->image != image)
1452                 return;
1453
1454         radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1455         radeon_emit(cs, color_values[0]);
1456         radeon_emit(cs, color_values[1]);
1457
1458         cmd_buffer->state.context_roll_without_scissor_emitted = true;
1459 }
1460
1461 /**
1462  * Set the clear color values to the image's metadata.
1463  */
1464 static void
1465 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1466                               struct radv_image *image,
1467                               uint32_t color_values[2])
1468 {
1469         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1470         uint64_t va = radv_buffer_get_va(image->bo);
1471
1472         va += image->offset + image->clear_value_offset;
1473
1474         assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1475
1476         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1477         radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
1478                         S_370_WR_CONFIRM(1) |
1479                         S_370_ENGINE_SEL(V_370_PFP));
1480         radeon_emit(cs, va);
1481         radeon_emit(cs, va >> 32);
1482         radeon_emit(cs, color_values[0]);
1483         radeon_emit(cs, color_values[1]);
1484 }
1485
1486 /**
1487  * Update the clear color values for this image.
1488  */
1489 void
1490 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1491                                  struct radv_image *image,
1492                                  int cb_idx,
1493                                  uint32_t color_values[2])
1494 {
1495         assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1496
1497         radv_set_color_clear_metadata(cmd_buffer, image, color_values);
1498
1499         radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1500                                            color_values);
1501 }
1502
1503 /**
1504  * Load the clear color values from the image's metadata.
1505  */
1506 static void
1507 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1508                                struct radv_image *image,
1509                                int cb_idx)
1510 {
1511         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1512         uint64_t va = radv_buffer_get_va(image->bo);
1513
1514         va += image->offset + image->clear_value_offset;
1515
1516         if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1517                 return;
1518
1519         uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1520
1521         if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1522                 radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
1523                 radeon_emit(cs, va);
1524                 radeon_emit(cs, va >> 32);
1525                 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
1526                 radeon_emit(cs, 2);
1527         } else {
1528                 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
1529                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1530                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
1531                                 COPY_DATA_DST_SEL(COPY_DATA_REG) |
1532                                 COPY_DATA_COUNT_SEL);
1533                 radeon_emit(cs, va);
1534                 radeon_emit(cs, va >> 32);
1535                 radeon_emit(cs, reg >> 2);
1536                 radeon_emit(cs, 0);
1537
1538                 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1539                 radeon_emit(cs, 0);
1540         }
1541 }
1542
1543 static void
1544 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1545 {
1546         int i;
1547         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1548         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1549         unsigned num_bpp64_colorbufs = 0;
1550
1551         /* this may happen for inherited secondary recording */
1552         if (!framebuffer)
1553                 return;
1554
1555         for (i = 0; i < 8; ++i) {
1556                 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1557                         radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1558                                        S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1559                         continue;
1560                 }
1561
1562                 int idx = subpass->color_attachments[i].attachment;
1563                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1564                 struct radv_image *image = att->attachment->image;
1565                 VkImageLayout layout = subpass->color_attachments[i].layout;
1566
1567                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1568
1569                 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1570                 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1571
1572                 radv_load_color_clear_metadata(cmd_buffer, image, i);
1573
1574                 if (image->surface.bpe >= 8)
1575                         num_bpp64_colorbufs++;
1576         }
1577
1578         if (subpass->depth_stencil_attachment) {
1579                 int idx = subpass->depth_stencil_attachment->attachment;
1580                 VkImageLayout layout = subpass->depth_stencil_attachment->layout;
1581                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1582                 struct radv_image *image = att->attachment->image;
1583                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo);
1584                 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1585                                                                                 cmd_buffer->queue_family_index,
1586                                                                                 cmd_buffer->queue_family_index);
1587                 /* We currently don't support writing decompressed HTILE */
1588                 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1589                        radv_layout_is_htile_compressed(image, layout, queue_mask));
1590
1591                 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1592
1593                 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1594                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1595                         cmd_buffer->state.offset_scale = att->ds.offset_scale;
1596                 }
1597                 radv_load_ds_clear_metadata(cmd_buffer, image);
1598         } else {
1599                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1600                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1601                 else
1602                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1603
1604                 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1605                 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1606         }
1607         radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1608                                S_028208_BR_X(framebuffer->width) |
1609                                S_028208_BR_Y(framebuffer->height));
1610
1611         if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
1612                 uint8_t watermark = 4; /* Default value for VI. */
1613
1614                 /* For optimal DCC performance. */
1615                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1616                         if (num_bpp64_colorbufs >= 5) {
1617                                 watermark = 8;
1618                         } else {
1619                                 watermark = 6;
1620                         }
1621                 }
1622
1623                 radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
1624                                        S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
1625                                        S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
1626         }
1627
1628         if (cmd_buffer->device->dfsm_allowed) {
1629                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1630                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1631         }
1632
1633         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1634 }
1635
1636 static void
1637 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1638 {
1639         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1640         struct radv_cmd_state *state = &cmd_buffer->state;
1641
1642         if (state->index_type != state->last_index_type) {
1643                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1644                         radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1645                                                    2, state->index_type);
1646                 } else {
1647                         radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1648                         radeon_emit(cs, state->index_type);
1649                 }
1650
1651                 state->last_index_type = state->index_type;
1652         }
1653
1654         radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1655         radeon_emit(cs, state->index_va);
1656         radeon_emit(cs, state->index_va >> 32);
1657
1658         radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1659         radeon_emit(cs, state->max_index_count);
1660
1661         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1662 }
1663
1664 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1665 {
1666         bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1667         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1668         uint32_t pa_sc_mode_cntl_1 =
1669                 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1670         uint32_t db_count_control;
1671
1672         if(!cmd_buffer->state.active_occlusion_queries) {
1673                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1674                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1675                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1676                             has_perfect_queries) {
1677                                 /* Re-enable out-of-order rasterization if the
1678                                  * bound pipeline supports it and if it's has
1679                                  * been disabled before starting any perfect
1680                                  * occlusion queries.
1681                                  */
1682                                 radeon_set_context_reg(cmd_buffer->cs,
1683                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1684                                                        pa_sc_mode_cntl_1);
1685                         }
1686                 }
1687                 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1688         } else {
1689                 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1690                 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1691
1692                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1693                         db_count_control =
1694                                 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1695                                 S_028004_SAMPLE_RATE(sample_rate) |
1696                                 S_028004_ZPASS_ENABLE(1) |
1697                                 S_028004_SLICE_EVEN_ENABLE(1) |
1698                                 S_028004_SLICE_ODD_ENABLE(1);
1699
1700                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1701                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1702                             has_perfect_queries) {
1703                                 /* If the bound pipeline has enabled
1704                                  * out-of-order rasterization, we should
1705                                  * disable it before starting any perfect
1706                                  * occlusion queries.
1707                                  */
1708                                 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1709
1710                                 radeon_set_context_reg(cmd_buffer->cs,
1711                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1712                                                        pa_sc_mode_cntl_1);
1713                         }
1714                 } else {
1715                         db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1716                                 S_028004_SAMPLE_RATE(sample_rate);
1717                 }
1718         }
1719
1720         radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1721
1722         cmd_buffer->state.context_roll_without_scissor_emitted = true;
1723 }
1724
1725 static void
1726 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1727 {
1728         uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1729
1730         if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1731                 radv_emit_viewport(cmd_buffer);
1732
1733         if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1734             !cmd_buffer->device->physical_device->has_scissor_bug)
1735                 radv_emit_scissor(cmd_buffer);
1736
1737         if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1738                 radv_emit_line_width(cmd_buffer);
1739
1740         if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1741                 radv_emit_blend_constants(cmd_buffer);
1742
1743         if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1744                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1745                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1746                 radv_emit_stencil(cmd_buffer);
1747
1748         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1749                 radv_emit_depth_bounds(cmd_buffer);
1750
1751         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1752                 radv_emit_depth_bias(cmd_buffer);
1753
1754         if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1755                 radv_emit_discard_rectangle(cmd_buffer);
1756
1757         cmd_buffer->state.dirty &= ~states;
1758 }
1759
1760 static void
1761 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1762                             VkPipelineBindPoint bind_point)
1763 {
1764         struct radv_descriptor_state *descriptors_state =
1765                 radv_get_descriptors_state(cmd_buffer, bind_point);
1766         struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1767         unsigned bo_offset;
1768
1769         if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1770                                          set->mapped_ptr,
1771                                          &bo_offset))
1772                 return;
1773
1774         set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1775         set->va += bo_offset;
1776 }
1777
1778 static void
1779 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1780                                     VkPipelineBindPoint bind_point)
1781 {
1782         struct radv_descriptor_state *descriptors_state =
1783                 radv_get_descriptors_state(cmd_buffer, bind_point);
1784         uint32_t size = MAX_SETS * 4;
1785         uint32_t offset;
1786         void *ptr;
1787
1788         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1789                                           256, &offset, &ptr))
1790                 return;
1791
1792         for (unsigned i = 0; i < MAX_SETS; i++) {
1793                 uint32_t *uptr = ((uint32_t *)ptr) + i;
1794                 uint64_t set_va = 0;
1795                 struct radv_descriptor_set *set = descriptors_state->sets[i];
1796                 if (descriptors_state->valid & (1u << i))
1797                         set_va = set->va;
1798                 uptr[0] = set_va & 0xffffffff;
1799         }
1800
1801         uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1802         va += offset;
1803
1804         if (cmd_buffer->state.pipeline) {
1805                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1806                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1807                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1808
1809                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1810                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1811                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1812
1813                 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1814                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1815                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1816
1817                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1818                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1819                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1820
1821                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1822                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1823                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1824         }
1825
1826         if (cmd_buffer->state.compute_pipeline)
1827                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1828                                            AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1829 }
1830
1831 static void
1832 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1833                        VkShaderStageFlags stages)
1834 {
1835         VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1836                                          VK_PIPELINE_BIND_POINT_COMPUTE :
1837                                          VK_PIPELINE_BIND_POINT_GRAPHICS;
1838         struct radv_descriptor_state *descriptors_state =
1839                 radv_get_descriptors_state(cmd_buffer, bind_point);
1840         struct radv_cmd_state *state = &cmd_buffer->state;
1841         bool flush_indirect_descriptors;
1842
1843         if (!descriptors_state->dirty)
1844                 return;
1845
1846         if (descriptors_state->push_dirty)
1847                 radv_flush_push_descriptors(cmd_buffer, bind_point);
1848
1849         flush_indirect_descriptors =
1850                 (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS &&
1851                  state->pipeline && state->pipeline->need_indirect_descriptor_sets) ||
1852                 (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE &&
1853                  state->compute_pipeline && state->compute_pipeline->need_indirect_descriptor_sets);
1854
1855         if (flush_indirect_descriptors)
1856                 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1857
1858         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1859                                                            cmd_buffer->cs,
1860                                                            MAX_SETS * MESA_SHADER_STAGES * 4);
1861
1862         if (cmd_buffer->state.pipeline) {
1863                 radv_foreach_stage(stage, stages) {
1864                         if (!cmd_buffer->state.pipeline->shaders[stage])
1865                                 continue;
1866
1867                         radv_emit_descriptor_pointers(cmd_buffer,
1868                                                       cmd_buffer->state.pipeline,
1869                                                       descriptors_state, stage);
1870                 }
1871         }
1872
1873         if (cmd_buffer->state.compute_pipeline &&
1874             (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1875                 radv_emit_descriptor_pointers(cmd_buffer,
1876                                               cmd_buffer->state.compute_pipeline,
1877                                               descriptors_state,
1878                                               MESA_SHADER_COMPUTE);
1879         }
1880
1881         descriptors_state->dirty = 0;
1882         descriptors_state->push_dirty = false;
1883
1884         assert(cmd_buffer->cs->cdw <= cdw_max);
1885
1886         if (unlikely(cmd_buffer->device->trace_bo))
1887                 radv_save_descriptors(cmd_buffer, bind_point);
1888 }
1889
1890 static void
1891 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1892                      VkShaderStageFlags stages)
1893 {
1894         struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1895                                          ? cmd_buffer->state.compute_pipeline
1896                                          : cmd_buffer->state.pipeline;
1897         VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1898                                          VK_PIPELINE_BIND_POINT_COMPUTE :
1899                                          VK_PIPELINE_BIND_POINT_GRAPHICS;
1900         struct radv_descriptor_state *descriptors_state =
1901                 radv_get_descriptors_state(cmd_buffer, bind_point);
1902         struct radv_pipeline_layout *layout = pipeline->layout;
1903         struct radv_shader_variant *shader, *prev_shader;
1904         unsigned offset;
1905         void *ptr;
1906         uint64_t va;
1907
1908         stages &= cmd_buffer->push_constant_stages;
1909         if (!stages ||
1910             (!layout->push_constant_size && !layout->dynamic_offset_count))
1911                 return;
1912
1913         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1914                                           16 * layout->dynamic_offset_count,
1915                                           256, &offset, &ptr))
1916                 return;
1917
1918         memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1919         memcpy((char*)ptr + layout->push_constant_size,
1920                descriptors_state->dynamic_buffers,
1921                16 * layout->dynamic_offset_count);
1922
1923         va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1924         va += offset;
1925
1926         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1927                                                            cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1928
1929         prev_shader = NULL;
1930         radv_foreach_stage(stage, stages) {
1931                 shader = radv_get_shader(pipeline, stage);
1932
1933                 /* Avoid redundantly emitting the address for merged stages. */
1934                 if (shader && shader != prev_shader) {
1935                         radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1936                                                    AC_UD_PUSH_CONSTANTS, va);
1937
1938                         prev_shader = shader;
1939                 }
1940         }
1941
1942         cmd_buffer->push_constant_stages &= ~stages;
1943         assert(cmd_buffer->cs->cdw <= cdw_max);
1944 }
1945
1946 static void
1947 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1948                               bool pipeline_is_dirty)
1949 {
1950         if ((pipeline_is_dirty ||
1951             (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1952             cmd_buffer->state.pipeline->vertex_elements.count &&
1953             radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1954                 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1955                 unsigned vb_offset;
1956                 void *vb_ptr;
1957                 uint32_t i = 0;
1958                 uint32_t count = velems->count;
1959                 uint64_t va;
1960
1961                 /* allocate some descriptor state for vertex buffers */
1962                 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1963                                                   &vb_offset, &vb_ptr))
1964                         return;
1965
1966                 for (i = 0; i < count; i++) {
1967                         uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1968                         uint32_t offset;
1969                         int vb = velems->binding[i];
1970                         struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1971                         uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1972
1973                         va = radv_buffer_get_va(buffer->bo);
1974
1975                         offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1976                         va += offset + buffer->offset;
1977                         desc[0] = va;
1978                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1979                         if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1980                                 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1981                         else
1982                                 desc[2] = buffer->size - offset;
1983                         desc[3] = velems->rsrc_word3[i];
1984                 }
1985
1986                 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1987                 va += vb_offset;
1988
1989                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1990                                            AC_UD_VS_VERTEX_BUFFERS, va);
1991
1992                 cmd_buffer->state.vb_va = va;
1993                 cmd_buffer->state.vb_size = count * 16;
1994                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1995         }
1996         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1997 }
1998
1999 static void
2000 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)
2001 {
2002         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2003         struct radv_userdata_info *loc;
2004         uint32_t base_reg;
2005
2006         for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2007                 if (!radv_get_shader(pipeline, stage))
2008                         continue;
2009
2010                 loc = radv_lookup_user_sgpr(pipeline, stage,
2011                                             AC_UD_STREAMOUT_BUFFERS);
2012                 if (loc->sgpr_idx == -1)
2013                         continue;
2014
2015                 base_reg = pipeline->user_data_0[stage];
2016
2017                 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2018                                          base_reg + loc->sgpr_idx * 4, va, false);
2019         }
2020
2021         if (pipeline->gs_copy_shader) {
2022                 loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_STREAMOUT_BUFFERS];
2023                 if (loc->sgpr_idx != -1) {
2024                         base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2025
2026                         radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
2027                                                  base_reg + loc->sgpr_idx * 4, va, false);
2028                 }
2029         }
2030 }
2031
2032 static void
2033 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)
2034 {
2035         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {
2036                 struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
2037                 struct radv_streamout_state *so = &cmd_buffer->state.streamout;
2038                 unsigned so_offset;
2039                 void *so_ptr;
2040                 uint64_t va;
2041
2042                 /* Allocate some descriptor state for streamout buffers. */
2043                 if (!radv_cmd_buffer_upload_alloc(cmd_buffer,
2044                                                   MAX_SO_BUFFERS * 16, 256,
2045                                                   &so_offset, &so_ptr))
2046                         return;
2047
2048                 for (uint32_t i = 0; i < MAX_SO_BUFFERS; i++) {
2049                         struct radv_buffer *buffer = sb[i].buffer;
2050                         uint32_t *desc = &((uint32_t *)so_ptr)[i * 4];
2051
2052                         if (!(so->enabled_mask & (1 << i)))
2053                                 continue;
2054
2055                         va = radv_buffer_get_va(buffer->bo) + buffer->offset;
2056
2057                         va += sb[i].offset;
2058
2059                         /* Set the descriptor.
2060                          *
2061                          * On VI, the format must be non-INVALID, otherwise
2062                          * the buffer will be considered not bound and store
2063                          * instructions will be no-ops.
2064                          */
2065                         desc[0] = va;
2066                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2067                         desc[2] = 0xffffffff;
2068                         desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2069                                   S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2070                                   S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2071                                   S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2072                                   S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2073                 }
2074
2075                 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2076                 va += so_offset;
2077
2078                 radv_emit_streamout_buffers(cmd_buffer, va);
2079         }
2080
2081         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;
2082 }
2083
2084 static void
2085 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
2086 {
2087         radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
2088         radv_flush_streamout_descriptors(cmd_buffer);
2089         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2090         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
2091 }
2092
2093 struct radv_draw_info {
2094         /**
2095          * Number of vertices.
2096          */
2097         uint32_t count;
2098
2099         /**
2100          * Index of the first vertex.
2101          */
2102         int32_t vertex_offset;
2103
2104         /**
2105          * First instance id.
2106          */
2107         uint32_t first_instance;
2108
2109         /**
2110          * Number of instances.
2111          */
2112         uint32_t instance_count;
2113
2114         /**
2115          * First index (indexed draws only).
2116          */
2117         uint32_t first_index;
2118
2119         /**
2120          * Whether it's an indexed draw.
2121          */
2122         bool indexed;
2123
2124         /**
2125          * Indirect draw parameters resource.
2126          */
2127         struct radv_buffer *indirect;
2128         uint64_t indirect_offset;
2129         uint32_t stride;
2130
2131         /**
2132          * Draw count parameters resource.
2133          */
2134         struct radv_buffer *count_buffer;
2135         uint64_t count_buffer_offset;
2136
2137         /**
2138          * Stream output parameters resource.
2139          */
2140         struct radv_buffer *strmout_buffer;
2141         uint64_t strmout_buffer_offset;
2142 };
2143
2144 static void
2145 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
2146                          const struct radv_draw_info *draw_info)
2147 {
2148         struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
2149         struct radv_cmd_state *state = &cmd_buffer->state;
2150         struct radeon_cmdbuf *cs = cmd_buffer->cs;
2151         uint32_t ia_multi_vgt_param;
2152         int32_t primitive_reset_en;
2153
2154         /* Draw state. */
2155         ia_multi_vgt_param =
2156                 si_get_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1,
2157                                           draw_info->indirect,
2158                                           draw_info->indirect ? 0 : draw_info->count);
2159
2160         if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
2161                 if (info->chip_class >= GFX9) {
2162                         radeon_set_uconfig_reg_idx(cs,
2163                                                    R_030960_IA_MULTI_VGT_PARAM,
2164                                                    4, ia_multi_vgt_param);
2165                 } else if (info->chip_class >= CIK) {
2166                         radeon_set_context_reg_idx(cs,
2167                                                    R_028AA8_IA_MULTI_VGT_PARAM,
2168                                                    1, ia_multi_vgt_param);
2169                 } else {
2170                         radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
2171                                                ia_multi_vgt_param);
2172                 }
2173                 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
2174         }
2175
2176         /* Primitive restart. */
2177         primitive_reset_en =
2178                 draw_info->indexed && state->pipeline->graphics.prim_restart_enable;
2179
2180         if (primitive_reset_en != state->last_primitive_reset_en) {
2181                 state->last_primitive_reset_en = primitive_reset_en;
2182                 if (info->chip_class >= GFX9) {
2183                         radeon_set_uconfig_reg(cs,
2184                                                R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
2185                                                primitive_reset_en);
2186                 } else {
2187                         radeon_set_context_reg(cs,
2188                                                R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
2189                                                primitive_reset_en);
2190                 }
2191         }
2192
2193         if (primitive_reset_en) {
2194                 uint32_t primitive_reset_index =
2195                         state->index_type ? 0xffffffffu : 0xffffu;
2196
2197                 if (primitive_reset_index != state->last_primitive_reset_index) {
2198                         radeon_set_context_reg(cs,
2199                                                R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
2200                                                primitive_reset_index);
2201                         state->last_primitive_reset_index = primitive_reset_index;
2202                 }
2203         }
2204
2205         if (draw_info->strmout_buffer) {
2206                 uint64_t va = radv_buffer_get_va(draw_info->strmout_buffer->bo);
2207
2208                 va += draw_info->strmout_buffer->offset +
2209                       draw_info->strmout_buffer_offset;
2210
2211                 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
2212                                        draw_info->stride);
2213
2214                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
2215                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
2216                                 COPY_DATA_DST_SEL(COPY_DATA_REG) |
2217                                 COPY_DATA_WR_CONFIRM);
2218                 radeon_emit(cs, va);
2219                 radeon_emit(cs, va >> 32);
2220                 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
2221                 radeon_emit(cs, 0); /* unused */
2222
2223                 radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);
2224         }
2225 }
2226
2227 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
2228                              VkPipelineStageFlags src_stage_mask)
2229 {
2230         if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
2231                               VK_PIPELINE_STAGE_TRANSFER_BIT |
2232                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2233                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2234                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
2235         }
2236
2237         if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
2238                               VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
2239                               VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
2240                               VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
2241                               VK_PIPELINE_STAGE_TRANSFER_BIT |
2242                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
2243                               VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
2244                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
2245                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
2246         } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
2247                                      VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
2248                                      VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
2249                                      VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
2250                                      VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
2251                                      VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
2252                                      VK_PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT)) {
2253                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
2254         }
2255 }
2256
2257 static enum radv_cmd_flush_bits
2258 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
2259                       VkAccessFlags src_flags,
2260                       struct radv_image *image)
2261 {
2262         bool flush_CB_meta = true, flush_DB_meta = true;
2263         enum radv_cmd_flush_bits flush_bits = 0;
2264         uint32_t b;
2265
2266         if (image) {
2267                 if (!radv_image_has_CB_metadata(image))
2268                         flush_CB_meta = false;
2269                 if (!radv_image_has_htile(image))
2270                         flush_DB_meta = false;
2271         }
2272
2273         for_each_bit(b, src_flags) {
2274                 switch ((VkAccessFlagBits)(1 << b)) {
2275                 case VK_ACCESS_SHADER_WRITE_BIT:
2276                 case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
2277                 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2278                         flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2279                         break;
2280                 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
2281                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2282                         if (flush_CB_meta)
2283                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2284                         break;
2285                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
2286                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2287                         if (flush_DB_meta)
2288                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2289                         break;
2290                 case VK_ACCESS_TRANSFER_WRITE_BIT:
2291                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
2292                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2293                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
2294
2295                         if (flush_CB_meta)
2296                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2297                         if (flush_DB_meta)
2298                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2299                         break;
2300                 default:
2301                         break;
2302                 }
2303         }
2304         return flush_bits;
2305 }
2306
2307 static enum radv_cmd_flush_bits
2308 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
2309                       VkAccessFlags dst_flags,
2310                       struct radv_image *image)
2311 {
2312         bool flush_CB_meta = true, flush_DB_meta = true;
2313         enum radv_cmd_flush_bits flush_bits = 0;
2314         bool flush_CB = true, flush_DB = true;
2315         bool image_is_coherent = false;
2316         uint32_t b;
2317
2318         if (image) {
2319                 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT)) {
2320                         flush_CB = false;
2321                         flush_DB = false;
2322                 }
2323
2324                 if (!radv_image_has_CB_metadata(image))
2325                         flush_CB_meta = false;
2326                 if (!radv_image_has_htile(image))
2327                         flush_DB_meta = false;
2328
2329                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
2330                         if (image->info.samples == 1 &&
2331                             (image->usage & (VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
2332                                              VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
2333                             !vk_format_is_stencil(image->vk_format)) {
2334                                 /* Single-sample color and single-sample depth
2335                                  * (not stencil) are coherent with shaders on
2336                                  * GFX9.
2337                                  */
2338                                 image_is_coherent = true;
2339                         }
2340                 }
2341         }
2342
2343         for_each_bit(b, dst_flags) {
2344                 switch ((VkAccessFlagBits)(1 << b)) {
2345                 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
2346                 case VK_ACCESS_INDEX_READ_BIT:
2347                 case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
2348                         break;
2349                 case VK_ACCESS_UNIFORM_READ_BIT:
2350                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
2351                         break;
2352                 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
2353                 case VK_ACCESS_TRANSFER_READ_BIT:
2354                 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
2355                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
2356                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
2357                         break;
2358                 case VK_ACCESS_SHADER_READ_BIT:
2359                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
2360
2361                         if (!image_is_coherent)
2362                                 flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
2363                         break;
2364                 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
2365                         if (flush_CB)
2366                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
2367                         if (flush_CB_meta)
2368                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
2369                         break;
2370                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2371                         if (flush_DB)
2372                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
2373                         if (flush_DB_meta)
2374                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2375                         break;
2376                 default:
2377                         break;
2378                 }
2379         }
2380         return flush_bits;
2381 }
2382
2383 void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
2384                           const struct radv_subpass_barrier *barrier)
2385 {
2386         cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask,
2387                                                               NULL);
2388         radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2389         cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2390                                                               NULL);
2391 }
2392
2393 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2394                                                  struct radv_subpass_attachment att)
2395 {
2396         unsigned idx = att.attachment;
2397         struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2398         VkImageSubresourceRange range;
2399         range.aspectMask = 0;
2400         range.baseMipLevel = view->base_mip;
2401         range.levelCount = 1;
2402         range.baseArrayLayer = view->base_layer;
2403         range.layerCount = cmd_buffer->state.framebuffer->layers;
2404
2405         if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
2406                 /* If the current subpass uses multiview, the driver might have
2407                  * performed a fast color/depth clear to the whole image
2408                  * (including all layers). To make sure the driver will
2409                  * decompress the image correctly (if needed), we have to
2410                  * account for the "real" number of layers. If the view mask is
2411                  * sparse, this will decompress more layers than needed.
2412                  */
2413                 range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);
2414         }
2415
2416         radv_handle_image_transition(cmd_buffer,
2417                                      view->image,
2418                                      cmd_buffer->state.attachments[idx].current_layout,
2419                                      att.layout, 0, 0, &range);
2420
2421         cmd_buffer->state.attachments[idx].current_layout = att.layout;
2422
2423
2424 }
2425
2426 void
2427 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2428                             const struct radv_subpass *subpass)
2429 {
2430         cmd_buffer->state.subpass = subpass;
2431
2432         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2433 }
2434
2435 static VkResult
2436 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2437                                  struct radv_render_pass *pass,
2438                                  const VkRenderPassBeginInfo *info)
2439 {
2440         struct radv_cmd_state *state = &cmd_buffer->state;
2441
2442         if (pass->attachment_count == 0) {
2443                 state->attachments = NULL;
2444                 return VK_SUCCESS;
2445         }
2446
2447         state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2448                                         pass->attachment_count *
2449                                         sizeof(state->attachments[0]),
2450                                         8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2451         if (state->attachments == NULL) {
2452                 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2453                 return cmd_buffer->record_result;
2454         }
2455
2456         for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2457                 struct radv_render_pass_attachment *att = &pass->attachments[i];
2458                 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2459                 VkImageAspectFlags clear_aspects = 0;
2460
2461                 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2462                         /* color attachment */
2463                         if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2464                                 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2465                         }
2466                 } else {
2467                         /* depthstencil attachment */
2468                         if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2469                             att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2470                                 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2471                                 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2472                                     att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2473                                         clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2474                         }
2475                         if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2476                             att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2477                                 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2478                         }
2479                 }
2480
2481                 state->attachments[i].pending_clear_aspects = clear_aspects;
2482                 state->attachments[i].cleared_views = 0;
2483                 if (clear_aspects && info) {
2484                         assert(info->clearValueCount > i);
2485                         state->attachments[i].clear_value = info->pClearValues[i];
2486                 }
2487
2488                 state->attachments[i].current_layout = att->initial_layout;
2489         }
2490
2491         return VK_SUCCESS;
2492 }
2493
2494 VkResult radv_AllocateCommandBuffers(
2495         VkDevice _device,
2496         const VkCommandBufferAllocateInfo *pAllocateInfo,
2497         VkCommandBuffer *pCommandBuffers)
2498 {
2499         RADV_FROM_HANDLE(radv_device, device, _device);
2500         RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2501
2502         VkResult result = VK_SUCCESS;
2503         uint32_t i;
2504
2505         for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2506
2507                 if (!list_empty(&pool->free_cmd_buffers)) {
2508                         struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2509
2510                         list_del(&cmd_buffer->pool_link);
2511                         list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2512
2513                         result = radv_reset_cmd_buffer(cmd_buffer);
2514                         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2515                         cmd_buffer->level = pAllocateInfo->level;
2516
2517                         pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2518                 } else {
2519                         result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2520                                                         &pCommandBuffers[i]);
2521                 }
2522                 if (result != VK_SUCCESS)
2523                         break;
2524         }
2525
2526         if (result != VK_SUCCESS) {
2527                 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2528                                         i, pCommandBuffers);
2529
2530                 /* From the Vulkan 1.0.66 spec:
2531                  *
2532                  * "vkAllocateCommandBuffers can be used to create multiple
2533                  *  command buffers. If the creation of any of those command
2534                  *  buffers fails, the implementation must destroy all
2535                  *  successfully created command buffer objects from this
2536                  *  command, set all entries of the pCommandBuffers array to
2537                  *  NULL and return the error."
2538                  */
2539                 memset(pCommandBuffers, 0,
2540                        sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2541         }
2542
2543         return result;
2544 }
2545
2546 void radv_FreeCommandBuffers(
2547         VkDevice device,
2548         VkCommandPool commandPool,
2549         uint32_t commandBufferCount,
2550         const VkCommandBuffer *pCommandBuffers)
2551 {
2552         for (uint32_t i = 0; i < commandBufferCount; i++) {
2553                 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2554
2555                 if (cmd_buffer) {
2556                         if (cmd_buffer->pool) {
2557                                 list_del(&cmd_buffer->pool_link);
2558                                 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2559                         } else
2560                                 radv_cmd_buffer_destroy(cmd_buffer);
2561
2562                 }
2563         }
2564 }
2565
2566 VkResult radv_ResetCommandBuffer(
2567         VkCommandBuffer commandBuffer,
2568         VkCommandBufferResetFlags flags)
2569 {
2570         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2571         return radv_reset_cmd_buffer(cmd_buffer);
2572 }
2573
2574 VkResult radv_BeginCommandBuffer(
2575         VkCommandBuffer commandBuffer,
2576         const VkCommandBufferBeginInfo *pBeginInfo)
2577 {
2578         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2579         VkResult result = VK_SUCCESS;
2580
2581         if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2582                 /* If the command buffer has already been resetted with
2583                  * vkResetCommandBuffer, no need to do it again.
2584                  */
2585                 result = radv_reset_cmd_buffer(cmd_buffer);
2586                 if (result != VK_SUCCESS)
2587                         return result;
2588         }
2589
2590         memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2591         cmd_buffer->state.last_primitive_reset_en = -1;
2592         cmd_buffer->state.last_index_type = -1;
2593         cmd_buffer->state.last_num_instances = -1;
2594         cmd_buffer->state.last_vertex_offset = -1;
2595         cmd_buffer->state.last_first_instance = -1;
2596         cmd_buffer->state.predication_type = -1;
2597         cmd_buffer->usage_flags = pBeginInfo->flags;
2598
2599         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&
2600             (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT)) {
2601                 assert(pBeginInfo->pInheritanceInfo);
2602                 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2603                 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2604
2605                 struct radv_subpass *subpass =
2606                         &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2607
2608                 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2609                 if (result != VK_SUCCESS)
2610                         return result;
2611
2612                 radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
2613         }
2614
2615         if (unlikely(cmd_buffer->device->trace_bo)) {
2616                 struct radv_device *device = cmd_buffer->device;
2617
2618                 radv_cs_add_buffer(device->ws, cmd_buffer->cs,
2619                                    device->trace_bo);
2620
2621                 radv_cmd_buffer_trace_emit(cmd_buffer);
2622         }
2623
2624         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2625
2626         return result;
2627 }
2628
2629 void radv_CmdBindVertexBuffers(
2630         VkCommandBuffer                             commandBuffer,
2631         uint32_t                                    firstBinding,
2632         uint32_t                                    bindingCount,
2633         const VkBuffer*                             pBuffers,
2634         const VkDeviceSize*                         pOffsets)
2635 {
2636         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2637         struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2638         bool changed = false;
2639
2640         /* We have to defer setting up vertex buffer since we need the buffer
2641          * stride from the pipeline. */
2642
2643         assert(firstBinding + bindingCount <= MAX_VBS);
2644         for (uint32_t i = 0; i < bindingCount; i++) {
2645                 uint32_t idx = firstBinding + i;
2646
2647                 if (!changed &&
2648                     (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2649                      vb[idx].offset != pOffsets[i])) {
2650                         changed = true;
2651                 }
2652
2653                 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2654                 vb[idx].offset = pOffsets[i];
2655
2656                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2657                                    vb[idx].buffer->bo);
2658         }
2659
2660         if (!changed) {
2661                 /* No state changes. */
2662                 return;
2663         }
2664
2665         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2666 }
2667
2668 void radv_CmdBindIndexBuffer(
2669         VkCommandBuffer                             commandBuffer,
2670         VkBuffer buffer,
2671         VkDeviceSize offset,
2672         VkIndexType indexType)
2673 {
2674         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2675         RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2676
2677         if (cmd_buffer->state.index_buffer == index_buffer &&
2678             cmd_buffer->state.index_offset == offset &&
2679             cmd_buffer->state.index_type == indexType) {
2680                 /* No state changes. */
2681                 return;
2682         }
2683
2684         cmd_buffer->state.index_buffer = index_buffer;
2685         cmd_buffer->state.index_offset = offset;
2686         cmd_buffer->state.index_type = indexType; /* vk matches hw */
2687         cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2688         cmd_buffer->state.index_va += index_buffer->offset + offset;
2689
2690         int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2691         cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2692         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2693         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);
2694 }
2695
2696
2697 static void
2698 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2699                          VkPipelineBindPoint bind_point,
2700                          struct radv_descriptor_set *set, unsigned idx)
2701 {
2702         struct radeon_winsys *ws = cmd_buffer->device->ws;
2703
2704         radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2705
2706         assert(set);
2707         assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2708
2709         if (!cmd_buffer->device->use_global_bo_list) {
2710                 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2711                         if (set->descriptors[j])
2712                                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);
2713         }
2714
2715         if(set->bo)
2716                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo);
2717 }
2718
2719 void radv_CmdBindDescriptorSets(
2720         VkCommandBuffer                             commandBuffer,
2721         VkPipelineBindPoint                         pipelineBindPoint,
2722         VkPipelineLayout                            _layout,
2723         uint32_t                                    firstSet,
2724         uint32_t                                    descriptorSetCount,
2725         const VkDescriptorSet*                      pDescriptorSets,
2726         uint32_t                                    dynamicOffsetCount,
2727         const uint32_t*                             pDynamicOffsets)
2728 {
2729         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2730         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2731         unsigned dyn_idx = 0;
2732
2733         const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2734         struct radv_descriptor_state *descriptors_state =
2735                 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2736
2737         for (unsigned i = 0; i < descriptorSetCount; ++i) {
2738                 unsigned idx = i + firstSet;
2739                 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2740                 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2741
2742                 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2743                         unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2744                         uint32_t *dst = descriptors_state->dynamic_buffers + idx * 4;
2745                         assert(dyn_idx < dynamicOffsetCount);
2746
2747                         struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2748                         uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2749                         dst[0] = va;
2750                         dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2751                         dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2752                         dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2753                                  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2754                                  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2755                                  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2756                                  S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2757                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2758                         cmd_buffer->push_constant_stages |=
2759                                              set->layout->dynamic_shader_stages;
2760                 }
2761         }
2762 }
2763
2764 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2765                                           struct radv_descriptor_set *set,
2766                                           struct radv_descriptor_set_layout *layout,
2767                                           VkPipelineBindPoint bind_point)
2768 {
2769         struct radv_descriptor_state *descriptors_state =
2770                 radv_get_descriptors_state(cmd_buffer, bind_point);
2771         set->size = layout->size;
2772         set->layout = layout;
2773
2774         if (descriptors_state->push_set.capacity < set->size) {
2775                 size_t new_size = MAX2(set->size, 1024);
2776                 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2777                 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2778
2779                 free(set->mapped_ptr);
2780                 set->mapped_ptr = malloc(new_size);
2781
2782                 if (!set->mapped_ptr) {
2783                         descriptors_state->push_set.capacity = 0;
2784                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2785                         return false;
2786                 }
2787
2788                 descriptors_state->push_set.capacity = new_size;
2789         }
2790
2791         return true;
2792 }
2793
2794 void radv_meta_push_descriptor_set(
2795         struct radv_cmd_buffer*              cmd_buffer,
2796         VkPipelineBindPoint                  pipelineBindPoint,
2797         VkPipelineLayout                     _layout,
2798         uint32_t                             set,
2799         uint32_t                             descriptorWriteCount,
2800         const VkWriteDescriptorSet*          pDescriptorWrites)
2801 {
2802         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2803         struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2804         unsigned bo_offset;
2805
2806         assert(set == 0);
2807         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2808
2809         push_set->size = layout->set[set].layout->size;
2810         push_set->layout = layout->set[set].layout;
2811
2812         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2813                                           &bo_offset,
2814                                           (void**) &push_set->mapped_ptr))
2815                 return;
2816
2817         push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2818         push_set->va += bo_offset;
2819
2820         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2821                                     radv_descriptor_set_to_handle(push_set),
2822                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2823
2824         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2825 }
2826
2827 void radv_CmdPushDescriptorSetKHR(
2828         VkCommandBuffer                             commandBuffer,
2829         VkPipelineBindPoint                         pipelineBindPoint,
2830         VkPipelineLayout                            _layout,
2831         uint32_t                                    set,
2832         uint32_t                                    descriptorWriteCount,
2833         const VkWriteDescriptorSet*                 pDescriptorWrites)
2834 {
2835         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2836         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2837         struct radv_descriptor_state *descriptors_state =
2838                 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2839         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2840
2841         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2842
2843         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2844                                            layout->set[set].layout,
2845                                            pipelineBindPoint))
2846                 return;
2847
2848         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2849                                     radv_descriptor_set_to_handle(push_set),
2850                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2851
2852         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2853         descriptors_state->push_dirty = true;
2854 }
2855
2856 void radv_CmdPushDescriptorSetWithTemplateKHR(
2857         VkCommandBuffer                             commandBuffer,
2858         VkDescriptorUpdateTemplate                  descriptorUpdateTemplate,
2859         VkPipelineLayout                            _layout,
2860         uint32_t                                    set,
2861         const void*                                 pData)
2862 {
2863         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2864         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2865         RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2866         struct radv_descriptor_state *descriptors_state =
2867                 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2868         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2869
2870         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2871
2872         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2873                                            layout->set[set].layout,
2874                                            templ->bind_point))
2875                 return;
2876
2877         radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2878                                                  descriptorUpdateTemplate, pData);
2879
2880         radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2881         descriptors_state->push_dirty = true;
2882 }
2883
2884 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2885                            VkPipelineLayout layout,
2886                            VkShaderStageFlags stageFlags,
2887                            uint32_t offset,
2888                            uint32_t size,
2889                            const void* pValues)
2890 {
2891         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2892         memcpy(cmd_buffer->push_constants + offset, pValues, size);
2893         cmd_buffer->push_constant_stages |= stageFlags;
2894 }
2895
2896 VkResult radv_EndCommandBuffer(
2897         VkCommandBuffer                             commandBuffer)
2898 {
2899         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2900
2901         if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2902                 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2903                         cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2904                 si_emit_cache_flush(cmd_buffer);
2905         }
2906
2907         /* Make sure CP DMA is idle at the end of IBs because the kernel
2908          * doesn't wait for it.
2909          */
2910         si_cp_dma_wait_for_idle(cmd_buffer);
2911
2912         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2913
2914         if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2915                 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2916
2917         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2918
2919         return cmd_buffer->record_result;
2920 }
2921
2922 static void
2923 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2924 {
2925         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2926
2927         if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2928                 return;
2929
2930         assert(!pipeline->ctx_cs.cdw);
2931
2932         cmd_buffer->state.emitted_compute_pipeline = pipeline;
2933
2934         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2935         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2936
2937         cmd_buffer->compute_scratch_size_needed =
2938                                   MAX2(cmd_buffer->compute_scratch_size_needed,
2939                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2940
2941         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2942                            pipeline->shaders[MESA_SHADER_COMPUTE]->bo);
2943
2944         if (unlikely(cmd_buffer->device->trace_bo))
2945                 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2946 }
2947
2948 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2949                                             VkPipelineBindPoint bind_point)
2950 {
2951         struct radv_descriptor_state *descriptors_state =
2952                 radv_get_descriptors_state(cmd_buffer, bind_point);
2953
2954         descriptors_state->dirty |= descriptors_state->valid;
2955 }
2956
2957 void radv_CmdBindPipeline(
2958         VkCommandBuffer                             commandBuffer,
2959         VkPipelineBindPoint                         pipelineBindPoint,
2960         VkPipeline                                  _pipeline)
2961 {
2962         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2963         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2964
2965         switch (pipelineBindPoint) {
2966         case VK_PIPELINE_BIND_POINT_COMPUTE:
2967                 if (cmd_buffer->state.compute_pipeline == pipeline)
2968                         return;
2969                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2970
2971                 cmd_buffer->state.compute_pipeline = pipeline;
2972                 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2973                 break;
2974         case VK_PIPELINE_BIND_POINT_GRAPHICS:
2975                 if (cmd_buffer->state.pipeline == pipeline)
2976                         return;
2977                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2978
2979                 cmd_buffer->state.pipeline = pipeline;
2980                 if (!pipeline)
2981                         break;
2982
2983                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2984                 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2985
2986                 /* the new vertex shader might not have the same user regs */
2987                 cmd_buffer->state.last_first_instance = -1;
2988                 cmd_buffer->state.last_vertex_offset = -1;
2989
2990                 /* Prefetch all pipeline shaders at first draw time. */
2991                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2992
2993                 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2994                 radv_bind_streamout_state(cmd_buffer, pipeline);
2995
2996                 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2997                         cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2998                 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2999                         cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
3000
3001                 if (radv_pipeline_has_tess(pipeline))
3002                         cmd_buffer->tess_rings_needed = true;
3003                 break;
3004         default:
3005                 assert(!"invalid bind point");
3006                 break;
3007         }
3008 }
3009
3010 void radv_CmdSetViewport(
3011         VkCommandBuffer                             commandBuffer,
3012         uint32_t                                    firstViewport,
3013         uint32_t                                    viewportCount,
3014         const VkViewport*                           pViewports)
3015 {
3016         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3017         struct radv_cmd_state *state = &cmd_buffer->state;
3018         MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
3019
3020         assert(firstViewport < MAX_VIEWPORTS);
3021         assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
3022
3023         if (!memcmp(state->dynamic.viewport.viewports + firstViewport,
3024                     pViewports, viewportCount * sizeof(*pViewports))) {
3025                 return;
3026         }
3027
3028         memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
3029                viewportCount * sizeof(*pViewports));
3030
3031         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
3032 }
3033
3034 void radv_CmdSetScissor(
3035         VkCommandBuffer                             commandBuffer,
3036         uint32_t                                    firstScissor,
3037         uint32_t                                    scissorCount,
3038         const VkRect2D*                             pScissors)
3039 {
3040         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3041         struct radv_cmd_state *state = &cmd_buffer->state;
3042         MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
3043
3044         assert(firstScissor < MAX_SCISSORS);
3045         assert(total_count >= 1 && total_count <= MAX_SCISSORS);
3046
3047         if (!memcmp(state->dynamic.scissor.scissors + firstScissor, pScissors,
3048                     scissorCount * sizeof(*pScissors))) {
3049                 return;
3050         }
3051
3052         memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
3053                scissorCount * sizeof(*pScissors));
3054
3055         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
3056 }
3057
3058 void radv_CmdSetLineWidth(
3059         VkCommandBuffer                             commandBuffer,
3060         float                                       lineWidth)
3061 {
3062         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3063
3064         if (cmd_buffer->state.dynamic.line_width == lineWidth)
3065                 return;
3066
3067         cmd_buffer->state.dynamic.line_width = lineWidth;
3068         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
3069 }
3070
3071 void radv_CmdSetDepthBias(
3072         VkCommandBuffer                             commandBuffer,
3073         float                                       depthBiasConstantFactor,
3074         float                                       depthBiasClamp,
3075         float                                       depthBiasSlopeFactor)
3076 {
3077         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3078         struct radv_cmd_state *state = &cmd_buffer->state;
3079
3080         if (state->dynamic.depth_bias.bias == depthBiasConstantFactor &&
3081             state->dynamic.depth_bias.clamp == depthBiasClamp &&
3082             state->dynamic.depth_bias.slope == depthBiasSlopeFactor) {
3083                 return;
3084         }
3085
3086         state->dynamic.depth_bias.bias = depthBiasConstantFactor;
3087         state->dynamic.depth_bias.clamp = depthBiasClamp;
3088         state->dynamic.depth_bias.slope = depthBiasSlopeFactor;
3089
3090         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
3091 }
3092
3093 void radv_CmdSetBlendConstants(
3094         VkCommandBuffer                             commandBuffer,
3095         const float                                 blendConstants[4])
3096 {
3097         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3098         struct radv_cmd_state *state = &cmd_buffer->state;
3099
3100         if (!memcmp(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4))
3101                 return;
3102
3103         memcpy(state->dynamic.blend_constants, blendConstants, sizeof(float) * 4);
3104
3105         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
3106 }
3107
3108 void radv_CmdSetDepthBounds(
3109         VkCommandBuffer                             commandBuffer,
3110         float                                       minDepthBounds,
3111         float                                       maxDepthBounds)
3112 {
3113         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3114         struct radv_cmd_state *state = &cmd_buffer->state;
3115
3116         if (state->dynamic.depth_bounds.min == minDepthBounds &&
3117             state->dynamic.depth_bounds.max == maxDepthBounds) {
3118                 return;
3119         }
3120
3121         state->dynamic.depth_bounds.min = minDepthBounds;
3122         state->dynamic.depth_bounds.max = maxDepthBounds;
3123
3124         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
3125 }
3126
3127 void radv_CmdSetStencilCompareMask(
3128         VkCommandBuffer                             commandBuffer,
3129         VkStencilFaceFlags                          faceMask,
3130         uint32_t                                    compareMask)
3131 {
3132         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3133         struct radv_cmd_state *state = &cmd_buffer->state;
3134         bool front_same = state->dynamic.stencil_compare_mask.front == compareMask;
3135         bool back_same = state->dynamic.stencil_compare_mask.back == compareMask;
3136
3137         if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3138             (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3139                 return;
3140         }
3141
3142         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3143                 state->dynamic.stencil_compare_mask.front = compareMask;
3144         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3145                 state->dynamic.stencil_compare_mask.back = compareMask;
3146
3147         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
3148 }
3149
3150 void radv_CmdSetStencilWriteMask(
3151         VkCommandBuffer                             commandBuffer,
3152         VkStencilFaceFlags                          faceMask,
3153         uint32_t                                    writeMask)
3154 {
3155         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3156         struct radv_cmd_state *state = &cmd_buffer->state;
3157         bool front_same = state->dynamic.stencil_write_mask.front == writeMask;
3158         bool back_same = state->dynamic.stencil_write_mask.back == writeMask;
3159
3160         if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3161             (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3162                 return;
3163         }
3164
3165         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3166                 state->dynamic.stencil_write_mask.front = writeMask;
3167         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3168                 state->dynamic.stencil_write_mask.back = writeMask;
3169
3170         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
3171 }
3172
3173 void radv_CmdSetStencilReference(
3174         VkCommandBuffer                             commandBuffer,
3175         VkStencilFaceFlags                          faceMask,
3176         uint32_t                                    reference)
3177 {
3178         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3179         struct radv_cmd_state *state = &cmd_buffer->state;
3180         bool front_same = state->dynamic.stencil_reference.front == reference;
3181         bool back_same = state->dynamic.stencil_reference.back == reference;
3182
3183         if ((!(faceMask & VK_STENCIL_FACE_FRONT_BIT) || front_same) &&
3184             (!(faceMask & VK_STENCIL_FACE_BACK_BIT) || back_same)) {
3185                 return;
3186         }
3187
3188         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
3189                 cmd_buffer->state.dynamic.stencil_reference.front = reference;
3190         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
3191                 cmd_buffer->state.dynamic.stencil_reference.back = reference;
3192
3193         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
3194 }
3195
3196 void radv_CmdSetDiscardRectangleEXT(
3197         VkCommandBuffer                             commandBuffer,
3198         uint32_t                                    firstDiscardRectangle,
3199         uint32_t                                    discardRectangleCount,
3200         const VkRect2D*                             pDiscardRectangles)
3201 {
3202         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3203         struct radv_cmd_state *state = &cmd_buffer->state;
3204         MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
3205
3206         assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
3207         assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
3208
3209         if (!memcmp(state->dynamic.discard_rectangle.rectangles + firstDiscardRectangle,
3210                     pDiscardRectangles, discardRectangleCount * sizeof(*pDiscardRectangles))) {
3211                 return;
3212         }
3213
3214         typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
3215                      pDiscardRectangles, discardRectangleCount);
3216
3217         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
3218 }
3219
3220 void radv_CmdExecuteCommands(
3221         VkCommandBuffer                             commandBuffer,
3222         uint32_t                                    commandBufferCount,
3223         const VkCommandBuffer*                      pCmdBuffers)
3224 {
3225         RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
3226
3227         assert(commandBufferCount > 0);
3228
3229         /* Emit pending flushes on primary prior to executing secondary */
3230         si_emit_cache_flush(primary);
3231
3232         for (uint32_t i = 0; i < commandBufferCount; i++) {
3233                 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
3234
3235                 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
3236                                                     secondary->scratch_size_needed);
3237                 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
3238                                                             secondary->compute_scratch_size_needed);
3239
3240                 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
3241                         primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
3242                 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
3243                         primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
3244                 if (secondary->tess_rings_needed)
3245                         primary->tess_rings_needed = true;
3246                 if (secondary->sample_positions_needed)
3247                         primary->sample_positions_needed = true;
3248
3249                 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
3250
3251
3252                 /* When the secondary command buffer is compute only we don't
3253                  * need to re-emit the current graphics pipeline.
3254                  */
3255                 if (secondary->state.emitted_pipeline) {
3256                         primary->state.emitted_pipeline =
3257                                 secondary->state.emitted_pipeline;
3258                 }
3259
3260                 /* When the secondary command buffer is graphics only we don't
3261                  * need to re-emit the current compute pipeline.
3262                  */
3263                 if (secondary->state.emitted_compute_pipeline) {
3264                         primary->state.emitted_compute_pipeline =
3265                                 secondary->state.emitted_compute_pipeline;
3266                 }
3267
3268                 /* Only re-emit the draw packets when needed. */
3269                 if (secondary->state.last_primitive_reset_en != -1) {
3270                         primary->state.last_primitive_reset_en =
3271                                 secondary->state.last_primitive_reset_en;
3272                 }
3273
3274                 if (secondary->state.last_primitive_reset_index) {
3275                         primary->state.last_primitive_reset_index =
3276                                 secondary->state.last_primitive_reset_index;
3277                 }
3278
3279                 if (secondary->state.last_ia_multi_vgt_param) {
3280                         primary->state.last_ia_multi_vgt_param =
3281                                 secondary->state.last_ia_multi_vgt_param;
3282                 }
3283
3284                 primary->state.last_first_instance = secondary->state.last_first_instance;
3285                 primary->state.last_num_instances = secondary->state.last_num_instances;
3286                 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
3287
3288                 if (secondary->state.last_index_type != -1) {
3289                         primary->state.last_index_type =
3290                                 secondary->state.last_index_type;
3291                 }
3292         }
3293
3294         /* After executing commands from secondary buffers we have to dirty
3295          * some states.
3296          */
3297         primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
3298                                 RADV_CMD_DIRTY_INDEX_BUFFER |
3299                                 RADV_CMD_DIRTY_DYNAMIC_ALL;
3300         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
3301         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
3302 }
3303
3304 VkResult radv_CreateCommandPool(
3305         VkDevice                                    _device,
3306         const VkCommandPoolCreateInfo*              pCreateInfo,
3307         const VkAllocationCallbacks*                pAllocator,
3308         VkCommandPool*                              pCmdPool)
3309 {
3310         RADV_FROM_HANDLE(radv_device, device, _device);
3311         struct radv_cmd_pool *pool;
3312
3313         pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
3314                            VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3315         if (pool == NULL)
3316                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3317
3318         if (pAllocator)
3319                 pool->alloc = *pAllocator;
3320         else
3321                 pool->alloc = device->alloc;
3322
3323         list_inithead(&pool->cmd_buffers);
3324         list_inithead(&pool->free_cmd_buffers);
3325
3326         pool->queue_family_index = pCreateInfo->queueFamilyIndex;
3327
3328         *pCmdPool = radv_cmd_pool_to_handle(pool);
3329
3330         return VK_SUCCESS;
3331
3332 }
3333
3334 void radv_DestroyCommandPool(
3335         VkDevice                                    _device,
3336         VkCommandPool                               commandPool,
3337         const VkAllocationCallbacks*                pAllocator)
3338 {
3339         RADV_FROM_HANDLE(radv_device, device, _device);
3340         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3341
3342         if (!pool)
3343                 return;
3344
3345         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3346                                  &pool->cmd_buffers, pool_link) {
3347                 radv_cmd_buffer_destroy(cmd_buffer);
3348         }
3349
3350         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3351                                  &pool->free_cmd_buffers, pool_link) {
3352                 radv_cmd_buffer_destroy(cmd_buffer);
3353         }
3354
3355         vk_free2(&device->alloc, pAllocator, pool);
3356 }
3357
3358 VkResult radv_ResetCommandPool(
3359         VkDevice                                    device,
3360         VkCommandPool                               commandPool,
3361         VkCommandPoolResetFlags                     flags)
3362 {
3363         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3364         VkResult result;
3365
3366         list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
3367                             &pool->cmd_buffers, pool_link) {
3368                 result = radv_reset_cmd_buffer(cmd_buffer);
3369                 if (result != VK_SUCCESS)
3370                         return result;
3371         }
3372
3373         return VK_SUCCESS;
3374 }
3375
3376 void radv_TrimCommandPool(
3377     VkDevice                                    device,
3378     VkCommandPool                               commandPool,
3379     VkCommandPoolTrimFlags                      flags)
3380 {
3381         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
3382
3383         if (!pool)
3384                 return;
3385
3386         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
3387                                  &pool->free_cmd_buffers, pool_link) {
3388                 radv_cmd_buffer_destroy(cmd_buffer);
3389         }
3390 }
3391
3392 static void
3393 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer,
3394                               uint32_t subpass_id)
3395 {
3396         struct radv_cmd_state *state = &cmd_buffer->state;
3397         struct radv_subpass *subpass = &state->pass->subpasses[subpass_id];
3398
3399         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3400                                                            cmd_buffer->cs, 2048);
3401
3402         radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
3403
3404         for (uint32_t i = 0; i < subpass->attachment_count; ++i) {
3405                 const uint32_t a = subpass->attachments[i].attachment;
3406                 if (a == VK_ATTACHMENT_UNUSED)
3407                         continue;
3408
3409                 radv_handle_subpass_image_transition(cmd_buffer,
3410                                                      subpass->attachments[i]);
3411         }
3412
3413         radv_cmd_buffer_set_subpass(cmd_buffer, subpass);
3414         radv_cmd_buffer_clear_subpass(cmd_buffer);
3415
3416         assert(cmd_buffer->cs->cdw <= cdw_max);
3417 }
3418
3419 void radv_CmdBeginRenderPass(
3420         VkCommandBuffer                             commandBuffer,
3421         const VkRenderPassBeginInfo*                pRenderPassBegin,
3422         VkSubpassContents                           contents)
3423 {
3424         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3425         RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3426         RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3427         VkResult result;
3428
3429         cmd_buffer->state.framebuffer = framebuffer;
3430         cmd_buffer->state.pass = pass;
3431         cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3432
3433         result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3434         if (result != VK_SUCCESS)
3435                 return;
3436
3437         radv_cmd_buffer_begin_subpass(cmd_buffer, 0);
3438 }
3439
3440 void radv_CmdBeginRenderPass2KHR(
3441     VkCommandBuffer                             commandBuffer,
3442     const VkRenderPassBeginInfo*                pRenderPassBeginInfo,
3443     const VkSubpassBeginInfoKHR*                pSubpassBeginInfo)
3444 {
3445         radv_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
3446                                 pSubpassBeginInfo->contents);
3447 }
3448
3449 static uint32_t
3450 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
3451 {
3452         struct radv_cmd_state *state = &cmd_buffer->state;
3453         uint32_t subpass_id = state->subpass - state->pass->subpasses;
3454
3455         /* The id of this subpass shouldn't exceed the number of subpasses in
3456          * this render pass minus 1.
3457          */
3458         assert(subpass_id < state->pass->subpass_count);
3459         return subpass_id;
3460 }
3461
3462 void radv_CmdNextSubpass(
3463     VkCommandBuffer                             commandBuffer,
3464     VkSubpassContents                           contents)
3465 {
3466         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3467
3468         radv_cmd_buffer_resolve_subpass(cmd_buffer);
3469
3470         uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);
3471         radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);
3472 }
3473
3474 void radv_CmdNextSubpass2KHR(
3475     VkCommandBuffer                             commandBuffer,
3476     const VkSubpassBeginInfoKHR*                pSubpassBeginInfo,
3477     const VkSubpassEndInfoKHR*                  pSubpassEndInfo)
3478 {
3479         radv_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
3480 }
3481
3482 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3483 {
3484         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3485         for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3486                 if (!radv_get_shader(pipeline, stage))
3487                         continue;
3488
3489                 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3490                 if (loc->sgpr_idx == -1)
3491                         continue;
3492                 uint32_t base_reg = pipeline->user_data_0[stage];
3493                 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3494
3495         }
3496         if (pipeline->gs_copy_shader) {
3497                 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3498                 if (loc->sgpr_idx != -1) {
3499                         uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3500                         radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3501                 }
3502         }
3503 }
3504
3505 static void
3506 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3507                          uint32_t vertex_count,
3508                          bool use_opaque)
3509 {
3510         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3511         radeon_emit(cmd_buffer->cs, vertex_count);
3512         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3513                                     S_0287F0_USE_OPAQUE(use_opaque));
3514 }
3515
3516 static void
3517 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3518                                  uint64_t index_va,
3519                                  uint32_t index_count)
3520 {
3521         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));
3522         radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3523         radeon_emit(cmd_buffer->cs, index_va);
3524         radeon_emit(cmd_buffer->cs, index_va >> 32);
3525         radeon_emit(cmd_buffer->cs, index_count);
3526         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3527 }
3528
3529 static void
3530 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3531                                   bool indexed,
3532                                   uint32_t draw_count,
3533                                   uint64_t count_va,
3534                                   uint32_t stride)
3535 {
3536         struct radeon_cmdbuf *cs = cmd_buffer->cs;
3537         unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3538                                       : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3539         bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3540         uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3541         bool predicating = cmd_buffer->state.predicating;
3542         assert(base_reg);
3543
3544         /* just reset draw state for vertex data */
3545         cmd_buffer->state.last_first_instance = -1;
3546         cmd_buffer->state.last_num_instances = -1;
3547         cmd_buffer->state.last_vertex_offset = -1;
3548
3549         if (draw_count == 1 && !count_va && !draw_id_enable) {
3550                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3551                                      PKT3_DRAW_INDIRECT, 3, predicating));
3552                 radeon_emit(cs, 0);
3553                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3554                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3555                 radeon_emit(cs, di_src_sel);
3556         } else {
3557                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3558                                      PKT3_DRAW_INDIRECT_MULTI,
3559                                      8, predicating));
3560                 radeon_emit(cs, 0);
3561                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3562                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3563                 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3564                             S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3565                             S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3566                 radeon_emit(cs, draw_count); /* count */
3567                 radeon_emit(cs, count_va); /* count_addr */
3568                 radeon_emit(cs, count_va >> 32);
3569                 radeon_emit(cs, stride); /* stride */
3570                 radeon_emit(cs, di_src_sel);
3571         }
3572 }
3573
3574 static void
3575 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3576                        const struct radv_draw_info *info)
3577 {
3578         struct radv_cmd_state *state = &cmd_buffer->state;
3579         struct radeon_winsys *ws = cmd_buffer->device->ws;
3580         struct radeon_cmdbuf *cs = cmd_buffer->cs;
3581
3582         if (info->indirect) {
3583                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3584                 uint64_t count_va = 0;
3585
3586                 va += info->indirect->offset + info->indirect_offset;
3587
3588                 radv_cs_add_buffer(ws, cs, info->indirect->bo);
3589
3590                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3591                 radeon_emit(cs, 1);
3592                 radeon_emit(cs, va);
3593                 radeon_emit(cs, va >> 32);
3594
3595                 if (info->count_buffer) {
3596                         count_va = radv_buffer_get_va(info->count_buffer->bo);
3597                         count_va += info->count_buffer->offset +
3598                                     info->count_buffer_offset;
3599
3600                         radv_cs_add_buffer(ws, cs, info->count_buffer->bo);
3601                 }
3602
3603                 if (!state->subpass->view_mask) {
3604                         radv_cs_emit_indirect_draw_packet(cmd_buffer,
3605                                                           info->indexed,
3606                                                           info->count,
3607                                                           count_va,
3608                                                           info->stride);
3609                 } else {
3610                         unsigned i;
3611                         for_each_bit(i, state->subpass->view_mask) {
3612                                 radv_emit_view_index(cmd_buffer, i);
3613
3614                                 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3615                                                                   info->indexed,
3616                                                                   info->count,
3617                                                                   count_va,
3618                                                                   info->stride);
3619                         }
3620                 }
3621         } else {
3622                 assert(state->pipeline->graphics.vtx_base_sgpr);
3623
3624                 if (info->vertex_offset != state->last_vertex_offset ||
3625                     info->first_instance != state->last_first_instance) {
3626                         radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3627                                               state->pipeline->graphics.vtx_emit_num);
3628
3629                         radeon_emit(cs, info->vertex_offset);
3630                         radeon_emit(cs, info->first_instance);
3631                         if (state->pipeline->graphics.vtx_emit_num == 3)
3632                                 radeon_emit(cs, 0);
3633                         state->last_first_instance = info->first_instance;
3634                         state->last_vertex_offset = info->vertex_offset;
3635                 }
3636
3637                 if (state->last_num_instances != info->instance_count) {
3638                         radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3639                         radeon_emit(cs, info->instance_count);
3640                         state->last_num_instances = info->instance_count;
3641                 }
3642
3643                 if (info->indexed) {
3644                         int index_size = state->index_type ? 4 : 2;
3645                         uint64_t index_va;
3646
3647                         index_va = state->index_va;
3648                         index_va += info->first_index * index_size;
3649
3650                         if (!state->subpass->view_mask) {
3651                                 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3652                                                                  index_va,
3653                                                                  info->count);
3654                         } else {
3655                                 unsigned i;
3656                                 for_each_bit(i, state->subpass->view_mask) {
3657                                         radv_emit_view_index(cmd_buffer, i);
3658
3659                                         radv_cs_emit_draw_indexed_packet(cmd_buffer,
3660                                                                          index_va,
3661                                                                          info->count);
3662                                 }
3663                         }
3664                 } else {
3665                         if (!state->subpass->view_mask) {
3666                                 radv_cs_emit_draw_packet(cmd_buffer,
3667                                                          info->count,
3668                                                          !!info->strmout_buffer);
3669                         } else {
3670                                 unsigned i;
3671                                 for_each_bit(i, state->subpass->view_mask) {
3672                                         radv_emit_view_index(cmd_buffer, i);
3673
3674                                         radv_cs_emit_draw_packet(cmd_buffer,
3675                                                                  info->count,
3676                                                                  !!info->strmout_buffer);
3677                                 }
3678                         }
3679                 }
3680         }
3681 }
3682
3683 /*
3684  * Vega and raven have a bug which triggers if there are multiple context
3685  * register contexts active at the same time with different scissor values.
3686  *
3687  * There are two possible workarounds:
3688  * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3689  *    there is only ever 1 active set of scissor values at the same time.
3690  *
3691  * 2) Whenever the hardware switches contexts we have to set the scissor
3692  *    registers again even if it is a noop. That way the new context gets
3693  *    the correct scissor values.
3694  *
3695  * This implements option 2. radv_need_late_scissor_emission needs to
3696  * return true on affected HW if radv_emit_all_graphics_states sets
3697  * any context registers.
3698  */
3699 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3700                                             const struct radv_draw_info *info)
3701 {
3702         struct radv_cmd_state *state = &cmd_buffer->state;
3703
3704         if (!cmd_buffer->device->physical_device->has_scissor_bug)
3705                 return false;
3706
3707         if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)
3708                 return true;
3709
3710         uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3711
3712         /* Index, vertex and streamout buffers don't change context regs, and
3713          * pipeline is already handled.
3714          */
3715         used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER |
3716                          RADV_CMD_DIRTY_VERTEX_BUFFER |
3717                          RADV_CMD_DIRTY_STREAMOUT_BUFFER |
3718                          RADV_CMD_DIRTY_PIPELINE);
3719
3720         if (cmd_buffer->state.dirty & used_states)
3721                 return true;
3722
3723         if (info->indexed && state->pipeline->graphics.prim_restart_enable &&
3724             (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3725                 return true;
3726
3727         return false;
3728 }
3729
3730 static void
3731 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3732                               const struct radv_draw_info *info)
3733 {
3734         bool late_scissor_emission;
3735
3736         if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3737             cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3738                 radv_emit_rbplus_state(cmd_buffer);
3739
3740         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3741                 radv_emit_graphics_pipeline(cmd_buffer);
3742
3743         /* This should be before the cmd_buffer->state.dirty is cleared
3744          * (excluding RADV_CMD_DIRTY_PIPELINE) and after
3745          * cmd_buffer->state.context_roll_without_scissor_emitted is set. */
3746         late_scissor_emission =
3747                 radv_need_late_scissor_emission(cmd_buffer, info);
3748
3749         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3750                 radv_emit_framebuffer_state(cmd_buffer);
3751
3752         if (info->indexed) {
3753                 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3754                         radv_emit_index_buffer(cmd_buffer);
3755         } else {
3756                 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3757                  * so the state must be re-emitted before the next indexed
3758                  * draw.
3759                  */
3760                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3761                         cmd_buffer->state.last_index_type = -1;
3762                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3763                 }
3764         }
3765
3766         radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3767
3768         radv_emit_draw_registers(cmd_buffer, info);
3769
3770         if (late_scissor_emission)
3771                 radv_emit_scissor(cmd_buffer);
3772 }
3773
3774 static void
3775 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3776           const struct radv_draw_info *info)
3777 {
3778         struct radeon_info *rad_info =
3779                 &cmd_buffer->device->physical_device->rad_info;
3780         bool has_prefetch =
3781                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3782         bool pipeline_is_dirty =
3783                 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3784                 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3785
3786         MAYBE_UNUSED unsigned cdw_max =
3787                 radeon_check_space(cmd_buffer->device->ws,
3788                                    cmd_buffer->cs, 4096);
3789
3790         if (likely(!info->indirect)) {
3791                 /* SI-CI treat instance_count==0 as instance_count==1. There is
3792                  * no workaround for indirect draws, but we can at least skip
3793                  * direct draws.
3794                  */
3795                 if (unlikely(!info->instance_count))
3796                         return;
3797
3798                 /* Handle count == 0. */
3799                 if (unlikely(!info->count && !info->strmout_buffer))
3800                         return;
3801         }
3802
3803         /* Use optimal packet order based on whether we need to sync the
3804          * pipeline.
3805          */
3806         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3807                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3808                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3809                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3810                 /* If we have to wait for idle, set all states first, so that
3811                  * all SET packets are processed in parallel with previous draw
3812                  * calls. Then upload descriptors, set shader pointers, and
3813                  * draw, and prefetch at the end. This ensures that the time
3814                  * the CUs are idle is very short. (there are only SET_SH
3815                  * packets between the wait and the draw)
3816                  */
3817                 radv_emit_all_graphics_states(cmd_buffer, info);
3818                 si_emit_cache_flush(cmd_buffer);
3819                 /* <-- CUs are idle here --> */
3820
3821                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3822
3823                 radv_emit_draw_packets(cmd_buffer, info);
3824                 /* <-- CUs are busy here --> */
3825
3826                 /* Start prefetches after the draw has been started. Both will
3827                  * run in parallel, but starting the draw first is more
3828                  * important.
3829                  */
3830                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3831                         radv_emit_prefetch_L2(cmd_buffer,
3832                                               cmd_buffer->state.pipeline, false);
3833                 }
3834         } else {
3835                 /* If we don't wait for idle, start prefetches first, then set
3836                  * states, and draw at the end.
3837                  */
3838                 si_emit_cache_flush(cmd_buffer);
3839
3840                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3841                         /* Only prefetch the vertex shader and VBO descriptors
3842                          * in order to start the draw as soon as possible.
3843                          */
3844                         radv_emit_prefetch_L2(cmd_buffer,
3845                                               cmd_buffer->state.pipeline, true);
3846                 }
3847
3848                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3849
3850                 radv_emit_all_graphics_states(cmd_buffer, info);
3851                 radv_emit_draw_packets(cmd_buffer, info);
3852
3853                 /* Prefetch the remaining shaders after the draw has been
3854                  * started.
3855                  */
3856                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3857                         radv_emit_prefetch_L2(cmd_buffer,
3858                                               cmd_buffer->state.pipeline, false);
3859                 }
3860         }
3861
3862         /* Workaround for a VGT hang when streamout is enabled.
3863          * It must be done after drawing.
3864          */
3865         if (cmd_buffer->state.streamout.streamout_enabled &&
3866             (rad_info->family == CHIP_HAWAII ||
3867              rad_info->family == CHIP_TONGA ||
3868              rad_info->family == CHIP_FIJI)) {
3869                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
3870         }
3871
3872         assert(cmd_buffer->cs->cdw <= cdw_max);
3873         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3874 }
3875
3876 void radv_CmdDraw(
3877         VkCommandBuffer                             commandBuffer,
3878         uint32_t                                    vertexCount,
3879         uint32_t                                    instanceCount,
3880         uint32_t                                    firstVertex,
3881         uint32_t                                    firstInstance)
3882 {
3883         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3884         struct radv_draw_info info = {};
3885
3886         info.count = vertexCount;
3887         info.instance_count = instanceCount;
3888         info.first_instance = firstInstance;
3889         info.vertex_offset = firstVertex;
3890
3891         radv_draw(cmd_buffer, &info);
3892 }
3893
3894 void radv_CmdDrawIndexed(
3895         VkCommandBuffer                             commandBuffer,
3896         uint32_t                                    indexCount,
3897         uint32_t                                    instanceCount,
3898         uint32_t                                    firstIndex,
3899         int32_t                                     vertexOffset,
3900         uint32_t                                    firstInstance)
3901 {
3902         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3903         struct radv_draw_info info = {};
3904
3905         info.indexed = true;
3906         info.count = indexCount;
3907         info.instance_count = instanceCount;
3908         info.first_index = firstIndex;
3909         info.vertex_offset = vertexOffset;
3910         info.first_instance = firstInstance;
3911
3912         radv_draw(cmd_buffer, &info);
3913 }
3914
3915 void radv_CmdDrawIndirect(
3916         VkCommandBuffer                             commandBuffer,
3917         VkBuffer                                    _buffer,
3918         VkDeviceSize                                offset,
3919         uint32_t                                    drawCount,
3920         uint32_t                                    stride)
3921 {
3922         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3923         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3924         struct radv_draw_info info = {};
3925
3926         info.count = drawCount;
3927         info.indirect = buffer;
3928         info.indirect_offset = offset;
3929         info.stride = stride;
3930
3931         radv_draw(cmd_buffer, &info);
3932 }
3933
3934 void radv_CmdDrawIndexedIndirect(
3935         VkCommandBuffer                             commandBuffer,
3936         VkBuffer                                    _buffer,
3937         VkDeviceSize                                offset,
3938         uint32_t                                    drawCount,
3939         uint32_t                                    stride)
3940 {
3941         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3942         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3943         struct radv_draw_info info = {};
3944
3945         info.indexed = true;
3946         info.count = drawCount;
3947         info.indirect = buffer;
3948         info.indirect_offset = offset;
3949         info.stride = stride;
3950
3951         radv_draw(cmd_buffer, &info);
3952 }
3953
3954 void radv_CmdDrawIndirectCountAMD(
3955         VkCommandBuffer                             commandBuffer,
3956         VkBuffer                                    _buffer,
3957         VkDeviceSize                                offset,
3958         VkBuffer                                    _countBuffer,
3959         VkDeviceSize                                countBufferOffset,
3960         uint32_t                                    maxDrawCount,
3961         uint32_t                                    stride)
3962 {
3963         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3964         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3965         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3966         struct radv_draw_info info = {};
3967
3968         info.count = maxDrawCount;
3969         info.indirect = buffer;
3970         info.indirect_offset = offset;
3971         info.count_buffer = count_buffer;
3972         info.count_buffer_offset = countBufferOffset;
3973         info.stride = stride;
3974
3975         radv_draw(cmd_buffer, &info);
3976 }
3977
3978 void radv_CmdDrawIndexedIndirectCountAMD(
3979         VkCommandBuffer                             commandBuffer,
3980         VkBuffer                                    _buffer,
3981         VkDeviceSize                                offset,
3982         VkBuffer                                    _countBuffer,
3983         VkDeviceSize                                countBufferOffset,
3984         uint32_t                                    maxDrawCount,
3985         uint32_t                                    stride)
3986 {
3987         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3988         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3989         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3990         struct radv_draw_info info = {};
3991
3992         info.indexed = true;
3993         info.count = maxDrawCount;
3994         info.indirect = buffer;
3995         info.indirect_offset = offset;
3996         info.count_buffer = count_buffer;
3997         info.count_buffer_offset = countBufferOffset;
3998         info.stride = stride;
3999
4000         radv_draw(cmd_buffer, &info);
4001 }
4002
4003 void radv_CmdDrawIndirectCountKHR(
4004         VkCommandBuffer                             commandBuffer,
4005         VkBuffer                                    _buffer,
4006         VkDeviceSize                                offset,
4007         VkBuffer                                    _countBuffer,
4008         VkDeviceSize                                countBufferOffset,
4009         uint32_t                                    maxDrawCount,
4010         uint32_t                                    stride)
4011 {
4012         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4013         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4014         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4015         struct radv_draw_info info = {};
4016
4017         info.count = maxDrawCount;
4018         info.indirect = buffer;
4019         info.indirect_offset = offset;
4020         info.count_buffer = count_buffer;
4021         info.count_buffer_offset = countBufferOffset;
4022         info.stride = stride;
4023
4024         radv_draw(cmd_buffer, &info);
4025 }
4026
4027 void radv_CmdDrawIndexedIndirectCountKHR(
4028         VkCommandBuffer                             commandBuffer,
4029         VkBuffer                                    _buffer,
4030         VkDeviceSize                                offset,
4031         VkBuffer                                    _countBuffer,
4032         VkDeviceSize                                countBufferOffset,
4033         uint32_t                                    maxDrawCount,
4034         uint32_t                                    stride)
4035 {
4036         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4037         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4038         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
4039         struct radv_draw_info info = {};
4040
4041         info.indexed = true;
4042         info.count = maxDrawCount;
4043         info.indirect = buffer;
4044         info.indirect_offset = offset;
4045         info.count_buffer = count_buffer;
4046         info.count_buffer_offset = countBufferOffset;
4047         info.stride = stride;
4048
4049         radv_draw(cmd_buffer, &info);
4050 }
4051
4052 struct radv_dispatch_info {
4053         /**
4054          * Determine the layout of the grid (in block units) to be used.
4055          */
4056         uint32_t blocks[3];
4057
4058         /**
4059          * A starting offset for the grid. If unaligned is set, the offset
4060          * must still be aligned.
4061          */
4062         uint32_t offsets[3];
4063         /**
4064          * Whether it's an unaligned compute dispatch.
4065          */
4066         bool unaligned;
4067
4068         /**
4069          * Indirect compute parameters resource.
4070          */
4071         struct radv_buffer *indirect;
4072         uint64_t indirect_offset;
4073 };
4074
4075 static void
4076 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
4077                            const struct radv_dispatch_info *info)
4078 {
4079         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4080         struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4081         unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
4082         struct radeon_winsys *ws = cmd_buffer->device->ws;
4083         bool predicating = cmd_buffer->state.predicating;
4084         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4085         struct radv_userdata_info *loc;
4086
4087         loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
4088                                     AC_UD_CS_GRID_SIZE);
4089
4090         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
4091
4092         if (info->indirect) {
4093                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
4094
4095                 va += info->indirect->offset + info->indirect_offset;
4096
4097                 radv_cs_add_buffer(ws, cs, info->indirect->bo);
4098
4099                 if (loc->sgpr_idx != -1) {
4100                         for (unsigned i = 0; i < 3; ++i) {
4101                                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
4102                                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
4103                                                 COPY_DATA_DST_SEL(COPY_DATA_REG));
4104                                 radeon_emit(cs, (va +  4 * i));
4105                                 radeon_emit(cs, (va + 4 * i) >> 32);
4106                                 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
4107                                                  + loc->sgpr_idx * 4) >> 2) + i);
4108                                 radeon_emit(cs, 0);
4109                         }
4110                 }
4111
4112                 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
4113                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, predicating) |
4114                                         PKT3_SHADER_TYPE_S(1));
4115                         radeon_emit(cs, va);
4116                         radeon_emit(cs, va >> 32);
4117                         radeon_emit(cs, dispatch_initiator);
4118                 } else {
4119                         radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
4120                                         PKT3_SHADER_TYPE_S(1));
4121                         radeon_emit(cs, 1);
4122                         radeon_emit(cs, va);
4123                         radeon_emit(cs, va >> 32);
4124
4125                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, predicating) |
4126                                         PKT3_SHADER_TYPE_S(1));
4127                         radeon_emit(cs, 0);
4128                         radeon_emit(cs, dispatch_initiator);
4129                 }
4130         } else {
4131                 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
4132                 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
4133
4134                 if (info->unaligned) {
4135                         unsigned *cs_block_size = compute_shader->info.cs.block_size;
4136                         unsigned remainder[3];
4137
4138                         /* If aligned, these should be an entire block size,
4139                          * not 0.
4140                          */
4141                         remainder[0] = blocks[0] + cs_block_size[0] -
4142                                        align_u32_npot(blocks[0], cs_block_size[0]);
4143                         remainder[1] = blocks[1] + cs_block_size[1] -
4144                                        align_u32_npot(blocks[1], cs_block_size[1]);
4145                         remainder[2] = blocks[2] + cs_block_size[2] -
4146                                        align_u32_npot(blocks[2], cs_block_size[2]);
4147
4148                         blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
4149                         blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
4150                         blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
4151
4152                         for(unsigned i = 0; i < 3; ++i) {
4153                                 assert(offsets[i] % cs_block_size[i] == 0);
4154                                 offsets[i] /= cs_block_size[i];
4155                         }
4156
4157                         radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4158                         radeon_emit(cs,
4159                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
4160                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
4161                         radeon_emit(cs,
4162                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
4163                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
4164                         radeon_emit(cs,
4165                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
4166                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
4167
4168                         dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
4169                 }
4170
4171                 if (loc->sgpr_idx != -1) {
4172                         assert(loc->num_sgprs == 3);
4173
4174                         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4175                                                   loc->sgpr_idx * 4, 3);
4176                         radeon_emit(cs, blocks[0]);
4177                         radeon_emit(cs, blocks[1]);
4178                         radeon_emit(cs, blocks[2]);
4179                 }
4180
4181                 if (offsets[0] || offsets[1] || offsets[2]) {
4182                         radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
4183                         radeon_emit(cs, offsets[0]);
4184                         radeon_emit(cs, offsets[1]);
4185                         radeon_emit(cs, offsets[2]);
4186
4187                         /* The blocks in the packet are not counts but end values. */
4188                         for (unsigned i = 0; i < 3; ++i)
4189                                 blocks[i] += offsets[i];
4190                 } else {
4191                         dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
4192                 }
4193
4194                 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, predicating) |
4195                                 PKT3_SHADER_TYPE_S(1));
4196                 radeon_emit(cs, blocks[0]);
4197                 radeon_emit(cs, blocks[1]);
4198                 radeon_emit(cs, blocks[2]);
4199                 radeon_emit(cs, dispatch_initiator);
4200         }
4201
4202         assert(cmd_buffer->cs->cdw <= cdw_max);
4203 }
4204
4205 static void
4206 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
4207 {
4208         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4209         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
4210 }
4211
4212 static void
4213 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
4214               const struct radv_dispatch_info *info)
4215 {
4216         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
4217         bool has_prefetch =
4218                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
4219         bool pipeline_is_dirty = pipeline &&
4220                                  pipeline != cmd_buffer->state.emitted_compute_pipeline;
4221
4222         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4223                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4224                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
4225                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
4226                 /* If we have to wait for idle, set all states first, so that
4227                  * all SET packets are processed in parallel with previous draw
4228                  * calls. Then upload descriptors, set shader pointers, and
4229                  * dispatch, and prefetch at the end. This ensures that the
4230                  * time the CUs are idle is very short. (there are only SET_SH
4231                  * packets between the wait and the draw)
4232                  */
4233                 radv_emit_compute_pipeline(cmd_buffer);
4234                 si_emit_cache_flush(cmd_buffer);
4235                 /* <-- CUs are idle here --> */
4236
4237                 radv_upload_compute_shader_descriptors(cmd_buffer);
4238
4239                 radv_emit_dispatch_packets(cmd_buffer, info);
4240                 /* <-- CUs are busy here --> */
4241
4242                 /* Start prefetches after the dispatch has been started. Both
4243                  * will run in parallel, but starting the dispatch first is
4244                  * more important.
4245                  */
4246                 if (has_prefetch && pipeline_is_dirty) {
4247                         radv_emit_shader_prefetch(cmd_buffer,
4248                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
4249                 }
4250         } else {
4251                 /* If we don't wait for idle, start prefetches first, then set
4252                  * states, and dispatch at the end.
4253                  */
4254                 si_emit_cache_flush(cmd_buffer);
4255
4256                 if (has_prefetch && pipeline_is_dirty) {
4257                         radv_emit_shader_prefetch(cmd_buffer,
4258                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
4259                 }
4260
4261                 radv_upload_compute_shader_descriptors(cmd_buffer);
4262
4263                 radv_emit_compute_pipeline(cmd_buffer);
4264                 radv_emit_dispatch_packets(cmd_buffer, info);
4265         }
4266
4267         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
4268 }
4269
4270 void radv_CmdDispatchBase(
4271         VkCommandBuffer                             commandBuffer,
4272         uint32_t                                    base_x,
4273         uint32_t                                    base_y,
4274         uint32_t                                    base_z,
4275         uint32_t                                    x,
4276         uint32_t                                    y,
4277         uint32_t                                    z)
4278 {
4279         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4280         struct radv_dispatch_info info = {};
4281
4282         info.blocks[0] = x;
4283         info.blocks[1] = y;
4284         info.blocks[2] = z;
4285
4286         info.offsets[0] = base_x;
4287         info.offsets[1] = base_y;
4288         info.offsets[2] = base_z;
4289         radv_dispatch(cmd_buffer, &info);
4290 }
4291
4292 void radv_CmdDispatch(
4293         VkCommandBuffer                             commandBuffer,
4294         uint32_t                                    x,
4295         uint32_t                                    y,
4296         uint32_t                                    z)
4297 {
4298         radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
4299 }
4300
4301 void radv_CmdDispatchIndirect(
4302         VkCommandBuffer                             commandBuffer,
4303         VkBuffer                                    _buffer,
4304         VkDeviceSize                                offset)
4305 {
4306         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4307         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4308         struct radv_dispatch_info info = {};
4309
4310         info.indirect = buffer;
4311         info.indirect_offset = offset;
4312
4313         radv_dispatch(cmd_buffer, &info);
4314 }
4315
4316 void radv_unaligned_dispatch(
4317         struct radv_cmd_buffer                      *cmd_buffer,
4318         uint32_t                                    x,
4319         uint32_t                                    y,
4320         uint32_t                                    z)
4321 {
4322         struct radv_dispatch_info info = {};
4323
4324         info.blocks[0] = x;
4325         info.blocks[1] = y;
4326         info.blocks[2] = z;
4327         info.unaligned = 1;
4328
4329         radv_dispatch(cmd_buffer, &info);
4330 }
4331
4332 void radv_CmdEndRenderPass(
4333         VkCommandBuffer                             commandBuffer)
4334 {
4335         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4336
4337         radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
4338
4339         radv_cmd_buffer_resolve_subpass(cmd_buffer);
4340
4341         for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
4342                 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
4343                 radv_handle_subpass_image_transition(cmd_buffer,
4344                                       (struct radv_subpass_attachment){i, layout});
4345         }
4346
4347         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
4348
4349         cmd_buffer->state.pass = NULL;
4350         cmd_buffer->state.subpass = NULL;
4351         cmd_buffer->state.attachments = NULL;
4352         cmd_buffer->state.framebuffer = NULL;
4353 }
4354
4355 void radv_CmdEndRenderPass2KHR(
4356     VkCommandBuffer                             commandBuffer,
4357     const VkSubpassEndInfoKHR*                  pSubpassEndInfo)
4358 {
4359         radv_CmdEndRenderPass(commandBuffer);
4360 }
4361
4362 /*
4363  * For HTILE we have the following interesting clear words:
4364  *   0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
4365  *   0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
4366  *   0xfffffff0: Clear depth to 1.0
4367  *   0x00000000: Clear depth to 0.0
4368  */
4369 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
4370                                   struct radv_image *image,
4371                                   const VkImageSubresourceRange *range,
4372                                   uint32_t clear_word)
4373 {
4374         assert(range->baseMipLevel == 0);
4375         assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
4376         unsigned layer_count = radv_get_layerCount(image, range);
4377         uint64_t size = image->surface.htile_slice_size * layer_count;
4378         VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
4379         uint64_t offset = image->offset + image->htile_offset +
4380                           image->surface.htile_slice_size * range->baseArrayLayer;
4381         struct radv_cmd_state *state = &cmd_buffer->state;
4382         VkClearDepthStencilValue value = {};
4383
4384         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4385                              RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4386
4387         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
4388                                               size, clear_word);
4389
4390         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4391
4392         if (vk_format_is_stencil(image->vk_format))
4393                 aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
4394
4395         radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
4396
4397         if (radv_image_is_tc_compat_htile(image)) {
4398                 /* Initialize the TC-compat metada value to 0 because by
4399                  * default DB_Z_INFO.RANGE_PRECISION is set to 1, and we only
4400                  * need have to conditionally update its value when performing
4401                  * a fast depth clear.
4402                  */
4403                 radv_set_tc_compat_zrange_metadata(cmd_buffer, image, 0);
4404         }
4405 }
4406
4407 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
4408                                                struct radv_image *image,
4409                                                VkImageLayout src_layout,
4410                                                VkImageLayout dst_layout,
4411                                                unsigned src_queue_mask,
4412                                                unsigned dst_queue_mask,
4413                                                const VkImageSubresourceRange *range)
4414 {
4415         if (!radv_image_has_htile(image))
4416                 return;
4417
4418         if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
4419                    radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
4420                 /* TODO: merge with the clear if applicable */
4421                 radv_initialize_htile(cmd_buffer, image, range, 0);
4422         } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4423                    radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4424                 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
4425                 radv_initialize_htile(cmd_buffer, image, range, clear_value);
4426         } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
4427                    !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
4428                 VkImageSubresourceRange local_range = *range;
4429                 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
4430                 local_range.baseMipLevel = 0;
4431                 local_range.levelCount = 1;
4432
4433                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4434                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4435
4436                 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
4437
4438                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4439                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4440         }
4441 }
4442
4443 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4444                                   struct radv_image *image, uint32_t value)
4445 {
4446         struct radv_cmd_state *state = &cmd_buffer->state;
4447
4448         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4449                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4450
4451         state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4452
4453         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4454 }
4455
4456 void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
4457                            struct radv_image *image)
4458 {
4459         struct radv_cmd_state *state = &cmd_buffer->state;
4460         static const uint32_t fmask_clear_values[4] = {
4461                 0x00000000,
4462                 0x02020202,
4463                 0xE4E4E4E4,
4464                 0x76543210
4465         };
4466         uint32_t log2_samples = util_logbase2(image->info.samples);
4467         uint32_t value = fmask_clear_values[log2_samples];
4468
4469         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4470                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4471
4472         state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
4473
4474         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4475 }
4476
4477 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4478                          struct radv_image *image, uint32_t value)
4479 {
4480         struct radv_cmd_state *state = &cmd_buffer->state;
4481
4482         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4483                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4484
4485         state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4486
4487         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4488                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4489 }
4490
4491 /**
4492  * Initialize DCC/FMASK/CMASK metadata for a color image.
4493  */
4494 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4495                                            struct radv_image *image,
4496                                            VkImageLayout src_layout,
4497                                            VkImageLayout dst_layout,
4498                                            unsigned src_queue_mask,
4499                                            unsigned dst_queue_mask)
4500 {
4501         if (radv_image_has_cmask(image)) {
4502                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4503
4504                 /*  TODO: clarify this. */
4505                 if (radv_image_has_fmask(image)) {
4506                         value = 0xccccccccu;
4507                 }
4508
4509                 radv_initialise_cmask(cmd_buffer, image, value);
4510         }
4511
4512         if (radv_image_has_fmask(image)) {
4513                 radv_initialize_fmask(cmd_buffer, image);
4514         }
4515
4516         if (radv_image_has_dcc(image)) {
4517                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4518                 bool need_decompress_pass = false;
4519
4520                 if (radv_layout_dcc_compressed(image, dst_layout,
4521                                                dst_queue_mask)) {
4522                         value = 0x20202020u;
4523                         need_decompress_pass = true;
4524                 }
4525
4526                 radv_initialize_dcc(cmd_buffer, image, value);
4527
4528                 radv_update_fce_metadata(cmd_buffer, image,
4529                                          need_decompress_pass);
4530         }
4531
4532         if (radv_image_has_cmask(image) || radv_image_has_dcc(image)) {
4533                 uint32_t color_values[2] = {};
4534                 radv_set_color_clear_metadata(cmd_buffer, image, color_values);
4535         }
4536 }
4537
4538 /**
4539  * Handle color image transitions for DCC/FMASK/CMASK.
4540  */
4541 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4542                                                struct radv_image *image,
4543                                                VkImageLayout src_layout,
4544                                                VkImageLayout dst_layout,
4545                                                unsigned src_queue_mask,
4546                                                unsigned dst_queue_mask,
4547                                                const VkImageSubresourceRange *range)
4548 {
4549         if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4550                 radv_init_color_image_metadata(cmd_buffer, image,
4551                                                src_layout, dst_layout,
4552                                                src_queue_mask, dst_queue_mask);
4553                 return;
4554         }
4555
4556         if (radv_image_has_dcc(image)) {
4557                 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4558                         radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4559                 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4560                            !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4561                         radv_decompress_dcc(cmd_buffer, image, range);
4562                 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4563                            !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4564                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4565                 }
4566         } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4567                 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4568                     !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4569                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4570                 }
4571
4572                 if (radv_image_has_fmask(image)) {
4573                         if (src_layout != VK_IMAGE_LAYOUT_GENERAL &&
4574                             dst_layout == VK_IMAGE_LAYOUT_GENERAL) {
4575                                 radv_expand_fmask_image_inplace(cmd_buffer, image, range);
4576                         }
4577                 }
4578         }
4579 }
4580
4581 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4582                                          struct radv_image *image,
4583                                          VkImageLayout src_layout,
4584                                          VkImageLayout dst_layout,
4585                                          uint32_t src_family,
4586                                          uint32_t dst_family,
4587                                          const VkImageSubresourceRange *range)
4588 {
4589         if (image->exclusive && src_family != dst_family) {
4590                 /* This is an acquire or a release operation and there will be
4591                  * a corresponding release/acquire. Do the transition in the
4592                  * most flexible queue. */
4593
4594                 assert(src_family == cmd_buffer->queue_family_index ||
4595                        dst_family == cmd_buffer->queue_family_index);
4596
4597                 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4598                         return;
4599
4600                 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4601                     (src_family == RADV_QUEUE_GENERAL ||
4602                      dst_family == RADV_QUEUE_GENERAL))
4603                         return;
4604         }
4605
4606         if (src_layout == dst_layout)
4607                 return;
4608
4609         unsigned src_queue_mask =
4610                 radv_image_queue_family_mask(image, src_family,
4611                                              cmd_buffer->queue_family_index);
4612         unsigned dst_queue_mask =
4613                 radv_image_queue_family_mask(image, dst_family,
4614                                              cmd_buffer->queue_family_index);
4615
4616         if (vk_format_is_depth(image->vk_format)) {
4617                 radv_handle_depth_image_transition(cmd_buffer, image,
4618                                                    src_layout, dst_layout,
4619                                                    src_queue_mask, dst_queue_mask,
4620                                                    range);
4621         } else {
4622                 radv_handle_color_image_transition(cmd_buffer, image,
4623                                                    src_layout, dst_layout,
4624                                                    src_queue_mask, dst_queue_mask,
4625                                                    range);
4626         }
4627 }
4628
4629 struct radv_barrier_info {
4630         uint32_t eventCount;
4631         const VkEvent *pEvents;
4632         VkPipelineStageFlags srcStageMask;
4633 };
4634
4635 static void
4636 radv_barrier(struct radv_cmd_buffer *cmd_buffer,
4637              uint32_t memoryBarrierCount,
4638              const VkMemoryBarrier *pMemoryBarriers,
4639              uint32_t bufferMemoryBarrierCount,
4640              const VkBufferMemoryBarrier *pBufferMemoryBarriers,
4641              uint32_t imageMemoryBarrierCount,
4642              const VkImageMemoryBarrier *pImageMemoryBarriers,
4643              const struct radv_barrier_info *info)
4644 {
4645         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4646         enum radv_cmd_flush_bits src_flush_bits = 0;
4647         enum radv_cmd_flush_bits dst_flush_bits = 0;
4648
4649         for (unsigned i = 0; i < info->eventCount; ++i) {
4650                 RADV_FROM_HANDLE(radv_event, event, info->pEvents[i]);
4651                 uint64_t va = radv_buffer_get_va(event->bo);
4652
4653                 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4654
4655                 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4656
4657                 radv_cp_wait_mem(cs, WAIT_REG_MEM_EQUAL, va, 1, 0xffffffff);
4658                 assert(cmd_buffer->cs->cdw <= cdw_max);
4659         }
4660
4661         for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4662                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask,
4663                                                         NULL);
4664                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4665                                                         NULL);
4666         }
4667
4668         for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4669                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask,
4670                                                         NULL);
4671                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4672                                                         NULL);
4673         }
4674
4675         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4676                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4677
4678                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask,
4679                                                         image);
4680                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4681                                                         image);
4682         }
4683
4684         radv_stage_flush(cmd_buffer, info->srcStageMask);
4685         cmd_buffer->state.flush_bits |= src_flush_bits;
4686
4687         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4688                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4689                 radv_handle_image_transition(cmd_buffer, image,
4690                                              pImageMemoryBarriers[i].oldLayout,
4691                                              pImageMemoryBarriers[i].newLayout,
4692                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
4693                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
4694                                              &pImageMemoryBarriers[i].subresourceRange);
4695         }
4696
4697         /* Make sure CP DMA is idle because the driver might have performed a
4698          * DMA operation for copying or filling buffers/images.
4699          */
4700         if (info->srcStageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4701                                   VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4702                 si_cp_dma_wait_for_idle(cmd_buffer);
4703
4704         cmd_buffer->state.flush_bits |= dst_flush_bits;
4705 }
4706
4707 void radv_CmdPipelineBarrier(
4708         VkCommandBuffer                             commandBuffer,
4709         VkPipelineStageFlags                        srcStageMask,
4710         VkPipelineStageFlags                        destStageMask,
4711         VkBool32                                    byRegion,
4712         uint32_t                                    memoryBarrierCount,
4713         const VkMemoryBarrier*                      pMemoryBarriers,
4714         uint32_t                                    bufferMemoryBarrierCount,
4715         const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
4716         uint32_t                                    imageMemoryBarrierCount,
4717         const VkImageMemoryBarrier*                 pImageMemoryBarriers)
4718 {
4719         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4720         struct radv_barrier_info info;
4721
4722         info.eventCount = 0;
4723         info.pEvents = NULL;
4724         info.srcStageMask = srcStageMask;
4725
4726         radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4727                      bufferMemoryBarrierCount, pBufferMemoryBarriers,
4728                      imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4729 }
4730
4731
4732 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4733                         struct radv_event *event,
4734                         VkPipelineStageFlags stageMask,
4735                         unsigned value)
4736 {
4737         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4738         uint64_t va = radv_buffer_get_va(event->bo);
4739
4740         si_emit_cache_flush(cmd_buffer);
4741
4742         radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);
4743
4744         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4745
4746         /* Flags that only require a top-of-pipe event. */
4747         VkPipelineStageFlags top_of_pipe_flags =
4748                 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT;
4749
4750         /* Flags that only require a post-index-fetch event. */
4751         VkPipelineStageFlags post_index_fetch_flags =
4752                 top_of_pipe_flags |
4753                 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
4754                 VK_PIPELINE_STAGE_VERTEX_INPUT_BIT;
4755
4756         /* Make sure CP DMA is idle because the driver might have performed a
4757          * DMA operation for copying or filling buffers/images.
4758          */
4759         if (stageMask & (VK_PIPELINE_STAGE_TRANSFER_BIT |
4760                          VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT))
4761                 si_cp_dma_wait_for_idle(cmd_buffer);
4762
4763         /* TODO: Emit EOS events for syncing PS/CS stages. */
4764
4765         if (!(stageMask & ~top_of_pipe_flags)) {
4766                 /* Just need to sync the PFP engine. */
4767                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4768                 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4769                                 S_370_WR_CONFIRM(1) |
4770                                 S_370_ENGINE_SEL(V_370_PFP));
4771                 radeon_emit(cs, va);
4772                 radeon_emit(cs, va >> 32);
4773                 radeon_emit(cs, value);
4774         } else if (!(stageMask & ~post_index_fetch_flags)) {
4775                 /* Sync ME because PFP reads index and indirect buffers. */
4776                 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
4777                 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) |
4778                                 S_370_WR_CONFIRM(1) |
4779                                 S_370_ENGINE_SEL(V_370_ME));
4780                 radeon_emit(cs, va);
4781                 radeon_emit(cs, va >> 32);
4782                 radeon_emit(cs, value);
4783         } else {
4784                 /* Otherwise, sync all prior GPU work using an EOP event. */
4785                 si_cs_emit_write_event_eop(cs,
4786                                            cmd_buffer->device->physical_device->rad_info.chip_class,
4787                                            radv_cmd_buffer_uses_mec(cmd_buffer),
4788                                            V_028A90_BOTTOM_OF_PIPE_TS, 0,
4789                                            EOP_DATA_SEL_VALUE_32BIT, va, value,
4790                                            cmd_buffer->gfx9_eop_bug_va);
4791         }
4792
4793         assert(cmd_buffer->cs->cdw <= cdw_max);
4794 }
4795
4796 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4797                       VkEvent _event,
4798                       VkPipelineStageFlags stageMask)
4799 {
4800         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4801         RADV_FROM_HANDLE(radv_event, event, _event);
4802
4803         write_event(cmd_buffer, event, stageMask, 1);
4804 }
4805
4806 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4807                         VkEvent _event,
4808                         VkPipelineStageFlags stageMask)
4809 {
4810         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4811         RADV_FROM_HANDLE(radv_event, event, _event);
4812
4813         write_event(cmd_buffer, event, stageMask, 0);
4814 }
4815
4816 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4817                         uint32_t eventCount,
4818                         const VkEvent* pEvents,
4819                         VkPipelineStageFlags srcStageMask,
4820                         VkPipelineStageFlags dstStageMask,
4821                         uint32_t memoryBarrierCount,
4822                         const VkMemoryBarrier* pMemoryBarriers,
4823                         uint32_t bufferMemoryBarrierCount,
4824                         const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4825                         uint32_t imageMemoryBarrierCount,
4826                         const VkImageMemoryBarrier* pImageMemoryBarriers)
4827 {
4828         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4829         struct radv_barrier_info info;
4830
4831         info.eventCount = eventCount;
4832         info.pEvents = pEvents;
4833         info.srcStageMask = 0;
4834
4835         radv_barrier(cmd_buffer, memoryBarrierCount, pMemoryBarriers,
4836                      bufferMemoryBarrierCount, pBufferMemoryBarriers,
4837                      imageMemoryBarrierCount, pImageMemoryBarriers, &info);
4838 }
4839
4840
4841 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4842                            uint32_t deviceMask)
4843 {
4844    /* No-op */
4845 }
4846
4847 /* VK_EXT_conditional_rendering */
4848 void radv_CmdBeginConditionalRenderingEXT(
4849         VkCommandBuffer                             commandBuffer,
4850         const VkConditionalRenderingBeginInfoEXT*   pConditionalRenderingBegin)
4851 {
4852         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4853         RADV_FROM_HANDLE(radv_buffer, buffer, pConditionalRenderingBegin->buffer);
4854         bool draw_visible = true;
4855         uint64_t va;
4856
4857         va = radv_buffer_get_va(buffer->bo) + pConditionalRenderingBegin->offset;
4858
4859         /* By default, if the 32-bit value at offset in buffer memory is zero,
4860          * then the rendering commands are discarded, otherwise they are
4861          * executed as normal. If the inverted flag is set, all commands are
4862          * discarded if the value is non zero.
4863          */
4864         if (pConditionalRenderingBegin->flags &
4865             VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT) {
4866                 draw_visible = false;
4867         }
4868
4869         si_emit_cache_flush(cmd_buffer);
4870
4871         /* Enable predication for this command buffer. */
4872         si_emit_set_predication_state(cmd_buffer, draw_visible, va);
4873         cmd_buffer->state.predicating = true;
4874
4875         /* Store conditional rendering user info. */
4876         cmd_buffer->state.predication_type = draw_visible;
4877         cmd_buffer->state.predication_va = va;
4878 }
4879
4880 void radv_CmdEndConditionalRenderingEXT(
4881         VkCommandBuffer                             commandBuffer)
4882 {
4883         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4884
4885         /* Disable predication for this command buffer. */
4886         si_emit_set_predication_state(cmd_buffer, false, 0);
4887         cmd_buffer->state.predicating = false;
4888
4889         /* Reset conditional rendering user info. */
4890         cmd_buffer->state.predication_type = -1;
4891         cmd_buffer->state.predication_va = 0;
4892 }
4893
4894 /* VK_EXT_transform_feedback */
4895 void radv_CmdBindTransformFeedbackBuffersEXT(
4896     VkCommandBuffer                             commandBuffer,
4897     uint32_t                                    firstBinding,
4898     uint32_t                                    bindingCount,
4899     const VkBuffer*                             pBuffers,
4900     const VkDeviceSize*                         pOffsets,
4901     const VkDeviceSize*                         pSizes)
4902 {
4903         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4904         struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4905         uint8_t enabled_mask = 0;
4906
4907         assert(firstBinding + bindingCount <= MAX_SO_BUFFERS);
4908         for (uint32_t i = 0; i < bindingCount; i++) {
4909                 uint32_t idx = firstBinding + i;
4910
4911                 sb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
4912                 sb[idx].offset = pOffsets[i];
4913                 sb[idx].size = pSizes[i];
4914
4915                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
4916                                    sb[idx].buffer->bo);
4917
4918                 enabled_mask |= 1 << idx;
4919         }
4920
4921         cmd_buffer->state.streamout.enabled_mask = enabled_mask;
4922
4923         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;
4924 }
4925
4926 static void
4927 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)
4928 {
4929         struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4930         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4931
4932         radeon_set_context_reg_seq(cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
4933         radeon_emit(cs,
4934                     S_028B94_STREAMOUT_0_EN(so->streamout_enabled) |
4935                     S_028B94_RAST_STREAM(0) |
4936                     S_028B94_STREAMOUT_1_EN(so->streamout_enabled) |
4937                     S_028B94_STREAMOUT_2_EN(so->streamout_enabled) |
4938                     S_028B94_STREAMOUT_3_EN(so->streamout_enabled));
4939         radeon_emit(cs, so->hw_enabled_mask &
4940                         so->enabled_stream_buffers_mask);
4941
4942         cmd_buffer->state.context_roll_without_scissor_emitted = true;
4943 }
4944
4945 static void
4946 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)
4947 {
4948         struct radv_streamout_state *so = &cmd_buffer->state.streamout;
4949         bool old_streamout_enabled = so->streamout_enabled;
4950         uint32_t old_hw_enabled_mask = so->hw_enabled_mask;
4951
4952         so->streamout_enabled = enable;
4953
4954         so->hw_enabled_mask = so->enabled_mask |
4955                               (so->enabled_mask << 4) |
4956                               (so->enabled_mask << 8) |
4957                               (so->enabled_mask << 12);
4958
4959         if ((old_streamout_enabled != so->streamout_enabled) ||
4960             (old_hw_enabled_mask != so->hw_enabled_mask))
4961                 radv_emit_streamout_enable(cmd_buffer);
4962 }
4963
4964 static void radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)
4965 {
4966         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4967         unsigned reg_strmout_cntl;
4968
4969         /* The register is at different places on different ASICs. */
4970         if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
4971                 reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
4972                 radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
4973         } else {
4974                 reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
4975                 radeon_set_config_reg(cs, reg_strmout_cntl, 0);
4976         }
4977
4978         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4979         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0));
4980
4981         radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
4982         radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
4983         radeon_emit(cs, reg_strmout_cntl >> 2);  /* register */
4984         radeon_emit(cs, 0);
4985         radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
4986         radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
4987         radeon_emit(cs, 4); /* poll interval */
4988 }
4989
4990 void radv_CmdBeginTransformFeedbackEXT(
4991     VkCommandBuffer                             commandBuffer,
4992     uint32_t                                    firstCounterBuffer,
4993     uint32_t                                    counterBufferCount,
4994     const VkBuffer*                             pCounterBuffers,
4995     const VkDeviceSize*                         pCounterBufferOffsets)
4996 {
4997         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4998         struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;
4999         struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5000         struct radeon_cmdbuf *cs = cmd_buffer->cs;
5001         uint32_t i;
5002
5003         radv_flush_vgt_streamout(cmd_buffer);
5004
5005         assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5006         for_each_bit(i, so->enabled_mask) {
5007                 int32_t counter_buffer_idx = i - firstCounterBuffer;
5008                 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5009                         counter_buffer_idx = -1;
5010
5011                 /* SI binds streamout buffers as shader resources.
5012                  * VGT only counts primitives and tells the shader through
5013                  * SGPRs what to do.
5014                  */
5015                 radeon_set_context_reg_seq(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 2);
5016                 radeon_emit(cs, sb[i].size >> 2);       /* BUFFER_SIZE (in DW) */
5017                 radeon_emit(cs, so->stride_in_dw[i]);                   /* VTX_STRIDE (in DW) */
5018
5019                 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5020
5021                 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5022                         /* The array of counter buffers is optional. */
5023                         RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5024                         uint64_t va = radv_buffer_get_va(buffer->bo);
5025
5026                         va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5027
5028                         /* Append */
5029                         radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5030                         radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5031                                         STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5032                                         STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM)); /* control */
5033                         radeon_emit(cs, 0); /* unused */
5034                         radeon_emit(cs, 0); /* unused */
5035                         radeon_emit(cs, va); /* src address lo */
5036                         radeon_emit(cs, va >> 32); /* src address hi */
5037
5038                         radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5039                 } else {
5040                         /* Start from the beginning. */
5041                         radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5042                         radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5043                                         STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5044                                         STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET)); /* control */
5045                         radeon_emit(cs, 0); /* unused */
5046                         radeon_emit(cs, 0); /* unused */
5047                         radeon_emit(cs, 0); /* unused */
5048                         radeon_emit(cs, 0); /* unused */
5049                 }
5050         }
5051
5052         radv_set_streamout_enable(cmd_buffer, true);
5053 }
5054
5055 void radv_CmdEndTransformFeedbackEXT(
5056     VkCommandBuffer                             commandBuffer,
5057     uint32_t                                    firstCounterBuffer,
5058     uint32_t                                    counterBufferCount,
5059     const VkBuffer*                             pCounterBuffers,
5060     const VkDeviceSize*                         pCounterBufferOffsets)
5061 {
5062         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5063         struct radv_streamout_state *so = &cmd_buffer->state.streamout;
5064         struct radeon_cmdbuf *cs = cmd_buffer->cs;
5065         uint32_t i;
5066
5067         radv_flush_vgt_streamout(cmd_buffer);
5068
5069         assert(firstCounterBuffer + counterBufferCount <= MAX_SO_BUFFERS);
5070         for_each_bit(i, so->enabled_mask) {
5071                 int32_t counter_buffer_idx = i - firstCounterBuffer;
5072                 if (counter_buffer_idx >= 0 && counter_buffer_idx >= counterBufferCount)
5073                         counter_buffer_idx = -1;
5074
5075                 if (counter_buffer_idx >= 0 && pCounterBuffers && pCounterBuffers[counter_buffer_idx]) {
5076                         /* The array of counters buffer is optional. */
5077                         RADV_FROM_HANDLE(radv_buffer, buffer, pCounterBuffers[counter_buffer_idx]);
5078                         uint64_t va = radv_buffer_get_va(buffer->bo);
5079
5080                         va += buffer->offset + pCounterBufferOffsets[counter_buffer_idx];
5081
5082                         radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
5083                         radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
5084                                         STRMOUT_DATA_TYPE(1) | /* offset in bytes */
5085                                         STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |
5086                                         STRMOUT_STORE_BUFFER_FILLED_SIZE); /* control */
5087                         radeon_emit(cs, va);            /* dst address lo */
5088                         radeon_emit(cs, va >> 32);      /* dst address hi */
5089                         radeon_emit(cs, 0);             /* unused */
5090                         radeon_emit(cs, 0);             /* unused */
5091
5092                         radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);
5093                 }
5094
5095                 /* Deactivate transform feedback by zeroing the buffer size.
5096                  * The counters (primitives generated, primitives emitted) may
5097                  * be enabled even if there is not buffer bound. This ensures
5098                  * that the primitives-emitted query won't increment.
5099                  */
5100                 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0);
5101
5102                 cmd_buffer->state.context_roll_without_scissor_emitted = true;
5103         }
5104
5105         radv_set_streamout_enable(cmd_buffer, false);
5106 }
5107
5108 void radv_CmdDrawIndirectByteCountEXT(
5109     VkCommandBuffer                             commandBuffer,
5110     uint32_t                                    instanceCount,
5111     uint32_t                                    firstInstance,
5112     VkBuffer                                    _counterBuffer,
5113     VkDeviceSize                                counterBufferOffset,
5114     uint32_t                                    counterOffset,
5115     uint32_t                                    vertexStride)
5116 {
5117         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
5118         RADV_FROM_HANDLE(radv_buffer, counterBuffer, _counterBuffer);
5119         struct radv_draw_info info = {};
5120
5121         info.instance_count = instanceCount;
5122         info.first_instance = firstInstance;
5123         info.strmout_buffer = counterBuffer;
5124         info.strmout_buffer_offset = counterBufferOffset;
5125         info.stride = vertexStride;
5126
5127         radv_draw(cmd_buffer, &info);
5128 }