src/amd/vulkan/radv_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "radv_private.h"
  29 #include "radv_radeon_winsys.h"
  30 #include "radv_shader.h"
  31 #include "radv_cs.h"
  32 #include "sid.h"
  33 #include "gfx9d.h"
  34 #include "vk_format.h"
  35 #include "radv_debug.h"
  36 #include "radv_meta.h"
  37
  38 #include "ac_debug.h"
  39
  40 enum {
  41         RADV_PREFETCH_VBO_DESCRIPTORS   = (1 << 0),
  42         RADV_PREFETCH_VS                = (1 << 1),
  43         RADV_PREFETCH_TCS               = (1 << 2),
  44         RADV_PREFETCH_TES               = (1 << 3),
  45         RADV_PREFETCH_GS                = (1 << 4),
  46         RADV_PREFETCH_PS                = (1 << 5),
  47         RADV_PREFETCH_SHADERS           = (RADV_PREFETCH_VS  |
  48                                            RADV_PREFETCH_TCS |
  49                                            RADV_PREFETCH_TES |
  50                                            RADV_PREFETCH_GS  |
  51                                            RADV_PREFETCH_PS)
  52 };
  53
  54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
  55                                          struct radv_image *image,
  56                                          VkImageLayout src_layout,
  57                                          VkImageLayout dst_layout,
  58                                          uint32_t src_family,
  59                                          uint32_t dst_family,
  60                                          const VkImageSubresourceRange *range,
  61                                          VkImageAspectFlags pending_clears);
  62
  63 const struct radv_dynamic_state default_dynamic_state = {
  64         .viewport = {
  65                 .count = 0,
  66         },
  67         .scissor = {
  68                 .count = 0,
  69         },
  70         .line_width = 1.0f,
  71         .depth_bias = {
  72                 .bias = 0.0f,
  73                 .clamp = 0.0f,
  74                 .slope = 0.0f,
  75         },
  76         .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
  77         .depth_bounds = {
  78                 .min = 0.0f,
  79                 .max = 1.0f,
  80         },
  81         .stencil_compare_mask = {
  82                 .front = ~0u,
  83                 .back = ~0u,
  84         },
  85         .stencil_write_mask = {
  86                 .front = ~0u,
  87                 .back = ~0u,
  88         },
  89         .stencil_reference = {
  90                 .front = 0u,
  91                 .back = 0u,
  92         },
  93 };
  94
  95 static void
  96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
  97                         const struct radv_dynamic_state *src)
  98 {
  99         struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
 100         uint32_t copy_mask = src->mask;
 101         uint32_t dest_mask = 0;
 102
 103         /* Make sure to copy the number of viewports/scissors because they can
 104          * only be specified at pipeline creation time.
 105          */
 106         dest->viewport.count = src->viewport.count;
 107         dest->scissor.count = src->scissor.count;
 108         dest->discard_rectangle.count = src->discard_rectangle.count;
 109
 110         if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
 111                 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
 112                            src->viewport.count * sizeof(VkViewport))) {
 113                         typed_memcpy(dest->viewport.viewports,
 114                                      src->viewport.viewports,
 115                                      src->viewport.count);
 116                         dest_mask |= RADV_DYNAMIC_VIEWPORT;
 117                 }
 118         }
 119
 120         if (copy_mask & RADV_DYNAMIC_SCISSOR) {
 121                 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
 122                            src->scissor.count * sizeof(VkRect2D))) {
 123                         typed_memcpy(dest->scissor.scissors,
 124                                      src->scissor.scissors, src->scissor.count);
 125                         dest_mask |= RADV_DYNAMIC_SCISSOR;
 126                 }
 127         }
 128
 129         if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
 130                 if (dest->line_width != src->line_width) {
 131                         dest->line_width = src->line_width;
 132                         dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
 133                 }
 134         }
 135
 136         if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
 137                 if (memcmp(&dest->depth_bias, &src->depth_bias,
 138                            sizeof(src->depth_bias))) {
 139                         dest->depth_bias = src->depth_bias;
 140                         dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
 141                 }
 142         }
 143
 144         if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
 145                 if (memcmp(&dest->blend_constants, &src->blend_constants,
 146                            sizeof(src->blend_constants))) {
 147                         typed_memcpy(dest->blend_constants,
 148                                      src->blend_constants, 4);
 149                         dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
 150                 }
 151         }
 152
 153         if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
 154                 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
 155                            sizeof(src->depth_bounds))) {
 156                         dest->depth_bounds = src->depth_bounds;
 157                         dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
 158                 }
 159         }
 160
 161         if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
 162                 if (memcmp(&dest->stencil_compare_mask,
 163                            &src->stencil_compare_mask,
 164                            sizeof(src->stencil_compare_mask))) {
 165                         dest->stencil_compare_mask = src->stencil_compare_mask;
 166                         dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
 167                 }
 168         }
 169
 170         if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
 171                 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
 172                            sizeof(src->stencil_write_mask))) {
 173                         dest->stencil_write_mask = src->stencil_write_mask;
 174                         dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
 175                 }
 176         }
 177
 178         if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
 179                 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
 180                            sizeof(src->stencil_reference))) {
 181                         dest->stencil_reference = src->stencil_reference;
 182                         dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
 183                 }
 184         }
 185
 186         if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
 187                 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
 188                            src->discard_rectangle.count * sizeof(VkRect2D))) {
 189                         typed_memcpy(dest->discard_rectangle.rectangles,
 190                                      src->discard_rectangle.rectangles,
 191                                      src->discard_rectangle.count);
 192                         dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
 193                 }
 194         }
 195
 196         cmd_buffer->state.dirty |= dest_mask;
 197 }
 198
 199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
 200 {
 201         return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
 202                cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
 203 }
 204
 205 enum ring_type radv_queue_family_to_ring(int f) {
 206         switch (f) {
 207         case RADV_QUEUE_GENERAL:
 208                 return RING_GFX;
 209         case RADV_QUEUE_COMPUTE:
 210                 return RING_COMPUTE;
 211         case RADV_QUEUE_TRANSFER:
 212                 return RING_DMA;
 213         default:
 214                 unreachable("Unknown queue family");
 215         }
 216 }
 217
 218 static VkResult radv_create_cmd_buffer(
 219         struct radv_device *                         device,
 220         struct radv_cmd_pool *                       pool,
 221         VkCommandBufferLevel                        level,
 222         VkCommandBuffer*                            pCommandBuffer)
 223 {
 224         struct radv_cmd_buffer *cmd_buffer;
 225         unsigned ring;
 226         cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
 227                                VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 228         if (cmd_buffer == NULL)
 229                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 230
 231         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
 232         cmd_buffer->device = device;
 233         cmd_buffer->pool = pool;
 234         cmd_buffer->level = level;
 235
 236         if (pool) {
 237                 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
 238                 cmd_buffer->queue_family_index = pool->queue_family_index;
 239
 240         } else {
 241                 /* Init the pool_link so we can safefly call list_del when we destroy
 242                  * the command buffer
 243                  */
 244                 list_inithead(&cmd_buffer->pool_link);
 245                 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
 246         }
 247
 248         ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
 249
 250         cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
 251         if (!cmd_buffer->cs) {
 252                 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 253                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 254         }
 255
 256         *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
 257
 258         list_inithead(&cmd_buffer->upload.list);
 259
 260         return VK_SUCCESS;
 261 }
 262
 263 static void
 264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
 265 {
 266         list_del(&cmd_buffer->pool_link);
 267
 268         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 269                                  &cmd_buffer->upload.list, list) {
 270                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 271                 list_del(&up->list);
 272                 free(up);
 273         }
 274
 275         if (cmd_buffer->upload.upload_bo)
 276                 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
 277         cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
 278
 279         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
 280                 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
 281
 282         vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 283 }
 284
 285 static VkResult
 286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 287 {
 288
 289         cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
 290
 291         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 292                                  &cmd_buffer->upload.list, list) {
 293                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 294                 list_del(&up->list);
 295                 free(up);
 296         }
 297
 298         cmd_buffer->push_constant_stages = 0;
 299         cmd_buffer->scratch_size_needed = 0;
 300         cmd_buffer->compute_scratch_size_needed = 0;
 301         cmd_buffer->esgs_ring_size_needed = 0;
 302         cmd_buffer->gsvs_ring_size_needed = 0;
 303         cmd_buffer->tess_rings_needed = false;
 304         cmd_buffer->sample_positions_needed = false;
 305
 306         if (cmd_buffer->upload.upload_bo)
 307                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 308                                    cmd_buffer->upload.upload_bo, 8);
 309         cmd_buffer->upload.offset = 0;
 310
 311         cmd_buffer->record_result = VK_SUCCESS;
 312
 313         cmd_buffer->ring_offsets_idx = -1;
 314
 315         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
 316                 cmd_buffer->descriptors[i].dirty = 0;
 317                 cmd_buffer->descriptors[i].valid = 0;
 318                 cmd_buffer->descriptors[i].push_dirty = false;
 319         }
 320
 321         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 322                 void *fence_ptr;
 323                 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
 324                                              &cmd_buffer->gfx9_fence_offset,
 325                                              &fence_ptr);
 326                 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
 327         }
 328
 329         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
 330
 331         return cmd_buffer->record_result;
 332 }
 333
 334 static bool
 335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
 336                                   uint64_t min_needed)
 337 {
 338         uint64_t new_size;
 339         struct radeon_winsys_bo *bo;
 340         struct radv_cmd_buffer_upload *upload;
 341         struct radv_device *device = cmd_buffer->device;
 342
 343         new_size = MAX2(min_needed, 16 * 1024);
 344         new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
 345
 346         bo = device->ws->buffer_create(device->ws,
 347                                        new_size, 4096,
 348                                        RADEON_DOMAIN_GTT,
 349                                        RADEON_FLAG_CPU_ACCESS|
 350                                        RADEON_FLAG_NO_INTERPROCESS_SHARING);
 351
 352         if (!bo) {
 353                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 354                 return false;
 355         }
 356
 357         radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
 358         if (cmd_buffer->upload.upload_bo) {
 359                 upload = malloc(sizeof(*upload));
 360
 361                 if (!upload) {
 362                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
 363                         device->ws->buffer_destroy(bo);
 364                         return false;
 365                 }
 366
 367                 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
 368                 list_add(&upload->list, &cmd_buffer->upload.list);
 369         }
 370
 371         cmd_buffer->upload.upload_bo = bo;
 372         cmd_buffer->upload.size = new_size;
 373         cmd_buffer->upload.offset = 0;
 374         cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
 375
 376         if (!cmd_buffer->upload.map) {
 377                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 378                 return false;
 379         }
 380
 381         return true;
 382 }
 383
 384 bool
 385 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
 386                              unsigned size,
 387                              unsigned alignment,
 388                              unsigned *out_offset,
 389                              void **ptr)
 390 {
 391         uint64_t offset = align(cmd_buffer->upload.offset, alignment);
 392         if (offset + size > cmd_buffer->upload.size) {
 393                 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
 394                         return false;
 395                 offset = 0;
 396         }
 397
 398         *out_offset = offset;
 399         *ptr = cmd_buffer->upload.map + offset;
 400
 401         cmd_buffer->upload.offset = offset + size;
 402         return true;
 403 }
 404
 405 bool
 406 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
 407                             unsigned size, unsigned alignment,
 408                             const void *data, unsigned *out_offset)
 409 {
 410         uint8_t *ptr;
 411
 412         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
 413                                           out_offset, (void **)&ptr))
 414                 return false;
 415
 416         if (ptr)
 417                 memcpy(ptr, data, size);
 418
 419         return true;
 420 }
 421
 422 static void
 423 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
 424                             unsigned count, const uint32_t *data)
 425 {
 426         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
 427         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
 428                     S_370_WR_CONFIRM(1) |
 429                     S_370_ENGINE_SEL(V_370_ME));
 430         radeon_emit(cs, va);
 431         radeon_emit(cs, va >> 32);
 432         radeon_emit_array(cs, data, count);
 433 }
 434
 435 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
 436 {
 437         struct radv_device *device = cmd_buffer->device;
 438         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 439         uint64_t va;
 440
 441         va = radv_buffer_get_va(device->trace_bo);
 442         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
 443                 va += 4;
 444
 445         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
 446
 447         ++cmd_buffer->state.trace_id;
 448         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 449         radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
 450         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
 451         radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
 452 }
 453
 454 static void
 455 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
 456                            enum radv_cmd_flush_bits flags)
 457 {
 458         if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
 459                 uint32_t *ptr = NULL;
 460                 uint64_t va = 0;
 461
 462                 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
 463                                 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
 464
 465                 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
 466                         va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
 467                              cmd_buffer->gfx9_fence_offset;
 468                         ptr = &cmd_buffer->gfx9_fence_idx;
 469                 }
 470
 471                 /* Force wait for graphics or compute engines to be idle. */
 472                 si_cs_emit_cache_flush(cmd_buffer->cs,
 473                                        cmd_buffer->device->physical_device->rad_info.chip_class,
 474                                        ptr, va,
 475                                        radv_cmd_buffer_uses_mec(cmd_buffer),
 476                                        flags);
 477         }
 478
 479         if (unlikely(cmd_buffer->device->trace_bo))
 480                 radv_cmd_buffer_trace_emit(cmd_buffer);
 481 }
 482
 483 static void
 484 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
 485                    struct radv_pipeline *pipeline, enum ring_type ring)
 486 {
 487         struct radv_device *device = cmd_buffer->device;
 488         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 489         uint32_t data[2];
 490         uint64_t va;
 491
 492         va = radv_buffer_get_va(device->trace_bo);
 493
 494         switch (ring) {
 495         case RING_GFX:
 496                 va += 8;
 497                 break;
 498         case RING_COMPUTE:
 499                 va += 16;
 500                 break;
 501         default:
 502                 assert(!"invalid ring type");
 503         }
 504
 505         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 506                                                            cmd_buffer->cs, 6);
 507
 508         data[0] = (uintptr_t)pipeline;
 509         data[1] = (uintptr_t)pipeline >> 32;
 510
 511         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 512         radv_emit_write_data_packet(cs, va, 2, data);
 513 }
 514
 515 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 516                              VkPipelineBindPoint bind_point,
 517                              struct radv_descriptor_set *set,
 518                              unsigned idx)
 519 {
 520         struct radv_descriptor_state *descriptors_state =
 521                 radv_get_descriptors_state(cmd_buffer, bind_point);
 522
 523         descriptors_state->sets[idx] = set;
 524         if (set)
 525                 descriptors_state->valid |= (1u << idx);
 526         else
 527                 descriptors_state->valid &= ~(1u << idx);
 528         descriptors_state->dirty |= (1u << idx);
 529 }
 530
 531 static void
 532 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
 533                       VkPipelineBindPoint bind_point)
 534 {
 535         struct radv_descriptor_state *descriptors_state =
 536                 radv_get_descriptors_state(cmd_buffer, bind_point);
 537         struct radv_device *device = cmd_buffer->device;
 538         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 539         uint32_t data[MAX_SETS * 2] = {};
 540         uint64_t va;
 541         unsigned i;
 542         va = radv_buffer_get_va(device->trace_bo) + 24;
 543
 544         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 545                                                            cmd_buffer->cs, 4 + MAX_SETS * 2);
 546
 547         for_each_bit(i, descriptors_state->valid) {
 548                 struct radv_descriptor_set *set = descriptors_state->sets[i];
 549                 data[i * 2] = (uintptr_t)set;
 550                 data[i * 2 + 1] = (uintptr_t)set >> 32;
 551         }
 552
 553         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 554         radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
 555 }
 556
 557 struct radv_userdata_info *
 558 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
 559                       gl_shader_stage stage,
 560                       int idx)
 561 {
 562         if (stage == MESA_SHADER_VERTEX) {
 563                 if (pipeline->shaders[MESA_SHADER_VERTEX])
 564                         return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
 565                 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
 566                         return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
 567                 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
 568                         return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
 569         } else if (stage == MESA_SHADER_TESS_EVAL) {
 570                 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
 571                         return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
 572                 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
 573                         return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
 574         }
 575         return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
 576 }
 577
 578 static void
 579 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
 580                            struct radv_pipeline *pipeline,
 581                            gl_shader_stage stage,
 582                            int idx, uint64_t va)
 583 {
 584         struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
 585         uint32_t base_reg = pipeline->user_data_0[stage];
 586         if (loc->sgpr_idx == -1)
 587                 return;
 588         assert(loc->num_sgprs == 2);
 589         assert(!loc->indirect);
 590         radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
 591         radeon_emit(cmd_buffer->cs, va);
 592         radeon_emit(cmd_buffer->cs, va >> 32);
 593 }
 594
 595 static void
 596 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
 597                               struct radv_pipeline *pipeline)
 598 {
 599         int num_samples = pipeline->graphics.ms.num_samples;
 600         struct radv_multisample_state *ms = &pipeline->graphics.ms;
 601         struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
 602
 603         if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
 604                 cmd_buffer->sample_positions_needed = true;
 605
 606         if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
 607                 return;
 608
 609         radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
 610         radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
 611         radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
 612
 613         radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
 614
 615         radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
 616
 617         /* GFX9: Flush DFSM when the AA mode changes. */
 618         if (cmd_buffer->device->dfsm_allowed) {
 619                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 620                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
 621         }
 622 }
 623
 624 static void
 625 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
 626                           struct radv_shader_variant *shader)
 627 {
 628         struct radeon_winsys *ws = cmd_buffer->device->ws;
 629         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 630         uint64_t va;
 631
 632         if (!shader)
 633                 return;
 634
 635         va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 636
 637         radv_cs_add_buffer(ws, cs, shader->bo, 8);
 638         si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
 639 }
 640
 641 static void
 642 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
 643                       struct radv_pipeline *pipeline,
 644                       bool vertex_stage_only)
 645 {
 646         struct radv_cmd_state *state = &cmd_buffer->state;
 647         uint32_t mask = state->prefetch_L2_mask;
 648
 649         if (vertex_stage_only) {
 650                 /* Fast prefetch path for starting draws as soon as possible.
 651                  */
 652                 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
 653                                                   RADV_PREFETCH_VBO_DESCRIPTORS);
 654         }
 655
 656         if (mask & RADV_PREFETCH_VS)
 657                 radv_emit_shader_prefetch(cmd_buffer,
 658                                           pipeline->shaders[MESA_SHADER_VERTEX]);
 659
 660         if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
 661                 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
 662
 663         if (mask & RADV_PREFETCH_TCS)
 664                 radv_emit_shader_prefetch(cmd_buffer,
 665                                           pipeline->shaders[MESA_SHADER_TESS_CTRL]);
 666
 667         if (mask & RADV_PREFETCH_TES)
 668                 radv_emit_shader_prefetch(cmd_buffer,
 669                                           pipeline->shaders[MESA_SHADER_TESS_EVAL]);
 670
 671         if (mask & RADV_PREFETCH_GS) {
 672                 radv_emit_shader_prefetch(cmd_buffer,
 673                                           pipeline->shaders[MESA_SHADER_GEOMETRY]);
 674                 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
 675         }
 676
 677         if (mask & RADV_PREFETCH_PS)
 678                 radv_emit_shader_prefetch(cmd_buffer,
 679                                           pipeline->shaders[MESA_SHADER_FRAGMENT]);
 680
 681         state->prefetch_L2_mask &= ~mask;
 682 }
 683
 684 static void
 685 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
 686 {
 687         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 688
 689         if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
 690                 return;
 691
 692         radv_update_multisample_state(cmd_buffer, pipeline);
 693
 694         cmd_buffer->scratch_size_needed =
 695                                   MAX2(cmd_buffer->scratch_size_needed,
 696                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
 697
 698         if (!cmd_buffer->state.emitted_pipeline ||
 699             cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
 700              pipeline->graphics.can_use_guardband)
 701                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
 702
 703         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
 704
 705         if (unlikely(cmd_buffer->device->trace_bo))
 706                 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
 707
 708         cmd_buffer->state.emitted_pipeline = pipeline;
 709
 710         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
 711 }
 712
 713 static void
 714 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
 715 {
 716         si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
 717                           cmd_buffer->state.dynamic.viewport.viewports);
 718 }
 719
 720 static void
 721 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
 722 {
 723         uint32_t count = cmd_buffer->state.dynamic.scissor.count;
 724
 725         /* Vega10/Raven scissor bug workaround. This must be done before VPORT
 726          * scissor registers are changed. There is also a more efficient but
 727          * more involved alternative workaround.
 728          */
 729         if (cmd_buffer->device->physical_device->has_scissor_bug) {
 730                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
 731                 si_emit_cache_flush(cmd_buffer);
 732         }
 733         si_write_scissors(cmd_buffer->cs, 0, count,
 734                           cmd_buffer->state.dynamic.scissor.scissors,
 735                           cmd_buffer->state.dynamic.viewport.viewports,
 736                           cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
 737 }
 738
 739 static void
 740 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
 741 {
 742         if (!cmd_buffer->state.dynamic.discard_rectangle.count)
 743                 return;
 744
 745         radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
 746                                    cmd_buffer->state.dynamic.discard_rectangle.count * 2);
 747         for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
 748                 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
 749                 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
 750                 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
 751                                             S_028214_BR_Y(rect.offset.y + rect.extent.height));
 752         }
 753 }
 754
 755 static void
 756 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
 757 {
 758         unsigned width = cmd_buffer->state.dynamic.line_width * 8;
 759
 760         radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
 761                                S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
 762 }
 763
 764 static void
 765 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
 766 {
 767         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 768
 769         radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
 770         radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
 771 }
 772
 773 static void
 774 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
 775 {
 776         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 777
 778         radeon_set_context_reg_seq(cmd_buffer->cs,
 779                                    R_028430_DB_STENCILREFMASK, 2);
 780         radeon_emit(cmd_buffer->cs,
 781                     S_028430_STENCILTESTVAL(d->stencil_reference.front) |
 782                     S_028430_STENCILMASK(d->stencil_compare_mask.front) |
 783                     S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
 784                     S_028430_STENCILOPVAL(1));
 785         radeon_emit(cmd_buffer->cs,
 786                     S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
 787                     S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
 788                     S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
 789                     S_028434_STENCILOPVAL_BF(1));
 790 }
 791
 792 static void
 793 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
 794 {
 795         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 796
 797         radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
 798                                fui(d->depth_bounds.min));
 799         radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
 800                                fui(d->depth_bounds.max));
 801 }
 802
 803 static void
 804 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
 805 {
 806         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 807         unsigned slope = fui(d->depth_bias.slope * 16.0f);
 808         unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
 809
 810
 811         radeon_set_context_reg_seq(cmd_buffer->cs,
 812                                    R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
 813         radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
 814         radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
 815         radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
 816         radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
 817         radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
 818 }
 819
 820 static void
 821 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
 822                          int index,
 823                          struct radv_attachment_info *att,
 824                          struct radv_image *image,
 825                          VkImageLayout layout)
 826 {
 827         bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
 828         struct radv_color_buffer_info *cb = &att->cb;
 829         uint32_t cb_color_info = cb->cb_color_info;
 830
 831         if (!radv_layout_dcc_compressed(image, layout,
 832                                         radv_image_queue_family_mask(image,
 833                                                                      cmd_buffer->queue_family_index,
 834                                                                      cmd_buffer->queue_family_index))) {
 835                 cb_color_info &= C_028C70_DCC_ENABLE;
 836         }
 837
 838         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 839                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
 840                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
 841                 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
 842                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
 843                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
 844                 radeon_emit(cmd_buffer->cs, cb_color_info);
 845                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
 846                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
 847                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
 848                 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
 849                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
 850                 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
 851
 852                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
 853                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
 854                 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
 855
 856                 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
 857                                        S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
 858         } else {
 859                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
 860                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
 861                 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
 862                 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
 863                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
 864                 radeon_emit(cmd_buffer->cs, cb_color_info);
 865                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
 866                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
 867                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
 868                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
 869                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
 870                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
 871
 872                 if (is_vi) { /* DCC BASE */
 873                         radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
 874                 }
 875         }
 876 }
 877
 878 static void
 879 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
 880                       struct radv_ds_buffer_info *ds,
 881                       struct radv_image *image,
 882                       VkImageLayout layout)
 883 {
 884         uint32_t db_z_info = ds->db_z_info;
 885         uint32_t db_stencil_info = ds->db_stencil_info;
 886
 887         if (!radv_layout_has_htile(image, layout,
 888                                    radv_image_queue_family_mask(image,
 889                                                                 cmd_buffer->queue_family_index,
 890                                                                 cmd_buffer->queue_family_index))) {
 891                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
 892                 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
 893         }
 894
 895         radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
 896         radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
 897
 898
 899         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 900                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
 901                 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
 902                 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
 903                 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
 904
 905                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
 906                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* DB_Z_INFO */
 907                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* DB_STENCIL_INFO */
 908                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* DB_Z_READ_BASE */
 909                 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32));        /* DB_Z_READ_BASE_HI */
 910                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* DB_STENCIL_READ_BASE */
 911                 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
 912                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* DB_Z_WRITE_BASE */
 913                 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32));       /* DB_Z_WRITE_BASE_HI */
 914                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
 915                 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
 916
 917                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
 918                 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
 919                 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
 920         } else {
 921                 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
 922
 923                 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
 924                 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
 925                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* R_028040_DB_Z_INFO */
 926                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* R_028044_DB_STENCIL_INFO */
 927                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* R_028048_DB_Z_READ_BASE */
 928                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* R_02804C_DB_STENCIL_READ_BASE */
 929                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* R_028050_DB_Z_WRITE_BASE */
 930                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
 931                 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
 932                 radeon_emit(cmd_buffer->cs, ds->db_depth_slice);        /* R_02805C_DB_DEPTH_SLICE */
 933
 934         }
 935
 936         radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
 937                                ds->pa_su_poly_offset_db_fmt_cntl);
 938 }
 939
 940 void
 941 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
 942                           struct radv_image *image,
 943                           VkClearDepthStencilValue ds_clear_value,
 944                           VkImageAspectFlags aspects)
 945 {
 946         uint64_t va = radv_buffer_get_va(image->bo);
 947         va += image->offset + image->clear_value_offset;
 948         unsigned reg_offset = 0, reg_count = 0;
 949
 950         assert(image->surface.htile_size);
 951
 952         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 953                 ++reg_count;
 954         } else {
 955                 ++reg_offset;
 956                 va += 4;
 957         }
 958         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
 959                 ++reg_count;
 960
 961         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
 962         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
 963                                     S_370_WR_CONFIRM(1) |
 964                                     S_370_ENGINE_SEL(V_370_PFP));
 965         radeon_emit(cmd_buffer->cs, va);
 966         radeon_emit(cmd_buffer->cs, va >> 32);
 967         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
 968                 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
 969         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
 970                 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
 971
 972         radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
 973         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
 974                 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
 975         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
 976                 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
 977 }
 978
 979 static void
 980 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
 981                            struct radv_image *image)
 982 {
 983         VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
 984         uint64_t va = radv_buffer_get_va(image->bo);
 985         va += image->offset + image->clear_value_offset;
 986         unsigned reg_offset = 0, reg_count = 0;
 987
 988         if (!image->surface.htile_size)
 989                 return;
 990
 991         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
 992                 ++reg_count;
 993         } else {
 994                 ++reg_offset;
 995                 va += 4;
 996         }
 997         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
 998                 ++reg_count;
 999
1000         radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1001         radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1002                                     COPY_DATA_DST_SEL(COPY_DATA_REG) |
1003                                     (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1004         radeon_emit(cmd_buffer->cs, va);
1005         radeon_emit(cmd_buffer->cs, va >> 32);
1006         radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1007         radeon_emit(cmd_buffer->cs, 0);
1008
1009         radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1010         radeon_emit(cmd_buffer->cs, 0);
1011 }
1012
1013 /*
1014  *with DCC some colors don't require CMASK elimiation before being
1015  * used as a texture. This sets a predicate value to determine if the
1016  * cmask eliminate is required.
1017  */
1018 void
1019 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1020                                   struct radv_image *image,
1021                                   bool value)
1022 {
1023         uint64_t pred_val = value;
1024         uint64_t va = radv_buffer_get_va(image->bo);
1025         va += image->offset + image->dcc_pred_offset;
1026
1027         assert(image->surface.dcc_size);
1028
1029         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1030         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1031                                     S_370_WR_CONFIRM(1) |
1032                                     S_370_ENGINE_SEL(V_370_PFP));
1033         radeon_emit(cmd_buffer->cs, va);
1034         radeon_emit(cmd_buffer->cs, va >> 32);
1035         radeon_emit(cmd_buffer->cs, pred_val);
1036         radeon_emit(cmd_buffer->cs, pred_val >> 32);
1037 }
1038
1039 void
1040 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1041                           struct radv_image *image,
1042                           int idx,
1043                           uint32_t color_values[2])
1044 {
1045         uint64_t va = radv_buffer_get_va(image->bo);
1046         va += image->offset + image->clear_value_offset;
1047
1048         assert(image->cmask.size || image->surface.dcc_size);
1049
1050         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1051         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1052                                     S_370_WR_CONFIRM(1) |
1053                                     S_370_ENGINE_SEL(V_370_PFP));
1054         radeon_emit(cmd_buffer->cs, va);
1055         radeon_emit(cmd_buffer->cs, va >> 32);
1056         radeon_emit(cmd_buffer->cs, color_values[0]);
1057         radeon_emit(cmd_buffer->cs, color_values[1]);
1058
1059         radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1060         radeon_emit(cmd_buffer->cs, color_values[0]);
1061         radeon_emit(cmd_buffer->cs, color_values[1]);
1062 }
1063
1064 static void
1065 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1066                            struct radv_image *image,
1067                            int idx)
1068 {
1069         uint64_t va = radv_buffer_get_va(image->bo);
1070         va += image->offset + image->clear_value_offset;
1071
1072         if (!image->cmask.size && !image->surface.dcc_size)
1073                 return;
1074
1075         uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1076
1077         radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1078         radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1079                                     COPY_DATA_DST_SEL(COPY_DATA_REG) |
1080                                     COPY_DATA_COUNT_SEL);
1081         radeon_emit(cmd_buffer->cs, va);
1082         radeon_emit(cmd_buffer->cs, va >> 32);
1083         radeon_emit(cmd_buffer->cs, reg >> 2);
1084         radeon_emit(cmd_buffer->cs, 0);
1085
1086         radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1087         radeon_emit(cmd_buffer->cs, 0);
1088 }
1089
1090 static void
1091 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1092 {
1093         int i;
1094         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1095         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1096
1097         /* this may happen for inherited secondary recording */
1098         if (!framebuffer)
1099                 return;
1100
1101         for (i = 0; i < 8; ++i) {
1102                 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1103                         radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1104                                        S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1105                         continue;
1106                 }
1107
1108                 int idx = subpass->color_attachments[i].attachment;
1109                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1110                 struct radv_image *image = att->attachment->image;
1111                 VkImageLayout layout = subpass->color_attachments[i].layout;
1112
1113                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1114
1115                 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1116                 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1117
1118                 radv_load_color_clear_regs(cmd_buffer, image, i);
1119         }
1120
1121         if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1122                 int idx = subpass->depth_stencil_attachment.attachment;
1123                 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1124                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1125                 struct radv_image *image = att->attachment->image;
1126                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1127                 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1128                                                                                 cmd_buffer->queue_family_index,
1129                                                                                 cmd_buffer->queue_family_index);
1130                 /* We currently don't support writing decompressed HTILE */
1131                 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1132                        radv_layout_is_htile_compressed(image, layout, queue_mask));
1133
1134                 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1135
1136                 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1137                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1138                         cmd_buffer->state.offset_scale = att->ds.offset_scale;
1139                 }
1140                 radv_load_depth_clear_regs(cmd_buffer, image);
1141         } else {
1142                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1143                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1144                 else
1145                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1146
1147                 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1148                 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1149         }
1150         radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1151                                S_028208_BR_X(framebuffer->width) |
1152                                S_028208_BR_Y(framebuffer->height));
1153
1154         if (cmd_buffer->device->dfsm_allowed) {
1155                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1156                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1157         }
1158
1159         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1160 }
1161
1162 static void
1163 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1164 {
1165         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1166         struct radv_cmd_state *state = &cmd_buffer->state;
1167
1168         if (state->index_type != state->last_index_type) {
1169                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1170                         radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1171                                                    2, state->index_type);
1172                 } else {
1173                         radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1174                         radeon_emit(cs, state->index_type);
1175                 }
1176
1177                 state->last_index_type = state->index_type;
1178         }
1179
1180         radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1181         radeon_emit(cs, state->index_va);
1182         radeon_emit(cs, state->index_va >> 32);
1183
1184         radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1185         radeon_emit(cs, state->max_index_count);
1186
1187         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1188 }
1189
1190 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1191 {
1192         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1193         uint32_t pa_sc_mode_cntl_1 =
1194                 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1195         uint32_t db_count_control;
1196
1197         if(!cmd_buffer->state.active_occlusion_queries) {
1198                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1199                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1200                             pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
1201                                 /* Re-enable out-of-order rasterization if the
1202                                  * bound pipeline supports it and if it's has
1203                                  * been disabled before starting occlusion
1204                                  * queries.
1205                                  */
1206                                 radeon_set_context_reg(cmd_buffer->cs,
1207                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1208                                                        pa_sc_mode_cntl_1);
1209                         }
1210                         db_count_control = 0;
1211                 } else {
1212                         db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1213                 }
1214         } else {
1215                 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1216                 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1217                 bool perfect = cmd_buffer->state.perfect_occlusion_queries_enabled;
1218
1219                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1220                         db_count_control =
1221                                 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1222                                 S_028004_SAMPLE_RATE(sample_rate) |
1223                                 S_028004_ZPASS_ENABLE(1) |
1224                                 S_028004_SLICE_EVEN_ENABLE(1) |
1225                                 S_028004_SLICE_ODD_ENABLE(1);
1226
1227                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1228                             pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
1229                                 /* If the bound pipeline has enabled
1230                                  * out-of-order rasterization, we should
1231                                  * disable it before starting occlusion
1232                                  * queries.
1233                                  */
1234                                 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1235
1236                                 radeon_set_context_reg(cmd_buffer->cs,
1237                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1238                                                        pa_sc_mode_cntl_1);
1239                         }
1240                 } else {
1241                         db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1242                                 S_028004_SAMPLE_RATE(sample_rate);
1243                 }
1244         }
1245
1246         radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1247 }
1248
1249 static void
1250 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1251 {
1252         uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1253
1254         if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1255                 radv_emit_viewport(cmd_buffer);
1256
1257         if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1258                 radv_emit_scissor(cmd_buffer);
1259
1260         if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1261                 radv_emit_line_width(cmd_buffer);
1262
1263         if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1264                 radv_emit_blend_constants(cmd_buffer);
1265
1266         if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1267                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1268                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1269                 radv_emit_stencil(cmd_buffer);
1270
1271         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1272                 radv_emit_depth_bounds(cmd_buffer);
1273
1274         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1275                 radv_emit_depth_bias(cmd_buffer);
1276
1277         if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1278                 radv_emit_discard_rectangle(cmd_buffer);
1279
1280         cmd_buffer->state.dirty &= ~states;
1281 }
1282
1283 static void
1284 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1285                                    struct radv_pipeline *pipeline,
1286                                    int idx,
1287                                    uint64_t va,
1288                                    gl_shader_stage stage)
1289 {
1290         struct radv_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1291         uint32_t base_reg = pipeline->user_data_0[stage];
1292
1293         if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1294                 return;
1295
1296         assert(!desc_set_loc->indirect);
1297         assert(desc_set_loc->num_sgprs == 2);
1298         radeon_set_sh_reg_seq(cmd_buffer->cs,
1299                               base_reg + desc_set_loc->sgpr_idx * 4, 2);
1300         radeon_emit(cmd_buffer->cs, va);
1301         radeon_emit(cmd_buffer->cs, va >> 32);
1302 }
1303
1304 static void
1305 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1306                                   VkShaderStageFlags stages,
1307                                   struct radv_descriptor_set *set,
1308                                   unsigned idx)
1309 {
1310         if (cmd_buffer->state.pipeline) {
1311                 radv_foreach_stage(stage, stages) {
1312                         if (cmd_buffer->state.pipeline->shaders[stage])
1313                                 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1314                                                                    idx, set->va,
1315                                                                    stage);
1316                 }
1317         }
1318
1319         if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1320                 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1321                                                    idx, set->va,
1322                                                    MESA_SHADER_COMPUTE);
1323 }
1324
1325 static void
1326 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1327                             VkPipelineBindPoint bind_point)
1328 {
1329         struct radv_descriptor_state *descriptors_state =
1330                 radv_get_descriptors_state(cmd_buffer, bind_point);
1331         struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1332         unsigned bo_offset;
1333
1334         if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1335                                          set->mapped_ptr,
1336                                          &bo_offset))
1337                 return;
1338
1339         set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1340         set->va += bo_offset;
1341 }
1342
1343 static void
1344 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1345                                     VkPipelineBindPoint bind_point)
1346 {
1347         struct radv_descriptor_state *descriptors_state =
1348                 radv_get_descriptors_state(cmd_buffer, bind_point);
1349         uint32_t size = MAX_SETS * 2 * 4;
1350         uint32_t offset;
1351         void *ptr;
1352
1353         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1354                                           256, &offset, &ptr))
1355                 return;
1356
1357         for (unsigned i = 0; i < MAX_SETS; i++) {
1358                 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1359                 uint64_t set_va = 0;
1360                 struct radv_descriptor_set *set = descriptors_state->sets[i];
1361                 if (descriptors_state->valid & (1u << i))
1362                         set_va = set->va;
1363                 uptr[0] = set_va & 0xffffffff;
1364                 uptr[1] = set_va >> 32;
1365         }
1366
1367         uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1368         va += offset;
1369
1370         if (cmd_buffer->state.pipeline) {
1371                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1372                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1373                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1374
1375                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1376                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1377                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1378
1379                 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1380                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1381                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1382
1383                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1384                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1385                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1386
1387                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1388                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1389                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1390         }
1391
1392         if (cmd_buffer->state.compute_pipeline)
1393                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1394                                            AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1395 }
1396
1397 static void
1398 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1399                        VkShaderStageFlags stages)
1400 {
1401         VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1402                                          VK_PIPELINE_BIND_POINT_COMPUTE :
1403                                          VK_PIPELINE_BIND_POINT_GRAPHICS;
1404         struct radv_descriptor_state *descriptors_state =
1405                 radv_get_descriptors_state(cmd_buffer, bind_point);
1406         unsigned i;
1407
1408         if (!descriptors_state->dirty)
1409                 return;
1410
1411         if (descriptors_state->push_dirty)
1412                 radv_flush_push_descriptors(cmd_buffer, bind_point);
1413
1414         if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1415             (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1416                 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1417         }
1418
1419         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1420                                                            cmd_buffer->cs,
1421                                                            MAX_SETS * MESA_SHADER_STAGES * 4);
1422
1423         for_each_bit(i, descriptors_state->dirty) {
1424                 struct radv_descriptor_set *set = descriptors_state->sets[i];
1425                 if (!(descriptors_state->valid & (1u << i)))
1426                         continue;
1427
1428                 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1429         }
1430         descriptors_state->dirty = 0;
1431         descriptors_state->push_dirty = false;
1432
1433         if (unlikely(cmd_buffer->device->trace_bo))
1434                 radv_save_descriptors(cmd_buffer, bind_point);
1435
1436         assert(cmd_buffer->cs->cdw <= cdw_max);
1437 }
1438
1439 static void
1440 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1441                      struct radv_pipeline *pipeline,
1442                      VkShaderStageFlags stages)
1443 {
1444         struct radv_pipeline_layout *layout = pipeline->layout;
1445         unsigned offset;
1446         void *ptr;
1447         uint64_t va;
1448
1449         stages &= cmd_buffer->push_constant_stages;
1450         if (!stages ||
1451             (!layout->push_constant_size && !layout->dynamic_offset_count))
1452                 return;
1453
1454         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1455                                           16 * layout->dynamic_offset_count,
1456                                           256, &offset, &ptr))
1457                 return;
1458
1459         memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1460         memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1461                16 * layout->dynamic_offset_count);
1462
1463         va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1464         va += offset;
1465
1466         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1467                                                            cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1468
1469         radv_foreach_stage(stage, stages) {
1470                 if (pipeline->shaders[stage]) {
1471                         radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1472                                                    AC_UD_PUSH_CONSTANTS, va);
1473                 }
1474         }
1475
1476         cmd_buffer->push_constant_stages &= ~stages;
1477         assert(cmd_buffer->cs->cdw <= cdw_max);
1478 }
1479
1480 static void
1481 radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1482 {
1483         if ((pipeline_is_dirty ||
1484             (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1485             cmd_buffer->state.pipeline->vertex_elements.count &&
1486             radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1487                 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1488                 unsigned vb_offset;
1489                 void *vb_ptr;
1490                 uint32_t i = 0;
1491                 uint32_t count = velems->count;
1492                 uint64_t va;
1493
1494                 /* allocate some descriptor state for vertex buffers */
1495                 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1496                                                   &vb_offset, &vb_ptr))
1497                         return;
1498
1499                 for (i = 0; i < count; i++) {
1500                         uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1501                         uint32_t offset;
1502                         int vb = velems->binding[i];
1503                         struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1504                         uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1505
1506                         va = radv_buffer_get_va(buffer->bo);
1507
1508                         offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1509                         va += offset + buffer->offset;
1510                         desc[0] = va;
1511                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1512                         if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1513                                 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1514                         else
1515                                 desc[2] = buffer->size - offset;
1516                         desc[3] = velems->rsrc_word3[i];
1517                 }
1518
1519                 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1520                 va += vb_offset;
1521
1522                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1523                                            AC_UD_VS_VERTEX_BUFFERS, va);
1524
1525                 cmd_buffer->state.vb_va = va;
1526                 cmd_buffer->state.vb_size = count * 16;
1527                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1528         }
1529         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1530 }
1531
1532 static void
1533 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1534 {
1535         radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1536         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1537         radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
1538                              VK_SHADER_STAGE_ALL_GRAPHICS);
1539 }
1540
1541 static void
1542 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1543                          bool instanced_draw, bool indirect_draw,
1544                          uint32_t draw_vertex_count)
1545 {
1546         struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1547         struct radv_cmd_state *state = &cmd_buffer->state;
1548         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1549         uint32_t ia_multi_vgt_param;
1550         int32_t primitive_reset_en;
1551
1552         /* Draw state. */
1553         ia_multi_vgt_param =
1554                 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1555                                           indirect_draw, draw_vertex_count);
1556
1557         if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1558                 if (info->chip_class >= GFX9) {
1559                         radeon_set_uconfig_reg_idx(cs,
1560                                                    R_030960_IA_MULTI_VGT_PARAM,
1561                                                    4, ia_multi_vgt_param);
1562                 } else if (info->chip_class >= CIK) {
1563                         radeon_set_context_reg_idx(cs,
1564                                                    R_028AA8_IA_MULTI_VGT_PARAM,
1565                                                    1, ia_multi_vgt_param);
1566                 } else {
1567                         radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1568                                                ia_multi_vgt_param);
1569                 }
1570                 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1571         }
1572
1573         /* Primitive restart. */
1574         primitive_reset_en =
1575                 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1576
1577         if (primitive_reset_en != state->last_primitive_reset_en) {
1578                 state->last_primitive_reset_en = primitive_reset_en;
1579                 if (info->chip_class >= GFX9) {
1580                         radeon_set_uconfig_reg(cs,
1581                                                R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1582                                                primitive_reset_en);
1583                 } else {
1584                         radeon_set_context_reg(cs,
1585                                                R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1586                                                primitive_reset_en);
1587                 }
1588         }
1589
1590         if (primitive_reset_en) {
1591                 uint32_t primitive_reset_index =
1592                         state->index_type ? 0xffffffffu : 0xffffu;
1593
1594                 if (primitive_reset_index != state->last_primitive_reset_index) {
1595                         radeon_set_context_reg(cs,
1596                                                R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1597                                                primitive_reset_index);
1598                         state->last_primitive_reset_index = primitive_reset_index;
1599                 }
1600         }
1601 }
1602
1603 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1604                              VkPipelineStageFlags src_stage_mask)
1605 {
1606         if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1607                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1608                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1609                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1610                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1611         }
1612
1613         if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1614                               VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1615                               VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1616                               VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1617                               VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1618                               VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1619                               VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1620                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1621                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1622                               VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1623                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1624                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1625         } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1626                                      VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1627                                      VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1628                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1629         }
1630 }
1631
1632 static enum radv_cmd_flush_bits
1633 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1634                                   VkAccessFlags src_flags)
1635 {
1636         enum radv_cmd_flush_bits flush_bits = 0;
1637         uint32_t b;
1638         for_each_bit(b, src_flags) {
1639                 switch ((VkAccessFlagBits)(1 << b)) {
1640                 case VK_ACCESS_SHADER_WRITE_BIT:
1641                         flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1642                         break;
1643                 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1644                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1645                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1646                         break;
1647                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1648                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1649                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1650                         break;
1651                 case VK_ACCESS_TRANSFER_WRITE_BIT:
1652                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1653                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1654                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1655                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1656                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
1657                         break;
1658                 default:
1659                         break;
1660                 }
1661         }
1662         return flush_bits;
1663 }
1664
1665 static enum radv_cmd_flush_bits
1666 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1667                       VkAccessFlags dst_flags,
1668                       struct radv_image *image)
1669 {
1670         enum radv_cmd_flush_bits flush_bits = 0;
1671         uint32_t b;
1672         for_each_bit(b, dst_flags) {
1673                 switch ((VkAccessFlagBits)(1 << b)) {
1674                 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1675                 case VK_ACCESS_INDEX_READ_BIT:
1676                         break;
1677                 case VK_ACCESS_UNIFORM_READ_BIT:
1678                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1679                         break;
1680                 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1681                 case VK_ACCESS_SHADER_READ_BIT:
1682                 case VK_ACCESS_TRANSFER_READ_BIT:
1683                 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1684                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1685                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
1686                         break;
1687                 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1688                         /* TODO: change to image && when the image gets passed
1689                          * through from the subpass. */
1690                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1691                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1692                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1693                         break;
1694                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1695                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1696                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1697                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1698                         break;
1699                 default:
1700                         break;
1701                 }
1702         }
1703         return flush_bits;
1704 }
1705
1706 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1707 {
1708         cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1709         radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1710         cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1711                                                               NULL);
1712 }
1713
1714 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1715                                                  VkAttachmentReference att)
1716 {
1717         unsigned idx = att.attachment;
1718         struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1719         VkImageSubresourceRange range;
1720         range.aspectMask = 0;
1721         range.baseMipLevel = view->base_mip;
1722         range.levelCount = 1;
1723         range.baseArrayLayer = view->base_layer;
1724         range.layerCount = cmd_buffer->state.framebuffer->layers;
1725
1726         radv_handle_image_transition(cmd_buffer,
1727                                      view->image,
1728                                      cmd_buffer->state.attachments[idx].current_layout,
1729                                      att.layout, 0, 0, &range,
1730                                      cmd_buffer->state.attachments[idx].pending_clear_aspects);
1731
1732         cmd_buffer->state.attachments[idx].current_layout = att.layout;
1733
1734
1735 }
1736
1737 void
1738 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1739                             const struct radv_subpass *subpass, bool transitions)
1740 {
1741         if (transitions) {
1742                 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1743
1744                 for (unsigned i = 0; i < subpass->color_count; ++i) {
1745                         if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1746                                 radv_handle_subpass_image_transition(cmd_buffer,
1747                                                                      subpass->color_attachments[i]);
1748                 }
1749
1750                 for (unsigned i = 0; i < subpass->input_count; ++i) {
1751                         radv_handle_subpass_image_transition(cmd_buffer,
1752                                                         subpass->input_attachments[i]);
1753                 }
1754
1755                 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1756                         radv_handle_subpass_image_transition(cmd_buffer,
1757                                                         subpass->depth_stencil_attachment);
1758                 }
1759         }
1760
1761         cmd_buffer->state.subpass = subpass;
1762
1763         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
1764 }
1765
1766 static VkResult
1767 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1768                                  struct radv_render_pass *pass,
1769                                  const VkRenderPassBeginInfo *info)
1770 {
1771         struct radv_cmd_state *state = &cmd_buffer->state;
1772
1773         if (pass->attachment_count == 0) {
1774                 state->attachments = NULL;
1775                 return VK_SUCCESS;
1776         }
1777
1778         state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1779                                         pass->attachment_count *
1780                                         sizeof(state->attachments[0]),
1781                                         8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1782         if (state->attachments == NULL) {
1783                 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1784                 return cmd_buffer->record_result;
1785         }
1786
1787         for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1788                 struct radv_render_pass_attachment *att = &pass->attachments[i];
1789                 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1790                 VkImageAspectFlags clear_aspects = 0;
1791
1792                 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1793                         /* color attachment */
1794                         if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1795                                 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1796                         }
1797                 } else {
1798                         /* depthstencil attachment */
1799                         if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1800                             att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1801                                 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1802                                 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1803                                     att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1804                                         clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1805                         }
1806                         if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1807                             att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1808                                 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1809                         }
1810                 }
1811
1812                 state->attachments[i].pending_clear_aspects = clear_aspects;
1813                 state->attachments[i].cleared_views = 0;
1814                 if (clear_aspects && info) {
1815                         assert(info->clearValueCount > i);
1816                         state->attachments[i].clear_value = info->pClearValues[i];
1817                 }
1818
1819                 state->attachments[i].current_layout = att->initial_layout;
1820         }
1821
1822         return VK_SUCCESS;
1823 }
1824
1825 VkResult radv_AllocateCommandBuffers(
1826         VkDevice _device,
1827         const VkCommandBufferAllocateInfo *pAllocateInfo,
1828         VkCommandBuffer *pCommandBuffers)
1829 {
1830         RADV_FROM_HANDLE(radv_device, device, _device);
1831         RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1832
1833         VkResult result = VK_SUCCESS;
1834         uint32_t i;
1835
1836         for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1837
1838                 if (!list_empty(&pool->free_cmd_buffers)) {
1839                         struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1840
1841                         list_del(&cmd_buffer->pool_link);
1842                         list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1843
1844                         result = radv_reset_cmd_buffer(cmd_buffer);
1845                         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1846                         cmd_buffer->level = pAllocateInfo->level;
1847
1848                         pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1849                 } else {
1850                         result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1851                                                         &pCommandBuffers[i]);
1852                 }
1853                 if (result != VK_SUCCESS)
1854                         break;
1855         }
1856
1857         if (result != VK_SUCCESS) {
1858                 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
1859                                         i, pCommandBuffers);
1860
1861                 /* From the Vulkan 1.0.66 spec:
1862                  *
1863                  * "vkAllocateCommandBuffers can be used to create multiple
1864                  *  command buffers. If the creation of any of those command
1865                  *  buffers fails, the implementation must destroy all
1866                  *  successfully created command buffer objects from this
1867                  *  command, set all entries of the pCommandBuffers array to
1868                  *  NULL and return the error."
1869                  */
1870                 memset(pCommandBuffers, 0,
1871                        sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
1872         }
1873
1874         return result;
1875 }
1876
1877 void radv_FreeCommandBuffers(
1878         VkDevice device,
1879         VkCommandPool commandPool,
1880         uint32_t commandBufferCount,
1881         const VkCommandBuffer *pCommandBuffers)
1882 {
1883         for (uint32_t i = 0; i < commandBufferCount; i++) {
1884                 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
1885
1886                 if (cmd_buffer) {
1887                         if (cmd_buffer->pool) {
1888                                 list_del(&cmd_buffer->pool_link);
1889                                 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
1890                         } else
1891                                 radv_cmd_buffer_destroy(cmd_buffer);
1892
1893                 }
1894         }
1895 }
1896
1897 VkResult radv_ResetCommandBuffer(
1898         VkCommandBuffer commandBuffer,
1899         VkCommandBufferResetFlags flags)
1900 {
1901         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1902         return radv_reset_cmd_buffer(cmd_buffer);
1903 }
1904
1905 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
1906 {
1907         struct radv_device *device = cmd_buffer->device;
1908         if (device->gfx_init) {
1909                 uint64_t va = radv_buffer_get_va(device->gfx_init);
1910                 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
1911                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
1912                 radeon_emit(cmd_buffer->cs, va);
1913                 radeon_emit(cmd_buffer->cs, va >> 32);
1914                 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
1915         } else
1916                 si_init_config(cmd_buffer);
1917 }
1918
1919 VkResult radv_BeginCommandBuffer(
1920         VkCommandBuffer commandBuffer,
1921         const VkCommandBufferBeginInfo *pBeginInfo)
1922 {
1923         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1924         VkResult result = VK_SUCCESS;
1925
1926         if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
1927                 /* If the command buffer has already been resetted with
1928                  * vkResetCommandBuffer, no need to do it again.
1929                  */
1930                 result = radv_reset_cmd_buffer(cmd_buffer);
1931                 if (result != VK_SUCCESS)
1932                         return result;
1933         }
1934
1935         memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1936         cmd_buffer->state.last_primitive_reset_en = -1;
1937         cmd_buffer->state.last_index_type = -1;
1938         cmd_buffer->state.last_num_instances = -1;
1939         cmd_buffer->state.last_vertex_offset = -1;
1940         cmd_buffer->state.last_first_instance = -1;
1941         cmd_buffer->usage_flags = pBeginInfo->flags;
1942
1943         /* setup initial configuration into command buffer */
1944         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
1945                 switch (cmd_buffer->queue_family_index) {
1946                 case RADV_QUEUE_GENERAL:
1947                         emit_gfx_buffer_state(cmd_buffer);
1948                         break;
1949                 case RADV_QUEUE_COMPUTE:
1950                         si_init_compute(cmd_buffer);
1951                         break;
1952                 case RADV_QUEUE_TRANSFER:
1953                 default:
1954                         break;
1955                 }
1956         }
1957
1958         if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
1959                 assert(pBeginInfo->pInheritanceInfo);
1960                 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
1961                 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1962
1963                 struct radv_subpass *subpass =
1964                         &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1965
1966                 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
1967                 if (result != VK_SUCCESS)
1968                         return result;
1969
1970                 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
1971         }
1972
1973         if (unlikely(cmd_buffer->device->trace_bo))
1974                 radv_cmd_buffer_trace_emit(cmd_buffer);
1975
1976         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
1977
1978         return result;
1979 }
1980
1981 void radv_CmdBindVertexBuffers(
1982         VkCommandBuffer                             commandBuffer,
1983         uint32_t                                    firstBinding,
1984         uint32_t                                    bindingCount,
1985         const VkBuffer*                             pBuffers,
1986         const VkDeviceSize*                         pOffsets)
1987 {
1988         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
1989         struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
1990         bool changed = false;
1991
1992         /* We have to defer setting up vertex buffer since we need the buffer
1993          * stride from the pipeline. */
1994
1995         assert(firstBinding + bindingCount <= MAX_VBS);
1996         for (uint32_t i = 0; i < bindingCount; i++) {
1997                 uint32_t idx = firstBinding + i;
1998
1999                 if (!changed &&
2000                     (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2001                      vb[idx].offset != pOffsets[i])) {
2002                         changed = true;
2003                 }
2004
2005                 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2006                 vb[idx].offset = pOffsets[i];
2007
2008                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2009                                    vb[idx].buffer->bo, 8);
2010         }
2011
2012         if (!changed) {
2013                 /* No state changes. */
2014                 return;
2015         }
2016
2017         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2018 }
2019
2020 void radv_CmdBindIndexBuffer(
2021         VkCommandBuffer                             commandBuffer,
2022         VkBuffer buffer,
2023         VkDeviceSize offset,
2024         VkIndexType indexType)
2025 {
2026         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2027         RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2028
2029         if (cmd_buffer->state.index_buffer == index_buffer &&
2030             cmd_buffer->state.index_offset == offset &&
2031             cmd_buffer->state.index_type == indexType) {
2032                 /* No state changes. */
2033                 return;
2034         }
2035
2036         cmd_buffer->state.index_buffer = index_buffer;
2037         cmd_buffer->state.index_offset = offset;
2038         cmd_buffer->state.index_type = indexType; /* vk matches hw */
2039         cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2040         cmd_buffer->state.index_va += index_buffer->offset + offset;
2041
2042         int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2043         cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2044         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2045         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2046 }
2047
2048
2049 static void
2050 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2051                          VkPipelineBindPoint bind_point,
2052                          struct radv_descriptor_set *set, unsigned idx)
2053 {
2054         struct radeon_winsys *ws = cmd_buffer->device->ws;
2055
2056         radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2057         if (!set)
2058                 return;
2059
2060         assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2061
2062         for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2063                 if (set->descriptors[j])
2064                         radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2065
2066         if(set->bo)
2067                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2068 }
2069
2070 void radv_CmdBindDescriptorSets(
2071         VkCommandBuffer                             commandBuffer,
2072         VkPipelineBindPoint                         pipelineBindPoint,
2073         VkPipelineLayout                            _layout,
2074         uint32_t                                    firstSet,
2075         uint32_t                                    descriptorSetCount,
2076         const VkDescriptorSet*                      pDescriptorSets,
2077         uint32_t                                    dynamicOffsetCount,
2078         const uint32_t*                             pDynamicOffsets)
2079 {
2080         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2081         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2082         unsigned dyn_idx = 0;
2083
2084         for (unsigned i = 0; i < descriptorSetCount; ++i) {
2085                 unsigned idx = i + firstSet;
2086                 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2087                 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2088
2089                 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2090                         unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2091                         uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2092                         assert(dyn_idx < dynamicOffsetCount);
2093
2094                         struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2095                         uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2096                         dst[0] = va;
2097                         dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2098                         dst[2] = range->size;
2099                         dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2100                                  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2101                                  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2102                                  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2103                                  S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2104                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2105                         cmd_buffer->push_constant_stages |=
2106                                              set->layout->dynamic_shader_stages;
2107                 }
2108         }
2109 }
2110
2111 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2112                                           struct radv_descriptor_set *set,
2113                                           struct radv_descriptor_set_layout *layout,
2114                                           VkPipelineBindPoint bind_point)
2115 {
2116         struct radv_descriptor_state *descriptors_state =
2117                 radv_get_descriptors_state(cmd_buffer, bind_point);
2118         set->size = layout->size;
2119         set->layout = layout;
2120
2121         if (descriptors_state->push_set.capacity < set->size) {
2122                 size_t new_size = MAX2(set->size, 1024);
2123                 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2124                 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2125
2126                 free(set->mapped_ptr);
2127                 set->mapped_ptr = malloc(new_size);
2128
2129                 if (!set->mapped_ptr) {
2130                         descriptors_state->push_set.capacity = 0;
2131                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2132                         return false;
2133                 }
2134
2135                 descriptors_state->push_set.capacity = new_size;
2136         }
2137
2138         return true;
2139 }
2140
2141 void radv_meta_push_descriptor_set(
2142         struct radv_cmd_buffer*              cmd_buffer,
2143         VkPipelineBindPoint                  pipelineBindPoint,
2144         VkPipelineLayout                     _layout,
2145         uint32_t                             set,
2146         uint32_t                             descriptorWriteCount,
2147         const VkWriteDescriptorSet*          pDescriptorWrites)
2148 {
2149         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2150         struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2151         unsigned bo_offset;
2152
2153         assert(set == 0);
2154         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2155
2156         push_set->size = layout->set[set].layout->size;
2157         push_set->layout = layout->set[set].layout;
2158
2159         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2160                                           &bo_offset,
2161                                           (void**) &push_set->mapped_ptr))
2162                 return;
2163
2164         push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2165         push_set->va += bo_offset;
2166
2167         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2168                                     radv_descriptor_set_to_handle(push_set),
2169                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2170
2171         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2172 }
2173
2174 void radv_CmdPushDescriptorSetKHR(
2175         VkCommandBuffer                             commandBuffer,
2176         VkPipelineBindPoint                         pipelineBindPoint,
2177         VkPipelineLayout                            _layout,
2178         uint32_t                                    set,
2179         uint32_t                                    descriptorWriteCount,
2180         const VkWriteDescriptorSet*                 pDescriptorWrites)
2181 {
2182         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2183         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2184         struct radv_descriptor_state *descriptors_state =
2185                 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2186         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2187
2188         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2189
2190         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2191                                            layout->set[set].layout,
2192                                            pipelineBindPoint))
2193                 return;
2194
2195         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2196                                     radv_descriptor_set_to_handle(push_set),
2197                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2198
2199         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2200         descriptors_state->push_dirty = true;
2201 }
2202
2203 void radv_CmdPushDescriptorSetWithTemplateKHR(
2204         VkCommandBuffer                             commandBuffer,
2205         VkDescriptorUpdateTemplateKHR               descriptorUpdateTemplate,
2206         VkPipelineLayout                            _layout,
2207         uint32_t                                    set,
2208         const void*                                 pData)
2209 {
2210         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2211         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2212         RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2213         struct radv_descriptor_state *descriptors_state =
2214                 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2215         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2216
2217         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2218
2219         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2220                                            layout->set[set].layout,
2221                                            templ->bind_point))
2222                 return;
2223
2224         radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2225                                                  descriptorUpdateTemplate, pData);
2226
2227         radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2228         descriptors_state->push_dirty = true;
2229 }
2230
2231 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2232                            VkPipelineLayout layout,
2233                            VkShaderStageFlags stageFlags,
2234                            uint32_t offset,
2235                            uint32_t size,
2236                            const void* pValues)
2237 {
2238         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2239         memcpy(cmd_buffer->push_constants + offset, pValues, size);
2240         cmd_buffer->push_constant_stages |= stageFlags;
2241 }
2242
2243 VkResult radv_EndCommandBuffer(
2244         VkCommandBuffer                             commandBuffer)
2245 {
2246         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2247
2248         if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2249                 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2250                         cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2251                 si_emit_cache_flush(cmd_buffer);
2252         }
2253
2254         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2255
2256         if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2257                 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2258
2259         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2260
2261         return cmd_buffer->record_result;
2262 }
2263
2264 static void
2265 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2266 {
2267         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2268
2269         if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2270                 return;
2271
2272         cmd_buffer->state.emitted_compute_pipeline = pipeline;
2273
2274         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2275         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2276
2277         cmd_buffer->compute_scratch_size_needed =
2278                                   MAX2(cmd_buffer->compute_scratch_size_needed,
2279                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2280
2281         if (unlikely(cmd_buffer->device->trace_bo))
2282                 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2283 }
2284
2285 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2286                                             VkPipelineBindPoint bind_point)
2287 {
2288         struct radv_descriptor_state *descriptors_state =
2289                 radv_get_descriptors_state(cmd_buffer, bind_point);
2290
2291         descriptors_state->dirty |= descriptors_state->valid;
2292 }
2293
2294 void radv_CmdBindPipeline(
2295         VkCommandBuffer                             commandBuffer,
2296         VkPipelineBindPoint                         pipelineBindPoint,
2297         VkPipeline                                  _pipeline)
2298 {
2299         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2300         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2301
2302         switch (pipelineBindPoint) {
2303         case VK_PIPELINE_BIND_POINT_COMPUTE:
2304                 if (cmd_buffer->state.compute_pipeline == pipeline)
2305                         return;
2306                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2307
2308                 cmd_buffer->state.compute_pipeline = pipeline;
2309                 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2310                 break;
2311         case VK_PIPELINE_BIND_POINT_GRAPHICS:
2312                 if (cmd_buffer->state.pipeline == pipeline)
2313                         return;
2314                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2315
2316                 cmd_buffer->state.pipeline = pipeline;
2317                 if (!pipeline)
2318                         break;
2319
2320                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2321                 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2322
2323                 /* the new vertex shader might not have the same user regs */
2324                 cmd_buffer->state.last_first_instance = -1;
2325                 cmd_buffer->state.last_vertex_offset = -1;
2326
2327                 /* Prefetch all pipeline shaders at first draw time. */
2328                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2329
2330                 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2331
2332                 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2333                         cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2334                 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2335                         cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2336
2337                 if (radv_pipeline_has_tess(pipeline))
2338                         cmd_buffer->tess_rings_needed = true;
2339
2340                 if (radv_pipeline_has_gs(pipeline)) {
2341                         struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2342                                                                              AC_UD_SCRATCH_RING_OFFSETS);
2343                         if (cmd_buffer->ring_offsets_idx == -1)
2344                                 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2345                         else if (loc->sgpr_idx != -1)
2346                                 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2347                 }
2348                 break;
2349         default:
2350                 assert(!"invalid bind point");
2351                 break;
2352         }
2353 }
2354
2355 void radv_CmdSetViewport(
2356         VkCommandBuffer                             commandBuffer,
2357         uint32_t                                    firstViewport,
2358         uint32_t                                    viewportCount,
2359         const VkViewport*                           pViewports)
2360 {
2361         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2362         struct radv_cmd_state *state = &cmd_buffer->state;
2363         MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2364
2365         assert(firstViewport < MAX_VIEWPORTS);
2366         assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2367
2368         if (cmd_buffer->device->physical_device->has_scissor_bug) {
2369                 /* Try to skip unnecessary PS partial flushes when the viewports
2370                  * don't change.
2371                  */
2372                 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2373                                       RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2374                     !memcmp(state->dynamic.viewport.viewports + firstViewport,
2375                             pViewports, viewportCount * sizeof(*pViewports))) {
2376                         return;
2377                 }
2378         }
2379
2380         memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2381                viewportCount * sizeof(*pViewports));
2382
2383         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2384 }
2385
2386 void radv_CmdSetScissor(
2387         VkCommandBuffer                             commandBuffer,
2388         uint32_t                                    firstScissor,
2389         uint32_t                                    scissorCount,
2390         const VkRect2D*                             pScissors)
2391 {
2392         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2393         struct radv_cmd_state *state = &cmd_buffer->state;
2394         MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2395
2396         assert(firstScissor < MAX_SCISSORS);
2397         assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2398
2399         if (cmd_buffer->device->physical_device->has_scissor_bug) {
2400                 /* Try to skip unnecessary PS partial flushes when the scissors
2401                  * don't change.
2402                  */
2403                 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2404                                       RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2405                     !memcmp(state->dynamic.scissor.scissors + firstScissor,
2406                             pScissors, scissorCount * sizeof(*pScissors))) {
2407                         return;
2408                 }
2409         }
2410
2411         memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2412                scissorCount * sizeof(*pScissors));
2413
2414         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2415 }
2416
2417 void radv_CmdSetLineWidth(
2418         VkCommandBuffer                             commandBuffer,
2419         float                                       lineWidth)
2420 {
2421         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2422         cmd_buffer->state.dynamic.line_width = lineWidth;
2423         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2424 }
2425
2426 void radv_CmdSetDepthBias(
2427         VkCommandBuffer                             commandBuffer,
2428         float                                       depthBiasConstantFactor,
2429         float                                       depthBiasClamp,
2430         float                                       depthBiasSlopeFactor)
2431 {
2432         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2433
2434         cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2435         cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2436         cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2437
2438         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2439 }
2440
2441 void radv_CmdSetBlendConstants(
2442         VkCommandBuffer                             commandBuffer,
2443         const float                                 blendConstants[4])
2444 {
2445         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2446
2447         memcpy(cmd_buffer->state.dynamic.blend_constants,
2448                blendConstants, sizeof(float) * 4);
2449
2450         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2451 }
2452
2453 void radv_CmdSetDepthBounds(
2454         VkCommandBuffer                             commandBuffer,
2455         float                                       minDepthBounds,
2456         float                                       maxDepthBounds)
2457 {
2458         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2459
2460         cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2461         cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2462
2463         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2464 }
2465
2466 void radv_CmdSetStencilCompareMask(
2467         VkCommandBuffer                             commandBuffer,
2468         VkStencilFaceFlags                          faceMask,
2469         uint32_t                                    compareMask)
2470 {
2471         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2472
2473         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2474                 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2475         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2476                 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2477
2478         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2479 }
2480
2481 void radv_CmdSetStencilWriteMask(
2482         VkCommandBuffer                             commandBuffer,
2483         VkStencilFaceFlags                          faceMask,
2484         uint32_t                                    writeMask)
2485 {
2486         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2487
2488         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2489                 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2490         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2491                 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2492
2493         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2494 }
2495
2496 void radv_CmdSetStencilReference(
2497         VkCommandBuffer                             commandBuffer,
2498         VkStencilFaceFlags                          faceMask,
2499         uint32_t                                    reference)
2500 {
2501         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2502
2503         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2504                 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2505         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2506                 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2507
2508         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2509 }
2510
2511 void radv_CmdSetDiscardRectangleEXT(
2512         VkCommandBuffer                             commandBuffer,
2513         uint32_t                                    firstDiscardRectangle,
2514         uint32_t                                    discardRectangleCount,
2515         const VkRect2D*                             pDiscardRectangles)
2516 {
2517         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2518         struct radv_cmd_state *state = &cmd_buffer->state;
2519         MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2520
2521         assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2522         assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2523
2524         typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2525                      pDiscardRectangles, discardRectangleCount);
2526
2527         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2528 }
2529
2530 void radv_CmdExecuteCommands(
2531         VkCommandBuffer                             commandBuffer,
2532         uint32_t                                    commandBufferCount,
2533         const VkCommandBuffer*                      pCmdBuffers)
2534 {
2535         RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2536
2537         assert(commandBufferCount > 0);
2538
2539         /* Emit pending flushes on primary prior to executing secondary */
2540         si_emit_cache_flush(primary);
2541
2542         for (uint32_t i = 0; i < commandBufferCount; i++) {
2543                 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2544
2545                 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2546                                                     secondary->scratch_size_needed);
2547                 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2548                                                             secondary->compute_scratch_size_needed);
2549
2550                 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2551                         primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2552                 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2553                         primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2554                 if (secondary->tess_rings_needed)
2555                         primary->tess_rings_needed = true;
2556                 if (secondary->sample_positions_needed)
2557                         primary->sample_positions_needed = true;
2558
2559                 if (secondary->ring_offsets_idx != -1) {
2560                         if (primary->ring_offsets_idx == -1)
2561                                 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2562                         else
2563                                 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2564                 }
2565                 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2566
2567
2568                 /* When the secondary command buffer is compute only we don't
2569                  * need to re-emit the current graphics pipeline.
2570                  */
2571                 if (secondary->state.emitted_pipeline) {
2572                         primary->state.emitted_pipeline =
2573                                 secondary->state.emitted_pipeline;
2574                 }
2575
2576                 /* When the secondary command buffer is graphics only we don't
2577                  * need to re-emit the current compute pipeline.
2578                  */
2579                 if (secondary->state.emitted_compute_pipeline) {
2580                         primary->state.emitted_compute_pipeline =
2581                                 secondary->state.emitted_compute_pipeline;
2582                 }
2583
2584                 /* Only re-emit the draw packets when needed. */
2585                 if (secondary->state.last_primitive_reset_en != -1) {
2586                         primary->state.last_primitive_reset_en =
2587                                 secondary->state.last_primitive_reset_en;
2588                 }
2589
2590                 if (secondary->state.last_primitive_reset_index) {
2591                         primary->state.last_primitive_reset_index =
2592                                 secondary->state.last_primitive_reset_index;
2593                 }
2594
2595                 if (secondary->state.last_ia_multi_vgt_param) {
2596                         primary->state.last_ia_multi_vgt_param =
2597                                 secondary->state.last_ia_multi_vgt_param;
2598                 }
2599
2600                 if (secondary->state.last_first_instance != -1) {
2601                         primary->state.last_first_instance =
2602                                 secondary->state.last_first_instance;
2603                 }
2604
2605                 if (secondary->state.last_num_instances != -1) {
2606                         primary->state.last_num_instances =
2607                                 secondary->state.last_num_instances;
2608                 }
2609
2610                 if (secondary->state.last_vertex_offset != -1) {
2611                         primary->state.last_vertex_offset =
2612                                 secondary->state.last_vertex_offset;
2613                 }
2614
2615                 if (secondary->state.last_index_type != -1) {
2616                         primary->state.last_index_type =
2617                                 secondary->state.last_index_type;
2618                 }
2619         }
2620
2621         /* After executing commands from secondary buffers we have to dirty
2622          * some states.
2623          */
2624         primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2625                                 RADV_CMD_DIRTY_INDEX_BUFFER |
2626                                 RADV_CMD_DIRTY_DYNAMIC_ALL;
2627         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2628         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2629 }
2630
2631 VkResult radv_CreateCommandPool(
2632         VkDevice                                    _device,
2633         const VkCommandPoolCreateInfo*              pCreateInfo,
2634         const VkAllocationCallbacks*                pAllocator,
2635         VkCommandPool*                              pCmdPool)
2636 {
2637         RADV_FROM_HANDLE(radv_device, device, _device);
2638         struct radv_cmd_pool *pool;
2639
2640         pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2641                            VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2642         if (pool == NULL)
2643                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2644
2645         if (pAllocator)
2646                 pool->alloc = *pAllocator;
2647         else
2648                 pool->alloc = device->alloc;
2649
2650         list_inithead(&pool->cmd_buffers);
2651         list_inithead(&pool->free_cmd_buffers);
2652
2653         pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2654
2655         *pCmdPool = radv_cmd_pool_to_handle(pool);
2656
2657         return VK_SUCCESS;
2658
2659 }
2660
2661 void radv_DestroyCommandPool(
2662         VkDevice                                    _device,
2663         VkCommandPool                               commandPool,
2664         const VkAllocationCallbacks*                pAllocator)
2665 {
2666         RADV_FROM_HANDLE(radv_device, device, _device);
2667         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2668
2669         if (!pool)
2670                 return;
2671
2672         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2673                                  &pool->cmd_buffers, pool_link) {
2674                 radv_cmd_buffer_destroy(cmd_buffer);
2675         }
2676
2677         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2678                                  &pool->free_cmd_buffers, pool_link) {
2679                 radv_cmd_buffer_destroy(cmd_buffer);
2680         }
2681
2682         vk_free2(&device->alloc, pAllocator, pool);
2683 }
2684
2685 VkResult radv_ResetCommandPool(
2686         VkDevice                                    device,
2687         VkCommandPool                               commandPool,
2688         VkCommandPoolResetFlags                     flags)
2689 {
2690         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2691         VkResult result;
2692
2693         list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2694                             &pool->cmd_buffers, pool_link) {
2695                 result = radv_reset_cmd_buffer(cmd_buffer);
2696                 if (result != VK_SUCCESS)
2697                         return result;
2698         }
2699
2700         return VK_SUCCESS;
2701 }
2702
2703 void radv_TrimCommandPool(
2704     VkDevice                                    device,
2705     VkCommandPool                               commandPool,
2706     VkCommandPoolTrimFlagsKHR                   flags)
2707 {
2708         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2709
2710         if (!pool)
2711                 return;
2712
2713         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2714                                  &pool->free_cmd_buffers, pool_link) {
2715                 radv_cmd_buffer_destroy(cmd_buffer);
2716         }
2717 }
2718
2719 void radv_CmdBeginRenderPass(
2720         VkCommandBuffer                             commandBuffer,
2721         const VkRenderPassBeginInfo*                pRenderPassBegin,
2722         VkSubpassContents                           contents)
2723 {
2724         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2725         RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2726         RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2727
2728         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2729                                                            cmd_buffer->cs, 2048);
2730         MAYBE_UNUSED VkResult result;
2731
2732         cmd_buffer->state.framebuffer = framebuffer;
2733         cmd_buffer->state.pass = pass;
2734         cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2735
2736         result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2737         if (result != VK_SUCCESS)
2738                 return;
2739
2740         radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2741         assert(cmd_buffer->cs->cdw <= cdw_max);
2742
2743         radv_cmd_buffer_clear_subpass(cmd_buffer);
2744 }
2745
2746 void radv_CmdNextSubpass(
2747     VkCommandBuffer                             commandBuffer,
2748     VkSubpassContents                           contents)
2749 {
2750         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2751
2752         radv_cmd_buffer_resolve_subpass(cmd_buffer);
2753
2754         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2755                                               2048);
2756
2757         radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2758         radv_cmd_buffer_clear_subpass(cmd_buffer);
2759 }
2760
2761 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2762 {
2763         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2764         for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2765                 if (!pipeline->shaders[stage])
2766                         continue;
2767                 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2768                 if (loc->sgpr_idx == -1)
2769                         continue;
2770                 uint32_t base_reg = pipeline->user_data_0[stage];
2771                 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2772
2773         }
2774         if (pipeline->gs_copy_shader) {
2775                 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2776                 if (loc->sgpr_idx != -1) {
2777                         uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2778                         radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2779                 }
2780         }
2781 }
2782
2783 static void
2784 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2785                          uint32_t vertex_count)
2786 {
2787         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2788         radeon_emit(cmd_buffer->cs, vertex_count);
2789         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2790                                     S_0287F0_USE_OPAQUE(0));
2791 }
2792
2793 static void
2794 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2795                                  uint64_t index_va,
2796                                  uint32_t index_count)
2797 {
2798         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2799         radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2800         radeon_emit(cmd_buffer->cs, index_va);
2801         radeon_emit(cmd_buffer->cs, index_va >> 32);
2802         radeon_emit(cmd_buffer->cs, index_count);
2803         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2804 }
2805
2806 static void
2807 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2808                                   bool indexed,
2809                                   uint32_t draw_count,
2810                                   uint64_t count_va,
2811                                   uint32_t stride)
2812 {
2813         struct radeon_winsys_cs *cs = cmd_buffer->cs;
2814         unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2815                                       : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2816         bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
2817         uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2818         assert(base_reg);
2819
2820         /* just reset draw state for vertex data */
2821         cmd_buffer->state.last_first_instance = -1;
2822         cmd_buffer->state.last_num_instances = -1;
2823         cmd_buffer->state.last_vertex_offset = -1;
2824
2825         if (draw_count == 1 && !count_va && !draw_id_enable) {
2826                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2827                                      PKT3_DRAW_INDIRECT, 3, false));
2828                 radeon_emit(cs, 0);
2829                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2830                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2831                 radeon_emit(cs, di_src_sel);
2832         } else {
2833                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2834                                      PKT3_DRAW_INDIRECT_MULTI,
2835                                      8, false));
2836                 radeon_emit(cs, 0);
2837                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2838                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2839                 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2840                             S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2841                             S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2842                 radeon_emit(cs, draw_count); /* count */
2843                 radeon_emit(cs, count_va); /* count_addr */
2844                 radeon_emit(cs, count_va >> 32);
2845                 radeon_emit(cs, stride); /* stride */
2846                 radeon_emit(cs, di_src_sel);
2847         }
2848 }
2849
2850 struct radv_draw_info {
2851         /**
2852          * Number of vertices.
2853          */
2854         uint32_t count;
2855
2856         /**
2857          * Index of the first vertex.
2858          */
2859         int32_t vertex_offset;
2860
2861         /**
2862          * First instance id.
2863          */
2864         uint32_t first_instance;
2865
2866         /**
2867          * Number of instances.
2868          */
2869         uint32_t instance_count;
2870
2871         /**
2872          * First index (indexed draws only).
2873          */
2874         uint32_t first_index;
2875
2876         /**
2877          * Whether it's an indexed draw.
2878          */
2879         bool indexed;
2880
2881         /**
2882          * Indirect draw parameters resource.
2883          */
2884         struct radv_buffer *indirect;
2885         uint64_t indirect_offset;
2886         uint32_t stride;
2887
2888         /**
2889          * Draw count parameters resource.
2890          */
2891         struct radv_buffer *count_buffer;
2892         uint64_t count_buffer_offset;
2893 };
2894
2895 static void
2896 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
2897                        const struct radv_draw_info *info)
2898 {
2899         struct radv_cmd_state *state = &cmd_buffer->state;
2900         struct radeon_winsys *ws = cmd_buffer->device->ws;
2901         struct radeon_winsys_cs *cs = cmd_buffer->cs;
2902
2903         if (info->indirect) {
2904                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
2905                 uint64_t count_va = 0;
2906
2907                 va += info->indirect->offset + info->indirect_offset;
2908
2909                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
2910
2911                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
2912                 radeon_emit(cs, 1);
2913                 radeon_emit(cs, va);
2914                 radeon_emit(cs, va >> 32);
2915
2916                 if (info->count_buffer) {
2917                         count_va = radv_buffer_get_va(info->count_buffer->bo);
2918                         count_va += info->count_buffer->offset +
2919                                     info->count_buffer_offset;
2920
2921                         radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
2922                 }
2923
2924                 if (!state->subpass->view_mask) {
2925                         radv_cs_emit_indirect_draw_packet(cmd_buffer,
2926                                                           info->indexed,
2927                                                           info->count,
2928                                                           count_va,
2929                                                           info->stride);
2930                 } else {
2931                         unsigned i;
2932                         for_each_bit(i, state->subpass->view_mask) {
2933                                 radv_emit_view_index(cmd_buffer, i);
2934
2935                                 radv_cs_emit_indirect_draw_packet(cmd_buffer,
2936                                                                   info->indexed,
2937                                                                   info->count,
2938                                                                   count_va,
2939                                                                   info->stride);
2940                         }
2941                 }
2942         } else {
2943                 assert(state->pipeline->graphics.vtx_base_sgpr);
2944
2945                 if (info->vertex_offset != state->last_vertex_offset ||
2946                     info->first_instance != state->last_first_instance) {
2947                         radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
2948                                               state->pipeline->graphics.vtx_emit_num);
2949
2950                         radeon_emit(cs, info->vertex_offset);
2951                         radeon_emit(cs, info->first_instance);
2952                         if (state->pipeline->graphics.vtx_emit_num == 3)
2953                                 radeon_emit(cs, 0);
2954                         state->last_first_instance = info->first_instance;
2955                         state->last_vertex_offset = info->vertex_offset;
2956                 }
2957
2958                 if (state->last_num_instances != info->instance_count) {
2959                         radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, state->predicating));
2960                         radeon_emit(cs, info->instance_count);
2961                         state->last_num_instances = info->instance_count;
2962                 }
2963
2964                 if (info->indexed) {
2965                         int index_size = state->index_type ? 4 : 2;
2966                         uint64_t index_va;
2967
2968                         index_va = state->index_va;
2969                         index_va += info->first_index * index_size;
2970
2971                         if (!state->subpass->view_mask) {
2972                                 radv_cs_emit_draw_indexed_packet(cmd_buffer,
2973                                                                  index_va,
2974                                                                  info->count);
2975                         } else {
2976                                 unsigned i;
2977                                 for_each_bit(i, state->subpass->view_mask) {
2978                                         radv_emit_view_index(cmd_buffer, i);
2979
2980                                         radv_cs_emit_draw_indexed_packet(cmd_buffer,
2981                                                                          index_va,
2982                                                                          info->count);
2983                                 }
2984                         }
2985                 } else {
2986                         if (!state->subpass->view_mask) {
2987                                 radv_cs_emit_draw_packet(cmd_buffer, info->count);
2988                         } else {
2989                                 unsigned i;
2990                                 for_each_bit(i, state->subpass->view_mask) {
2991                                         radv_emit_view_index(cmd_buffer, i);
2992
2993                                         radv_cs_emit_draw_packet(cmd_buffer,
2994                                                                  info->count);
2995                                 }
2996                         }
2997                 }
2998         }
2999 }
3000
3001 static void
3002 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3003                               const struct radv_draw_info *info)
3004 {
3005         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3006                 radv_emit_graphics_pipeline(cmd_buffer);
3007
3008         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3009                 radv_emit_framebuffer_state(cmd_buffer);
3010
3011         if (info->indexed) {
3012                 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3013                         radv_emit_index_buffer(cmd_buffer);
3014         } else {
3015                 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3016                  * so the state must be re-emitted before the next indexed
3017                  * draw.
3018                  */
3019                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3020                         cmd_buffer->state.last_index_type = -1;
3021                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3022                 }
3023         }
3024
3025         radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3026
3027         radv_emit_draw_registers(cmd_buffer, info->indexed,
3028                                  info->instance_count > 1, info->indirect,
3029                                  info->indirect ? 0 : info->count);
3030 }
3031
3032 static void
3033 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3034           const struct radv_draw_info *info)
3035 {
3036         bool has_prefetch =
3037                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3038         bool pipeline_is_dirty =
3039                 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3040                 cmd_buffer->state.pipeline &&
3041                 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3042
3043         MAYBE_UNUSED unsigned cdw_max =
3044                 radeon_check_space(cmd_buffer->device->ws,
3045                                    cmd_buffer->cs, 4096);
3046
3047         /* Use optimal packet order based on whether we need to sync the
3048          * pipeline.
3049          */
3050         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3051                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3052                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3053                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3054                 /* If we have to wait for idle, set all states first, so that
3055                  * all SET packets are processed in parallel with previous draw
3056                  * calls. Then upload descriptors, set shader pointers, and
3057                  * draw, and prefetch at the end. This ensures that the time
3058                  * the CUs are idle is very short. (there are only SET_SH
3059                  * packets between the wait and the draw)
3060                  */
3061                 radv_emit_all_graphics_states(cmd_buffer, info);
3062                 si_emit_cache_flush(cmd_buffer);
3063                 /* <-- CUs are idle here --> */
3064
3065                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3066
3067                 radv_emit_draw_packets(cmd_buffer, info);
3068                 /* <-- CUs are busy here --> */
3069
3070                 /* Start prefetches after the draw has been started. Both will
3071                  * run in parallel, but starting the draw first is more
3072                  * important.
3073                  */
3074                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3075                         radv_emit_prefetch_L2(cmd_buffer,
3076                                               cmd_buffer->state.pipeline, false);
3077                 }
3078         } else {
3079                 /* If we don't wait for idle, start prefetches first, then set
3080                  * states, and draw at the end.
3081                  */
3082                 si_emit_cache_flush(cmd_buffer);
3083
3084                 if (cmd_buffer->state.prefetch_L2_mask) {
3085                         /* Only prefetch the vertex shader and VBO descriptors
3086                          * in order to start the draw as soon as possible.
3087                          */
3088                         radv_emit_prefetch_L2(cmd_buffer,
3089                                               cmd_buffer->state.pipeline, true);
3090                 }
3091
3092                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3093
3094                 radv_emit_all_graphics_states(cmd_buffer, info);
3095                 radv_emit_draw_packets(cmd_buffer, info);
3096
3097                 /* Prefetch the remaining shaders after the draw has been
3098                  * started.
3099                  */
3100                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3101                         radv_emit_prefetch_L2(cmd_buffer,
3102                                               cmd_buffer->state.pipeline, false);
3103                 }
3104         }
3105
3106         assert(cmd_buffer->cs->cdw <= cdw_max);
3107         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3108 }
3109
3110 void radv_CmdDraw(
3111         VkCommandBuffer                             commandBuffer,
3112         uint32_t                                    vertexCount,
3113         uint32_t                                    instanceCount,
3114         uint32_t                                    firstVertex,
3115         uint32_t                                    firstInstance)
3116 {
3117         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3118         struct radv_draw_info info = {};
3119
3120         info.count = vertexCount;
3121         info.instance_count = instanceCount;
3122         info.first_instance = firstInstance;
3123         info.vertex_offset = firstVertex;
3124
3125         radv_draw(cmd_buffer, &info);
3126 }
3127
3128 void radv_CmdDrawIndexed(
3129         VkCommandBuffer                             commandBuffer,
3130         uint32_t                                    indexCount,
3131         uint32_t                                    instanceCount,
3132         uint32_t                                    firstIndex,
3133         int32_t                                     vertexOffset,
3134         uint32_t                                    firstInstance)
3135 {
3136         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3137         struct radv_draw_info info = {};
3138
3139         info.indexed = true;
3140         info.count = indexCount;
3141         info.instance_count = instanceCount;
3142         info.first_index = firstIndex;
3143         info.vertex_offset = vertexOffset;
3144         info.first_instance = firstInstance;
3145
3146         radv_draw(cmd_buffer, &info);
3147 }
3148
3149 void radv_CmdDrawIndirect(
3150         VkCommandBuffer                             commandBuffer,
3151         VkBuffer                                    _buffer,
3152         VkDeviceSize                                offset,
3153         uint32_t                                    drawCount,
3154         uint32_t                                    stride)
3155 {
3156         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3157         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3158         struct radv_draw_info info = {};
3159
3160         info.count = drawCount;
3161         info.indirect = buffer;
3162         info.indirect_offset = offset;
3163         info.stride = stride;
3164
3165         radv_draw(cmd_buffer, &info);
3166 }
3167
3168 void radv_CmdDrawIndexedIndirect(
3169         VkCommandBuffer                             commandBuffer,
3170         VkBuffer                                    _buffer,
3171         VkDeviceSize                                offset,
3172         uint32_t                                    drawCount,
3173         uint32_t                                    stride)
3174 {
3175         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3176         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3177         struct radv_draw_info info = {};
3178
3179         info.indexed = true;
3180         info.count = drawCount;
3181         info.indirect = buffer;
3182         info.indirect_offset = offset;
3183         info.stride = stride;
3184
3185         radv_draw(cmd_buffer, &info);
3186 }
3187
3188 void radv_CmdDrawIndirectCountAMD(
3189         VkCommandBuffer                             commandBuffer,
3190         VkBuffer                                    _buffer,
3191         VkDeviceSize                                offset,
3192         VkBuffer                                    _countBuffer,
3193         VkDeviceSize                                countBufferOffset,
3194         uint32_t                                    maxDrawCount,
3195         uint32_t                                    stride)
3196 {
3197         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3198         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3199         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3200         struct radv_draw_info info = {};
3201
3202         info.count = maxDrawCount;
3203         info.indirect = buffer;
3204         info.indirect_offset = offset;
3205         info.count_buffer = count_buffer;
3206         info.count_buffer_offset = countBufferOffset;
3207         info.stride = stride;
3208
3209         radv_draw(cmd_buffer, &info);
3210 }
3211
3212 void radv_CmdDrawIndexedIndirectCountAMD(
3213         VkCommandBuffer                             commandBuffer,
3214         VkBuffer                                    _buffer,
3215         VkDeviceSize                                offset,
3216         VkBuffer                                    _countBuffer,
3217         VkDeviceSize                                countBufferOffset,
3218         uint32_t                                    maxDrawCount,
3219         uint32_t                                    stride)
3220 {
3221         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3222         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3223         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3224         struct radv_draw_info info = {};
3225
3226         info.indexed = true;
3227         info.count = maxDrawCount;
3228         info.indirect = buffer;
3229         info.indirect_offset = offset;
3230         info.count_buffer = count_buffer;
3231         info.count_buffer_offset = countBufferOffset;
3232         info.stride = stride;
3233
3234         radv_draw(cmd_buffer, &info);
3235 }
3236
3237 struct radv_dispatch_info {
3238         /**
3239          * Determine the layout of the grid (in block units) to be used.
3240          */
3241         uint32_t blocks[3];
3242
3243         /**
3244          * A starting offset for the grid. If unaligned is set, the offset
3245          * must still be aligned.
3246          */
3247         uint32_t offsets[3];
3248         /**
3249          * Whether it's an unaligned compute dispatch.
3250          */
3251         bool unaligned;
3252
3253         /**
3254          * Indirect compute parameters resource.
3255          */
3256         struct radv_buffer *indirect;
3257         uint64_t indirect_offset;
3258 };
3259
3260 static void
3261 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3262                            const struct radv_dispatch_info *info)
3263 {
3264         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3265         struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3266         unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3267         struct radeon_winsys *ws = cmd_buffer->device->ws;
3268         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3269         struct radv_userdata_info *loc;
3270
3271         loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3272                                     AC_UD_CS_GRID_SIZE);
3273
3274         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3275
3276         if (info->indirect) {
3277                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3278
3279                 va += info->indirect->offset + info->indirect_offset;
3280
3281                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3282
3283                 if (loc->sgpr_idx != -1) {
3284                         for (unsigned i = 0; i < 3; ++i) {
3285                                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3286                                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3287                                                 COPY_DATA_DST_SEL(COPY_DATA_REG));
3288                                 radeon_emit(cs, (va +  4 * i));
3289                                 radeon_emit(cs, (va + 4 * i) >> 32);
3290                                 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3291                                                  + loc->sgpr_idx * 4) >> 2) + i);
3292                                 radeon_emit(cs, 0);
3293                         }
3294                 }
3295
3296                 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3297                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3298                                         PKT3_SHADER_TYPE_S(1));
3299                         radeon_emit(cs, va);
3300                         radeon_emit(cs, va >> 32);
3301                         radeon_emit(cs, dispatch_initiator);
3302                 } else {
3303                         radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3304                                         PKT3_SHADER_TYPE_S(1));
3305                         radeon_emit(cs, 1);
3306                         radeon_emit(cs, va);
3307                         radeon_emit(cs, va >> 32);
3308
3309                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3310                                         PKT3_SHADER_TYPE_S(1));
3311                         radeon_emit(cs, 0);
3312                         radeon_emit(cs, dispatch_initiator);
3313                 }
3314         } else {
3315                 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3316                 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3317
3318                 if (info->unaligned) {
3319                         unsigned *cs_block_size = compute_shader->info.cs.block_size;
3320                         unsigned remainder[3];
3321
3322                         /* If aligned, these should be an entire block size,
3323                          * not 0.
3324                          */
3325                         remainder[0] = blocks[0] + cs_block_size[0] -
3326                                        align_u32_npot(blocks[0], cs_block_size[0]);
3327                         remainder[1] = blocks[1] + cs_block_size[1] -
3328                                        align_u32_npot(blocks[1], cs_block_size[1]);
3329                         remainder[2] = blocks[2] + cs_block_size[2] -
3330                                        align_u32_npot(blocks[2], cs_block_size[2]);
3331
3332                         blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3333                         blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3334                         blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3335
3336                         for(unsigned i = 0; i < 3; ++i) {
3337                                 assert(offsets[i] % cs_block_size[i] == 0);
3338                                 offsets[i] /= cs_block_size[i];
3339                         }
3340
3341                         radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3342                         radeon_emit(cs,
3343                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3344                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3345                         radeon_emit(cs,
3346                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3347                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3348                         radeon_emit(cs,
3349                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3350                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3351
3352                         dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3353                 }
3354
3355                 if (loc->sgpr_idx != -1) {
3356                         assert(!loc->indirect);
3357                         assert(loc->num_sgprs == 3);
3358
3359                         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3360                                                   loc->sgpr_idx * 4, 3);
3361                         radeon_emit(cs, blocks[0]);
3362                         radeon_emit(cs, blocks[1]);
3363                         radeon_emit(cs, blocks[2]);
3364                 }
3365
3366                 if (offsets[0] || offsets[1] || offsets[2]) {
3367                         radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3368                         radeon_emit(cs, offsets[0]);
3369                         radeon_emit(cs, offsets[1]);
3370                         radeon_emit(cs, offsets[2]);
3371
3372                         /* The blocks in the packet are not counts but end values. */
3373                         for (unsigned i = 0; i < 3; ++i)
3374                                 blocks[i] += offsets[i];
3375                 } else {
3376                         dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3377                 }
3378
3379                 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3380                                 PKT3_SHADER_TYPE_S(1));
3381                 radeon_emit(cs, blocks[0]);
3382                 radeon_emit(cs, blocks[1]);
3383                 radeon_emit(cs, blocks[2]);
3384                 radeon_emit(cs, dispatch_initiator);
3385         }
3386
3387         assert(cmd_buffer->cs->cdw <= cdw_max);
3388 }
3389
3390 static void
3391 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3392 {
3393         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3394         radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline,
3395                              VK_SHADER_STAGE_COMPUTE_BIT);
3396 }
3397
3398 static void
3399 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3400               const struct radv_dispatch_info *info)
3401 {
3402         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3403         bool has_prefetch =
3404                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3405         bool pipeline_is_dirty = pipeline &&
3406                                  pipeline != cmd_buffer->state.emitted_compute_pipeline;
3407
3408         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3409                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3410                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3411                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3412                 /* If we have to wait for idle, set all states first, so that
3413                  * all SET packets are processed in parallel with previous draw
3414                  * calls. Then upload descriptors, set shader pointers, and
3415                  * dispatch, and prefetch at the end. This ensures that the
3416                  * time the CUs are idle is very short. (there are only SET_SH
3417                  * packets between the wait and the draw)
3418                  */
3419                 radv_emit_compute_pipeline(cmd_buffer);
3420                 si_emit_cache_flush(cmd_buffer);
3421                 /* <-- CUs are idle here --> */
3422
3423                 radv_upload_compute_shader_descriptors(cmd_buffer);
3424
3425                 radv_emit_dispatch_packets(cmd_buffer, info);
3426                 /* <-- CUs are busy here --> */
3427
3428                 /* Start prefetches after the dispatch has been started. Both
3429                  * will run in parallel, but starting the dispatch first is
3430                  * more important.
3431                  */
3432                 if (has_prefetch && pipeline_is_dirty) {
3433                         radv_emit_shader_prefetch(cmd_buffer,
3434                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3435                 }
3436         } else {
3437                 /* If we don't wait for idle, start prefetches first, then set
3438                  * states, and dispatch at the end.
3439                  */
3440                 si_emit_cache_flush(cmd_buffer);
3441
3442                 if (has_prefetch && pipeline_is_dirty) {
3443                         radv_emit_shader_prefetch(cmd_buffer,
3444                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3445                 }
3446
3447                 radv_upload_compute_shader_descriptors(cmd_buffer);
3448
3449                 radv_emit_compute_pipeline(cmd_buffer);
3450                 radv_emit_dispatch_packets(cmd_buffer, info);
3451         }
3452
3453         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3454 }
3455
3456 void radv_CmdDispatchBase(
3457         VkCommandBuffer                             commandBuffer,
3458         uint32_t                                    base_x,
3459         uint32_t                                    base_y,
3460         uint32_t                                    base_z,
3461         uint32_t                                    x,
3462         uint32_t                                    y,
3463         uint32_t                                    z)
3464 {
3465         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3466         struct radv_dispatch_info info = {};
3467
3468         info.blocks[0] = x;
3469         info.blocks[1] = y;
3470         info.blocks[2] = z;
3471
3472         info.offsets[0] = base_x;
3473         info.offsets[1] = base_y;
3474         info.offsets[2] = base_z;
3475         radv_dispatch(cmd_buffer, &info);
3476 }
3477
3478 void radv_CmdDispatch(
3479         VkCommandBuffer                             commandBuffer,
3480         uint32_t                                    x,
3481         uint32_t                                    y,
3482         uint32_t                                    z)
3483 {
3484         radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3485 }
3486
3487 void radv_CmdDispatchIndirect(
3488         VkCommandBuffer                             commandBuffer,
3489         VkBuffer                                    _buffer,
3490         VkDeviceSize                                offset)
3491 {
3492         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3493         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3494         struct radv_dispatch_info info = {};
3495
3496         info.indirect = buffer;
3497         info.indirect_offset = offset;
3498
3499         radv_dispatch(cmd_buffer, &info);
3500 }
3501
3502 void radv_unaligned_dispatch(
3503         struct radv_cmd_buffer                      *cmd_buffer,
3504         uint32_t                                    x,
3505         uint32_t                                    y,
3506         uint32_t                                    z)
3507 {
3508         struct radv_dispatch_info info = {};
3509
3510         info.blocks[0] = x;
3511         info.blocks[1] = y;
3512         info.blocks[2] = z;
3513         info.unaligned = 1;
3514
3515         radv_dispatch(cmd_buffer, &info);
3516 }
3517
3518 void radv_CmdEndRenderPass(
3519         VkCommandBuffer                             commandBuffer)
3520 {
3521         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3522
3523         radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3524
3525         radv_cmd_buffer_resolve_subpass(cmd_buffer);
3526
3527         for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3528                 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3529                 radv_handle_subpass_image_transition(cmd_buffer,
3530                                       (VkAttachmentReference){i, layout});
3531         }
3532
3533         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3534
3535         cmd_buffer->state.pass = NULL;
3536         cmd_buffer->state.subpass = NULL;
3537         cmd_buffer->state.attachments = NULL;
3538         cmd_buffer->state.framebuffer = NULL;
3539 }
3540
3541 /*
3542  * For HTILE we have the following interesting clear words:
3543  *   0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3544  *   0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3545  *   0xfffffff0: Clear depth to 1.0
3546  *   0x00000000: Clear depth to 0.0
3547  */
3548 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3549                                   struct radv_image *image,
3550                                   const VkImageSubresourceRange *range,
3551                                   uint32_t clear_word)
3552 {
3553         assert(range->baseMipLevel == 0);
3554         assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3555         unsigned layer_count = radv_get_layerCount(image, range);
3556         uint64_t size = image->surface.htile_slice_size * layer_count;
3557         uint64_t offset = image->offset + image->htile_offset +
3558                           image->surface.htile_slice_size * range->baseArrayLayer;
3559         struct radv_cmd_state *state = &cmd_buffer->state;
3560
3561         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3562                              RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3563
3564         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3565                                               size, clear_word);
3566
3567         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3568 }
3569
3570 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3571                                                struct radv_image *image,
3572                                                VkImageLayout src_layout,
3573                                                VkImageLayout dst_layout,
3574                                                unsigned src_queue_mask,
3575                                                unsigned dst_queue_mask,
3576                                                const VkImageSubresourceRange *range,
3577                                                VkImageAspectFlags pending_clears)
3578 {
3579         if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3580             (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3581             cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3582             cmd_buffer->state.render_area.extent.width == image->info.width &&
3583             cmd_buffer->state.render_area.extent.height == image->info.height) {
3584                 /* The clear will initialize htile. */
3585                 return;
3586         } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3587                    radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3588                 /* TODO: merge with the clear if applicable */
3589                 radv_initialize_htile(cmd_buffer, image, range, 0);
3590         } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3591                    radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3592                 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3593                 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3594         } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3595                    !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3596                 VkImageSubresourceRange local_range = *range;
3597                 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3598                 local_range.baseMipLevel = 0;
3599                 local_range.levelCount = 1;
3600
3601                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3602                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3603
3604                 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3605
3606                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3607                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3608         }
3609 }
3610
3611 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3612                            struct radv_image *image, uint32_t value)
3613 {
3614         struct radv_cmd_state *state = &cmd_buffer->state;
3615
3616         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3617                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3618
3619         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3620                                               image->offset + image->cmask.offset,
3621                                               image->cmask.size, value);
3622
3623         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3624 }
3625
3626 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3627                                                struct radv_image *image,
3628                                                VkImageLayout src_layout,
3629                                                VkImageLayout dst_layout,
3630                                                unsigned src_queue_mask,
3631                                                unsigned dst_queue_mask,
3632                                                const VkImageSubresourceRange *range)
3633 {
3634         if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3635                 if (image->fmask.size)
3636                         radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3637                 else
3638                         radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3639         } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3640                    !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3641                 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3642         }
3643 }
3644
3645 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3646                          struct radv_image *image, uint32_t value)
3647 {
3648         struct radv_cmd_state *state = &cmd_buffer->state;
3649
3650         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3651                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3652
3653         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
3654                                               image->offset + image->dcc_offset,
3655                                               image->surface.dcc_size, value);
3656
3657         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3658                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3659 }
3660
3661 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3662                                              struct radv_image *image,
3663                                              VkImageLayout src_layout,
3664                                              VkImageLayout dst_layout,
3665                                              unsigned src_queue_mask,
3666                                              unsigned dst_queue_mask,
3667                                              const VkImageSubresourceRange *range)
3668 {
3669         if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
3670                 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
3671         } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3672                 radv_initialize_dcc(cmd_buffer, image,
3673                                     radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask) ?
3674                                          0x20202020u : 0xffffffffu);
3675         } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
3676                    !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
3677                 radv_decompress_dcc(cmd_buffer, image, range);
3678         } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3679                    !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3680                 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3681         }
3682 }
3683
3684 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3685                                          struct radv_image *image,
3686                                          VkImageLayout src_layout,
3687                                          VkImageLayout dst_layout,
3688                                          uint32_t src_family,
3689                                          uint32_t dst_family,
3690                                          const VkImageSubresourceRange *range,
3691                                          VkImageAspectFlags pending_clears)
3692 {
3693         if (image->exclusive && src_family != dst_family) {
3694                 /* This is an acquire or a release operation and there will be
3695                  * a corresponding release/acquire. Do the transition in the
3696                  * most flexible queue. */
3697
3698                 assert(src_family == cmd_buffer->queue_family_index ||
3699                        dst_family == cmd_buffer->queue_family_index);
3700
3701                 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3702                         return;
3703
3704                 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3705                     (src_family == RADV_QUEUE_GENERAL ||
3706                      dst_family == RADV_QUEUE_GENERAL))
3707                         return;
3708         }
3709
3710         unsigned src_queue_mask = radv_image_queue_family_mask(image, src_family, cmd_buffer->queue_family_index);
3711         unsigned dst_queue_mask = radv_image_queue_family_mask(image, dst_family, cmd_buffer->queue_family_index);
3712
3713         if (image->surface.htile_size)
3714                 radv_handle_depth_image_transition(cmd_buffer, image, src_layout,
3715                                                    dst_layout, src_queue_mask,
3716                                                    dst_queue_mask, range,
3717                                                    pending_clears);
3718
3719         if (image->cmask.size || image->fmask.size)
3720                 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3721                                                    dst_layout, src_queue_mask,
3722                                                    dst_queue_mask, range);
3723
3724         if (image->surface.dcc_size)
3725                 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3726                                                  dst_layout, src_queue_mask,
3727                                                  dst_queue_mask, range);
3728 }
3729
3730 void radv_CmdPipelineBarrier(
3731         VkCommandBuffer                             commandBuffer,
3732         VkPipelineStageFlags                        srcStageMask,
3733         VkPipelineStageFlags                        destStageMask,
3734         VkBool32                                    byRegion,
3735         uint32_t                                    memoryBarrierCount,
3736         const VkMemoryBarrier*                      pMemoryBarriers,
3737         uint32_t                                    bufferMemoryBarrierCount,
3738         const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
3739         uint32_t                                    imageMemoryBarrierCount,
3740         const VkImageMemoryBarrier*                 pImageMemoryBarriers)
3741 {
3742         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3743         enum radv_cmd_flush_bits src_flush_bits = 0;
3744         enum radv_cmd_flush_bits dst_flush_bits = 0;
3745
3746         for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3747                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3748                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3749                                                         NULL);
3750         }
3751
3752         for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3753                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3754                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3755                                                         NULL);
3756         }
3757
3758         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3759                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3760                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3761                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3762                                                         image);
3763         }
3764
3765         radv_stage_flush(cmd_buffer, srcStageMask);
3766         cmd_buffer->state.flush_bits |= src_flush_bits;
3767
3768         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3769                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3770                 radv_handle_image_transition(cmd_buffer, image,
3771                                              pImageMemoryBarriers[i].oldLayout,
3772                                              pImageMemoryBarriers[i].newLayout,
3773                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
3774                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
3775                                              &pImageMemoryBarriers[i].subresourceRange,
3776                                              0);
3777         }
3778
3779         cmd_buffer->state.flush_bits |= dst_flush_bits;
3780 }
3781
3782
3783 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3784                         struct radv_event *event,
3785                         VkPipelineStageFlags stageMask,
3786                         unsigned value)
3787 {
3788         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3789         uint64_t va = radv_buffer_get_va(event->bo);
3790
3791         radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3792
3793         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3794
3795         /* TODO: this is overkill. Probably should figure something out from
3796          * the stage mask. */
3797
3798         si_cs_emit_write_event_eop(cs,
3799                                    cmd_buffer->state.predicating,
3800                                    cmd_buffer->device->physical_device->rad_info.chip_class,
3801                                    radv_cmd_buffer_uses_mec(cmd_buffer),
3802                                    V_028A90_BOTTOM_OF_PIPE_TS, 0,
3803                                    1, va, 2, value);
3804
3805         assert(cmd_buffer->cs->cdw <= cdw_max);
3806 }
3807
3808 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3809                       VkEvent _event,
3810                       VkPipelineStageFlags stageMask)
3811 {
3812         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3813         RADV_FROM_HANDLE(radv_event, event, _event);
3814
3815         write_event(cmd_buffer, event, stageMask, 1);
3816 }
3817
3818 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3819                         VkEvent _event,
3820                         VkPipelineStageFlags stageMask)
3821 {
3822         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3823         RADV_FROM_HANDLE(radv_event, event, _event);
3824
3825         write_event(cmd_buffer, event, stageMask, 0);
3826 }
3827
3828 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3829                         uint32_t eventCount,
3830                         const VkEvent* pEvents,
3831                         VkPipelineStageFlags srcStageMask,
3832                         VkPipelineStageFlags dstStageMask,
3833                         uint32_t memoryBarrierCount,
3834                         const VkMemoryBarrier* pMemoryBarriers,
3835                         uint32_t bufferMemoryBarrierCount,
3836                         const VkBufferMemoryBarrier* pBufferMemoryBarriers,
3837                         uint32_t imageMemoryBarrierCount,
3838                         const VkImageMemoryBarrier* pImageMemoryBarriers)
3839 {
3840         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3841         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3842
3843         for (unsigned i = 0; i < eventCount; ++i) {
3844                 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
3845                 uint64_t va = radv_buffer_get_va(event->bo);
3846
3847                 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3848
3849                 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
3850
3851                 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
3852                 assert(cmd_buffer->cs->cdw <= cdw_max);
3853         }
3854
3855
3856         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3857                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3858
3859                 radv_handle_image_transition(cmd_buffer, image,
3860                                              pImageMemoryBarriers[i].oldLayout,
3861                                              pImageMemoryBarriers[i].newLayout,
3862                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
3863                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
3864                                              &pImageMemoryBarriers[i].subresourceRange,
3865                                              0);
3866         }
3867
3868         /* TODO: figure out how to do memory barriers without waiting */
3869         cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
3870                                         RADV_CMD_FLAG_INV_GLOBAL_L2 |
3871                                         RADV_CMD_FLAG_INV_VMEM_L1 |
3872                                         RADV_CMD_FLAG_INV_SMEM_L1;
3873 }
3874
3875
3876 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
3877                            uint32_t deviceMask)
3878 {
3879    /* No-op */
3880 }