src/amd/vulkan/radv_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "radv_private.h"
  29 #include "radv_radeon_winsys.h"
  30 #include "radv_shader.h"
  31 #include "radv_cs.h"
  32 #include "sid.h"
  33 #include "gfx9d.h"
  34 #include "vk_format.h"
  35 #include "radv_debug.h"
  36 #include "radv_meta.h"
  37
  38 #include "ac_debug.h"
  39
  40 enum {
  41         RADV_PREFETCH_VBO_DESCRIPTORS   = (1 << 0),
  42         RADV_PREFETCH_VS                = (1 << 1),
  43         RADV_PREFETCH_TCS               = (1 << 2),
  44         RADV_PREFETCH_TES               = (1 << 3),
  45         RADV_PREFETCH_GS                = (1 << 4),
  46         RADV_PREFETCH_PS                = (1 << 5),
  47         RADV_PREFETCH_SHADERS           = (RADV_PREFETCH_VS  |
  48                                            RADV_PREFETCH_TCS |
  49                                            RADV_PREFETCH_TES |
  50                                            RADV_PREFETCH_GS  |
  51                                            RADV_PREFETCH_PS)
  52 };
  53
  54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
  55                                          struct radv_image *image,
  56                                          VkImageLayout src_layout,
  57                                          VkImageLayout dst_layout,
  58                                          uint32_t src_family,
  59                                          uint32_t dst_family,
  60                                          const VkImageSubresourceRange *range,
  61                                          VkImageAspectFlags pending_clears);
  62
  63 const struct radv_dynamic_state default_dynamic_state = {
  64         .viewport = {
  65                 .count = 0,
  66         },
  67         .scissor = {
  68                 .count = 0,
  69         },
  70         .line_width = 1.0f,
  71         .depth_bias = {
  72                 .bias = 0.0f,
  73                 .clamp = 0.0f,
  74                 .slope = 0.0f,
  75         },
  76         .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
  77         .depth_bounds = {
  78                 .min = 0.0f,
  79                 .max = 1.0f,
  80         },
  81         .stencil_compare_mask = {
  82                 .front = ~0u,
  83                 .back = ~0u,
  84         },
  85         .stencil_write_mask = {
  86                 .front = ~0u,
  87                 .back = ~0u,
  88         },
  89         .stencil_reference = {
  90                 .front = 0u,
  91                 .back = 0u,
  92         },
  93 };
  94
  95 static void
  96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
  97                         const struct radv_dynamic_state *src)
  98 {
  99         struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
 100         uint32_t copy_mask = src->mask;
 101         uint32_t dest_mask = 0;
 102
 103         /* Make sure to copy the number of viewports/scissors because they can
 104          * only be specified at pipeline creation time.
 105          */
 106         dest->viewport.count = src->viewport.count;
 107         dest->scissor.count = src->scissor.count;
 108         dest->discard_rectangle.count = src->discard_rectangle.count;
 109
 110         if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
 111                 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
 112                            src->viewport.count * sizeof(VkViewport))) {
 113                         typed_memcpy(dest->viewport.viewports,
 114                                      src->viewport.viewports,
 115                                      src->viewport.count);
 116                         dest_mask |= RADV_DYNAMIC_VIEWPORT;
 117                 }
 118         }
 119
 120         if (copy_mask & RADV_DYNAMIC_SCISSOR) {
 121                 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
 122                            src->scissor.count * sizeof(VkRect2D))) {
 123                         typed_memcpy(dest->scissor.scissors,
 124                                      src->scissor.scissors, src->scissor.count);
 125                         dest_mask |= RADV_DYNAMIC_SCISSOR;
 126                 }
 127         }
 128
 129         if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
 130                 if (dest->line_width != src->line_width) {
 131                         dest->line_width = src->line_width;
 132                         dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
 133                 }
 134         }
 135
 136         if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
 137                 if (memcmp(&dest->depth_bias, &src->depth_bias,
 138                            sizeof(src->depth_bias))) {
 139                         dest->depth_bias = src->depth_bias;
 140                         dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
 141                 }
 142         }
 143
 144         if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
 145                 if (memcmp(&dest->blend_constants, &src->blend_constants,
 146                            sizeof(src->blend_constants))) {
 147                         typed_memcpy(dest->blend_constants,
 148                                      src->blend_constants, 4);
 149                         dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
 150                 }
 151         }
 152
 153         if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
 154                 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
 155                            sizeof(src->depth_bounds))) {
 156                         dest->depth_bounds = src->depth_bounds;
 157                         dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
 158                 }
 159         }
 160
 161         if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
 162                 if (memcmp(&dest->stencil_compare_mask,
 163                            &src->stencil_compare_mask,
 164                            sizeof(src->stencil_compare_mask))) {
 165                         dest->stencil_compare_mask = src->stencil_compare_mask;
 166                         dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
 167                 }
 168         }
 169
 170         if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
 171                 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
 172                            sizeof(src->stencil_write_mask))) {
 173                         dest->stencil_write_mask = src->stencil_write_mask;
 174                         dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
 175                 }
 176         }
 177
 178         if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
 179                 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
 180                            sizeof(src->stencil_reference))) {
 181                         dest->stencil_reference = src->stencil_reference;
 182                         dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
 183                 }
 184         }
 185
 186         if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
 187                 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
 188                            src->discard_rectangle.count * sizeof(VkRect2D))) {
 189                         typed_memcpy(dest->discard_rectangle.rectangles,
 190                                      src->discard_rectangle.rectangles,
 191                                      src->discard_rectangle.count);
 192                         dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
 193                 }
 194         }
 195
 196         cmd_buffer->state.dirty |= dest_mask;
 197 }
 198
 199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
 200 {
 201         return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
 202                cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
 203 }
 204
 205 enum ring_type radv_queue_family_to_ring(int f) {
 206         switch (f) {
 207         case RADV_QUEUE_GENERAL:
 208                 return RING_GFX;
 209         case RADV_QUEUE_COMPUTE:
 210                 return RING_COMPUTE;
 211         case RADV_QUEUE_TRANSFER:
 212                 return RING_DMA;
 213         default:
 214                 unreachable("Unknown queue family");
 215         }
 216 }
 217
 218 static VkResult radv_create_cmd_buffer(
 219         struct radv_device *                         device,
 220         struct radv_cmd_pool *                       pool,
 221         VkCommandBufferLevel                        level,
 222         VkCommandBuffer*                            pCommandBuffer)
 223 {
 224         struct radv_cmd_buffer *cmd_buffer;
 225         unsigned ring;
 226         cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
 227                                VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 228         if (cmd_buffer == NULL)
 229                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 230
 231         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
 232         cmd_buffer->device = device;
 233         cmd_buffer->pool = pool;
 234         cmd_buffer->level = level;
 235
 236         if (pool) {
 237                 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
 238                 cmd_buffer->queue_family_index = pool->queue_family_index;
 239
 240         } else {
 241                 /* Init the pool_link so we can safely call list_del when we destroy
 242                  * the command buffer
 243                  */
 244                 list_inithead(&cmd_buffer->pool_link);
 245                 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
 246         }
 247
 248         ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
 249
 250         cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
 251         if (!cmd_buffer->cs) {
 252                 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 253                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
 254         }
 255
 256         *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
 257
 258         list_inithead(&cmd_buffer->upload.list);
 259
 260         return VK_SUCCESS;
 261 }
 262
 263 static void
 264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
 265 {
 266         list_del(&cmd_buffer->pool_link);
 267
 268         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 269                                  &cmd_buffer->upload.list, list) {
 270                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 271                 list_del(&up->list);
 272                 free(up);
 273         }
 274
 275         if (cmd_buffer->upload.upload_bo)
 276                 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
 277         cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
 278
 279         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
 280                 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
 281
 282         vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 283 }
 284
 285 static VkResult
 286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 287 {
 288
 289         cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
 290
 291         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 292                                  &cmd_buffer->upload.list, list) {
 293                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 294                 list_del(&up->list);
 295                 free(up);
 296         }
 297
 298         cmd_buffer->push_constant_stages = 0;
 299         cmd_buffer->scratch_size_needed = 0;
 300         cmd_buffer->compute_scratch_size_needed = 0;
 301         cmd_buffer->esgs_ring_size_needed = 0;
 302         cmd_buffer->gsvs_ring_size_needed = 0;
 303         cmd_buffer->tess_rings_needed = false;
 304         cmd_buffer->sample_positions_needed = false;
 305
 306         if (cmd_buffer->upload.upload_bo)
 307                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 308                                    cmd_buffer->upload.upload_bo, 8);
 309         cmd_buffer->upload.offset = 0;
 310
 311         cmd_buffer->record_result = VK_SUCCESS;
 312
 313         cmd_buffer->ring_offsets_idx = -1;
 314
 315         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
 316                 cmd_buffer->descriptors[i].dirty = 0;
 317                 cmd_buffer->descriptors[i].valid = 0;
 318                 cmd_buffer->descriptors[i].push_dirty = false;
 319         }
 320
 321         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 322                 void *fence_ptr;
 323                 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
 324                                              &cmd_buffer->gfx9_fence_offset,
 325                                              &fence_ptr);
 326                 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
 327         }
 328
 329         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
 330
 331         return cmd_buffer->record_result;
 332 }
 333
 334 static bool
 335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
 336                                   uint64_t min_needed)
 337 {
 338         uint64_t new_size;
 339         struct radeon_winsys_bo *bo;
 340         struct radv_cmd_buffer_upload *upload;
 341         struct radv_device *device = cmd_buffer->device;
 342
 343         new_size = MAX2(min_needed, 16 * 1024);
 344         new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
 345
 346         bo = device->ws->buffer_create(device->ws,
 347                                        new_size, 4096,
 348                                        RADEON_DOMAIN_GTT,
 349                                        RADEON_FLAG_CPU_ACCESS|
 350                                        RADEON_FLAG_NO_INTERPROCESS_SHARING |
 351                                        RADEON_FLAG_32BIT);
 352
 353         if (!bo) {
 354                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 355                 return false;
 356         }
 357
 358         radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
 359         if (cmd_buffer->upload.upload_bo) {
 360                 upload = malloc(sizeof(*upload));
 361
 362                 if (!upload) {
 363                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
 364                         device->ws->buffer_destroy(bo);
 365                         return false;
 366                 }
 367
 368                 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
 369                 list_add(&upload->list, &cmd_buffer->upload.list);
 370         }
 371
 372         cmd_buffer->upload.upload_bo = bo;
 373         cmd_buffer->upload.size = new_size;
 374         cmd_buffer->upload.offset = 0;
 375         cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
 376
 377         if (!cmd_buffer->upload.map) {
 378                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 379                 return false;
 380         }
 381
 382         return true;
 383 }
 384
 385 bool
 386 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
 387                              unsigned size,
 388                              unsigned alignment,
 389                              unsigned *out_offset,
 390                              void **ptr)
 391 {
 392         uint64_t offset = align(cmd_buffer->upload.offset, alignment);
 393         if (offset + size > cmd_buffer->upload.size) {
 394                 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
 395                         return false;
 396                 offset = 0;
 397         }
 398
 399         *out_offset = offset;
 400         *ptr = cmd_buffer->upload.map + offset;
 401
 402         cmd_buffer->upload.offset = offset + size;
 403         return true;
 404 }
 405
 406 bool
 407 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
 408                             unsigned size, unsigned alignment,
 409                             const void *data, unsigned *out_offset)
 410 {
 411         uint8_t *ptr;
 412
 413         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
 414                                           out_offset, (void **)&ptr))
 415                 return false;
 416
 417         if (ptr)
 418                 memcpy(ptr, data, size);
 419
 420         return true;
 421 }
 422
 423 static void
 424 radv_emit_write_data_packet(struct radeon_cmdbuf *cs, uint64_t va,
 425                             unsigned count, const uint32_t *data)
 426 {
 427         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
 428         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
 429                     S_370_WR_CONFIRM(1) |
 430                     S_370_ENGINE_SEL(V_370_ME));
 431         radeon_emit(cs, va);
 432         radeon_emit(cs, va >> 32);
 433         radeon_emit_array(cs, data, count);
 434 }
 435
 436 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
 437 {
 438         struct radv_device *device = cmd_buffer->device;
 439         struct radeon_cmdbuf *cs = cmd_buffer->cs;
 440         uint64_t va;
 441
 442         va = radv_buffer_get_va(device->trace_bo);
 443         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
 444                 va += 4;
 445
 446         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
 447
 448         ++cmd_buffer->state.trace_id;
 449         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 450         radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
 451         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
 452         radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
 453 }
 454
 455 static void
 456 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
 457                            enum radv_cmd_flush_bits flags)
 458 {
 459         if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
 460                 uint32_t *ptr = NULL;
 461                 uint64_t va = 0;
 462
 463                 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
 464                                 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
 465
 466                 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
 467                         va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
 468                              cmd_buffer->gfx9_fence_offset;
 469                         ptr = &cmd_buffer->gfx9_fence_idx;
 470                 }
 471
 472                 /* Force wait for graphics or compute engines to be idle. */
 473                 si_cs_emit_cache_flush(cmd_buffer->cs,
 474                                        cmd_buffer->device->physical_device->rad_info.chip_class,
 475                                        ptr, va,
 476                                        radv_cmd_buffer_uses_mec(cmd_buffer),
 477                                        flags);
 478         }
 479
 480         if (unlikely(cmd_buffer->device->trace_bo))
 481                 radv_cmd_buffer_trace_emit(cmd_buffer);
 482 }
 483
 484 static void
 485 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
 486                    struct radv_pipeline *pipeline, enum ring_type ring)
 487 {
 488         struct radv_device *device = cmd_buffer->device;
 489         struct radeon_cmdbuf *cs = cmd_buffer->cs;
 490         uint32_t data[2];
 491         uint64_t va;
 492
 493         va = radv_buffer_get_va(device->trace_bo);
 494
 495         switch (ring) {
 496         case RING_GFX:
 497                 va += 8;
 498                 break;
 499         case RING_COMPUTE:
 500                 va += 16;
 501                 break;
 502         default:
 503                 assert(!"invalid ring type");
 504         }
 505
 506         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 507                                                            cmd_buffer->cs, 6);
 508
 509         data[0] = (uintptr_t)pipeline;
 510         data[1] = (uintptr_t)pipeline >> 32;
 511
 512         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 513         radv_emit_write_data_packet(cs, va, 2, data);
 514 }
 515
 516 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 517                              VkPipelineBindPoint bind_point,
 518                              struct radv_descriptor_set *set,
 519                              unsigned idx)
 520 {
 521         struct radv_descriptor_state *descriptors_state =
 522                 radv_get_descriptors_state(cmd_buffer, bind_point);
 523
 524         descriptors_state->sets[idx] = set;
 525         if (set)
 526                 descriptors_state->valid |= (1u << idx);
 527         else
 528                 descriptors_state->valid &= ~(1u << idx);
 529         descriptors_state->dirty |= (1u << idx);
 530 }
 531
 532 static void
 533 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
 534                       VkPipelineBindPoint bind_point)
 535 {
 536         struct radv_descriptor_state *descriptors_state =
 537                 radv_get_descriptors_state(cmd_buffer, bind_point);
 538         struct radv_device *device = cmd_buffer->device;
 539         struct radeon_cmdbuf *cs = cmd_buffer->cs;
 540         uint32_t data[MAX_SETS * 2] = {};
 541         uint64_t va;
 542         unsigned i;
 543         va = radv_buffer_get_va(device->trace_bo) + 24;
 544
 545         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 546                                                            cmd_buffer->cs, 4 + MAX_SETS * 2);
 547
 548         for_each_bit(i, descriptors_state->valid) {
 549                 struct radv_descriptor_set *set = descriptors_state->sets[i];
 550                 data[i * 2] = (uintptr_t)set;
 551                 data[i * 2 + 1] = (uintptr_t)set >> 32;
 552         }
 553
 554         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 555         radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
 556 }
 557
 558 struct radv_userdata_info *
 559 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
 560                       gl_shader_stage stage,
 561                       int idx)
 562 {
 563         struct radv_shader_variant *shader = radv_get_shader(pipeline, stage);
 564         return &shader->info.user_sgprs_locs.shader_data[idx];
 565 }
 566
 567 static void
 568 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
 569                            struct radv_pipeline *pipeline,
 570                            gl_shader_stage stage,
 571                            int idx, uint64_t va)
 572 {
 573         struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
 574         uint32_t base_reg = pipeline->user_data_0[stage];
 575         if (loc->sgpr_idx == -1)
 576                 return;
 577
 578         assert(loc->num_sgprs == (HAVE_32BIT_POINTERS ? 1 : 2));
 579         assert(!loc->indirect);
 580
 581         radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,
 582                                  base_reg + loc->sgpr_idx * 4, va, false);
 583 }
 584
 585 static void
 586 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer,
 587                               struct radv_pipeline *pipeline,
 588                               struct radv_descriptor_state *descriptors_state,
 589                               gl_shader_stage stage)
 590 {
 591         struct radv_device *device = cmd_buffer->device;
 592         struct radeon_cmdbuf *cs = cmd_buffer->cs;
 593         uint32_t sh_base = pipeline->user_data_0[stage];
 594         struct radv_userdata_locations *locs =
 595                 &pipeline->shaders[stage]->info.user_sgprs_locs;
 596         unsigned mask;
 597
 598         mask = descriptors_state->dirty & descriptors_state->valid;
 599
 600         for (int i = 0; i < MAX_SETS; i++) {
 601                 struct radv_userdata_info *loc = &locs->descriptor_sets[i];
 602                 if (loc->sgpr_idx != -1 && !loc->indirect)
 603                         continue;
 604                 mask &= ~(1 << i);
 605         }
 606
 607         while (mask) {
 608                 int start, count;
 609
 610                 u_bit_scan_consecutive_range(&mask, &start, &count);
 611
 612                 struct radv_userdata_info *loc = &locs->descriptor_sets[start];
 613                 unsigned sh_offset = sh_base + loc->sgpr_idx * 4;
 614
 615                 radv_emit_shader_pointer_head(cs, sh_offset, count,
 616                                               HAVE_32BIT_POINTERS);
 617                 for (int i = 0; i < count; i++) {
 618                         struct radv_descriptor_set *set =
 619                                 descriptors_state->sets[start + i];
 620
 621                         radv_emit_shader_pointer_body(device, cs, set->va,
 622                                                       HAVE_32BIT_POINTERS);
 623                 }
 624         }
 625 }
 626
 627 static void
 628 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
 629                               struct radv_pipeline *pipeline)
 630 {
 631         int num_samples = pipeline->graphics.ms.num_samples;
 632         struct radv_multisample_state *ms = &pipeline->graphics.ms;
 633         struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
 634
 635         if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
 636                 cmd_buffer->sample_positions_needed = true;
 637
 638         if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
 639                 return;
 640
 641         radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
 642         radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
 643         radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
 644
 645         radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
 646
 647         radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
 648
 649         /* GFX9: Flush DFSM when the AA mode changes. */
 650         if (cmd_buffer->device->dfsm_allowed) {
 651                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 652                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
 653         }
 654 }
 655
 656 static void
 657 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
 658                           struct radv_shader_variant *shader)
 659 {
 660         uint64_t va;
 661
 662         if (!shader)
 663                 return;
 664
 665         va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 666
 667         si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
 668 }
 669
 670 static void
 671 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
 672                       struct radv_pipeline *pipeline,
 673                       bool vertex_stage_only)
 674 {
 675         struct radv_cmd_state *state = &cmd_buffer->state;
 676         uint32_t mask = state->prefetch_L2_mask;
 677
 678         if (vertex_stage_only) {
 679                 /* Fast prefetch path for starting draws as soon as possible.
 680                  */
 681                 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
 682                                                   RADV_PREFETCH_VBO_DESCRIPTORS);
 683         }
 684
 685         if (mask & RADV_PREFETCH_VS)
 686                 radv_emit_shader_prefetch(cmd_buffer,
 687                                           pipeline->shaders[MESA_SHADER_VERTEX]);
 688
 689         if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
 690                 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
 691
 692         if (mask & RADV_PREFETCH_TCS)
 693                 radv_emit_shader_prefetch(cmd_buffer,
 694                                           pipeline->shaders[MESA_SHADER_TESS_CTRL]);
 695
 696         if (mask & RADV_PREFETCH_TES)
 697                 radv_emit_shader_prefetch(cmd_buffer,
 698                                           pipeline->shaders[MESA_SHADER_TESS_EVAL]);
 699
 700         if (mask & RADV_PREFETCH_GS) {
 701                 radv_emit_shader_prefetch(cmd_buffer,
 702                                           pipeline->shaders[MESA_SHADER_GEOMETRY]);
 703                 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
 704         }
 705
 706         if (mask & RADV_PREFETCH_PS)
 707                 radv_emit_shader_prefetch(cmd_buffer,
 708                                           pipeline->shaders[MESA_SHADER_FRAGMENT]);
 709
 710         state->prefetch_L2_mask &= ~mask;
 711 }
 712
 713 static void
 714 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
 715 {
 716         if (!cmd_buffer->device->physical_device->rbplus_allowed)
 717                 return;
 718
 719         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 720         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
 721         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 722
 723         unsigned sx_ps_downconvert = 0;
 724         unsigned sx_blend_opt_epsilon = 0;
 725         unsigned sx_blend_opt_control = 0;
 726
 727         for (unsigned i = 0; i < subpass->color_count; ++i) {
 728                 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
 729                         continue;
 730
 731                 int idx = subpass->color_attachments[i].attachment;
 732                 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
 733
 734                 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
 735                 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
 736                 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
 737                 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
 738
 739                 bool has_alpha, has_rgb;
 740
 741                 /* Set if RGB and A are present. */
 742                 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
 743
 744                 if (format == V_028C70_COLOR_8 ||
 745                     format == V_028C70_COLOR_16 ||
 746                     format == V_028C70_COLOR_32)
 747                         has_rgb = !has_alpha;
 748                 else
 749                         has_rgb = true;
 750
 751                 /* Check the colormask and export format. */
 752                 if (!(colormask & 0x7))
 753                         has_rgb = false;
 754                 if (!(colormask & 0x8))
 755                         has_alpha = false;
 756
 757                 if (spi_format == V_028714_SPI_SHADER_ZERO) {
 758                         has_rgb = false;
 759                         has_alpha = false;
 760                 }
 761
 762                 /* Disable value checking for disabled channels. */
 763                 if (!has_rgb)
 764                         sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 765                 if (!has_alpha)
 766                         sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 767
 768                 /* Enable down-conversion for 32bpp and smaller formats. */
 769                 switch (format) {
 770                 case V_028C70_COLOR_8:
 771                 case V_028C70_COLOR_8_8:
 772                 case V_028C70_COLOR_8_8_8_8:
 773                         /* For 1 and 2-channel formats, use the superset thereof. */
 774                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
 775                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 776                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 777                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
 778                                 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
 779                         }
 780                         break;
 781
 782                 case V_028C70_COLOR_5_6_5:
 783                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 784                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
 785                                 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
 786                         }
 787                         break;
 788
 789                 case V_028C70_COLOR_1_5_5_5:
 790                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 791                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
 792                                 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
 793                         }
 794                         break;
 795
 796                 case V_028C70_COLOR_4_4_4_4:
 797                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 798                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
 799                                 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
 800                         }
 801                         break;
 802
 803                 case V_028C70_COLOR_32:
 804                         if (swap == V_028C70_SWAP_STD &&
 805                             spi_format == V_028714_SPI_SHADER_32_R)
 806                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
 807                         else if (swap == V_028C70_SWAP_ALT_REV &&
 808                                  spi_format == V_028714_SPI_SHADER_32_AR)
 809                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
 810                         break;
 811
 812                 case V_028C70_COLOR_16:
 813                 case V_028C70_COLOR_16_16:
 814                         /* For 1-channel formats, use the superset thereof. */
 815                         if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
 816                             spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
 817                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 818                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 819                                 if (swap == V_028C70_SWAP_STD ||
 820                                     swap == V_028C70_SWAP_STD_REV)
 821                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
 822                                 else
 823                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
 824                         }
 825                         break;
 826
 827                 case V_028C70_COLOR_10_11_11:
 828                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 829                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
 830                                 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
 831                         }
 832                         break;
 833
 834                 case V_028C70_COLOR_2_10_10_10:
 835                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 836                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
 837                                 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
 838                         }
 839                         break;
 840                 }
 841         }
 842
 843         radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
 844         radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
 845         radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
 846         radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
 847 }
 848
 849 static void
 850 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
 851 {
 852         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 853
 854         if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
 855                 return;
 856
 857         radv_update_multisample_state(cmd_buffer, pipeline);
 858
 859         cmd_buffer->scratch_size_needed =
 860                                   MAX2(cmd_buffer->scratch_size_needed,
 861                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
 862
 863         if (!cmd_buffer->state.emitted_pipeline ||
 864             cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
 865              pipeline->graphics.can_use_guardband)
 866                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
 867
 868         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
 869
 870         for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
 871                 if (!pipeline->shaders[i])
 872                         continue;
 873
 874                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 875                                    pipeline->shaders[i]->bo, 8);
 876         }
 877
 878         if (radv_pipeline_has_gs(pipeline))
 879                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 880                                    pipeline->gs_copy_shader->bo, 8);
 881
 882         if (unlikely(cmd_buffer->device->trace_bo))
 883                 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
 884
 885         cmd_buffer->state.emitted_pipeline = pipeline;
 886
 887         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
 888 }
 889
 890 static void
 891 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
 892 {
 893         si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
 894                           cmd_buffer->state.dynamic.viewport.viewports);
 895 }
 896
 897 static void
 898 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
 899 {
 900         uint32_t count = cmd_buffer->state.dynamic.scissor.count;
 901
 902         si_write_scissors(cmd_buffer->cs, 0, count,
 903                           cmd_buffer->state.dynamic.scissor.scissors,
 904                           cmd_buffer->state.dynamic.viewport.viewports,
 905                           cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
 906 }
 907
 908 static void
 909 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
 910 {
 911         if (!cmd_buffer->state.dynamic.discard_rectangle.count)
 912                 return;
 913
 914         radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
 915                                    cmd_buffer->state.dynamic.discard_rectangle.count * 2);
 916         for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
 917                 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
 918                 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
 919                 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
 920                                             S_028214_BR_Y(rect.offset.y + rect.extent.height));
 921         }
 922 }
 923
 924 static void
 925 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
 926 {
 927         unsigned width = cmd_buffer->state.dynamic.line_width * 8;
 928
 929         radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
 930                                S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
 931 }
 932
 933 static void
 934 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
 935 {
 936         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 937
 938         radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
 939         radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
 940 }
 941
 942 static void
 943 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
 944 {
 945         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 946
 947         radeon_set_context_reg_seq(cmd_buffer->cs,
 948                                    R_028430_DB_STENCILREFMASK, 2);
 949         radeon_emit(cmd_buffer->cs,
 950                     S_028430_STENCILTESTVAL(d->stencil_reference.front) |
 951                     S_028430_STENCILMASK(d->stencil_compare_mask.front) |
 952                     S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
 953                     S_028430_STENCILOPVAL(1));
 954         radeon_emit(cmd_buffer->cs,
 955                     S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
 956                     S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
 957                     S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
 958                     S_028434_STENCILOPVAL_BF(1));
 959 }
 960
 961 static void
 962 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
 963 {
 964         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 965
 966         radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
 967                                fui(d->depth_bounds.min));
 968         radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
 969                                fui(d->depth_bounds.max));
 970 }
 971
 972 static void
 973 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
 974 {
 975         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 976         unsigned slope = fui(d->depth_bias.slope * 16.0f);
 977         unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
 978
 979
 980         radeon_set_context_reg_seq(cmd_buffer->cs,
 981                                    R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
 982         radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
 983         radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
 984         radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
 985         radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
 986         radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
 987 }
 988
 989 static void
 990 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
 991                          int index,
 992                          struct radv_attachment_info *att,
 993                          struct radv_image *image,
 994                          VkImageLayout layout)
 995 {
 996         bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
 997         struct radv_color_buffer_info *cb = &att->cb;
 998         uint32_t cb_color_info = cb->cb_color_info;
 999
1000         if (!radv_layout_dcc_compressed(image, layout,
1001                                         radv_image_queue_family_mask(image,
1002                                                                      cmd_buffer->queue_family_index,
1003                                                                      cmd_buffer->queue_family_index))) {
1004                 cb_color_info &= C_028C70_DCC_ENABLE;
1005         }
1006
1007         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1008                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1009                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1010                 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
1011                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
1012                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1013                 radeon_emit(cmd_buffer->cs, cb_color_info);
1014                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1015                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1016                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1017                 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
1018                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1019                 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
1020
1021                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
1022                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
1023                 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1024
1025                 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1026                                        S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1027         } else {
1028                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1029                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1030                 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1031                 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1032                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1033                 radeon_emit(cmd_buffer->cs, cb_color_info);
1034                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1035                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1036                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1037                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1038                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1039                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1040
1041                 if (is_vi) { /* DCC BASE */
1042                         radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1043                 }
1044         }
1045 }
1046
1047 static void
1048 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer,
1049                              struct radv_ds_buffer_info *ds,
1050                              struct radv_image *image, VkImageLayout layout,
1051                              bool requires_cond_write)
1052 {
1053         uint32_t db_z_info = ds->db_z_info;
1054         uint32_t db_z_info_reg;
1055
1056         if (!radv_image_is_tc_compat_htile(image))
1057                 return;
1058
1059         if (!radv_layout_has_htile(image, layout,
1060                                    radv_image_queue_family_mask(image,
1061                                                                 cmd_buffer->queue_family_index,
1062                                                                 cmd_buffer->queue_family_index))) {
1063                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1064         }
1065
1066         db_z_info &= C_028040_ZRANGE_PRECISION;
1067
1068         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1069                 db_z_info_reg = R_028038_DB_Z_INFO;
1070         } else {
1071                 db_z_info_reg = R_028040_DB_Z_INFO;
1072         }
1073
1074         /* When we don't know the last fast clear value we need to emit a
1075          * conditional packet, otherwise we can update DB_Z_INFO directly.
1076          */
1077         if (requires_cond_write) {
1078                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_WRITE, 7, 0));
1079
1080                 const uint32_t write_space = 0 << 8;    /* register */
1081                 const uint32_t poll_space = 1 << 4;     /* memory */
1082                 const uint32_t function = 3 << 0;       /* equal to the reference */
1083                 const uint32_t options = write_space | poll_space | function;
1084                 radeon_emit(cmd_buffer->cs, options);
1085
1086                 /* poll address - location of the depth clear value */
1087                 uint64_t va = radv_buffer_get_va(image->bo);
1088                 va += image->offset + image->clear_value_offset;
1089
1090                 /* In presence of stencil format, we have to adjust the base
1091                  * address because the first value is the stencil clear value.
1092                  */
1093                 if (vk_format_is_stencil(image->vk_format))
1094                         va += 4;
1095
1096                 radeon_emit(cmd_buffer->cs, va);
1097                 radeon_emit(cmd_buffer->cs, va >> 32);
1098
1099                 radeon_emit(cmd_buffer->cs, fui(0.0f));          /* reference value */
1100                 radeon_emit(cmd_buffer->cs, (uint32_t)-1);       /* comparison mask */
1101                 radeon_emit(cmd_buffer->cs, db_z_info_reg >> 2); /* write address low */
1102                 radeon_emit(cmd_buffer->cs, 0u);                 /* write address high */
1103                 radeon_emit(cmd_buffer->cs, db_z_info);
1104         } else {
1105                 radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);
1106         }
1107 }
1108
1109 static void
1110 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1111                       struct radv_ds_buffer_info *ds,
1112                       struct radv_image *image,
1113                       VkImageLayout layout)
1114 {
1115         uint32_t db_z_info = ds->db_z_info;
1116         uint32_t db_stencil_info = ds->db_stencil_info;
1117
1118         if (!radv_layout_has_htile(image, layout,
1119                                    radv_image_queue_family_mask(image,
1120                                                                 cmd_buffer->queue_family_index,
1121                                                                 cmd_buffer->queue_family_index))) {
1122                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1123                 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1124         }
1125
1126         radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1127         radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1128
1129
1130         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1131                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1132                 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1133                 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1134                 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1135
1136                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1137                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* DB_Z_INFO */
1138                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* DB_STENCIL_INFO */
1139                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* DB_Z_READ_BASE */
1140                 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32));        /* DB_Z_READ_BASE_HI */
1141                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* DB_STENCIL_READ_BASE */
1142                 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1143                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* DB_Z_WRITE_BASE */
1144                 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32));       /* DB_Z_WRITE_BASE_HI */
1145                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1146                 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1147
1148                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1149                 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1150                 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1151         } else {
1152                 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1153
1154                 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1155                 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1156                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* R_028040_DB_Z_INFO */
1157                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* R_028044_DB_STENCIL_INFO */
1158                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* R_028048_DB_Z_READ_BASE */
1159                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* R_02804C_DB_STENCIL_READ_BASE */
1160                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* R_028050_DB_Z_WRITE_BASE */
1161                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1162                 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1163                 radeon_emit(cmd_buffer->cs, ds->db_depth_slice);        /* R_02805C_DB_DEPTH_SLICE */
1164
1165         }
1166
1167         /* Update the ZRANGE_PRECISION value for the TC-compat bug. */
1168         radv_update_zrange_precision(cmd_buffer, ds, image, layout, true);
1169
1170         radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1171                                ds->pa_su_poly_offset_db_fmt_cntl);
1172 }
1173
1174 /**
1175  * Update the fast clear depth/stencil values if the image is bound as a
1176  * depth/stencil buffer.
1177  */
1178 static void
1179 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,
1180                                 struct radv_image *image,
1181                                 VkClearDepthStencilValue ds_clear_value,
1182                                 VkImageAspectFlags aspects)
1183 {
1184         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1185         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1186         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1187         struct radv_attachment_info *att;
1188         uint32_t att_idx;
1189
1190         if (!framebuffer || !subpass)
1191                 return;
1192
1193         att_idx = subpass->depth_stencil_attachment.attachment;
1194         if (att_idx == VK_ATTACHMENT_UNUSED)
1195                 return;
1196
1197         att = &framebuffer->attachments[att_idx];
1198         if (att->attachment->image != image)
1199                 return;
1200
1201         radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
1202         radeon_emit(cs, ds_clear_value.stencil);
1203         radeon_emit(cs, fui(ds_clear_value.depth));
1204
1205         /* Update the ZRANGE_PRECISION value for the TC-compat bug. This is
1206          * only needed when clearing Z to 0.0.
1207          */
1208         if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1209             ds_clear_value.depth == 0.0) {
1210                 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1211
1212                 radv_update_zrange_precision(cmd_buffer, &att->ds, image,
1213                                              layout, false);
1214         }
1215 }
1216
1217 /**
1218  * Set the clear depth/stencil values to the image's metadata.
1219  */
1220 void
1221 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1222                            struct radv_image *image,
1223                            VkClearDepthStencilValue ds_clear_value,
1224                            VkImageAspectFlags aspects)
1225 {
1226         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1227         uint64_t va = radv_buffer_get_va(image->bo);
1228         unsigned reg_offset = 0, reg_count = 0;
1229
1230         va += image->offset + image->clear_value_offset;
1231
1232         assert(radv_image_has_htile(image));
1233
1234         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1235                 ++reg_count;
1236         } else {
1237                 ++reg_offset;
1238                 va += 4;
1239         }
1240         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1241                 ++reg_count;
1242
1243         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1244         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1245                         S_370_WR_CONFIRM(1) |
1246                         S_370_ENGINE_SEL(V_370_PFP));
1247         radeon_emit(cs, va);
1248         radeon_emit(cs, va >> 32);
1249         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1250                 radeon_emit(cs, ds_clear_value.stencil);
1251         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1252                 radeon_emit(cs, fui(ds_clear_value.depth));
1253
1254         radv_update_bound_fast_clear_ds(cmd_buffer, image, ds_clear_value,
1255                                         aspects);
1256 }
1257
1258 /**
1259  * Load the clear depth/stencil values from the image's metadata.
1260  */
1261 static void
1262 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1263                             struct radv_image *image)
1264 {
1265         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1266         VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1267         uint64_t va = radv_buffer_get_va(image->bo);
1268         unsigned reg_offset = 0, reg_count = 0;
1269
1270         va += image->offset + image->clear_value_offset;
1271
1272         if (!radv_image_has_htile(image))
1273                 return;
1274
1275         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1276                 ++reg_count;
1277         } else {
1278                 ++reg_offset;
1279                 va += 4;
1280         }
1281         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1282                 ++reg_count;
1283
1284         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
1285         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1286                         COPY_DATA_DST_SEL(COPY_DATA_REG) |
1287                         (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1288         radeon_emit(cs, va);
1289         radeon_emit(cs, va >> 32);
1290         radeon_emit(cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1291         radeon_emit(cs, 0);
1292
1293         radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1294         radeon_emit(cs, 0);
1295 }
1296
1297 /*
1298  * With DCC some colors don't require CMASK elimination before being
1299  * used as a texture. This sets a predicate value to determine if the
1300  * cmask eliminate is required.
1301  */
1302 void
1303 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1304                                   struct radv_image *image,
1305                                   bool value)
1306 {
1307         uint64_t pred_val = value;
1308         uint64_t va = radv_buffer_get_va(image->bo);
1309         va += image->offset + image->dcc_pred_offset;
1310
1311         assert(radv_image_has_dcc(image));
1312
1313         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1314         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1315                                     S_370_WR_CONFIRM(1) |
1316                                     S_370_ENGINE_SEL(V_370_PFP));
1317         radeon_emit(cmd_buffer->cs, va);
1318         radeon_emit(cmd_buffer->cs, va >> 32);
1319         radeon_emit(cmd_buffer->cs, pred_val);
1320         radeon_emit(cmd_buffer->cs, pred_val >> 32);
1321 }
1322
1323 /**
1324  * Update the fast clear color values if the image is bound as a color buffer.
1325  */
1326 static void
1327 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer,
1328                                    struct radv_image *image,
1329                                    int cb_idx,
1330                                    uint32_t color_values[2])
1331 {
1332         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1333         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1334         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1335         struct radv_attachment_info *att;
1336         uint32_t att_idx;
1337
1338         if (!framebuffer || !subpass)
1339                 return;
1340
1341         att_idx = subpass->color_attachments[cb_idx].attachment;
1342         if (att_idx == VK_ATTACHMENT_UNUSED)
1343                 return;
1344
1345         att = &framebuffer->attachments[att_idx];
1346         if (att->attachment->image != image)
1347                 return;
1348
1349         radeon_set_context_reg_seq(cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c, 2);
1350         radeon_emit(cs, color_values[0]);
1351         radeon_emit(cs, color_values[1]);
1352 }
1353
1354 /**
1355  * Set the clear color values to the image's metadata.
1356  */
1357 void
1358 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1359                               struct radv_image *image,
1360                               int cb_idx,
1361                               uint32_t color_values[2])
1362 {
1363         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1364         uint64_t va = radv_buffer_get_va(image->bo);
1365
1366         va += image->offset + image->clear_value_offset;
1367
1368         assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1369
1370         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1371         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1372                         S_370_WR_CONFIRM(1) |
1373                         S_370_ENGINE_SEL(V_370_PFP));
1374         radeon_emit(cs, va);
1375         radeon_emit(cs, va >> 32);
1376         radeon_emit(cs, color_values[0]);
1377         radeon_emit(cs, color_values[1]);
1378
1379         radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx,
1380                                            color_values);
1381 }
1382
1383 /**
1384  * Load the clear color values from the image's metadata.
1385  */
1386 static void
1387 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
1388                                struct radv_image *image,
1389                                int cb_idx)
1390 {
1391         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1392         uint64_t va = radv_buffer_get_va(image->bo);
1393
1394         va += image->offset + image->clear_value_offset;
1395
1396         if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1397                 return;
1398
1399         uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
1400
1401         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1402         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1403                         COPY_DATA_DST_SEL(COPY_DATA_REG) |
1404                         COPY_DATA_COUNT_SEL);
1405         radeon_emit(cs, va);
1406         radeon_emit(cs, va >> 32);
1407         radeon_emit(cs, reg >> 2);
1408         radeon_emit(cs, 0);
1409
1410         radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1411         radeon_emit(cs, 0);
1412 }
1413
1414 static void
1415 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1416 {
1417         int i;
1418         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1419         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1420
1421         /* this may happen for inherited secondary recording */
1422         if (!framebuffer)
1423                 return;
1424
1425         for (i = 0; i < 8; ++i) {
1426                 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1427                         radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1428                                        S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1429                         continue;
1430                 }
1431
1432                 int idx = subpass->color_attachments[i].attachment;
1433                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1434                 struct radv_image *image = att->attachment->image;
1435                 VkImageLayout layout = subpass->color_attachments[i].layout;
1436
1437                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1438
1439                 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1440                 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1441
1442                 radv_load_color_clear_metadata(cmd_buffer, image, i);
1443         }
1444
1445         if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1446                 int idx = subpass->depth_stencil_attachment.attachment;
1447                 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1448                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1449                 struct radv_image *image = att->attachment->image;
1450                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1451                 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1452                                                                                 cmd_buffer->queue_family_index,
1453                                                                                 cmd_buffer->queue_family_index);
1454                 /* We currently don't support writing decompressed HTILE */
1455                 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1456                        radv_layout_is_htile_compressed(image, layout, queue_mask));
1457
1458                 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1459
1460                 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1461                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1462                         cmd_buffer->state.offset_scale = att->ds.offset_scale;
1463                 }
1464                 radv_load_ds_clear_metadata(cmd_buffer, image);
1465         } else {
1466                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1467                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1468                 else
1469                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1470
1471                 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1472                 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1473         }
1474         radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1475                                S_028208_BR_X(framebuffer->width) |
1476                                S_028208_BR_Y(framebuffer->height));
1477
1478         if (cmd_buffer->device->dfsm_allowed) {
1479                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1480                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1481         }
1482
1483         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1484 }
1485
1486 static void
1487 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1488 {
1489         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1490         struct radv_cmd_state *state = &cmd_buffer->state;
1491
1492         if (state->index_type != state->last_index_type) {
1493                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1494                         radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1495                                                    2, state->index_type);
1496                 } else {
1497                         radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1498                         radeon_emit(cs, state->index_type);
1499                 }
1500
1501                 state->last_index_type = state->index_type;
1502         }
1503
1504         radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1505         radeon_emit(cs, state->index_va);
1506         radeon_emit(cs, state->index_va >> 32);
1507
1508         radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1509         radeon_emit(cs, state->max_index_count);
1510
1511         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1512 }
1513
1514 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1515 {
1516         bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;
1517         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1518         uint32_t pa_sc_mode_cntl_1 =
1519                 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1520         uint32_t db_count_control;
1521
1522         if(!cmd_buffer->state.active_occlusion_queries) {
1523                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1524                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1525                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1526                             has_perfect_queries) {
1527                                 /* Re-enable out-of-order rasterization if the
1528                                  * bound pipeline supports it and if it's has
1529                                  * been disabled before starting any perfect
1530                                  * occlusion queries.
1531                                  */
1532                                 radeon_set_context_reg(cmd_buffer->cs,
1533                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1534                                                        pa_sc_mode_cntl_1);
1535                         }
1536                         db_count_control = 0;
1537                 } else {
1538                         db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1539                 }
1540         } else {
1541                 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1542                 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1543
1544                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1545                         db_count_control =
1546                                 S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
1547                                 S_028004_SAMPLE_RATE(sample_rate) |
1548                                 S_028004_ZPASS_ENABLE(1) |
1549                                 S_028004_SLICE_EVEN_ENABLE(1) |
1550                                 S_028004_SLICE_ODD_ENABLE(1);
1551
1552                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1553                             pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
1554                             has_perfect_queries) {
1555                                 /* If the bound pipeline has enabled
1556                                  * out-of-order rasterization, we should
1557                                  * disable it before starting any perfect
1558                                  * occlusion queries.
1559                                  */
1560                                 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1561
1562                                 radeon_set_context_reg(cmd_buffer->cs,
1563                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1564                                                        pa_sc_mode_cntl_1);
1565                         }
1566                 } else {
1567                         db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1568                                 S_028004_SAMPLE_RATE(sample_rate);
1569                 }
1570         }
1571
1572         radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1573 }
1574
1575 static void
1576 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1577 {
1578         uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1579
1580         if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1581                 radv_emit_viewport(cmd_buffer);
1582
1583         if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT) &&
1584             !cmd_buffer->device->physical_device->has_scissor_bug)
1585                 radv_emit_scissor(cmd_buffer);
1586
1587         if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1588                 radv_emit_line_width(cmd_buffer);
1589
1590         if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1591                 radv_emit_blend_constants(cmd_buffer);
1592
1593         if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1594                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1595                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1596                 radv_emit_stencil(cmd_buffer);
1597
1598         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1599                 radv_emit_depth_bounds(cmd_buffer);
1600
1601         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1602                 radv_emit_depth_bias(cmd_buffer);
1603
1604         if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1605                 radv_emit_discard_rectangle(cmd_buffer);
1606
1607         cmd_buffer->state.dirty &= ~states;
1608 }
1609
1610 static void
1611 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1612                             VkPipelineBindPoint bind_point)
1613 {
1614         struct radv_descriptor_state *descriptors_state =
1615                 radv_get_descriptors_state(cmd_buffer, bind_point);
1616         struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1617         unsigned bo_offset;
1618
1619         if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1620                                          set->mapped_ptr,
1621                                          &bo_offset))
1622                 return;
1623
1624         set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1625         set->va += bo_offset;
1626 }
1627
1628 static void
1629 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1630                                     VkPipelineBindPoint bind_point)
1631 {
1632         struct radv_descriptor_state *descriptors_state =
1633                 radv_get_descriptors_state(cmd_buffer, bind_point);
1634         uint32_t size = MAX_SETS * 2 * 4;
1635         uint32_t offset;
1636         void *ptr;
1637
1638         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1639                                           256, &offset, &ptr))
1640                 return;
1641
1642         for (unsigned i = 0; i < MAX_SETS; i++) {
1643                 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1644                 uint64_t set_va = 0;
1645                 struct radv_descriptor_set *set = descriptors_state->sets[i];
1646                 if (descriptors_state->valid & (1u << i))
1647                         set_va = set->va;
1648                 uptr[0] = set_va & 0xffffffff;
1649                 uptr[1] = set_va >> 32;
1650         }
1651
1652         uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1653         va += offset;
1654
1655         if (cmd_buffer->state.pipeline) {
1656                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1657                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1658                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1659
1660                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1661                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1662                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1663
1664                 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1665                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1666                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1667
1668                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1669                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1670                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1671
1672                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1673                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1674                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1675         }
1676
1677         if (cmd_buffer->state.compute_pipeline)
1678                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1679                                            AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1680 }
1681
1682 static void
1683 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1684                        VkShaderStageFlags stages)
1685 {
1686         VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1687                                          VK_PIPELINE_BIND_POINT_COMPUTE :
1688                                          VK_PIPELINE_BIND_POINT_GRAPHICS;
1689         struct radv_descriptor_state *descriptors_state =
1690                 radv_get_descriptors_state(cmd_buffer, bind_point);
1691
1692         if (!descriptors_state->dirty)
1693                 return;
1694
1695         if (descriptors_state->push_dirty)
1696                 radv_flush_push_descriptors(cmd_buffer, bind_point);
1697
1698         if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1699             (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1700                 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1701         }
1702
1703         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1704                                                            cmd_buffer->cs,
1705                                                            MAX_SETS * MESA_SHADER_STAGES * 4);
1706
1707         if (cmd_buffer->state.pipeline) {
1708                 radv_foreach_stage(stage, stages) {
1709                         if (!cmd_buffer->state.pipeline->shaders[stage])
1710                                 continue;
1711
1712                         radv_emit_descriptor_pointers(cmd_buffer,
1713                                                       cmd_buffer->state.pipeline,
1714                                                       descriptors_state, stage);
1715                 }
1716         }
1717
1718         if (cmd_buffer->state.compute_pipeline &&
1719             (stages & VK_SHADER_STAGE_COMPUTE_BIT)) {
1720                 radv_emit_descriptor_pointers(cmd_buffer,
1721                                               cmd_buffer->state.compute_pipeline,
1722                                               descriptors_state,
1723                                               MESA_SHADER_COMPUTE);
1724         }
1725
1726         descriptors_state->dirty = 0;
1727         descriptors_state->push_dirty = false;
1728
1729         if (unlikely(cmd_buffer->device->trace_bo))
1730                 radv_save_descriptors(cmd_buffer, bind_point);
1731
1732         assert(cmd_buffer->cs->cdw <= cdw_max);
1733 }
1734
1735 static void
1736 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1737                      VkShaderStageFlags stages)
1738 {
1739         struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1740                                          ? cmd_buffer->state.compute_pipeline
1741                                          : cmd_buffer->state.pipeline;
1742         struct radv_pipeline_layout *layout = pipeline->layout;
1743         struct radv_shader_variant *shader, *prev_shader;
1744         unsigned offset;
1745         void *ptr;
1746         uint64_t va;
1747
1748         stages &= cmd_buffer->push_constant_stages;
1749         if (!stages ||
1750             (!layout->push_constant_size && !layout->dynamic_offset_count))
1751                 return;
1752
1753         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1754                                           16 * layout->dynamic_offset_count,
1755                                           256, &offset, &ptr))
1756                 return;
1757
1758         memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1759         memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1760                16 * layout->dynamic_offset_count);
1761
1762         va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1763         va += offset;
1764
1765         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1766                                                            cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1767
1768         prev_shader = NULL;
1769         radv_foreach_stage(stage, stages) {
1770                 shader = radv_get_shader(pipeline, stage);
1771
1772                 /* Avoid redundantly emitting the address for merged stages. */
1773                 if (shader && shader != prev_shader) {
1774                         radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1775                                                    AC_UD_PUSH_CONSTANTS, va);
1776
1777                         prev_shader = shader;
1778                 }
1779         }
1780
1781         cmd_buffer->push_constant_stages &= ~stages;
1782         assert(cmd_buffer->cs->cdw <= cdw_max);
1783 }
1784
1785 static void
1786 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1787                               bool pipeline_is_dirty)
1788 {
1789         if ((pipeline_is_dirty ||
1790             (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1791             cmd_buffer->state.pipeline->vertex_elements.count &&
1792             radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.has_vertex_buffers) {
1793                 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1794                 unsigned vb_offset;
1795                 void *vb_ptr;
1796                 uint32_t i = 0;
1797                 uint32_t count = velems->count;
1798                 uint64_t va;
1799
1800                 /* allocate some descriptor state for vertex buffers */
1801                 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1802                                                   &vb_offset, &vb_ptr))
1803                         return;
1804
1805                 for (i = 0; i < count; i++) {
1806                         uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1807                         uint32_t offset;
1808                         int vb = velems->binding[i];
1809                         struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1810                         uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1811
1812                         va = radv_buffer_get_va(buffer->bo);
1813
1814                         offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1815                         va += offset + buffer->offset;
1816                         desc[0] = va;
1817                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1818                         if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1819                                 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1820                         else
1821                                 desc[2] = buffer->size - offset;
1822                         desc[3] = velems->rsrc_word3[i];
1823                 }
1824
1825                 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1826                 va += vb_offset;
1827
1828                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1829                                            AC_UD_VS_VERTEX_BUFFERS, va);
1830
1831                 cmd_buffer->state.vb_va = va;
1832                 cmd_buffer->state.vb_size = count * 16;
1833                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1834         }
1835         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1836 }
1837
1838 static void
1839 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1840 {
1841         radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1842         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1843         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1844 }
1845
1846 static void
1847 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1848                          bool instanced_draw, bool indirect_draw,
1849                          uint32_t draw_vertex_count)
1850 {
1851         struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1852         struct radv_cmd_state *state = &cmd_buffer->state;
1853         struct radeon_cmdbuf *cs = cmd_buffer->cs;
1854         uint32_t ia_multi_vgt_param;
1855         int32_t primitive_reset_en;
1856
1857         /* Draw state. */
1858         ia_multi_vgt_param =
1859                 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1860                                           indirect_draw, draw_vertex_count);
1861
1862         if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1863                 if (info->chip_class >= GFX9) {
1864                         radeon_set_uconfig_reg_idx(cs,
1865                                                    R_030960_IA_MULTI_VGT_PARAM,
1866                                                    4, ia_multi_vgt_param);
1867                 } else if (info->chip_class >= CIK) {
1868                         radeon_set_context_reg_idx(cs,
1869                                                    R_028AA8_IA_MULTI_VGT_PARAM,
1870                                                    1, ia_multi_vgt_param);
1871                 } else {
1872                         radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1873                                                ia_multi_vgt_param);
1874                 }
1875                 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1876         }
1877
1878         /* Primitive restart. */
1879         primitive_reset_en =
1880                 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1881
1882         if (primitive_reset_en != state->last_primitive_reset_en) {
1883                 state->last_primitive_reset_en = primitive_reset_en;
1884                 if (info->chip_class >= GFX9) {
1885                         radeon_set_uconfig_reg(cs,
1886                                                R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1887                                                primitive_reset_en);
1888                 } else {
1889                         radeon_set_context_reg(cs,
1890                                                R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1891                                                primitive_reset_en);
1892                 }
1893         }
1894
1895         if (primitive_reset_en) {
1896                 uint32_t primitive_reset_index =
1897                         state->index_type ? 0xffffffffu : 0xffffu;
1898
1899                 if (primitive_reset_index != state->last_primitive_reset_index) {
1900                         radeon_set_context_reg(cs,
1901                                                R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1902                                                primitive_reset_index);
1903                         state->last_primitive_reset_index = primitive_reset_index;
1904                 }
1905         }
1906 }
1907
1908 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1909                              VkPipelineStageFlags src_stage_mask)
1910 {
1911         if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1912                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1913                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1914                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1915                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1916         }
1917
1918         if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1919                               VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1920                               VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1921                               VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1922                               VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1923                               VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1924                               VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1925                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1926                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1927                               VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1928                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1929                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1930         } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1931                                      VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1932                                      VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1933                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1934         }
1935 }
1936
1937 static enum radv_cmd_flush_bits
1938 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1939                                   VkAccessFlags src_flags)
1940 {
1941         enum radv_cmd_flush_bits flush_bits = 0;
1942         uint32_t b;
1943         for_each_bit(b, src_flags) {
1944                 switch ((VkAccessFlagBits)(1 << b)) {
1945                 case VK_ACCESS_SHADER_WRITE_BIT:
1946                         flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1947                         break;
1948                 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1949                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1950                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1951                         break;
1952                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1953                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1954                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1955                         break;
1956                 case VK_ACCESS_TRANSFER_WRITE_BIT:
1957                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1958                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1959                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1960                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1961                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
1962                         break;
1963                 default:
1964                         break;
1965                 }
1966         }
1967         return flush_bits;
1968 }
1969
1970 static enum radv_cmd_flush_bits
1971 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1972                       VkAccessFlags dst_flags,
1973                       struct radv_image *image)
1974 {
1975         enum radv_cmd_flush_bits flush_bits = 0;
1976         uint32_t b;
1977         for_each_bit(b, dst_flags) {
1978                 switch ((VkAccessFlagBits)(1 << b)) {
1979                 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1980                 case VK_ACCESS_INDEX_READ_BIT:
1981                         break;
1982                 case VK_ACCESS_UNIFORM_READ_BIT:
1983                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1984                         break;
1985                 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1986                 case VK_ACCESS_SHADER_READ_BIT:
1987                 case VK_ACCESS_TRANSFER_READ_BIT:
1988                 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1989                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1990                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
1991                         break;
1992                 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1993                         /* TODO: change to image && when the image gets passed
1994                          * through from the subpass. */
1995                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1996                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1997                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1998                         break;
1999                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
2000                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
2001                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
2002                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
2003                         break;
2004                 default:
2005                         break;
2006                 }
2007         }
2008         return flush_bits;
2009 }
2010
2011 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
2012 {
2013         cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
2014         radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
2015         cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
2016                                                               NULL);
2017 }
2018
2019 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
2020                                                  VkAttachmentReference att)
2021 {
2022         unsigned idx = att.attachment;
2023         struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
2024         VkImageSubresourceRange range;
2025         range.aspectMask = 0;
2026         range.baseMipLevel = view->base_mip;
2027         range.levelCount = 1;
2028         range.baseArrayLayer = view->base_layer;
2029         range.layerCount = cmd_buffer->state.framebuffer->layers;
2030
2031         radv_handle_image_transition(cmd_buffer,
2032                                      view->image,
2033                                      cmd_buffer->state.attachments[idx].current_layout,
2034                                      att.layout, 0, 0, &range,
2035                                      cmd_buffer->state.attachments[idx].pending_clear_aspects);
2036
2037         cmd_buffer->state.attachments[idx].current_layout = att.layout;
2038
2039
2040 }
2041
2042 void
2043 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
2044                             const struct radv_subpass *subpass, bool transitions)
2045 {
2046         if (transitions) {
2047                 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
2048
2049                 for (unsigned i = 0; i < subpass->color_count; ++i) {
2050                         if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
2051                                 radv_handle_subpass_image_transition(cmd_buffer,
2052                                                                      subpass->color_attachments[i]);
2053                 }
2054
2055                 for (unsigned i = 0; i < subpass->input_count; ++i) {
2056                         radv_handle_subpass_image_transition(cmd_buffer,
2057                                                         subpass->input_attachments[i]);
2058                 }
2059
2060                 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
2061                         radv_handle_subpass_image_transition(cmd_buffer,
2062                                                         subpass->depth_stencil_attachment);
2063                 }
2064         }
2065
2066         cmd_buffer->state.subpass = subpass;
2067
2068         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
2069 }
2070
2071 static VkResult
2072 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
2073                                  struct radv_render_pass *pass,
2074                                  const VkRenderPassBeginInfo *info)
2075 {
2076         struct radv_cmd_state *state = &cmd_buffer->state;
2077
2078         if (pass->attachment_count == 0) {
2079                 state->attachments = NULL;
2080                 return VK_SUCCESS;
2081         }
2082
2083         state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
2084                                         pass->attachment_count *
2085                                         sizeof(state->attachments[0]),
2086                                         8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2087         if (state->attachments == NULL) {
2088                 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2089                 return cmd_buffer->record_result;
2090         }
2091
2092         for (uint32_t i = 0; i < pass->attachment_count; ++i) {
2093                 struct radv_render_pass_attachment *att = &pass->attachments[i];
2094                 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
2095                 VkImageAspectFlags clear_aspects = 0;
2096
2097                 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
2098                         /* color attachment */
2099                         if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2100                                 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
2101                         }
2102                 } else {
2103                         /* depthstencil attachment */
2104                         if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
2105                             att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2106                                 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
2107                                 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2108                                     att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
2109                                         clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2110                         }
2111                         if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
2112                             att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
2113                                 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
2114                         }
2115                 }
2116
2117                 state->attachments[i].pending_clear_aspects = clear_aspects;
2118                 state->attachments[i].cleared_views = 0;
2119                 if (clear_aspects && info) {
2120                         assert(info->clearValueCount > i);
2121                         state->attachments[i].clear_value = info->pClearValues[i];
2122                 }
2123
2124                 state->attachments[i].current_layout = att->initial_layout;
2125         }
2126
2127         return VK_SUCCESS;
2128 }
2129
2130 VkResult radv_AllocateCommandBuffers(
2131         VkDevice _device,
2132         const VkCommandBufferAllocateInfo *pAllocateInfo,
2133         VkCommandBuffer *pCommandBuffers)
2134 {
2135         RADV_FROM_HANDLE(radv_device, device, _device);
2136         RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
2137
2138         VkResult result = VK_SUCCESS;
2139         uint32_t i;
2140
2141         for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
2142
2143                 if (!list_empty(&pool->free_cmd_buffers)) {
2144                         struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
2145
2146                         list_del(&cmd_buffer->pool_link);
2147                         list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
2148
2149                         result = radv_reset_cmd_buffer(cmd_buffer);
2150                         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2151                         cmd_buffer->level = pAllocateInfo->level;
2152
2153                         pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
2154                 } else {
2155                         result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
2156                                                         &pCommandBuffers[i]);
2157                 }
2158                 if (result != VK_SUCCESS)
2159                         break;
2160         }
2161
2162         if (result != VK_SUCCESS) {
2163                 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2164                                         i, pCommandBuffers);
2165
2166                 /* From the Vulkan 1.0.66 spec:
2167                  *
2168                  * "vkAllocateCommandBuffers can be used to create multiple
2169                  *  command buffers. If the creation of any of those command
2170                  *  buffers fails, the implementation must destroy all
2171                  *  successfully created command buffer objects from this
2172                  *  command, set all entries of the pCommandBuffers array to
2173                  *  NULL and return the error."
2174                  */
2175                 memset(pCommandBuffers, 0,
2176                        sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2177         }
2178
2179         return result;
2180 }
2181
2182 void radv_FreeCommandBuffers(
2183         VkDevice device,
2184         VkCommandPool commandPool,
2185         uint32_t commandBufferCount,
2186         const VkCommandBuffer *pCommandBuffers)
2187 {
2188         for (uint32_t i = 0; i < commandBufferCount; i++) {
2189                 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2190
2191                 if (cmd_buffer) {
2192                         if (cmd_buffer->pool) {
2193                                 list_del(&cmd_buffer->pool_link);
2194                                 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2195                         } else
2196                                 radv_cmd_buffer_destroy(cmd_buffer);
2197
2198                 }
2199         }
2200 }
2201
2202 VkResult radv_ResetCommandBuffer(
2203         VkCommandBuffer commandBuffer,
2204         VkCommandBufferResetFlags flags)
2205 {
2206         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2207         return radv_reset_cmd_buffer(cmd_buffer);
2208 }
2209
2210 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2211 {
2212         struct radv_device *device = cmd_buffer->device;
2213         if (device->gfx_init) {
2214                 uint64_t va = radv_buffer_get_va(device->gfx_init);
2215                 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2216                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2217                 radeon_emit(cmd_buffer->cs, va);
2218                 radeon_emit(cmd_buffer->cs, va >> 32);
2219                 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2220         } else
2221                 si_init_config(cmd_buffer);
2222 }
2223
2224 VkResult radv_BeginCommandBuffer(
2225         VkCommandBuffer commandBuffer,
2226         const VkCommandBufferBeginInfo *pBeginInfo)
2227 {
2228         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2229         VkResult result = VK_SUCCESS;
2230
2231         if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2232                 /* If the command buffer has already been resetted with
2233                  * vkResetCommandBuffer, no need to do it again.
2234                  */
2235                 result = radv_reset_cmd_buffer(cmd_buffer);
2236                 if (result != VK_SUCCESS)
2237                         return result;
2238         }
2239
2240         memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2241         cmd_buffer->state.last_primitive_reset_en = -1;
2242         cmd_buffer->state.last_index_type = -1;
2243         cmd_buffer->state.last_num_instances = -1;
2244         cmd_buffer->state.last_vertex_offset = -1;
2245         cmd_buffer->state.last_first_instance = -1;
2246         cmd_buffer->usage_flags = pBeginInfo->flags;
2247
2248         /* setup initial configuration into command buffer */
2249         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2250                 switch (cmd_buffer->queue_family_index) {
2251                 case RADV_QUEUE_GENERAL:
2252                         emit_gfx_buffer_state(cmd_buffer);
2253                         break;
2254                 case RADV_QUEUE_COMPUTE:
2255                         si_init_compute(cmd_buffer);
2256                         break;
2257                 case RADV_QUEUE_TRANSFER:
2258                 default:
2259                         break;
2260                 }
2261         }
2262
2263         if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2264                 assert(pBeginInfo->pInheritanceInfo);
2265                 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2266                 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2267
2268                 struct radv_subpass *subpass =
2269                         &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2270
2271                 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2272                 if (result != VK_SUCCESS)
2273                         return result;
2274
2275                 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2276         }
2277
2278         if (unlikely(cmd_buffer->device->trace_bo))
2279                 radv_cmd_buffer_trace_emit(cmd_buffer);
2280
2281         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2282
2283         return result;
2284 }
2285
2286 void radv_CmdBindVertexBuffers(
2287         VkCommandBuffer                             commandBuffer,
2288         uint32_t                                    firstBinding,
2289         uint32_t                                    bindingCount,
2290         const VkBuffer*                             pBuffers,
2291         const VkDeviceSize*                         pOffsets)
2292 {
2293         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2294         struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2295         bool changed = false;
2296
2297         /* We have to defer setting up vertex buffer since we need the buffer
2298          * stride from the pipeline. */
2299
2300         assert(firstBinding + bindingCount <= MAX_VBS);
2301         for (uint32_t i = 0; i < bindingCount; i++) {
2302                 uint32_t idx = firstBinding + i;
2303
2304                 if (!changed &&
2305                     (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2306                      vb[idx].offset != pOffsets[i])) {
2307                         changed = true;
2308                 }
2309
2310                 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2311                 vb[idx].offset = pOffsets[i];
2312
2313                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2314                                    vb[idx].buffer->bo, 8);
2315         }
2316
2317         if (!changed) {
2318                 /* No state changes. */
2319                 return;
2320         }
2321
2322         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2323 }
2324
2325 void radv_CmdBindIndexBuffer(
2326         VkCommandBuffer                             commandBuffer,
2327         VkBuffer buffer,
2328         VkDeviceSize offset,
2329         VkIndexType indexType)
2330 {
2331         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2332         RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2333
2334         if (cmd_buffer->state.index_buffer == index_buffer &&
2335             cmd_buffer->state.index_offset == offset &&
2336             cmd_buffer->state.index_type == indexType) {
2337                 /* No state changes. */
2338                 return;
2339         }
2340
2341         cmd_buffer->state.index_buffer = index_buffer;
2342         cmd_buffer->state.index_offset = offset;
2343         cmd_buffer->state.index_type = indexType; /* vk matches hw */
2344         cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2345         cmd_buffer->state.index_va += index_buffer->offset + offset;
2346
2347         int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2348         cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2349         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2350         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2351 }
2352
2353
2354 static void
2355 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2356                          VkPipelineBindPoint bind_point,
2357                          struct radv_descriptor_set *set, unsigned idx)
2358 {
2359         struct radeon_winsys *ws = cmd_buffer->device->ws;
2360
2361         radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2362         if (!set)
2363                 return;
2364
2365         assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2366
2367         if (!cmd_buffer->device->use_global_bo_list) {
2368                 for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2369                         if (set->descriptors[j])
2370                                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2371         }
2372
2373         if(set->bo)
2374                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2375 }
2376
2377 void radv_CmdBindDescriptorSets(
2378         VkCommandBuffer                             commandBuffer,
2379         VkPipelineBindPoint                         pipelineBindPoint,
2380         VkPipelineLayout                            _layout,
2381         uint32_t                                    firstSet,
2382         uint32_t                                    descriptorSetCount,
2383         const VkDescriptorSet*                      pDescriptorSets,
2384         uint32_t                                    dynamicOffsetCount,
2385         const uint32_t*                             pDynamicOffsets)
2386 {
2387         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2388         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2389         unsigned dyn_idx = 0;
2390
2391         const bool no_dynamic_bounds = cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;
2392
2393         for (unsigned i = 0; i < descriptorSetCount; ++i) {
2394                 unsigned idx = i + firstSet;
2395                 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2396                 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2397
2398                 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2399                         unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2400                         uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2401                         assert(dyn_idx < dynamicOffsetCount);
2402
2403                         struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2404                         uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2405                         dst[0] = va;
2406                         dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2407                         dst[2] = no_dynamic_bounds ? 0xffffffffu : range->size;
2408                         dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2409                                  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2410                                  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2411                                  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2412                                  S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2413                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2414                         cmd_buffer->push_constant_stages |=
2415                                              set->layout->dynamic_shader_stages;
2416                 }
2417         }
2418 }
2419
2420 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2421                                           struct radv_descriptor_set *set,
2422                                           struct radv_descriptor_set_layout *layout,
2423                                           VkPipelineBindPoint bind_point)
2424 {
2425         struct radv_descriptor_state *descriptors_state =
2426                 radv_get_descriptors_state(cmd_buffer, bind_point);
2427         set->size = layout->size;
2428         set->layout = layout;
2429
2430         if (descriptors_state->push_set.capacity < set->size) {
2431                 size_t new_size = MAX2(set->size, 1024);
2432                 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2433                 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2434
2435                 free(set->mapped_ptr);
2436                 set->mapped_ptr = malloc(new_size);
2437
2438                 if (!set->mapped_ptr) {
2439                         descriptors_state->push_set.capacity = 0;
2440                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2441                         return false;
2442                 }
2443
2444                 descriptors_state->push_set.capacity = new_size;
2445         }
2446
2447         return true;
2448 }
2449
2450 void radv_meta_push_descriptor_set(
2451         struct radv_cmd_buffer*              cmd_buffer,
2452         VkPipelineBindPoint                  pipelineBindPoint,
2453         VkPipelineLayout                     _layout,
2454         uint32_t                             set,
2455         uint32_t                             descriptorWriteCount,
2456         const VkWriteDescriptorSet*          pDescriptorWrites)
2457 {
2458         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2459         struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2460         unsigned bo_offset;
2461
2462         assert(set == 0);
2463         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2464
2465         push_set->size = layout->set[set].layout->size;
2466         push_set->layout = layout->set[set].layout;
2467
2468         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2469                                           &bo_offset,
2470                                           (void**) &push_set->mapped_ptr))
2471                 return;
2472
2473         push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2474         push_set->va += bo_offset;
2475
2476         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2477                                     radv_descriptor_set_to_handle(push_set),
2478                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2479
2480         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2481 }
2482
2483 void radv_CmdPushDescriptorSetKHR(
2484         VkCommandBuffer                             commandBuffer,
2485         VkPipelineBindPoint                         pipelineBindPoint,
2486         VkPipelineLayout                            _layout,
2487         uint32_t                                    set,
2488         uint32_t                                    descriptorWriteCount,
2489         const VkWriteDescriptorSet*                 pDescriptorWrites)
2490 {
2491         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2492         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2493         struct radv_descriptor_state *descriptors_state =
2494                 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2495         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2496
2497         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2498
2499         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2500                                            layout->set[set].layout,
2501                                            pipelineBindPoint))
2502                 return;
2503
2504         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2505                                     radv_descriptor_set_to_handle(push_set),
2506                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2507
2508         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2509         descriptors_state->push_dirty = true;
2510 }
2511
2512 void radv_CmdPushDescriptorSetWithTemplateKHR(
2513         VkCommandBuffer                             commandBuffer,
2514         VkDescriptorUpdateTemplateKHR               descriptorUpdateTemplate,
2515         VkPipelineLayout                            _layout,
2516         uint32_t                                    set,
2517         const void*                                 pData)
2518 {
2519         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2520         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2521         RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2522         struct radv_descriptor_state *descriptors_state =
2523                 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2524         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2525
2526         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2527
2528         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2529                                            layout->set[set].layout,
2530                                            templ->bind_point))
2531                 return;
2532
2533         radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2534                                                  descriptorUpdateTemplate, pData);
2535
2536         radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2537         descriptors_state->push_dirty = true;
2538 }
2539
2540 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2541                            VkPipelineLayout layout,
2542                            VkShaderStageFlags stageFlags,
2543                            uint32_t offset,
2544                            uint32_t size,
2545                            const void* pValues)
2546 {
2547         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2548         memcpy(cmd_buffer->push_constants + offset, pValues, size);
2549         cmd_buffer->push_constant_stages |= stageFlags;
2550 }
2551
2552 VkResult radv_EndCommandBuffer(
2553         VkCommandBuffer                             commandBuffer)
2554 {
2555         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2556
2557         if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2558                 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2559                         cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2560                 si_emit_cache_flush(cmd_buffer);
2561         }
2562
2563         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2564
2565         if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2566                 return vk_error(cmd_buffer->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2567
2568         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2569
2570         return cmd_buffer->record_result;
2571 }
2572
2573 static void
2574 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2575 {
2576         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2577
2578         if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2579                 return;
2580
2581         cmd_buffer->state.emitted_compute_pipeline = pipeline;
2582
2583         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2584         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2585
2586         cmd_buffer->compute_scratch_size_needed =
2587                                   MAX2(cmd_buffer->compute_scratch_size_needed,
2588                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2589
2590         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2591                            pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
2592
2593         if (unlikely(cmd_buffer->device->trace_bo))
2594                 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2595 }
2596
2597 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2598                                             VkPipelineBindPoint bind_point)
2599 {
2600         struct radv_descriptor_state *descriptors_state =
2601                 radv_get_descriptors_state(cmd_buffer, bind_point);
2602
2603         descriptors_state->dirty |= descriptors_state->valid;
2604 }
2605
2606 void radv_CmdBindPipeline(
2607         VkCommandBuffer                             commandBuffer,
2608         VkPipelineBindPoint                         pipelineBindPoint,
2609         VkPipeline                                  _pipeline)
2610 {
2611         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2612         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2613
2614         switch (pipelineBindPoint) {
2615         case VK_PIPELINE_BIND_POINT_COMPUTE:
2616                 if (cmd_buffer->state.compute_pipeline == pipeline)
2617                         return;
2618                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2619
2620                 cmd_buffer->state.compute_pipeline = pipeline;
2621                 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2622                 break;
2623         case VK_PIPELINE_BIND_POINT_GRAPHICS:
2624                 if (cmd_buffer->state.pipeline == pipeline)
2625                         return;
2626                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2627
2628                 cmd_buffer->state.pipeline = pipeline;
2629                 if (!pipeline)
2630                         break;
2631
2632                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2633                 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2634
2635                 /* the new vertex shader might not have the same user regs */
2636                 cmd_buffer->state.last_first_instance = -1;
2637                 cmd_buffer->state.last_vertex_offset = -1;
2638
2639                 /* Prefetch all pipeline shaders at first draw time. */
2640                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2641
2642                 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2643
2644                 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2645                         cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2646                 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2647                         cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2648
2649                 if (radv_pipeline_has_tess(pipeline))
2650                         cmd_buffer->tess_rings_needed = true;
2651
2652                 if (radv_pipeline_has_gs(pipeline)) {
2653                         struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2654                                                                              AC_UD_SCRATCH_RING_OFFSETS);
2655                         if (cmd_buffer->ring_offsets_idx == -1)
2656                                 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2657                         else if (loc->sgpr_idx != -1)
2658                                 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2659                 }
2660                 break;
2661         default:
2662                 assert(!"invalid bind point");
2663                 break;
2664         }
2665 }
2666
2667 void radv_CmdSetViewport(
2668         VkCommandBuffer                             commandBuffer,
2669         uint32_t                                    firstViewport,
2670         uint32_t                                    viewportCount,
2671         const VkViewport*                           pViewports)
2672 {
2673         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2674         struct radv_cmd_state *state = &cmd_buffer->state;
2675         MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2676
2677         assert(firstViewport < MAX_VIEWPORTS);
2678         assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2679
2680         memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2681                viewportCount * sizeof(*pViewports));
2682
2683         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2684 }
2685
2686 void radv_CmdSetScissor(
2687         VkCommandBuffer                             commandBuffer,
2688         uint32_t                                    firstScissor,
2689         uint32_t                                    scissorCount,
2690         const VkRect2D*                             pScissors)
2691 {
2692         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2693         struct radv_cmd_state *state = &cmd_buffer->state;
2694         MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2695
2696         assert(firstScissor < MAX_SCISSORS);
2697         assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2698
2699         memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2700                scissorCount * sizeof(*pScissors));
2701
2702         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2703 }
2704
2705 void radv_CmdSetLineWidth(
2706         VkCommandBuffer                             commandBuffer,
2707         float                                       lineWidth)
2708 {
2709         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2710         cmd_buffer->state.dynamic.line_width = lineWidth;
2711         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2712 }
2713
2714 void radv_CmdSetDepthBias(
2715         VkCommandBuffer                             commandBuffer,
2716         float                                       depthBiasConstantFactor,
2717         float                                       depthBiasClamp,
2718         float                                       depthBiasSlopeFactor)
2719 {
2720         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2721
2722         cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2723         cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2724         cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2725
2726         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2727 }
2728
2729 void radv_CmdSetBlendConstants(
2730         VkCommandBuffer                             commandBuffer,
2731         const float                                 blendConstants[4])
2732 {
2733         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2734
2735         memcpy(cmd_buffer->state.dynamic.blend_constants,
2736                blendConstants, sizeof(float) * 4);
2737
2738         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2739 }
2740
2741 void radv_CmdSetDepthBounds(
2742         VkCommandBuffer                             commandBuffer,
2743         float                                       minDepthBounds,
2744         float                                       maxDepthBounds)
2745 {
2746         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2747
2748         cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2749         cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2750
2751         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2752 }
2753
2754 void radv_CmdSetStencilCompareMask(
2755         VkCommandBuffer                             commandBuffer,
2756         VkStencilFaceFlags                          faceMask,
2757         uint32_t                                    compareMask)
2758 {
2759         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2760
2761         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2762                 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2763         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2764                 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2765
2766         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2767 }
2768
2769 void radv_CmdSetStencilWriteMask(
2770         VkCommandBuffer                             commandBuffer,
2771         VkStencilFaceFlags                          faceMask,
2772         uint32_t                                    writeMask)
2773 {
2774         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2775
2776         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2777                 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2778         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2779                 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2780
2781         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2782 }
2783
2784 void radv_CmdSetStencilReference(
2785         VkCommandBuffer                             commandBuffer,
2786         VkStencilFaceFlags                          faceMask,
2787         uint32_t                                    reference)
2788 {
2789         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2790
2791         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2792                 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2793         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2794                 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2795
2796         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2797 }
2798
2799 void radv_CmdSetDiscardRectangleEXT(
2800         VkCommandBuffer                             commandBuffer,
2801         uint32_t                                    firstDiscardRectangle,
2802         uint32_t                                    discardRectangleCount,
2803         const VkRect2D*                             pDiscardRectangles)
2804 {
2805         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2806         struct radv_cmd_state *state = &cmd_buffer->state;
2807         MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2808
2809         assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2810         assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2811
2812         typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2813                      pDiscardRectangles, discardRectangleCount);
2814
2815         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2816 }
2817
2818 void radv_CmdExecuteCommands(
2819         VkCommandBuffer                             commandBuffer,
2820         uint32_t                                    commandBufferCount,
2821         const VkCommandBuffer*                      pCmdBuffers)
2822 {
2823         RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2824
2825         assert(commandBufferCount > 0);
2826
2827         /* Emit pending flushes on primary prior to executing secondary */
2828         si_emit_cache_flush(primary);
2829
2830         for (uint32_t i = 0; i < commandBufferCount; i++) {
2831                 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2832
2833                 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2834                                                     secondary->scratch_size_needed);
2835                 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2836                                                             secondary->compute_scratch_size_needed);
2837
2838                 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2839                         primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2840                 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2841                         primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2842                 if (secondary->tess_rings_needed)
2843                         primary->tess_rings_needed = true;
2844                 if (secondary->sample_positions_needed)
2845                         primary->sample_positions_needed = true;
2846
2847                 if (secondary->ring_offsets_idx != -1) {
2848                         if (primary->ring_offsets_idx == -1)
2849                                 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2850                         else
2851                                 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2852                 }
2853                 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2854
2855
2856                 /* When the secondary command buffer is compute only we don't
2857                  * need to re-emit the current graphics pipeline.
2858                  */
2859                 if (secondary->state.emitted_pipeline) {
2860                         primary->state.emitted_pipeline =
2861                                 secondary->state.emitted_pipeline;
2862                 }
2863
2864                 /* When the secondary command buffer is graphics only we don't
2865                  * need to re-emit the current compute pipeline.
2866                  */
2867                 if (secondary->state.emitted_compute_pipeline) {
2868                         primary->state.emitted_compute_pipeline =
2869                                 secondary->state.emitted_compute_pipeline;
2870                 }
2871
2872                 /* Only re-emit the draw packets when needed. */
2873                 if (secondary->state.last_primitive_reset_en != -1) {
2874                         primary->state.last_primitive_reset_en =
2875                                 secondary->state.last_primitive_reset_en;
2876                 }
2877
2878                 if (secondary->state.last_primitive_reset_index) {
2879                         primary->state.last_primitive_reset_index =
2880                                 secondary->state.last_primitive_reset_index;
2881                 }
2882
2883                 if (secondary->state.last_ia_multi_vgt_param) {
2884                         primary->state.last_ia_multi_vgt_param =
2885                                 secondary->state.last_ia_multi_vgt_param;
2886                 }
2887
2888                 primary->state.last_first_instance = secondary->state.last_first_instance;
2889                 primary->state.last_num_instances = secondary->state.last_num_instances;
2890                 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2891
2892                 if (secondary->state.last_index_type != -1) {
2893                         primary->state.last_index_type =
2894                                 secondary->state.last_index_type;
2895                 }
2896         }
2897
2898         /* After executing commands from secondary buffers we have to dirty
2899          * some states.
2900          */
2901         primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2902                                 RADV_CMD_DIRTY_INDEX_BUFFER |
2903                                 RADV_CMD_DIRTY_DYNAMIC_ALL;
2904         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2905         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2906 }
2907
2908 VkResult radv_CreateCommandPool(
2909         VkDevice                                    _device,
2910         const VkCommandPoolCreateInfo*              pCreateInfo,
2911         const VkAllocationCallbacks*                pAllocator,
2912         VkCommandPool*                              pCmdPool)
2913 {
2914         RADV_FROM_HANDLE(radv_device, device, _device);
2915         struct radv_cmd_pool *pool;
2916
2917         pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2918                            VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2919         if (pool == NULL)
2920                 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2921
2922         if (pAllocator)
2923                 pool->alloc = *pAllocator;
2924         else
2925                 pool->alloc = device->alloc;
2926
2927         list_inithead(&pool->cmd_buffers);
2928         list_inithead(&pool->free_cmd_buffers);
2929
2930         pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2931
2932         *pCmdPool = radv_cmd_pool_to_handle(pool);
2933
2934         return VK_SUCCESS;
2935
2936 }
2937
2938 void radv_DestroyCommandPool(
2939         VkDevice                                    _device,
2940         VkCommandPool                               commandPool,
2941         const VkAllocationCallbacks*                pAllocator)
2942 {
2943         RADV_FROM_HANDLE(radv_device, device, _device);
2944         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2945
2946         if (!pool)
2947                 return;
2948
2949         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2950                                  &pool->cmd_buffers, pool_link) {
2951                 radv_cmd_buffer_destroy(cmd_buffer);
2952         }
2953
2954         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2955                                  &pool->free_cmd_buffers, pool_link) {
2956                 radv_cmd_buffer_destroy(cmd_buffer);
2957         }
2958
2959         vk_free2(&device->alloc, pAllocator, pool);
2960 }
2961
2962 VkResult radv_ResetCommandPool(
2963         VkDevice                                    device,
2964         VkCommandPool                               commandPool,
2965         VkCommandPoolResetFlags                     flags)
2966 {
2967         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2968         VkResult result;
2969
2970         list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2971                             &pool->cmd_buffers, pool_link) {
2972                 result = radv_reset_cmd_buffer(cmd_buffer);
2973                 if (result != VK_SUCCESS)
2974                         return result;
2975         }
2976
2977         return VK_SUCCESS;
2978 }
2979
2980 void radv_TrimCommandPool(
2981     VkDevice                                    device,
2982     VkCommandPool                               commandPool,
2983     VkCommandPoolTrimFlagsKHR                   flags)
2984 {
2985         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2986
2987         if (!pool)
2988                 return;
2989
2990         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2991                                  &pool->free_cmd_buffers, pool_link) {
2992                 radv_cmd_buffer_destroy(cmd_buffer);
2993         }
2994 }
2995
2996 void radv_CmdBeginRenderPass(
2997         VkCommandBuffer                             commandBuffer,
2998         const VkRenderPassBeginInfo*                pRenderPassBegin,
2999         VkSubpassContents                           contents)
3000 {
3001         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3002         RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
3003         RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
3004
3005         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
3006                                                            cmd_buffer->cs, 2048);
3007         MAYBE_UNUSED VkResult result;
3008
3009         cmd_buffer->state.framebuffer = framebuffer;
3010         cmd_buffer->state.pass = pass;
3011         cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
3012
3013         result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
3014         if (result != VK_SUCCESS)
3015                 return;
3016
3017         radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
3018         assert(cmd_buffer->cs->cdw <= cdw_max);
3019
3020         radv_cmd_buffer_clear_subpass(cmd_buffer);
3021 }
3022
3023 void radv_CmdNextSubpass(
3024     VkCommandBuffer                             commandBuffer,
3025     VkSubpassContents                           contents)
3026 {
3027         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3028
3029         radv_cmd_buffer_resolve_subpass(cmd_buffer);
3030
3031         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
3032                                               2048);
3033
3034         radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
3035         radv_cmd_buffer_clear_subpass(cmd_buffer);
3036 }
3037
3038 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
3039 {
3040         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
3041         for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
3042                 if (!pipeline->shaders[stage])
3043                         continue;
3044                 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
3045                 if (loc->sgpr_idx == -1)
3046                         continue;
3047                 uint32_t base_reg = pipeline->user_data_0[stage];
3048                 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3049
3050         }
3051         if (pipeline->gs_copy_shader) {
3052                 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
3053                 if (loc->sgpr_idx != -1) {
3054                         uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
3055                         radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
3056                 }
3057         }
3058 }
3059
3060 static void
3061 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3062                          uint32_t vertex_count)
3063 {
3064         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
3065         radeon_emit(cmd_buffer->cs, vertex_count);
3066         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
3067                                     S_0287F0_USE_OPAQUE(0));
3068 }
3069
3070 static void
3071 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
3072                                  uint64_t index_va,
3073                                  uint32_t index_count)
3074 {
3075         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
3076         radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
3077         radeon_emit(cmd_buffer->cs, index_va);
3078         radeon_emit(cmd_buffer->cs, index_va >> 32);
3079         radeon_emit(cmd_buffer->cs, index_count);
3080         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
3081 }
3082
3083 static void
3084 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
3085                                   bool indexed,
3086                                   uint32_t draw_count,
3087                                   uint64_t count_va,
3088                                   uint32_t stride)
3089 {
3090         struct radeon_cmdbuf *cs = cmd_buffer->cs;
3091         unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
3092                                       : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
3093         bool draw_id_enable = radv_get_shader(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX)->info.info.vs.needs_draw_id;
3094         uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
3095         assert(base_reg);
3096
3097         /* just reset draw state for vertex data */
3098         cmd_buffer->state.last_first_instance = -1;
3099         cmd_buffer->state.last_num_instances = -1;
3100         cmd_buffer->state.last_vertex_offset = -1;
3101
3102         if (draw_count == 1 && !count_va && !draw_id_enable) {
3103                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
3104                                      PKT3_DRAW_INDIRECT, 3, false));
3105                 radeon_emit(cs, 0);
3106                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3107                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3108                 radeon_emit(cs, di_src_sel);
3109         } else {
3110                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
3111                                      PKT3_DRAW_INDIRECT_MULTI,
3112                                      8, false));
3113                 radeon_emit(cs, 0);
3114                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
3115                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
3116                 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
3117                             S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
3118                             S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
3119                 radeon_emit(cs, draw_count); /* count */
3120                 radeon_emit(cs, count_va); /* count_addr */
3121                 radeon_emit(cs, count_va >> 32);
3122                 radeon_emit(cs, stride); /* stride */
3123                 radeon_emit(cs, di_src_sel);
3124         }
3125 }
3126
3127 struct radv_draw_info {
3128         /**
3129          * Number of vertices.
3130          */
3131         uint32_t count;
3132
3133         /**
3134          * Index of the first vertex.
3135          */
3136         int32_t vertex_offset;
3137
3138         /**
3139          * First instance id.
3140          */
3141         uint32_t first_instance;
3142
3143         /**
3144          * Number of instances.
3145          */
3146         uint32_t instance_count;
3147
3148         /**
3149          * First index (indexed draws only).
3150          */
3151         uint32_t first_index;
3152
3153         /**
3154          * Whether it's an indexed draw.
3155          */
3156         bool indexed;
3157
3158         /**
3159          * Indirect draw parameters resource.
3160          */
3161         struct radv_buffer *indirect;
3162         uint64_t indirect_offset;
3163         uint32_t stride;
3164
3165         /**
3166          * Draw count parameters resource.
3167          */
3168         struct radv_buffer *count_buffer;
3169         uint64_t count_buffer_offset;
3170 };
3171
3172 static void
3173 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3174                        const struct radv_draw_info *info)
3175 {
3176         struct radv_cmd_state *state = &cmd_buffer->state;
3177         struct radeon_winsys *ws = cmd_buffer->device->ws;
3178         struct radeon_cmdbuf *cs = cmd_buffer->cs;
3179
3180         if (info->indirect) {
3181                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3182                 uint64_t count_va = 0;
3183
3184                 va += info->indirect->offset + info->indirect_offset;
3185
3186                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3187
3188                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3189                 radeon_emit(cs, 1);
3190                 radeon_emit(cs, va);
3191                 radeon_emit(cs, va >> 32);
3192
3193                 if (info->count_buffer) {
3194                         count_va = radv_buffer_get_va(info->count_buffer->bo);
3195                         count_va += info->count_buffer->offset +
3196                                     info->count_buffer_offset;
3197
3198                         radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3199                 }
3200
3201                 if (!state->subpass->view_mask) {
3202                         radv_cs_emit_indirect_draw_packet(cmd_buffer,
3203                                                           info->indexed,
3204                                                           info->count,
3205                                                           count_va,
3206                                                           info->stride);
3207                 } else {
3208                         unsigned i;
3209                         for_each_bit(i, state->subpass->view_mask) {
3210                                 radv_emit_view_index(cmd_buffer, i);
3211
3212                                 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3213                                                                   info->indexed,
3214                                                                   info->count,
3215                                                                   count_va,
3216                                                                   info->stride);
3217                         }
3218                 }
3219         } else {
3220                 assert(state->pipeline->graphics.vtx_base_sgpr);
3221
3222                 if (info->vertex_offset != state->last_vertex_offset ||
3223                     info->first_instance != state->last_first_instance) {
3224                         radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3225                                               state->pipeline->graphics.vtx_emit_num);
3226
3227                         radeon_emit(cs, info->vertex_offset);
3228                         radeon_emit(cs, info->first_instance);
3229                         if (state->pipeline->graphics.vtx_emit_num == 3)
3230                                 radeon_emit(cs, 0);
3231                         state->last_first_instance = info->first_instance;
3232                         state->last_vertex_offset = info->vertex_offset;
3233                 }
3234
3235                 if (state->last_num_instances != info->instance_count) {
3236                         radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3237                         radeon_emit(cs, info->instance_count);
3238                         state->last_num_instances = info->instance_count;
3239                 }
3240
3241                 if (info->indexed) {
3242                         int index_size = state->index_type ? 4 : 2;
3243                         uint64_t index_va;
3244
3245                         index_va = state->index_va;
3246                         index_va += info->first_index * index_size;
3247
3248                         if (!state->subpass->view_mask) {
3249                                 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3250                                                                  index_va,
3251                                                                  info->count);
3252                         } else {
3253                                 unsigned i;
3254                                 for_each_bit(i, state->subpass->view_mask) {
3255                                         radv_emit_view_index(cmd_buffer, i);
3256
3257                                         radv_cs_emit_draw_indexed_packet(cmd_buffer,
3258                                                                          index_va,
3259                                                                          info->count);
3260                                 }
3261                         }
3262                 } else {
3263                         if (!state->subpass->view_mask) {
3264                                 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3265                         } else {
3266                                 unsigned i;
3267                                 for_each_bit(i, state->subpass->view_mask) {
3268                                         radv_emit_view_index(cmd_buffer, i);
3269
3270                                         radv_cs_emit_draw_packet(cmd_buffer,
3271                                                                  info->count);
3272                                 }
3273                         }
3274                 }
3275         }
3276 }
3277
3278 /*
3279  * Vega and raven have a bug which triggers if there are multiple context
3280  * register contexts active at the same time with different scissor values.
3281  *
3282  * There are two possible workarounds:
3283  * 1) Wait for PS_PARTIAL_FLUSH every time the scissor is changed. That way
3284  *    there is only ever 1 active set of scissor values at the same time.
3285  *
3286  * 2) Whenever the hardware switches contexts we have to set the scissor
3287  *    registers again even if it is a noop. That way the new context gets
3288  *    the correct scissor values.
3289  *
3290  * This implements option 2. radv_need_late_scissor_emission needs to
3291  * return true on affected HW if radv_emit_all_graphics_states sets
3292  * any context registers.
3293  */
3294 static bool radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,
3295                                             bool indexed_draw)
3296 {
3297         struct radv_cmd_state *state = &cmd_buffer->state;
3298
3299         if (!cmd_buffer->device->physical_device->has_scissor_bug)
3300                 return false;
3301
3302         uint32_t used_states = cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;
3303
3304         /* Index & Vertex buffer don't change context regs, and pipeline is handled later. */
3305         used_states &= ~(RADV_CMD_DIRTY_INDEX_BUFFER | RADV_CMD_DIRTY_VERTEX_BUFFER | RADV_CMD_DIRTY_PIPELINE);
3306
3307         /* Assume all state changes except  these two can imply context rolls. */
3308         if (cmd_buffer->state.dirty & used_states)
3309                 return true;
3310
3311         if (cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3312                 return true;
3313
3314         if (indexed_draw && state->pipeline->graphics.prim_restart_enable &&
3315             (state->index_type ? 0xffffffffu : 0xffffu) != state->last_primitive_reset_index)
3316                 return true;
3317
3318         return false;
3319 }
3320
3321 static void
3322 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3323                               const struct radv_draw_info *info)
3324 {
3325         bool late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info->indexed);
3326
3327         if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3328             cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3329                 radv_emit_rbplus_state(cmd_buffer);
3330
3331         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3332                 radv_emit_graphics_pipeline(cmd_buffer);
3333
3334         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3335                 radv_emit_framebuffer_state(cmd_buffer);
3336
3337         if (info->indexed) {
3338                 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3339                         radv_emit_index_buffer(cmd_buffer);
3340         } else {
3341                 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3342                  * so the state must be re-emitted before the next indexed
3343                  * draw.
3344                  */
3345                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3346                         cmd_buffer->state.last_index_type = -1;
3347                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3348                 }
3349         }
3350
3351         radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3352
3353         radv_emit_draw_registers(cmd_buffer, info->indexed,
3354                                  info->instance_count > 1, info->indirect,
3355                                  info->indirect ? 0 : info->count);
3356
3357         if (late_scissor_emission)
3358                 radv_emit_scissor(cmd_buffer);
3359 }
3360
3361 static void
3362 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3363           const struct radv_draw_info *info)
3364 {
3365         bool has_prefetch =
3366                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3367         bool pipeline_is_dirty =
3368                 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3369                 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3370
3371         MAYBE_UNUSED unsigned cdw_max =
3372                 radeon_check_space(cmd_buffer->device->ws,
3373                                    cmd_buffer->cs, 4096);
3374
3375         /* Use optimal packet order based on whether we need to sync the
3376          * pipeline.
3377          */
3378         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3379                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3380                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3381                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3382                 /* If we have to wait for idle, set all states first, so that
3383                  * all SET packets are processed in parallel with previous draw
3384                  * calls. Then upload descriptors, set shader pointers, and
3385                  * draw, and prefetch at the end. This ensures that the time
3386                  * the CUs are idle is very short. (there are only SET_SH
3387                  * packets between the wait and the draw)
3388                  */
3389                 radv_emit_all_graphics_states(cmd_buffer, info);
3390                 si_emit_cache_flush(cmd_buffer);
3391                 /* <-- CUs are idle here --> */
3392
3393                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3394
3395                 radv_emit_draw_packets(cmd_buffer, info);
3396                 /* <-- CUs are busy here --> */
3397
3398                 /* Start prefetches after the draw has been started. Both will
3399                  * run in parallel, but starting the draw first is more
3400                  * important.
3401                  */
3402                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3403                         radv_emit_prefetch_L2(cmd_buffer,
3404                                               cmd_buffer->state.pipeline, false);
3405                 }
3406         } else {
3407                 /* If we don't wait for idle, start prefetches first, then set
3408                  * states, and draw at the end.
3409                  */
3410                 si_emit_cache_flush(cmd_buffer);
3411
3412                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3413                         /* Only prefetch the vertex shader and VBO descriptors
3414                          * in order to start the draw as soon as possible.
3415                          */
3416                         radv_emit_prefetch_L2(cmd_buffer,
3417                                               cmd_buffer->state.pipeline, true);
3418                 }
3419
3420                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3421
3422                 radv_emit_all_graphics_states(cmd_buffer, info);
3423                 radv_emit_draw_packets(cmd_buffer, info);
3424
3425                 /* Prefetch the remaining shaders after the draw has been
3426                  * started.
3427                  */
3428                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3429                         radv_emit_prefetch_L2(cmd_buffer,
3430                                               cmd_buffer->state.pipeline, false);
3431                 }
3432         }
3433
3434         assert(cmd_buffer->cs->cdw <= cdw_max);
3435         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3436 }
3437
3438 void radv_CmdDraw(
3439         VkCommandBuffer                             commandBuffer,
3440         uint32_t                                    vertexCount,
3441         uint32_t                                    instanceCount,
3442         uint32_t                                    firstVertex,
3443         uint32_t                                    firstInstance)
3444 {
3445         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3446         struct radv_draw_info info = {};
3447
3448         info.count = vertexCount;
3449         info.instance_count = instanceCount;
3450         info.first_instance = firstInstance;
3451         info.vertex_offset = firstVertex;
3452
3453         radv_draw(cmd_buffer, &info);
3454 }
3455
3456 void radv_CmdDrawIndexed(
3457         VkCommandBuffer                             commandBuffer,
3458         uint32_t                                    indexCount,
3459         uint32_t                                    instanceCount,
3460         uint32_t                                    firstIndex,
3461         int32_t                                     vertexOffset,
3462         uint32_t                                    firstInstance)
3463 {
3464         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3465         struct radv_draw_info info = {};
3466
3467         info.indexed = true;
3468         info.count = indexCount;
3469         info.instance_count = instanceCount;
3470         info.first_index = firstIndex;
3471         info.vertex_offset = vertexOffset;
3472         info.first_instance = firstInstance;
3473
3474         radv_draw(cmd_buffer, &info);
3475 }
3476
3477 void radv_CmdDrawIndirect(
3478         VkCommandBuffer                             commandBuffer,
3479         VkBuffer                                    _buffer,
3480         VkDeviceSize                                offset,
3481         uint32_t                                    drawCount,
3482         uint32_t                                    stride)
3483 {
3484         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3485         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3486         struct radv_draw_info info = {};
3487
3488         info.count = drawCount;
3489         info.indirect = buffer;
3490         info.indirect_offset = offset;
3491         info.stride = stride;
3492
3493         radv_draw(cmd_buffer, &info);
3494 }
3495
3496 void radv_CmdDrawIndexedIndirect(
3497         VkCommandBuffer                             commandBuffer,
3498         VkBuffer                                    _buffer,
3499         VkDeviceSize                                offset,
3500         uint32_t                                    drawCount,
3501         uint32_t                                    stride)
3502 {
3503         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3504         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3505         struct radv_draw_info info = {};
3506
3507         info.indexed = true;
3508         info.count = drawCount;
3509         info.indirect = buffer;
3510         info.indirect_offset = offset;
3511         info.stride = stride;
3512
3513         radv_draw(cmd_buffer, &info);
3514 }
3515
3516 void radv_CmdDrawIndirectCountAMD(
3517         VkCommandBuffer                             commandBuffer,
3518         VkBuffer                                    _buffer,
3519         VkDeviceSize                                offset,
3520         VkBuffer                                    _countBuffer,
3521         VkDeviceSize                                countBufferOffset,
3522         uint32_t                                    maxDrawCount,
3523         uint32_t                                    stride)
3524 {
3525         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3526         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3527         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3528         struct radv_draw_info info = {};
3529
3530         info.count = maxDrawCount;
3531         info.indirect = buffer;
3532         info.indirect_offset = offset;
3533         info.count_buffer = count_buffer;
3534         info.count_buffer_offset = countBufferOffset;
3535         info.stride = stride;
3536
3537         radv_draw(cmd_buffer, &info);
3538 }
3539
3540 void radv_CmdDrawIndexedIndirectCountAMD(
3541         VkCommandBuffer                             commandBuffer,
3542         VkBuffer                                    _buffer,
3543         VkDeviceSize                                offset,
3544         VkBuffer                                    _countBuffer,
3545         VkDeviceSize                                countBufferOffset,
3546         uint32_t                                    maxDrawCount,
3547         uint32_t                                    stride)
3548 {
3549         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3550         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3551         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3552         struct radv_draw_info info = {};
3553
3554         info.indexed = true;
3555         info.count = maxDrawCount;
3556         info.indirect = buffer;
3557         info.indirect_offset = offset;
3558         info.count_buffer = count_buffer;
3559         info.count_buffer_offset = countBufferOffset;
3560         info.stride = stride;
3561
3562         radv_draw(cmd_buffer, &info);
3563 }
3564
3565 void radv_CmdDrawIndirectCountKHR(
3566         VkCommandBuffer                             commandBuffer,
3567         VkBuffer                                    _buffer,
3568         VkDeviceSize                                offset,
3569         VkBuffer                                    _countBuffer,
3570         VkDeviceSize                                countBufferOffset,
3571         uint32_t                                    maxDrawCount,
3572         uint32_t                                    stride)
3573 {
3574         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3575         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3576         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3577         struct radv_draw_info info = {};
3578
3579         info.count = maxDrawCount;
3580         info.indirect = buffer;
3581         info.indirect_offset = offset;
3582         info.count_buffer = count_buffer;
3583         info.count_buffer_offset = countBufferOffset;
3584         info.stride = stride;
3585
3586         radv_draw(cmd_buffer, &info);
3587 }
3588
3589 void radv_CmdDrawIndexedIndirectCountKHR(
3590         VkCommandBuffer                             commandBuffer,
3591         VkBuffer                                    _buffer,
3592         VkDeviceSize                                offset,
3593         VkBuffer                                    _countBuffer,
3594         VkDeviceSize                                countBufferOffset,
3595         uint32_t                                    maxDrawCount,
3596         uint32_t                                    stride)
3597 {
3598         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3599         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3600         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3601         struct radv_draw_info info = {};
3602
3603         info.indexed = true;
3604         info.count = maxDrawCount;
3605         info.indirect = buffer;
3606         info.indirect_offset = offset;
3607         info.count_buffer = count_buffer;
3608         info.count_buffer_offset = countBufferOffset;
3609         info.stride = stride;
3610
3611         radv_draw(cmd_buffer, &info);
3612 }
3613
3614 struct radv_dispatch_info {
3615         /**
3616          * Determine the layout of the grid (in block units) to be used.
3617          */
3618         uint32_t blocks[3];
3619
3620         /**
3621          * A starting offset for the grid. If unaligned is set, the offset
3622          * must still be aligned.
3623          */
3624         uint32_t offsets[3];
3625         /**
3626          * Whether it's an unaligned compute dispatch.
3627          */
3628         bool unaligned;
3629
3630         /**
3631          * Indirect compute parameters resource.
3632          */
3633         struct radv_buffer *indirect;
3634         uint64_t indirect_offset;
3635 };
3636
3637 static void
3638 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3639                            const struct radv_dispatch_info *info)
3640 {
3641         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3642         struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3643         unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3644         struct radeon_winsys *ws = cmd_buffer->device->ws;
3645         struct radeon_cmdbuf *cs = cmd_buffer->cs;
3646         struct radv_userdata_info *loc;
3647
3648         loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3649                                     AC_UD_CS_GRID_SIZE);
3650
3651         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3652
3653         if (info->indirect) {
3654                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3655
3656                 va += info->indirect->offset + info->indirect_offset;
3657
3658                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3659
3660                 if (loc->sgpr_idx != -1) {
3661                         for (unsigned i = 0; i < 3; ++i) {
3662                                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3663                                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3664                                                 COPY_DATA_DST_SEL(COPY_DATA_REG));
3665                                 radeon_emit(cs, (va +  4 * i));
3666                                 radeon_emit(cs, (va + 4 * i) >> 32);
3667                                 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3668                                                  + loc->sgpr_idx * 4) >> 2) + i);
3669                                 radeon_emit(cs, 0);
3670                         }
3671                 }
3672
3673                 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3674                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3675                                         PKT3_SHADER_TYPE_S(1));
3676                         radeon_emit(cs, va);
3677                         radeon_emit(cs, va >> 32);
3678                         radeon_emit(cs, dispatch_initiator);
3679                 } else {
3680                         radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3681                                         PKT3_SHADER_TYPE_S(1));
3682                         radeon_emit(cs, 1);
3683                         radeon_emit(cs, va);
3684                         radeon_emit(cs, va >> 32);
3685
3686                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3687                                         PKT3_SHADER_TYPE_S(1));
3688                         radeon_emit(cs, 0);
3689                         radeon_emit(cs, dispatch_initiator);
3690                 }
3691         } else {
3692                 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3693                 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3694
3695                 if (info->unaligned) {
3696                         unsigned *cs_block_size = compute_shader->info.cs.block_size;
3697                         unsigned remainder[3];
3698
3699                         /* If aligned, these should be an entire block size,
3700                          * not 0.
3701                          */
3702                         remainder[0] = blocks[0] + cs_block_size[0] -
3703                                        align_u32_npot(blocks[0], cs_block_size[0]);
3704                         remainder[1] = blocks[1] + cs_block_size[1] -
3705                                        align_u32_npot(blocks[1], cs_block_size[1]);
3706                         remainder[2] = blocks[2] + cs_block_size[2] -
3707                                        align_u32_npot(blocks[2], cs_block_size[2]);
3708
3709                         blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3710                         blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3711                         blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3712
3713                         for(unsigned i = 0; i < 3; ++i) {
3714                                 assert(offsets[i] % cs_block_size[i] == 0);
3715                                 offsets[i] /= cs_block_size[i];
3716                         }
3717
3718                         radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3719                         radeon_emit(cs,
3720                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3721                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3722                         radeon_emit(cs,
3723                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3724                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3725                         radeon_emit(cs,
3726                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3727                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3728
3729                         dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3730                 }
3731
3732                 if (loc->sgpr_idx != -1) {
3733                         assert(!loc->indirect);
3734                         assert(loc->num_sgprs == 3);
3735
3736                         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3737                                                   loc->sgpr_idx * 4, 3);
3738                         radeon_emit(cs, blocks[0]);
3739                         radeon_emit(cs, blocks[1]);
3740                         radeon_emit(cs, blocks[2]);
3741                 }
3742
3743                 if (offsets[0] || offsets[1] || offsets[2]) {
3744                         radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3745                         radeon_emit(cs, offsets[0]);
3746                         radeon_emit(cs, offsets[1]);
3747                         radeon_emit(cs, offsets[2]);
3748
3749                         /* The blocks in the packet are not counts but end values. */
3750                         for (unsigned i = 0; i < 3; ++i)
3751                                 blocks[i] += offsets[i];
3752                 } else {
3753                         dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3754                 }
3755
3756                 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3757                                 PKT3_SHADER_TYPE_S(1));
3758                 radeon_emit(cs, blocks[0]);
3759                 radeon_emit(cs, blocks[1]);
3760                 radeon_emit(cs, blocks[2]);
3761                 radeon_emit(cs, dispatch_initiator);
3762         }
3763
3764         assert(cmd_buffer->cs->cdw <= cdw_max);
3765 }
3766
3767 static void
3768 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3769 {
3770         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3771         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3772 }
3773
3774 static void
3775 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3776               const struct radv_dispatch_info *info)
3777 {
3778         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3779         bool has_prefetch =
3780                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3781         bool pipeline_is_dirty = pipeline &&
3782                                  pipeline != cmd_buffer->state.emitted_compute_pipeline;
3783
3784         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3785                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3786                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3787                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3788                 /* If we have to wait for idle, set all states first, so that
3789                  * all SET packets are processed in parallel with previous draw
3790                  * calls. Then upload descriptors, set shader pointers, and
3791                  * dispatch, and prefetch at the end. This ensures that the
3792                  * time the CUs are idle is very short. (there are only SET_SH
3793                  * packets between the wait and the draw)
3794                  */
3795                 radv_emit_compute_pipeline(cmd_buffer);
3796                 si_emit_cache_flush(cmd_buffer);
3797                 /* <-- CUs are idle here --> */
3798
3799                 radv_upload_compute_shader_descriptors(cmd_buffer);
3800
3801                 radv_emit_dispatch_packets(cmd_buffer, info);
3802                 /* <-- CUs are busy here --> */
3803
3804                 /* Start prefetches after the dispatch has been started. Both
3805                  * will run in parallel, but starting the dispatch first is
3806                  * more important.
3807                  */
3808                 if (has_prefetch && pipeline_is_dirty) {
3809                         radv_emit_shader_prefetch(cmd_buffer,
3810                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3811                 }
3812         } else {
3813                 /* If we don't wait for idle, start prefetches first, then set
3814                  * states, and dispatch at the end.
3815                  */
3816                 si_emit_cache_flush(cmd_buffer);
3817
3818                 if (has_prefetch && pipeline_is_dirty) {
3819                         radv_emit_shader_prefetch(cmd_buffer,
3820                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3821                 }
3822
3823                 radv_upload_compute_shader_descriptors(cmd_buffer);
3824
3825                 radv_emit_compute_pipeline(cmd_buffer);
3826                 radv_emit_dispatch_packets(cmd_buffer, info);
3827         }
3828
3829         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3830 }
3831
3832 void radv_CmdDispatchBase(
3833         VkCommandBuffer                             commandBuffer,
3834         uint32_t                                    base_x,
3835         uint32_t                                    base_y,
3836         uint32_t                                    base_z,
3837         uint32_t                                    x,
3838         uint32_t                                    y,
3839         uint32_t                                    z)
3840 {
3841         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3842         struct radv_dispatch_info info = {};
3843
3844         info.blocks[0] = x;
3845         info.blocks[1] = y;
3846         info.blocks[2] = z;
3847
3848         info.offsets[0] = base_x;
3849         info.offsets[1] = base_y;
3850         info.offsets[2] = base_z;
3851         radv_dispatch(cmd_buffer, &info);
3852 }
3853
3854 void radv_CmdDispatch(
3855         VkCommandBuffer                             commandBuffer,
3856         uint32_t                                    x,
3857         uint32_t                                    y,
3858         uint32_t                                    z)
3859 {
3860         radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3861 }
3862
3863 void radv_CmdDispatchIndirect(
3864         VkCommandBuffer                             commandBuffer,
3865         VkBuffer                                    _buffer,
3866         VkDeviceSize                                offset)
3867 {
3868         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3869         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3870         struct radv_dispatch_info info = {};
3871
3872         info.indirect = buffer;
3873         info.indirect_offset = offset;
3874
3875         radv_dispatch(cmd_buffer, &info);
3876 }
3877
3878 void radv_unaligned_dispatch(
3879         struct radv_cmd_buffer                      *cmd_buffer,
3880         uint32_t                                    x,
3881         uint32_t                                    y,
3882         uint32_t                                    z)
3883 {
3884         struct radv_dispatch_info info = {};
3885
3886         info.blocks[0] = x;
3887         info.blocks[1] = y;
3888         info.blocks[2] = z;
3889         info.unaligned = 1;
3890
3891         radv_dispatch(cmd_buffer, &info);
3892 }
3893
3894 void radv_CmdEndRenderPass(
3895         VkCommandBuffer                             commandBuffer)
3896 {
3897         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3898
3899         radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3900
3901         radv_cmd_buffer_resolve_subpass(cmd_buffer);
3902
3903         for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3904                 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3905                 radv_handle_subpass_image_transition(cmd_buffer,
3906                                       (VkAttachmentReference){i, layout});
3907         }
3908
3909         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3910
3911         cmd_buffer->state.pass = NULL;
3912         cmd_buffer->state.subpass = NULL;
3913         cmd_buffer->state.attachments = NULL;
3914         cmd_buffer->state.framebuffer = NULL;
3915 }
3916
3917 /*
3918  * For HTILE we have the following interesting clear words:
3919  *   0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3920  *   0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3921  *   0xfffffff0: Clear depth to 1.0
3922  *   0x00000000: Clear depth to 0.0
3923  */
3924 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3925                                   struct radv_image *image,
3926                                   const VkImageSubresourceRange *range,
3927                                   uint32_t clear_word)
3928 {
3929         assert(range->baseMipLevel == 0);
3930         assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3931         unsigned layer_count = radv_get_layerCount(image, range);
3932         uint64_t size = image->surface.htile_slice_size * layer_count;
3933         uint64_t offset = image->offset + image->htile_offset +
3934                           image->surface.htile_slice_size * range->baseArrayLayer;
3935         struct radv_cmd_state *state = &cmd_buffer->state;
3936
3937         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3938                              RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3939
3940         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3941                                               size, clear_word);
3942
3943         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3944
3945         /* Initialize the depth clear registers and update the ZRANGE_PRECISION
3946          * value for the TC-compat bug (because ZRANGE_PRECISION is 1 by
3947          * default). This is only needed whean clearing Z to 0.0f.
3948          */
3949         if (radv_image_is_tc_compat_htile(image) && clear_word == 0) {
3950                 VkImageAspectFlags aspects = VK_IMAGE_ASPECT_DEPTH_BIT;
3951                 VkClearDepthStencilValue value = {};
3952
3953                 if (vk_format_is_stencil(image->vk_format))
3954                         aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
3955
3956                 radv_set_ds_clear_metadata(cmd_buffer, image, value, aspects);
3957         }
3958 }
3959
3960 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3961                                                struct radv_image *image,
3962                                                VkImageLayout src_layout,
3963                                                VkImageLayout dst_layout,
3964                                                unsigned src_queue_mask,
3965                                                unsigned dst_queue_mask,
3966                                                const VkImageSubresourceRange *range,
3967                                                VkImageAspectFlags pending_clears)
3968 {
3969         if (!radv_image_has_htile(image))
3970                 return;
3971
3972         if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3973             (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3974             cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3975             cmd_buffer->state.render_area.extent.width == image->info.width &&
3976             cmd_buffer->state.render_area.extent.height == image->info.height) {
3977                 /* The clear will initialize htile. */
3978                 return;
3979         } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3980                    radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3981                 /* TODO: merge with the clear if applicable */
3982                 radv_initialize_htile(cmd_buffer, image, range, 0);
3983         } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3984                    radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3985                 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3986                 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3987         } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3988                    !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3989                 VkImageSubresourceRange local_range = *range;
3990                 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3991                 local_range.baseMipLevel = 0;
3992                 local_range.levelCount = 1;
3993
3994                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3995                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3996
3997                 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3998
3999                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
4000                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
4001         }
4002 }
4003
4004 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
4005                                   struct radv_image *image, uint32_t value)
4006 {
4007         struct radv_cmd_state *state = &cmd_buffer->state;
4008
4009         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4010                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4011
4012         state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
4013
4014         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4015 }
4016
4017 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
4018                          struct radv_image *image, uint32_t value)
4019 {
4020         struct radv_cmd_state *state = &cmd_buffer->state;
4021
4022         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4023                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4024
4025         state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
4026
4027         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
4028                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
4029 }
4030
4031 /**
4032  * Initialize DCC/FMASK/CMASK metadata for a color image.
4033  */
4034 static void radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer,
4035                                            struct radv_image *image,
4036                                            VkImageLayout src_layout,
4037                                            VkImageLayout dst_layout,
4038                                            unsigned src_queue_mask,
4039                                            unsigned dst_queue_mask)
4040 {
4041         if (radv_image_has_cmask(image)) {
4042                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4043
4044                 /*  TODO: clarify this. */
4045                 if (radv_image_has_fmask(image)) {
4046                         value = 0xccccccccu;
4047                 }
4048
4049                 radv_initialise_cmask(cmd_buffer, image, value);
4050         }
4051
4052         if (radv_image_has_dcc(image)) {
4053                 uint32_t value = 0xffffffffu; /* Fully expanded mode. */
4054
4055                 if (radv_layout_dcc_compressed(image, dst_layout,
4056                                                dst_queue_mask)) {
4057                         value = 0x20202020u;
4058                 }
4059
4060                 radv_initialize_dcc(cmd_buffer, image, value);
4061         }
4062 }
4063
4064 /**
4065  * Handle color image transitions for DCC/FMASK/CMASK.
4066  */
4067 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
4068                                                struct radv_image *image,
4069                                                VkImageLayout src_layout,
4070                                                VkImageLayout dst_layout,
4071                                                unsigned src_queue_mask,
4072                                                unsigned dst_queue_mask,
4073                                                const VkImageSubresourceRange *range)
4074 {
4075         if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
4076                 radv_init_color_image_metadata(cmd_buffer, image,
4077                                                src_layout, dst_layout,
4078                                                src_queue_mask, dst_queue_mask);
4079                 return;
4080         }
4081
4082         if (radv_image_has_dcc(image)) {
4083                 if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
4084                         radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
4085                 } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
4086                            !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
4087                         radv_decompress_dcc(cmd_buffer, image, range);
4088                 } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4089                            !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4090                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4091                 }
4092         } else if (radv_image_has_cmask(image) || radv_image_has_fmask(image)) {
4093                 if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
4094                     !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
4095                         radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
4096                 }
4097         }
4098 }
4099
4100 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
4101                                          struct radv_image *image,
4102                                          VkImageLayout src_layout,
4103                                          VkImageLayout dst_layout,
4104                                          uint32_t src_family,
4105                                          uint32_t dst_family,
4106                                          const VkImageSubresourceRange *range,
4107                                          VkImageAspectFlags pending_clears)
4108 {
4109         if (image->exclusive && src_family != dst_family) {
4110                 /* This is an acquire or a release operation and there will be
4111                  * a corresponding release/acquire. Do the transition in the
4112                  * most flexible queue. */
4113
4114                 assert(src_family == cmd_buffer->queue_family_index ||
4115                        dst_family == cmd_buffer->queue_family_index);
4116
4117                 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
4118                         return;
4119
4120                 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
4121                     (src_family == RADV_QUEUE_GENERAL ||
4122                      dst_family == RADV_QUEUE_GENERAL))
4123                         return;
4124         }
4125
4126         unsigned src_queue_mask =
4127                 radv_image_queue_family_mask(image, src_family,
4128                                              cmd_buffer->queue_family_index);
4129         unsigned dst_queue_mask =
4130                 radv_image_queue_family_mask(image, dst_family,
4131                                              cmd_buffer->queue_family_index);
4132
4133         if (vk_format_is_depth(image->vk_format)) {
4134                 radv_handle_depth_image_transition(cmd_buffer, image,
4135                                                    src_layout, dst_layout,
4136                                                    src_queue_mask, dst_queue_mask,
4137                                                    range, pending_clears);
4138         } else {
4139                 radv_handle_color_image_transition(cmd_buffer, image,
4140                                                    src_layout, dst_layout,
4141                                                    src_queue_mask, dst_queue_mask,
4142                                                    range);
4143         }
4144 }
4145
4146 void radv_CmdPipelineBarrier(
4147         VkCommandBuffer                             commandBuffer,
4148         VkPipelineStageFlags                        srcStageMask,
4149         VkPipelineStageFlags                        destStageMask,
4150         VkBool32                                    byRegion,
4151         uint32_t                                    memoryBarrierCount,
4152         const VkMemoryBarrier*                      pMemoryBarriers,
4153         uint32_t                                    bufferMemoryBarrierCount,
4154         const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
4155         uint32_t                                    imageMemoryBarrierCount,
4156         const VkImageMemoryBarrier*                 pImageMemoryBarriers)
4157 {
4158         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4159         enum radv_cmd_flush_bits src_flush_bits = 0;
4160         enum radv_cmd_flush_bits dst_flush_bits = 0;
4161
4162         for (uint32_t i = 0; i < memoryBarrierCount; i++) {
4163                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
4164                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
4165                                                         NULL);
4166         }
4167
4168         for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
4169                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
4170                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
4171                                                         NULL);
4172         }
4173
4174         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4175                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4176                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
4177                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
4178                                                         image);
4179         }
4180
4181         radv_stage_flush(cmd_buffer, srcStageMask);
4182         cmd_buffer->state.flush_bits |= src_flush_bits;
4183
4184         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4185                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4186                 radv_handle_image_transition(cmd_buffer, image,
4187                                              pImageMemoryBarriers[i].oldLayout,
4188                                              pImageMemoryBarriers[i].newLayout,
4189                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
4190                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
4191                                              &pImageMemoryBarriers[i].subresourceRange,
4192                                              0);
4193         }
4194
4195         cmd_buffer->state.flush_bits |= dst_flush_bits;
4196 }
4197
4198
4199 static void write_event(struct radv_cmd_buffer *cmd_buffer,
4200                         struct radv_event *event,
4201                         VkPipelineStageFlags stageMask,
4202                         unsigned value)
4203 {
4204         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4205         uint64_t va = radv_buffer_get_va(event->bo);
4206
4207         radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4208
4209         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
4210
4211         /* TODO: this is overkill. Probably should figure something out from
4212          * the stage mask. */
4213
4214         si_cs_emit_write_event_eop(cs,
4215                                    cmd_buffer->state.predicating,
4216                                    cmd_buffer->device->physical_device->rad_info.chip_class,
4217                                    radv_cmd_buffer_uses_mec(cmd_buffer),
4218                                    V_028A90_BOTTOM_OF_PIPE_TS, 0,
4219                                    1, va, 2, value);
4220
4221         assert(cmd_buffer->cs->cdw <= cdw_max);
4222 }
4223
4224 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
4225                       VkEvent _event,
4226                       VkPipelineStageFlags stageMask)
4227 {
4228         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4229         RADV_FROM_HANDLE(radv_event, event, _event);
4230
4231         write_event(cmd_buffer, event, stageMask, 1);
4232 }
4233
4234 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
4235                         VkEvent _event,
4236                         VkPipelineStageFlags stageMask)
4237 {
4238         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4239         RADV_FROM_HANDLE(radv_event, event, _event);
4240
4241         write_event(cmd_buffer, event, stageMask, 0);
4242 }
4243
4244 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
4245                         uint32_t eventCount,
4246                         const VkEvent* pEvents,
4247                         VkPipelineStageFlags srcStageMask,
4248                         VkPipelineStageFlags dstStageMask,
4249                         uint32_t memoryBarrierCount,
4250                         const VkMemoryBarrier* pMemoryBarriers,
4251                         uint32_t bufferMemoryBarrierCount,
4252                         const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4253                         uint32_t imageMemoryBarrierCount,
4254                         const VkImageMemoryBarrier* pImageMemoryBarriers)
4255 {
4256         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4257         struct radeon_cmdbuf *cs = cmd_buffer->cs;
4258
4259         for (unsigned i = 0; i < eventCount; ++i) {
4260                 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4261                 uint64_t va = radv_buffer_get_va(event->bo);
4262
4263                 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4264
4265                 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4266
4267                 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4268                 assert(cmd_buffer->cs->cdw <= cdw_max);
4269         }
4270
4271
4272         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4273                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4274
4275                 radv_handle_image_transition(cmd_buffer, image,
4276                                              pImageMemoryBarriers[i].oldLayout,
4277                                              pImageMemoryBarriers[i].newLayout,
4278                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
4279                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
4280                                              &pImageMemoryBarriers[i].subresourceRange,
4281                                              0);
4282         }
4283
4284         /* TODO: figure out how to do memory barriers without waiting */
4285         cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4286                                         RADV_CMD_FLAG_INV_GLOBAL_L2 |
4287                                         RADV_CMD_FLAG_INV_VMEM_L1 |
4288                                         RADV_CMD_FLAG_INV_SMEM_L1;
4289 }
4290
4291
4292 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4293                            uint32_t deviceMask)
4294 {
4295    /* No-op */
4296 }