src/amd/vulkan/radv_cmd_buffer.c

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #include "radv_private.h"
  29 #include "radv_radeon_winsys.h"
  30 #include "radv_shader.h"
  31 #include "radv_cs.h"
  32 #include "sid.h"
  33 #include "gfx9d.h"
  34 #include "vk_format.h"
  35 #include "radv_debug.h"
  36 #include "radv_meta.h"
  37
  38 #include "ac_debug.h"
  39
  40 enum {
  41         RADV_PREFETCH_VBO_DESCRIPTORS   = (1 << 0),
  42         RADV_PREFETCH_VS                = (1 << 1),
  43         RADV_PREFETCH_TCS               = (1 << 2),
  44         RADV_PREFETCH_TES               = (1 << 3),
  45         RADV_PREFETCH_GS                = (1 << 4),
  46         RADV_PREFETCH_PS                = (1 << 5),
  47         RADV_PREFETCH_SHADERS           = (RADV_PREFETCH_VS  |
  48                                            RADV_PREFETCH_TCS |
  49                                            RADV_PREFETCH_TES |
  50                                            RADV_PREFETCH_GS  |
  51                                            RADV_PREFETCH_PS)
  52 };
  53
  54 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
  55                                          struct radv_image *image,
  56                                          VkImageLayout src_layout,
  57                                          VkImageLayout dst_layout,
  58                                          uint32_t src_family,
  59                                          uint32_t dst_family,
  60                                          const VkImageSubresourceRange *range,
  61                                          VkImageAspectFlags pending_clears);
  62
  63 const struct radv_dynamic_state default_dynamic_state = {
  64         .viewport = {
  65                 .count = 0,
  66         },
  67         .scissor = {
  68                 .count = 0,
  69         },
  70         .line_width = 1.0f,
  71         .depth_bias = {
  72                 .bias = 0.0f,
  73                 .clamp = 0.0f,
  74                 .slope = 0.0f,
  75         },
  76         .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
  77         .depth_bounds = {
  78                 .min = 0.0f,
  79                 .max = 1.0f,
  80         },
  81         .stencil_compare_mask = {
  82                 .front = ~0u,
  83                 .back = ~0u,
  84         },
  85         .stencil_write_mask = {
  86                 .front = ~0u,
  87                 .back = ~0u,
  88         },
  89         .stencil_reference = {
  90                 .front = 0u,
  91                 .back = 0u,
  92         },
  93 };
  94
  95 static void
  96 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer,
  97                         const struct radv_dynamic_state *src)
  98 {
  99         struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;
 100         uint32_t copy_mask = src->mask;
 101         uint32_t dest_mask = 0;
 102
 103         /* Make sure to copy the number of viewports/scissors because they can
 104          * only be specified at pipeline creation time.
 105          */
 106         dest->viewport.count = src->viewport.count;
 107         dest->scissor.count = src->scissor.count;
 108         dest->discard_rectangle.count = src->discard_rectangle.count;
 109
 110         if (copy_mask & RADV_DYNAMIC_VIEWPORT) {
 111                 if (memcmp(&dest->viewport.viewports, &src->viewport.viewports,
 112                            src->viewport.count * sizeof(VkViewport))) {
 113                         typed_memcpy(dest->viewport.viewports,
 114                                      src->viewport.viewports,
 115                                      src->viewport.count);
 116                         dest_mask |= RADV_DYNAMIC_VIEWPORT;
 117                 }
 118         }
 119
 120         if (copy_mask & RADV_DYNAMIC_SCISSOR) {
 121                 if (memcmp(&dest->scissor.scissors, &src->scissor.scissors,
 122                            src->scissor.count * sizeof(VkRect2D))) {
 123                         typed_memcpy(dest->scissor.scissors,
 124                                      src->scissor.scissors, src->scissor.count);
 125                         dest_mask |= RADV_DYNAMIC_SCISSOR;
 126                 }
 127         }
 128
 129         if (copy_mask & RADV_DYNAMIC_LINE_WIDTH) {
 130                 if (dest->line_width != src->line_width) {
 131                         dest->line_width = src->line_width;
 132                         dest_mask |= RADV_DYNAMIC_LINE_WIDTH;
 133                 }
 134         }
 135
 136         if (copy_mask & RADV_DYNAMIC_DEPTH_BIAS) {
 137                 if (memcmp(&dest->depth_bias, &src->depth_bias,
 138                            sizeof(src->depth_bias))) {
 139                         dest->depth_bias = src->depth_bias;
 140                         dest_mask |= RADV_DYNAMIC_DEPTH_BIAS;
 141                 }
 142         }
 143
 144         if (copy_mask & RADV_DYNAMIC_BLEND_CONSTANTS) {
 145                 if (memcmp(&dest->blend_constants, &src->blend_constants,
 146                            sizeof(src->blend_constants))) {
 147                         typed_memcpy(dest->blend_constants,
 148                                      src->blend_constants, 4);
 149                         dest_mask |= RADV_DYNAMIC_BLEND_CONSTANTS;
 150                 }
 151         }
 152
 153         if (copy_mask & RADV_DYNAMIC_DEPTH_BOUNDS) {
 154                 if (memcmp(&dest->depth_bounds, &src->depth_bounds,
 155                            sizeof(src->depth_bounds))) {
 156                         dest->depth_bounds = src->depth_bounds;
 157                         dest_mask |= RADV_DYNAMIC_DEPTH_BOUNDS;
 158                 }
 159         }
 160
 161         if (copy_mask & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
 162                 if (memcmp(&dest->stencil_compare_mask,
 163                            &src->stencil_compare_mask,
 164                            sizeof(src->stencil_compare_mask))) {
 165                         dest->stencil_compare_mask = src->stencil_compare_mask;
 166                         dest_mask |= RADV_DYNAMIC_STENCIL_COMPARE_MASK;
 167                 }
 168         }
 169
 170         if (copy_mask & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
 171                 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask,
 172                            sizeof(src->stencil_write_mask))) {
 173                         dest->stencil_write_mask = src->stencil_write_mask;
 174                         dest_mask |= RADV_DYNAMIC_STENCIL_WRITE_MASK;
 175                 }
 176         }
 177
 178         if (copy_mask & RADV_DYNAMIC_STENCIL_REFERENCE) {
 179                 if (memcmp(&dest->stencil_reference, &src->stencil_reference,
 180                            sizeof(src->stencil_reference))) {
 181                         dest->stencil_reference = src->stencil_reference;
 182                         dest_mask |= RADV_DYNAMIC_STENCIL_REFERENCE;
 183                 }
 184         }
 185
 186         if (copy_mask & RADV_DYNAMIC_DISCARD_RECTANGLE) {
 187                 if (memcmp(&dest->discard_rectangle.rectangles, &src->discard_rectangle.rectangles,
 188                            src->discard_rectangle.count * sizeof(VkRect2D))) {
 189                         typed_memcpy(dest->discard_rectangle.rectangles,
 190                                      src->discard_rectangle.rectangles,
 191                                      src->discard_rectangle.count);
 192                         dest_mask |= RADV_DYNAMIC_DISCARD_RECTANGLE;
 193                 }
 194         }
 195
 196         cmd_buffer->state.dirty |= dest_mask;
 197 }
 198
 199 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
 200 {
 201         return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
 202                cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
 203 }
 204
 205 enum ring_type radv_queue_family_to_ring(int f) {
 206         switch (f) {
 207         case RADV_QUEUE_GENERAL:
 208                 return RING_GFX;
 209         case RADV_QUEUE_COMPUTE:
 210                 return RING_COMPUTE;
 211         case RADV_QUEUE_TRANSFER:
 212                 return RING_DMA;
 213         default:
 214                 unreachable("Unknown queue family");
 215         }
 216 }
 217
 218 static VkResult radv_create_cmd_buffer(
 219         struct radv_device *                         device,
 220         struct radv_cmd_pool *                       pool,
 221         VkCommandBufferLevel                        level,
 222         VkCommandBuffer*                            pCommandBuffer)
 223 {
 224         struct radv_cmd_buffer *cmd_buffer;
 225         unsigned ring;
 226         cmd_buffer = vk_zalloc(&pool->alloc, sizeof(*cmd_buffer), 8,
 227                                VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
 228         if (cmd_buffer == NULL)
 229                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 230
 231         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
 232         cmd_buffer->device = device;
 233         cmd_buffer->pool = pool;
 234         cmd_buffer->level = level;
 235
 236         if (pool) {
 237                 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
 238                 cmd_buffer->queue_family_index = pool->queue_family_index;
 239
 240         } else {
 241                 /* Init the pool_link so we can safefly call list_del when we destroy
 242                  * the command buffer
 243                  */
 244                 list_inithead(&cmd_buffer->pool_link);
 245                 cmd_buffer->queue_family_index = RADV_QUEUE_GENERAL;
 246         }
 247
 248         ring = radv_queue_family_to_ring(cmd_buffer->queue_family_index);
 249
 250         cmd_buffer->cs = device->ws->cs_create(device->ws, ring);
 251         if (!cmd_buffer->cs) {
 252                 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 253                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
 254         }
 255
 256         *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);
 257
 258         list_inithead(&cmd_buffer->upload.list);
 259
 260         return VK_SUCCESS;
 261 }
 262
 263 static void
 264 radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
 265 {
 266         list_del(&cmd_buffer->pool_link);
 267
 268         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 269                                  &cmd_buffer->upload.list, list) {
 270                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 271                 list_del(&up->list);
 272                 free(up);
 273         }
 274
 275         if (cmd_buffer->upload.upload_bo)
 276                 cmd_buffer->device->ws->buffer_destroy(cmd_buffer->upload.upload_bo);
 277         cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);
 278
 279         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++)
 280                 free(cmd_buffer->descriptors[i].push_set.set.mapped_ptr);
 281
 282         vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
 283 }
 284
 285 static VkResult
 286 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
 287 {
 288
 289         cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
 290
 291         list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
 292                                  &cmd_buffer->upload.list, list) {
 293                 cmd_buffer->device->ws->buffer_destroy(up->upload_bo);
 294                 list_del(&up->list);
 295                 free(up);
 296         }
 297
 298         cmd_buffer->push_constant_stages = 0;
 299         cmd_buffer->scratch_size_needed = 0;
 300         cmd_buffer->compute_scratch_size_needed = 0;
 301         cmd_buffer->esgs_ring_size_needed = 0;
 302         cmd_buffer->gsvs_ring_size_needed = 0;
 303         cmd_buffer->tess_rings_needed = false;
 304         cmd_buffer->sample_positions_needed = false;
 305
 306         if (cmd_buffer->upload.upload_bo)
 307                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 308                                    cmd_buffer->upload.upload_bo, 8);
 309         cmd_buffer->upload.offset = 0;
 310
 311         cmd_buffer->record_result = VK_SUCCESS;
 312
 313         cmd_buffer->ring_offsets_idx = -1;
 314
 315         for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
 316                 cmd_buffer->descriptors[i].dirty = 0;
 317                 cmd_buffer->descriptors[i].valid = 0;
 318                 cmd_buffer->descriptors[i].push_dirty = false;
 319         }
 320
 321         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 322                 void *fence_ptr;
 323                 radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0,
 324                                              &cmd_buffer->gfx9_fence_offset,
 325                                              &fence_ptr);
 326                 cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo;
 327         }
 328
 329         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
 330
 331         return cmd_buffer->record_result;
 332 }
 333
 334 static bool
 335 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
 336                                   uint64_t min_needed)
 337 {
 338         uint64_t new_size;
 339         struct radeon_winsys_bo *bo;
 340         struct radv_cmd_buffer_upload *upload;
 341         struct radv_device *device = cmd_buffer->device;
 342
 343         new_size = MAX2(min_needed, 16 * 1024);
 344         new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);
 345
 346         bo = device->ws->buffer_create(device->ws,
 347                                        new_size, 4096,
 348                                        RADEON_DOMAIN_GTT,
 349                                        RADEON_FLAG_CPU_ACCESS|
 350                                        RADEON_FLAG_NO_INTERPROCESS_SHARING);
 351
 352         if (!bo) {
 353                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 354                 return false;
 355         }
 356
 357         radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo, 8);
 358         if (cmd_buffer->upload.upload_bo) {
 359                 upload = malloc(sizeof(*upload));
 360
 361                 if (!upload) {
 362                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
 363                         device->ws->buffer_destroy(bo);
 364                         return false;
 365                 }
 366
 367                 memcpy(upload, &cmd_buffer->upload, sizeof(*upload));
 368                 list_add(&upload->list, &cmd_buffer->upload.list);
 369         }
 370
 371         cmd_buffer->upload.upload_bo = bo;
 372         cmd_buffer->upload.size = new_size;
 373         cmd_buffer->upload.offset = 0;
 374         cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);
 375
 376         if (!cmd_buffer->upload.map) {
 377                 cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
 378                 return false;
 379         }
 380
 381         return true;
 382 }
 383
 384 bool
 385 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
 386                              unsigned size,
 387                              unsigned alignment,
 388                              unsigned *out_offset,
 389                              void **ptr)
 390 {
 391         uint64_t offset = align(cmd_buffer->upload.offset, alignment);
 392         if (offset + size > cmd_buffer->upload.size) {
 393                 if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))
 394                         return false;
 395                 offset = 0;
 396         }
 397
 398         *out_offset = offset;
 399         *ptr = cmd_buffer->upload.map + offset;
 400
 401         cmd_buffer->upload.offset = offset + size;
 402         return true;
 403 }
 404
 405 bool
 406 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
 407                             unsigned size, unsigned alignment,
 408                             const void *data, unsigned *out_offset)
 409 {
 410         uint8_t *ptr;
 411
 412         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, alignment,
 413                                           out_offset, (void **)&ptr))
 414                 return false;
 415
 416         if (ptr)
 417                 memcpy(ptr, data, size);
 418
 419         return true;
 420 }
 421
 422 static void
 423 radv_emit_write_data_packet(struct radeon_winsys_cs *cs, uint64_t va,
 424                             unsigned count, const uint32_t *data)
 425 {
 426         radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));
 427         radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
 428                     S_370_WR_CONFIRM(1) |
 429                     S_370_ENGINE_SEL(V_370_ME));
 430         radeon_emit(cs, va);
 431         radeon_emit(cs, va >> 32);
 432         radeon_emit_array(cs, data, count);
 433 }
 434
 435 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)
 436 {
 437         struct radv_device *device = cmd_buffer->device;
 438         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 439         uint64_t va;
 440
 441         va = radv_buffer_get_va(device->trace_bo);
 442         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)
 443                 va += 4;
 444
 445         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 7);
 446
 447         ++cmd_buffer->state.trace_id;
 448         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 449         radv_emit_write_data_packet(cs, va, 1, &cmd_buffer->state.trace_id);
 450         radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
 451         radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));
 452 }
 453
 454 static void
 455 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer,
 456                            enum radv_cmd_flush_bits flags)
 457 {
 458         if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
 459                 uint32_t *ptr = NULL;
 460                 uint64_t va = 0;
 461
 462                 assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
 463                                 RADV_CMD_FLAG_CS_PARTIAL_FLUSH));
 464
 465                 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
 466                         va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) +
 467                              cmd_buffer->gfx9_fence_offset;
 468                         ptr = &cmd_buffer->gfx9_fence_idx;
 469                 }
 470
 471                 /* Force wait for graphics or compute engines to be idle. */
 472                 si_cs_emit_cache_flush(cmd_buffer->cs,
 473                                        cmd_buffer->device->physical_device->rad_info.chip_class,
 474                                        ptr, va,
 475                                        radv_cmd_buffer_uses_mec(cmd_buffer),
 476                                        flags);
 477         }
 478
 479         if (unlikely(cmd_buffer->device->trace_bo))
 480                 radv_cmd_buffer_trace_emit(cmd_buffer);
 481 }
 482
 483 static void
 484 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer,
 485                    struct radv_pipeline *pipeline, enum ring_type ring)
 486 {
 487         struct radv_device *device = cmd_buffer->device;
 488         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 489         uint32_t data[2];
 490         uint64_t va;
 491
 492         va = radv_buffer_get_va(device->trace_bo);
 493
 494         switch (ring) {
 495         case RING_GFX:
 496                 va += 8;
 497                 break;
 498         case RING_COMPUTE:
 499                 va += 16;
 500                 break;
 501         default:
 502                 assert(!"invalid ring type");
 503         }
 504
 505         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 506                                                            cmd_buffer->cs, 6);
 507
 508         data[0] = (uintptr_t)pipeline;
 509         data[1] = (uintptr_t)pipeline >> 32;
 510
 511         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 512         radv_emit_write_data_packet(cs, va, 2, data);
 513 }
 514
 515 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 516                              VkPipelineBindPoint bind_point,
 517                              struct radv_descriptor_set *set,
 518                              unsigned idx)
 519 {
 520         struct radv_descriptor_state *descriptors_state =
 521                 radv_get_descriptors_state(cmd_buffer, bind_point);
 522
 523         descriptors_state->sets[idx] = set;
 524         if (set)
 525                 descriptors_state->valid |= (1u << idx);
 526         else
 527                 descriptors_state->valid &= ~(1u << idx);
 528         descriptors_state->dirty |= (1u << idx);
 529 }
 530
 531 static void
 532 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer,
 533                       VkPipelineBindPoint bind_point)
 534 {
 535         struct radv_descriptor_state *descriptors_state =
 536                 radv_get_descriptors_state(cmd_buffer, bind_point);
 537         struct radv_device *device = cmd_buffer->device;
 538         struct radeon_winsys_cs *cs = cmd_buffer->cs;
 539         uint32_t data[MAX_SETS * 2] = {};
 540         uint64_t va;
 541         unsigned i;
 542         va = radv_buffer_get_va(device->trace_bo) + 24;
 543
 544         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(device->ws,
 545                                                            cmd_buffer->cs, 4 + MAX_SETS * 2);
 546
 547         for_each_bit(i, descriptors_state->valid) {
 548                 struct radv_descriptor_set *set = descriptors_state->sets[i];
 549                 data[i * 2] = (uintptr_t)set;
 550                 data[i * 2 + 1] = (uintptr_t)set >> 32;
 551         }
 552
 553         radv_cs_add_buffer(device->ws, cs, device->trace_bo, 8);
 554         radv_emit_write_data_packet(cs, va, MAX_SETS * 2, data);
 555 }
 556
 557 struct radv_userdata_info *
 558 radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
 559                       gl_shader_stage stage,
 560                       int idx)
 561 {
 562         if (stage == MESA_SHADER_VERTEX) {
 563                 if (pipeline->shaders[MESA_SHADER_VERTEX])
 564                         return &pipeline->shaders[MESA_SHADER_VERTEX]->info.user_sgprs_locs.shader_data[idx];
 565                 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
 566                         return &pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.user_sgprs_locs.shader_data[idx];
 567                 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
 568                         return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
 569         } else if (stage == MESA_SHADER_TESS_EVAL) {
 570                 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
 571                         return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.user_sgprs_locs.shader_data[idx];
 572                 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
 573                         return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.user_sgprs_locs.shader_data[idx];
 574         }
 575         return &pipeline->shaders[stage]->info.user_sgprs_locs.shader_data[idx];
 576 }
 577
 578 static void
 579 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer,
 580                            struct radv_pipeline *pipeline,
 581                            gl_shader_stage stage,
 582                            int idx, uint64_t va)
 583 {
 584         struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, idx);
 585         uint32_t base_reg = pipeline->user_data_0[stage];
 586         if (loc->sgpr_idx == -1)
 587                 return;
 588         assert(loc->num_sgprs == 2);
 589         assert(!loc->indirect);
 590         radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
 591         radeon_emit(cmd_buffer->cs, va);
 592         radeon_emit(cmd_buffer->cs, va >> 32);
 593 }
 594
 595 static void
 596 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
 597                               struct radv_pipeline *pipeline)
 598 {
 599         int num_samples = pipeline->graphics.ms.num_samples;
 600         struct radv_multisample_state *ms = &pipeline->graphics.ms;
 601         struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;
 602
 603         if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.needs_sample_positions)
 604                 cmd_buffer->sample_positions_needed = true;
 605
 606         if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
 607                 return;
 608
 609         radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
 610         radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
 611         radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
 612
 613         radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
 614
 615         radv_cayman_emit_msaa_sample_locs(cmd_buffer->cs, num_samples);
 616
 617         /* GFX9: Flush DFSM when the AA mode changes. */
 618         if (cmd_buffer->device->dfsm_allowed) {
 619                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 620                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
 621         }
 622 }
 623
 624 static void
 625 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
 626                           struct radv_shader_variant *shader)
 627 {
 628         uint64_t va;
 629
 630         if (!shader)
 631                 return;
 632
 633         va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 634
 635         si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
 636 }
 637
 638 static void
 639 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
 640                       struct radv_pipeline *pipeline,
 641                       bool vertex_stage_only)
 642 {
 643         struct radv_cmd_state *state = &cmd_buffer->state;
 644         uint32_t mask = state->prefetch_L2_mask;
 645
 646         if (vertex_stage_only) {
 647                 /* Fast prefetch path for starting draws as soon as possible.
 648                  */
 649                 mask = state->prefetch_L2_mask & (RADV_PREFETCH_VS |
 650                                                   RADV_PREFETCH_VBO_DESCRIPTORS);
 651         }
 652
 653         if (mask & RADV_PREFETCH_VS)
 654                 radv_emit_shader_prefetch(cmd_buffer,
 655                                           pipeline->shaders[MESA_SHADER_VERTEX]);
 656
 657         if (mask & RADV_PREFETCH_VBO_DESCRIPTORS)
 658                 si_cp_dma_prefetch(cmd_buffer, state->vb_va, state->vb_size);
 659
 660         if (mask & RADV_PREFETCH_TCS)
 661                 radv_emit_shader_prefetch(cmd_buffer,
 662                                           pipeline->shaders[MESA_SHADER_TESS_CTRL]);
 663
 664         if (mask & RADV_PREFETCH_TES)
 665                 radv_emit_shader_prefetch(cmd_buffer,
 666                                           pipeline->shaders[MESA_SHADER_TESS_EVAL]);
 667
 668         if (mask & RADV_PREFETCH_GS) {
 669                 radv_emit_shader_prefetch(cmd_buffer,
 670                                           pipeline->shaders[MESA_SHADER_GEOMETRY]);
 671                 radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);
 672         }
 673
 674         if (mask & RADV_PREFETCH_PS)
 675                 radv_emit_shader_prefetch(cmd_buffer,
 676                                           pipeline->shaders[MESA_SHADER_FRAGMENT]);
 677
 678         state->prefetch_L2_mask &= ~mask;
 679 }
 680
 681 static void
 682 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
 683 {
 684         if (!cmd_buffer->device->physical_device->rbplus_allowed)
 685                 return;
 686
 687         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 688         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
 689         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 690
 691         unsigned sx_ps_downconvert = 0;
 692         unsigned sx_blend_opt_epsilon = 0;
 693         unsigned sx_blend_opt_control = 0;
 694
 695         for (unsigned i = 0; i < subpass->color_count; ++i) {
 696                 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
 697                         continue;
 698
 699                 int idx = subpass->color_attachments[i].attachment;
 700                 struct radv_color_buffer_info *cb = &framebuffer->attachments[idx].cb;
 701
 702                 unsigned format = G_028C70_FORMAT(cb->cb_color_info);
 703                 unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
 704                 uint32_t spi_format = (pipeline->graphics.col_format >> (i * 4)) & 0xf;
 705                 uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 4)) & 0xf;
 706
 707                 bool has_alpha, has_rgb;
 708
 709                 /* Set if RGB and A are present. */
 710                 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
 711
 712                 if (format == V_028C70_COLOR_8 ||
 713                     format == V_028C70_COLOR_16 ||
 714                     format == V_028C70_COLOR_32)
 715                         has_rgb = !has_alpha;
 716                 else
 717                         has_rgb = true;
 718
 719                 /* Check the colormask and export format. */
 720                 if (!(colormask & 0x7))
 721                         has_rgb = false;
 722                 if (!(colormask & 0x8))
 723                         has_alpha = false;
 724
 725                 if (spi_format == V_028714_SPI_SHADER_ZERO) {
 726                         has_rgb = false;
 727                         has_alpha = false;
 728                 }
 729
 730                 /* Disable value checking for disabled channels. */
 731                 if (!has_rgb)
 732                         sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
 733                 if (!has_alpha)
 734                         sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
 735
 736                 /* Enable down-conversion for 32bpp and smaller formats. */
 737                 switch (format) {
 738                 case V_028C70_COLOR_8:
 739                 case V_028C70_COLOR_8_8:
 740                 case V_028C70_COLOR_8_8_8_8:
 741                         /* For 1 and 2-channel formats, use the superset thereof. */
 742                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
 743                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 744                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 745                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
 746                                 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
 747                         }
 748                         break;
 749
 750                 case V_028C70_COLOR_5_6_5:
 751                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 752                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
 753                                 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
 754                         }
 755                         break;
 756
 757                 case V_028C70_COLOR_1_5_5_5:
 758                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 759                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
 760                                 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
 761                         }
 762                         break;
 763
 764                 case V_028C70_COLOR_4_4_4_4:
 765                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 766                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
 767                                 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
 768                         }
 769                         break;
 770
 771                 case V_028C70_COLOR_32:
 772                         if (swap == V_028C70_SWAP_STD &&
 773                             spi_format == V_028714_SPI_SHADER_32_R)
 774                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
 775                         else if (swap == V_028C70_SWAP_ALT_REV &&
 776                                  spi_format == V_028714_SPI_SHADER_32_AR)
 777                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
 778                         break;
 779
 780                 case V_028C70_COLOR_16:
 781                 case V_028C70_COLOR_16_16:
 782                         /* For 1-channel formats, use the superset thereof. */
 783                         if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
 784                             spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
 785                             spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
 786                             spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
 787                                 if (swap == V_028C70_SWAP_STD ||
 788                                     swap == V_028C70_SWAP_STD_REV)
 789                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
 790                                 else
 791                                         sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
 792                         }
 793                         break;
 794
 795                 case V_028C70_COLOR_10_11_11:
 796                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 797                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
 798                                 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
 799                         }
 800                         break;
 801
 802                 case V_028C70_COLOR_2_10_10_10:
 803                         if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
 804                                 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
 805                                 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
 806                         }
 807                         break;
 808                 }
 809         }
 810
 811         radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);
 812         radeon_emit(cmd_buffer->cs, sx_ps_downconvert);
 813         radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);
 814         radeon_emit(cmd_buffer->cs, sx_blend_opt_control);
 815 }
 816
 817 static void
 818 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
 819 {
 820         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
 821
 822         if (!pipeline || cmd_buffer->state.emitted_pipeline == pipeline)
 823                 return;
 824
 825         radv_update_multisample_state(cmd_buffer, pipeline);
 826
 827         cmd_buffer->scratch_size_needed =
 828                                   MAX2(cmd_buffer->scratch_size_needed,
 829                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
 830
 831         if (!cmd_buffer->state.emitted_pipeline ||
 832             cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=
 833              pipeline->graphics.can_use_guardband)
 834                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
 835
 836         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
 837
 838         for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
 839                 if (!pipeline->shaders[i])
 840                         continue;
 841
 842                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 843                                    pipeline->shaders[i]->bo, 8);
 844         }
 845
 846         if (radv_pipeline_has_gs(pipeline))
 847                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
 848                                    pipeline->gs_copy_shader->bo, 8);
 849
 850         if (unlikely(cmd_buffer->device->trace_bo))
 851                 radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
 852
 853         cmd_buffer->state.emitted_pipeline = pipeline;
 854
 855         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;
 856 }
 857
 858 static void
 859 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)
 860 {
 861         si_write_viewport(cmd_buffer->cs, 0, cmd_buffer->state.dynamic.viewport.count,
 862                           cmd_buffer->state.dynamic.viewport.viewports);
 863 }
 864
 865 static void
 866 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
 867 {
 868         uint32_t count = cmd_buffer->state.dynamic.scissor.count;
 869
 870         /* Vega10/Raven scissor bug workaround. This must be done before VPORT
 871          * scissor registers are changed. There is also a more efficient but
 872          * more involved alternative workaround.
 873          */
 874         if (cmd_buffer->device->physical_device->has_scissor_bug) {
 875                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
 876                 si_emit_cache_flush(cmd_buffer);
 877         }
 878         si_write_scissors(cmd_buffer->cs, 0, count,
 879                           cmd_buffer->state.dynamic.scissor.scissors,
 880                           cmd_buffer->state.dynamic.viewport.viewports,
 881                           cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);
 882 }
 883
 884 static void
 885 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)
 886 {
 887         if (!cmd_buffer->state.dynamic.discard_rectangle.count)
 888                 return;
 889
 890         radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,
 891                                    cmd_buffer->state.dynamic.discard_rectangle.count * 2);
 892         for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {
 893                 VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];
 894                 radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));
 895                 radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |
 896                                             S_028214_BR_Y(rect.offset.y + rect.extent.height));
 897         }
 898 }
 899
 900 static void
 901 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)
 902 {
 903         unsigned width = cmd_buffer->state.dynamic.line_width * 8;
 904
 905         radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,
 906                                S_028A08_WIDTH(CLAMP(width, 0, 0xFFF)));
 907 }
 908
 909 static void
 910 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)
 911 {
 912         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 913
 914         radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);
 915         radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);
 916 }
 917
 918 static void
 919 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)
 920 {
 921         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 922
 923         radeon_set_context_reg_seq(cmd_buffer->cs,
 924                                    R_028430_DB_STENCILREFMASK, 2);
 925         radeon_emit(cmd_buffer->cs,
 926                     S_028430_STENCILTESTVAL(d->stencil_reference.front) |
 927                     S_028430_STENCILMASK(d->stencil_compare_mask.front) |
 928                     S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) |
 929                     S_028430_STENCILOPVAL(1));
 930         radeon_emit(cmd_buffer->cs,
 931                     S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |
 932                     S_028434_STENCILMASK_BF(d->stencil_compare_mask.back) |
 933                     S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) |
 934                     S_028434_STENCILOPVAL_BF(1));
 935 }
 936
 937 static void
 938 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)
 939 {
 940         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 941
 942         radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN,
 943                                fui(d->depth_bounds.min));
 944         radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX,
 945                                fui(d->depth_bounds.max));
 946 }
 947
 948 static void
 949 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)
 950 {
 951         struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;
 952         unsigned slope = fui(d->depth_bias.slope * 16.0f);
 953         unsigned bias = fui(d->depth_bias.bias * cmd_buffer->state.offset_scale);
 954
 955
 956         radeon_set_context_reg_seq(cmd_buffer->cs,
 957                                    R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);
 958         radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */
 959         radeon_emit(cmd_buffer->cs, slope); /* FRONT SCALE */
 960         radeon_emit(cmd_buffer->cs, bias); /* FRONT OFFSET */
 961         radeon_emit(cmd_buffer->cs, slope); /* BACK SCALE */
 962         radeon_emit(cmd_buffer->cs, bias); /* BACK OFFSET */
 963 }
 964
 965 static void
 966 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
 967                          int index,
 968                          struct radv_attachment_info *att,
 969                          struct radv_image *image,
 970                          VkImageLayout layout)
 971 {
 972         bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= VI;
 973         struct radv_color_buffer_info *cb = &att->cb;
 974         uint32_t cb_color_info = cb->cb_color_info;
 975
 976         if (!radv_layout_dcc_compressed(image, layout,
 977                                         radv_image_queue_family_mask(image,
 978                                                                      cmd_buffer->queue_family_index,
 979                                                                      cmd_buffer->queue_family_index))) {
 980                 cb_color_info &= C_028C70_DCC_ENABLE;
 981         }
 982
 983         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
 984                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
 985                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
 986                 radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));
 987                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);
 988                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
 989                 radeon_emit(cmd_buffer->cs, cb_color_info);
 990                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
 991                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
 992                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
 993                 radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));
 994                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
 995                 radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));
 996
 997                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);
 998                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);
 999                 radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));
1000
1001                 radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,
1002                                        S_0287A0_EPITCH(att->attachment->image->surface.u.gfx9.surf.epitch));
1003         } else {
1004                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
1005                 radeon_emit(cmd_buffer->cs, cb->cb_color_base);
1006                 radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);
1007                 radeon_emit(cmd_buffer->cs, cb->cb_color_slice);
1008                 radeon_emit(cmd_buffer->cs, cb->cb_color_view);
1009                 radeon_emit(cmd_buffer->cs, cb_color_info);
1010                 radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);
1011                 radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);
1012                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);
1013                 radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);
1014                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);
1015                 radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);
1016
1017                 if (is_vi) { /* DCC BASE */
1018                         radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base);
1019                 }
1020         }
1021 }
1022
1023 static void
1024 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
1025                       struct radv_ds_buffer_info *ds,
1026                       struct radv_image *image,
1027                       VkImageLayout layout)
1028 {
1029         uint32_t db_z_info = ds->db_z_info;
1030         uint32_t db_stencil_info = ds->db_stencil_info;
1031
1032         if (!radv_layout_has_htile(image, layout,
1033                                    radv_image_queue_family_mask(image,
1034                                                                 cmd_buffer->queue_family_index,
1035                                                                 cmd_buffer->queue_family_index))) {
1036                 db_z_info &= C_028040_TILE_SURFACE_ENABLE;
1037                 db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1038         }
1039
1040         radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);
1041         radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, ds->db_htile_surface);
1042
1043
1044         if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1045                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);
1046                 radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
1047                 radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));
1048                 radeon_emit(cmd_buffer->cs, ds->db_depth_size);
1049
1050                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);
1051                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* DB_Z_INFO */
1052                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* DB_STENCIL_INFO */
1053                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* DB_Z_READ_BASE */
1054                 radeon_emit(cmd_buffer->cs, S_028044_BASE_HI(ds->db_z_read_base >> 32));        /* DB_Z_READ_BASE_HI */
1055                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* DB_STENCIL_READ_BASE */
1056                 radeon_emit(cmd_buffer->cs, S_02804C_BASE_HI(ds->db_stencil_read_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
1057                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* DB_Z_WRITE_BASE */
1058                 radeon_emit(cmd_buffer->cs, S_028054_BASE_HI(ds->db_z_write_base >> 32));       /* DB_Z_WRITE_BASE_HI */
1059                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* DB_STENCIL_WRITE_BASE */
1060                 radeon_emit(cmd_buffer->cs, S_02805C_BASE_HI(ds->db_stencil_write_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
1061
1062                 radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);
1063                 radeon_emit(cmd_buffer->cs, ds->db_z_info2);
1064                 radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);
1065         } else {
1066                 radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
1067
1068                 radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);
1069                 radeon_emit(cmd_buffer->cs, ds->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
1070                 radeon_emit(cmd_buffer->cs, db_z_info);                 /* R_028040_DB_Z_INFO */
1071                 radeon_emit(cmd_buffer->cs, db_stencil_info);           /* R_028044_DB_STENCIL_INFO */
1072                 radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* R_028048_DB_Z_READ_BASE */
1073                 radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* R_02804C_DB_STENCIL_READ_BASE */
1074                 radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* R_028050_DB_Z_WRITE_BASE */
1075                 radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */
1076                 radeon_emit(cmd_buffer->cs, ds->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
1077                 radeon_emit(cmd_buffer->cs, ds->db_depth_slice);        /* R_02805C_DB_DEPTH_SLICE */
1078
1079         }
1080
1081         radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1082                                ds->pa_su_poly_offset_db_fmt_cntl);
1083 }
1084
1085 void
1086 radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1087                           struct radv_image *image,
1088                           VkClearDepthStencilValue ds_clear_value,
1089                           VkImageAspectFlags aspects)
1090 {
1091         uint64_t va = radv_buffer_get_va(image->bo);
1092         va += image->offset + image->clear_value_offset;
1093         unsigned reg_offset = 0, reg_count = 0;
1094
1095         assert(radv_image_has_htile(image));
1096
1097         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1098                 ++reg_count;
1099         } else {
1100                 ++reg_offset;
1101                 va += 4;
1102         }
1103         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1104                 ++reg_count;
1105
1106         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
1107         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1108                                     S_370_WR_CONFIRM(1) |
1109                                     S_370_ENGINE_SEL(V_370_PFP));
1110         radeon_emit(cmd_buffer->cs, va);
1111         radeon_emit(cmd_buffer->cs, va >> 32);
1112         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1113                 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil);
1114         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1115                 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth));
1116
1117         radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
1118         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT)
1119                 radeon_emit(cmd_buffer->cs, ds_clear_value.stencil); /* R_028028_DB_STENCIL_CLEAR */
1120         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1121                 radeon_emit(cmd_buffer->cs, fui(ds_clear_value.depth)); /* R_02802C_DB_DEPTH_CLEAR */
1122 }
1123
1124 static void
1125 radv_load_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1126                            struct radv_image *image)
1127 {
1128         VkImageAspectFlags aspects = vk_format_aspects(image->vk_format);
1129         uint64_t va = radv_buffer_get_va(image->bo);
1130         va += image->offset + image->clear_value_offset;
1131         unsigned reg_offset = 0, reg_count = 0;
1132
1133         if (!radv_image_has_htile(image))
1134                 return;
1135
1136         if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1137                 ++reg_count;
1138         } else {
1139                 ++reg_offset;
1140                 va += 4;
1141         }
1142         if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT)
1143                 ++reg_count;
1144
1145         radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0));
1146         radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1147                                     COPY_DATA_DST_SEL(COPY_DATA_REG) |
1148                                     (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0));
1149         radeon_emit(cmd_buffer->cs, va);
1150         radeon_emit(cmd_buffer->cs, va >> 32);
1151         radeon_emit(cmd_buffer->cs, (R_028028_DB_STENCIL_CLEAR + 4 * reg_offset) >> 2);
1152         radeon_emit(cmd_buffer->cs, 0);
1153
1154         radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1155         radeon_emit(cmd_buffer->cs, 0);
1156 }
1157
1158 /*
1159  *with DCC some colors don't require CMASK elimiation before being
1160  * used as a texture. This sets a predicate value to determine if the
1161  * cmask eliminate is required.
1162  */
1163 void
1164 radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1165                                   struct radv_image *image,
1166                                   bool value)
1167 {
1168         uint64_t pred_val = value;
1169         uint64_t va = radv_buffer_get_va(image->bo);
1170         va += image->offset + image->dcc_pred_offset;
1171
1172         assert(radv_image_has_dcc(image));
1173
1174         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1175         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1176                                     S_370_WR_CONFIRM(1) |
1177                                     S_370_ENGINE_SEL(V_370_PFP));
1178         radeon_emit(cmd_buffer->cs, va);
1179         radeon_emit(cmd_buffer->cs, va >> 32);
1180         radeon_emit(cmd_buffer->cs, pred_val);
1181         radeon_emit(cmd_buffer->cs, pred_val >> 32);
1182 }
1183
1184 void
1185 radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1186                           struct radv_image *image,
1187                           int idx,
1188                           uint32_t color_values[2])
1189 {
1190         uint64_t va = radv_buffer_get_va(image->bo);
1191         va += image->offset + image->clear_value_offset;
1192
1193         assert(radv_image_has_cmask(image) || radv_image_has_dcc(image));
1194
1195         radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 4, 0));
1196         radeon_emit(cmd_buffer->cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
1197                                     S_370_WR_CONFIRM(1) |
1198                                     S_370_ENGINE_SEL(V_370_PFP));
1199         radeon_emit(cmd_buffer->cs, va);
1200         radeon_emit(cmd_buffer->cs, va >> 32);
1201         radeon_emit(cmd_buffer->cs, color_values[0]);
1202         radeon_emit(cmd_buffer->cs, color_values[1]);
1203
1204         radeon_set_context_reg_seq(cmd_buffer->cs, R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c, 2);
1205         radeon_emit(cmd_buffer->cs, color_values[0]);
1206         radeon_emit(cmd_buffer->cs, color_values[1]);
1207 }
1208
1209 static void
1210 radv_load_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1211                            struct radv_image *image,
1212                            int idx)
1213 {
1214         uint64_t va = radv_buffer_get_va(image->bo);
1215         va += image->offset + image->clear_value_offset;
1216
1217         if (!radv_image_has_cmask(image) && !radv_image_has_dcc(image))
1218                 return;
1219
1220         uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + idx * 0x3c;
1221
1222         radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
1223         radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
1224                                     COPY_DATA_DST_SEL(COPY_DATA_REG) |
1225                                     COPY_DATA_COUNT_SEL);
1226         radeon_emit(cmd_buffer->cs, va);
1227         radeon_emit(cmd_buffer->cs, va >> 32);
1228         radeon_emit(cmd_buffer->cs, reg >> 2);
1229         radeon_emit(cmd_buffer->cs, 0);
1230
1231         radeon_emit(cmd_buffer->cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1232         radeon_emit(cmd_buffer->cs, 0);
1233 }
1234
1235 static void
1236 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
1237 {
1238         int i;
1239         struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
1240         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1241
1242         /* this may happen for inherited secondary recording */
1243         if (!framebuffer)
1244                 return;
1245
1246         for (i = 0; i < 8; ++i) {
1247                 if (i >= subpass->color_count || subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
1248                         radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1249                                        S_028C70_FORMAT(V_028C70_COLOR_INVALID));
1250                         continue;
1251                 }
1252
1253                 int idx = subpass->color_attachments[i].attachment;
1254                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1255                 struct radv_image *image = att->attachment->image;
1256                 VkImageLayout layout = subpass->color_attachments[i].layout;
1257
1258                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1259
1260                 assert(att->attachment->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT);
1261                 radv_emit_fb_color_state(cmd_buffer, i, att, image, layout);
1262
1263                 radv_load_color_clear_regs(cmd_buffer, image, i);
1264         }
1265
1266         if(subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1267                 int idx = subpass->depth_stencil_attachment.attachment;
1268                 VkImageLayout layout = subpass->depth_stencil_attachment.layout;
1269                 struct radv_attachment_info *att = &framebuffer->attachments[idx];
1270                 struct radv_image *image = att->attachment->image;
1271                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, att->attachment->bo, 8);
1272                 MAYBE_UNUSED uint32_t queue_mask = radv_image_queue_family_mask(image,
1273                                                                                 cmd_buffer->queue_family_index,
1274                                                                                 cmd_buffer->queue_family_index);
1275                 /* We currently don't support writing decompressed HTILE */
1276                 assert(radv_layout_has_htile(image, layout, queue_mask) ==
1277                        radv_layout_is_htile_compressed(image, layout, queue_mask));
1278
1279                 radv_emit_fb_ds_state(cmd_buffer, &att->ds, image, layout);
1280
1281                 if (att->ds.offset_scale != cmd_buffer->state.offset_scale) {
1282                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
1283                         cmd_buffer->state.offset_scale = att->ds.offset_scale;
1284                 }
1285                 radv_load_depth_clear_regs(cmd_buffer, image);
1286         } else {
1287                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
1288                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);
1289                 else
1290                         radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);
1291
1292                 radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
1293                 radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
1294         }
1295         radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
1296                                S_028208_BR_X(framebuffer->width) |
1297                                S_028208_BR_Y(framebuffer->height));
1298
1299         if (cmd_buffer->device->dfsm_allowed) {
1300                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1301                 radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
1302         }
1303
1304         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;
1305 }
1306
1307 static void
1308 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
1309 {
1310         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1311         struct radv_cmd_state *state = &cmd_buffer->state;
1312
1313         if (state->index_type != state->last_index_type) {
1314                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
1315                         radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
1316                                                    2, state->index_type);
1317                 } else {
1318                         radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
1319                         radeon_emit(cs, state->index_type);
1320                 }
1321
1322                 state->last_index_type = state->index_type;
1323         }
1324
1325         radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
1326         radeon_emit(cs, state->index_va);
1327         radeon_emit(cs, state->index_va >> 32);
1328
1329         radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
1330         radeon_emit(cs, state->max_index_count);
1331
1332         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;
1333 }
1334
1335 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
1336 {
1337         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
1338         uint32_t pa_sc_mode_cntl_1 =
1339                 pipeline ? pipeline->graphics.ms.pa_sc_mode_cntl_1 : 0;
1340         uint32_t db_count_control;
1341
1342         if(!cmd_buffer->state.active_occlusion_queries) {
1343                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1344                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1345                             pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
1346                                 /* Re-enable out-of-order rasterization if the
1347                                  * bound pipeline supports it and if it's has
1348                                  * been disabled before starting occlusion
1349                                  * queries.
1350                                  */
1351                                 radeon_set_context_reg(cmd_buffer->cs,
1352                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1353                                                        pa_sc_mode_cntl_1);
1354                         }
1355                         db_count_control = 0;
1356                 } else {
1357                         db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1358                 }
1359         } else {
1360                 const struct radv_subpass *subpass = cmd_buffer->state.subpass;
1361                 uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
1362                 bool perfect = cmd_buffer->state.perfect_occlusion_queries_enabled;
1363
1364                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
1365                         db_count_control =
1366                                 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1367                                 S_028004_SAMPLE_RATE(sample_rate) |
1368                                 S_028004_ZPASS_ENABLE(1) |
1369                                 S_028004_SLICE_EVEN_ENABLE(1) |
1370                                 S_028004_SLICE_ODD_ENABLE(1);
1371
1372                         if (G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
1373                             pipeline->graphics.disable_out_of_order_rast_for_occlusion) {
1374                                 /* If the bound pipeline has enabled
1375                                  * out-of-order rasterization, we should
1376                                  * disable it before starting occlusion
1377                                  * queries.
1378                                  */
1379                                 pa_sc_mode_cntl_1 &= C_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE;
1380
1381                                 radeon_set_context_reg(cmd_buffer->cs,
1382                                                        R_028A4C_PA_SC_MODE_CNTL_1,
1383                                                        pa_sc_mode_cntl_1);
1384                         }
1385                 } else {
1386                         db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
1387                                 S_028004_SAMPLE_RATE(sample_rate);
1388                 }
1389         }
1390
1391         radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);
1392 }
1393
1394 static void
1395 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
1396 {
1397         uint32_t states = cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;
1398
1399         if (states & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1400                 radv_emit_viewport(cmd_buffer);
1401
1402         if (states & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT))
1403                 radv_emit_scissor(cmd_buffer);
1404
1405         if (states & RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH)
1406                 radv_emit_line_width(cmd_buffer);
1407
1408         if (states & RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS)
1409                 radv_emit_blend_constants(cmd_buffer);
1410
1411         if (states & (RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE |
1412                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
1413                                        RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK))
1414                 radv_emit_stencil(cmd_buffer);
1415
1416         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS)
1417                 radv_emit_depth_bounds(cmd_buffer);
1418
1419         if (states & RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS)
1420                 radv_emit_depth_bias(cmd_buffer);
1421
1422         if (states & RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE)
1423                 radv_emit_discard_rectangle(cmd_buffer);
1424
1425         cmd_buffer->state.dirty &= ~states;
1426 }
1427
1428 static void
1429 emit_stage_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1430                                    struct radv_pipeline *pipeline,
1431                                    int idx,
1432                                    uint64_t va,
1433                                    gl_shader_stage stage)
1434 {
1435         struct radv_userdata_info *desc_set_loc = &pipeline->shaders[stage]->info.user_sgprs_locs.descriptor_sets[idx];
1436         uint32_t base_reg = pipeline->user_data_0[stage];
1437
1438         if (desc_set_loc->sgpr_idx == -1 || desc_set_loc->indirect)
1439                 return;
1440
1441         assert(!desc_set_loc->indirect);
1442         assert(desc_set_loc->num_sgprs == 2);
1443         radeon_set_sh_reg_seq(cmd_buffer->cs,
1444                               base_reg + desc_set_loc->sgpr_idx * 4, 2);
1445         radeon_emit(cmd_buffer->cs, va);
1446         radeon_emit(cmd_buffer->cs, va >> 32);
1447 }
1448
1449 static void
1450 radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
1451                                   VkShaderStageFlags stages,
1452                                   struct radv_descriptor_set *set,
1453                                   unsigned idx)
1454 {
1455         if (cmd_buffer->state.pipeline) {
1456                 radv_foreach_stage(stage, stages) {
1457                         if (cmd_buffer->state.pipeline->shaders[stage])
1458                                 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.pipeline,
1459                                                                    idx, set->va,
1460                                                                    stage);
1461                 }
1462         }
1463
1464         if (cmd_buffer->state.compute_pipeline && (stages & VK_SHADER_STAGE_COMPUTE_BIT))
1465                 emit_stage_descriptor_set_userdata(cmd_buffer, cmd_buffer->state.compute_pipeline,
1466                                                    idx, set->va,
1467                                                    MESA_SHADER_COMPUTE);
1468 }
1469
1470 static void
1471 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer,
1472                             VkPipelineBindPoint bind_point)
1473 {
1474         struct radv_descriptor_state *descriptors_state =
1475                 radv_get_descriptors_state(cmd_buffer, bind_point);
1476         struct radv_descriptor_set *set = &descriptors_state->push_set.set;
1477         unsigned bo_offset;
1478
1479         if (!radv_cmd_buffer_upload_data(cmd_buffer, set->size, 32,
1480                                          set->mapped_ptr,
1481                                          &bo_offset))
1482                 return;
1483
1484         set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1485         set->va += bo_offset;
1486 }
1487
1488 static void
1489 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,
1490                                     VkPipelineBindPoint bind_point)
1491 {
1492         struct radv_descriptor_state *descriptors_state =
1493                 radv_get_descriptors_state(cmd_buffer, bind_point);
1494         uint32_t size = MAX_SETS * 2 * 4;
1495         uint32_t offset;
1496         void *ptr;
1497
1498         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size,
1499                                           256, &offset, &ptr))
1500                 return;
1501
1502         for (unsigned i = 0; i < MAX_SETS; i++) {
1503                 uint32_t *uptr = ((uint32_t *)ptr) + i * 2;
1504                 uint64_t set_va = 0;
1505                 struct radv_descriptor_set *set = descriptors_state->sets[i];
1506                 if (descriptors_state->valid & (1u << i))
1507                         set_va = set->va;
1508                 uptr[0] = set_va & 0xffffffff;
1509                 uptr[1] = set_va >> 32;
1510         }
1511
1512         uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1513         va += offset;
1514
1515         if (cmd_buffer->state.pipeline) {
1516                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX])
1517                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1518                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1519
1520                 if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT])
1521                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_FRAGMENT,
1522                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1523
1524                 if (radv_pipeline_has_gs(cmd_buffer->state.pipeline))
1525                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
1526                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1527
1528                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1529                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_CTRL,
1530                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1531
1532                 if (radv_pipeline_has_tess(cmd_buffer->state.pipeline))
1533                         radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_TESS_EVAL,
1534                                                    AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1535         }
1536
1537         if (cmd_buffer->state.compute_pipeline)
1538                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE,
1539                                            AC_UD_INDIRECT_DESCRIPTOR_SETS, va);
1540 }
1541
1542 static void
1543 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer,
1544                        VkShaderStageFlags stages)
1545 {
1546         VkPipelineBindPoint bind_point = stages & VK_SHADER_STAGE_COMPUTE_BIT ?
1547                                          VK_PIPELINE_BIND_POINT_COMPUTE :
1548                                          VK_PIPELINE_BIND_POINT_GRAPHICS;
1549         struct radv_descriptor_state *descriptors_state =
1550                 radv_get_descriptors_state(cmd_buffer, bind_point);
1551         unsigned i;
1552
1553         if (!descriptors_state->dirty)
1554                 return;
1555
1556         if (descriptors_state->push_dirty)
1557                 radv_flush_push_descriptors(cmd_buffer, bind_point);
1558
1559         if ((cmd_buffer->state.pipeline && cmd_buffer->state.pipeline->need_indirect_descriptor_sets) ||
1560             (cmd_buffer->state.compute_pipeline && cmd_buffer->state.compute_pipeline->need_indirect_descriptor_sets)) {
1561                 radv_flush_indirect_descriptor_sets(cmd_buffer, bind_point);
1562         }
1563
1564         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1565                                                            cmd_buffer->cs,
1566                                                            MAX_SETS * MESA_SHADER_STAGES * 4);
1567
1568         for_each_bit(i, descriptors_state->dirty) {
1569                 struct radv_descriptor_set *set = descriptors_state->sets[i];
1570                 if (!(descriptors_state->valid & (1u << i)))
1571                         continue;
1572
1573                 radv_emit_descriptor_set_userdata(cmd_buffer, stages, set, i);
1574         }
1575         descriptors_state->dirty = 0;
1576         descriptors_state->push_dirty = false;
1577
1578         if (unlikely(cmd_buffer->device->trace_bo))
1579                 radv_save_descriptors(cmd_buffer, bind_point);
1580
1581         assert(cmd_buffer->cs->cdw <= cdw_max);
1582 }
1583
1584 static void
1585 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
1586                      VkShaderStageFlags stages)
1587 {
1588         struct radv_pipeline *pipeline = stages & VK_SHADER_STAGE_COMPUTE_BIT
1589                                          ? cmd_buffer->state.compute_pipeline
1590                                          : cmd_buffer->state.pipeline;
1591         struct radv_pipeline_layout *layout = pipeline->layout;
1592         unsigned offset;
1593         void *ptr;
1594         uint64_t va;
1595
1596         stages &= cmd_buffer->push_constant_stages;
1597         if (!stages ||
1598             (!layout->push_constant_size && !layout->dynamic_offset_count))
1599                 return;
1600
1601         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, layout->push_constant_size +
1602                                           16 * layout->dynamic_offset_count,
1603                                           256, &offset, &ptr))
1604                 return;
1605
1606         memcpy(ptr, cmd_buffer->push_constants, layout->push_constant_size);
1607         memcpy((char*)ptr + layout->push_constant_size, cmd_buffer->dynamic_buffers,
1608                16 * layout->dynamic_offset_count);
1609
1610         va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1611         va += offset;
1612
1613         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
1614                                                            cmd_buffer->cs, MESA_SHADER_STAGES * 4);
1615
1616         radv_foreach_stage(stage, stages) {
1617                 if (pipeline->shaders[stage]) {
1618                         radv_emit_userdata_address(cmd_buffer, pipeline, stage,
1619                                                    AC_UD_PUSH_CONSTANTS, va);
1620                 }
1621         }
1622
1623         cmd_buffer->push_constant_stages &= ~stages;
1624         assert(cmd_buffer->cs->cdw <= cdw_max);
1625 }
1626
1627 static void
1628 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer,
1629                               bool pipeline_is_dirty)
1630 {
1631         if ((pipeline_is_dirty ||
1632             (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
1633             cmd_buffer->state.pipeline->vertex_elements.count &&
1634             radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.has_vertex_buffers) {
1635                 struct radv_vertex_elements_info *velems = &cmd_buffer->state.pipeline->vertex_elements;
1636                 unsigned vb_offset;
1637                 void *vb_ptr;
1638                 uint32_t i = 0;
1639                 uint32_t count = velems->count;
1640                 uint64_t va;
1641
1642                 /* allocate some descriptor state for vertex buffers */
1643                 if (!radv_cmd_buffer_upload_alloc(cmd_buffer, count * 16, 256,
1644                                                   &vb_offset, &vb_ptr))
1645                         return;
1646
1647                 for (i = 0; i < count; i++) {
1648                         uint32_t *desc = &((uint32_t *)vb_ptr)[i * 4];
1649                         uint32_t offset;
1650                         int vb = velems->binding[i];
1651                         struct radv_buffer *buffer = cmd_buffer->vertex_bindings[vb].buffer;
1652                         uint32_t stride = cmd_buffer->state.pipeline->binding_stride[vb];
1653
1654                         va = radv_buffer_get_va(buffer->bo);
1655
1656                         offset = cmd_buffer->vertex_bindings[vb].offset + velems->offset[i];
1657                         va += offset + buffer->offset;
1658                         desc[0] = va;
1659                         desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) | S_008F04_STRIDE(stride);
1660                         if (cmd_buffer->device->physical_device->rad_info.chip_class <= CIK && stride)
1661                                 desc[2] = (buffer->size - offset - velems->format_size[i]) / stride + 1;
1662                         else
1663                                 desc[2] = buffer->size - offset;
1664                         desc[3] = velems->rsrc_word3[i];
1665                 }
1666
1667                 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1668                 va += vb_offset;
1669
1670                 radv_emit_userdata_address(cmd_buffer, cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
1671                                            AC_UD_VS_VERTEX_BUFFERS, va);
1672
1673                 cmd_buffer->state.vb_va = va;
1674                 cmd_buffer->state.vb_size = count * 16;
1675                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;
1676         }
1677         cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;
1678 }
1679
1680 static void
1681 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)
1682 {
1683         radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);
1684         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1685         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
1686 }
1687
1688 static void
1689 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
1690                          bool instanced_draw, bool indirect_draw,
1691                          uint32_t draw_vertex_count)
1692 {
1693         struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
1694         struct radv_cmd_state *state = &cmd_buffer->state;
1695         struct radeon_winsys_cs *cs = cmd_buffer->cs;
1696         uint32_t ia_multi_vgt_param;
1697         int32_t primitive_reset_en;
1698
1699         /* Draw state. */
1700         ia_multi_vgt_param =
1701                 si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw,
1702                                           indirect_draw, draw_vertex_count);
1703
1704         if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
1705                 if (info->chip_class >= GFX9) {
1706                         radeon_set_uconfig_reg_idx(cs,
1707                                                    R_030960_IA_MULTI_VGT_PARAM,
1708                                                    4, ia_multi_vgt_param);
1709                 } else if (info->chip_class >= CIK) {
1710                         radeon_set_context_reg_idx(cs,
1711                                                    R_028AA8_IA_MULTI_VGT_PARAM,
1712                                                    1, ia_multi_vgt_param);
1713                 } else {
1714                         radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM,
1715                                                ia_multi_vgt_param);
1716                 }
1717                 state->last_ia_multi_vgt_param = ia_multi_vgt_param;
1718         }
1719
1720         /* Primitive restart. */
1721         primitive_reset_en =
1722                 indexed_draw && state->pipeline->graphics.prim_restart_enable;
1723
1724         if (primitive_reset_en != state->last_primitive_reset_en) {
1725                 state->last_primitive_reset_en = primitive_reset_en;
1726                 if (info->chip_class >= GFX9) {
1727                         radeon_set_uconfig_reg(cs,
1728                                                R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
1729                                                primitive_reset_en);
1730                 } else {
1731                         radeon_set_context_reg(cs,
1732                                                R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
1733                                                primitive_reset_en);
1734                 }
1735         }
1736
1737         if (primitive_reset_en) {
1738                 uint32_t primitive_reset_index =
1739                         state->index_type ? 0xffffffffu : 0xffffu;
1740
1741                 if (primitive_reset_index != state->last_primitive_reset_index) {
1742                         radeon_set_context_reg(cs,
1743                                                R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
1744                                                primitive_reset_index);
1745                         state->last_primitive_reset_index = primitive_reset_index;
1746                 }
1747         }
1748 }
1749
1750 static void radv_stage_flush(struct radv_cmd_buffer *cmd_buffer,
1751                              VkPipelineStageFlags src_stage_mask)
1752 {
1753         if (src_stage_mask & (VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT |
1754                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1755                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1756                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1757                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
1758         }
1759
1760         if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
1761                               VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
1762                               VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
1763                               VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
1764                               VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
1765                               VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
1766                               VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
1767                               VK_PIPELINE_STAGE_TRANSFER_BIT |
1768                               VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT |
1769                               VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT |
1770                               VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)) {
1771                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
1772         } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
1773                                      VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
1774                                      VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
1775                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
1776         }
1777 }
1778
1779 static enum radv_cmd_flush_bits
1780 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
1781                                   VkAccessFlags src_flags)
1782 {
1783         enum radv_cmd_flush_bits flush_bits = 0;
1784         uint32_t b;
1785         for_each_bit(b, src_flags) {
1786                 switch ((VkAccessFlagBits)(1 << b)) {
1787                 case VK_ACCESS_SHADER_WRITE_BIT:
1788                         flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
1789                         break;
1790                 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
1791                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1792                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1793                         break;
1794                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
1795                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1796                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1797                         break;
1798                 case VK_ACCESS_TRANSFER_WRITE_BIT:
1799                         flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1800                                       RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
1801                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1802                                       RADV_CMD_FLAG_FLUSH_AND_INV_DB_META |
1803                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
1804                         break;
1805                 default:
1806                         break;
1807                 }
1808         }
1809         return flush_bits;
1810 }
1811
1812 static enum radv_cmd_flush_bits
1813 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
1814                       VkAccessFlags dst_flags,
1815                       struct radv_image *image)
1816 {
1817         enum radv_cmd_flush_bits flush_bits = 0;
1818         uint32_t b;
1819         for_each_bit(b, dst_flags) {
1820                 switch ((VkAccessFlagBits)(1 << b)) {
1821                 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT:
1822                 case VK_ACCESS_INDEX_READ_BIT:
1823                         break;
1824                 case VK_ACCESS_UNIFORM_READ_BIT:
1825                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
1826                         break;
1827                 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
1828                 case VK_ACCESS_SHADER_READ_BIT:
1829                 case VK_ACCESS_TRANSFER_READ_BIT:
1830                 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
1831                         flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
1832                                       RADV_CMD_FLAG_INV_GLOBAL_L2;
1833                         break;
1834                 case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
1835                         /* TODO: change to image && when the image gets passed
1836                          * through from the subpass. */
1837                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1838                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
1839                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
1840                         break;
1841                 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
1842                         if (!image || (image->usage & VK_IMAGE_USAGE_STORAGE_BIT))
1843                                 flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1844                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
1845                         break;
1846                 default:
1847                         break;
1848                 }
1849         }
1850         return flush_bits;
1851 }
1852
1853 static void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass_barrier *barrier)
1854 {
1855         cmd_buffer->state.flush_bits |= radv_src_access_flush(cmd_buffer, barrier->src_access_mask);
1856         radv_stage_flush(cmd_buffer, barrier->src_stage_mask);
1857         cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask,
1858                                                               NULL);
1859 }
1860
1861 static void radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,
1862                                                  VkAttachmentReference att)
1863 {
1864         unsigned idx = att.attachment;
1865         struct radv_image_view *view = cmd_buffer->state.framebuffer->attachments[idx].attachment;
1866         VkImageSubresourceRange range;
1867         range.aspectMask = 0;
1868         range.baseMipLevel = view->base_mip;
1869         range.levelCount = 1;
1870         range.baseArrayLayer = view->base_layer;
1871         range.layerCount = cmd_buffer->state.framebuffer->layers;
1872
1873         radv_handle_image_transition(cmd_buffer,
1874                                      view->image,
1875                                      cmd_buffer->state.attachments[idx].current_layout,
1876                                      att.layout, 0, 0, &range,
1877                                      cmd_buffer->state.attachments[idx].pending_clear_aspects);
1878
1879         cmd_buffer->state.attachments[idx].current_layout = att.layout;
1880
1881
1882 }
1883
1884 void
1885 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1886                             const struct radv_subpass *subpass, bool transitions)
1887 {
1888         if (transitions) {
1889                 radv_subpass_barrier(cmd_buffer, &subpass->start_barrier);
1890
1891                 for (unsigned i = 0; i < subpass->color_count; ++i) {
1892                         if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED)
1893                                 radv_handle_subpass_image_transition(cmd_buffer,
1894                                                                      subpass->color_attachments[i]);
1895                 }
1896
1897                 for (unsigned i = 0; i < subpass->input_count; ++i) {
1898                         radv_handle_subpass_image_transition(cmd_buffer,
1899                                                         subpass->input_attachments[i]);
1900                 }
1901
1902                 if (subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
1903                         radv_handle_subpass_image_transition(cmd_buffer,
1904                                                         subpass->depth_stencil_attachment);
1905                 }
1906         }
1907
1908         cmd_buffer->state.subpass = subpass;
1909
1910         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;
1911 }
1912
1913 static VkResult
1914 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer,
1915                                  struct radv_render_pass *pass,
1916                                  const VkRenderPassBeginInfo *info)
1917 {
1918         struct radv_cmd_state *state = &cmd_buffer->state;
1919
1920         if (pass->attachment_count == 0) {
1921                 state->attachments = NULL;
1922                 return VK_SUCCESS;
1923         }
1924
1925         state->attachments = vk_alloc(&cmd_buffer->pool->alloc,
1926                                         pass->attachment_count *
1927                                         sizeof(state->attachments[0]),
1928                                         8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1929         if (state->attachments == NULL) {
1930                 cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
1931                 return cmd_buffer->record_result;
1932         }
1933
1934         for (uint32_t i = 0; i < pass->attachment_count; ++i) {
1935                 struct radv_render_pass_attachment *att = &pass->attachments[i];
1936                 VkImageAspectFlags att_aspects = vk_format_aspects(att->format);
1937                 VkImageAspectFlags clear_aspects = 0;
1938
1939                 if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
1940                         /* color attachment */
1941                         if (att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1942                                 clear_aspects |= VK_IMAGE_ASPECT_COLOR_BIT;
1943                         }
1944                 } else {
1945                         /* depthstencil attachment */
1946                         if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
1947                             att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1948                                 clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT;
1949                                 if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1950                                     att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE)
1951                                         clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1952                         }
1953                         if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
1954                             att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) {
1955                                 clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT;
1956                         }
1957                 }
1958
1959                 state->attachments[i].pending_clear_aspects = clear_aspects;
1960                 state->attachments[i].cleared_views = 0;
1961                 if (clear_aspects && info) {
1962                         assert(info->clearValueCount > i);
1963                         state->attachments[i].clear_value = info->pClearValues[i];
1964                 }
1965
1966                 state->attachments[i].current_layout = att->initial_layout;
1967         }
1968
1969         return VK_SUCCESS;
1970 }
1971
1972 VkResult radv_AllocateCommandBuffers(
1973         VkDevice _device,
1974         const VkCommandBufferAllocateInfo *pAllocateInfo,
1975         VkCommandBuffer *pCommandBuffers)
1976 {
1977         RADV_FROM_HANDLE(radv_device, device, _device);
1978         RADV_FROM_HANDLE(radv_cmd_pool, pool, pAllocateInfo->commandPool);
1979
1980         VkResult result = VK_SUCCESS;
1981         uint32_t i;
1982
1983         for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
1984
1985                 if (!list_empty(&pool->free_cmd_buffers)) {
1986                         struct radv_cmd_buffer *cmd_buffer = list_first_entry(&pool->free_cmd_buffers, struct radv_cmd_buffer, pool_link);
1987
1988                         list_del(&cmd_buffer->pool_link);
1989                         list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
1990
1991                         result = radv_reset_cmd_buffer(cmd_buffer);
1992                         cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1993                         cmd_buffer->level = pAllocateInfo->level;
1994
1995                         pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);
1996                 } else {
1997                         result = radv_create_cmd_buffer(device, pool, pAllocateInfo->level,
1998                                                         &pCommandBuffers[i]);
1999                 }
2000                 if (result != VK_SUCCESS)
2001                         break;
2002         }
2003
2004         if (result != VK_SUCCESS) {
2005                 radv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
2006                                         i, pCommandBuffers);
2007
2008                 /* From the Vulkan 1.0.66 spec:
2009                  *
2010                  * "vkAllocateCommandBuffers can be used to create multiple
2011                  *  command buffers. If the creation of any of those command
2012                  *  buffers fails, the implementation must destroy all
2013                  *  successfully created command buffer objects from this
2014                  *  command, set all entries of the pCommandBuffers array to
2015                  *  NULL and return the error."
2016                  */
2017                 memset(pCommandBuffers, 0,
2018                        sizeof(*pCommandBuffers) * pAllocateInfo->commandBufferCount);
2019         }
2020
2021         return result;
2022 }
2023
2024 void radv_FreeCommandBuffers(
2025         VkDevice device,
2026         VkCommandPool commandPool,
2027         uint32_t commandBufferCount,
2028         const VkCommandBuffer *pCommandBuffers)
2029 {
2030         for (uint32_t i = 0; i < commandBufferCount; i++) {
2031                 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
2032
2033                 if (cmd_buffer) {
2034                         if (cmd_buffer->pool) {
2035                                 list_del(&cmd_buffer->pool_link);
2036                                 list_addtail(&cmd_buffer->pool_link, &cmd_buffer->pool->free_cmd_buffers);
2037                         } else
2038                                 radv_cmd_buffer_destroy(cmd_buffer);
2039
2040                 }
2041         }
2042 }
2043
2044 VkResult radv_ResetCommandBuffer(
2045         VkCommandBuffer commandBuffer,
2046         VkCommandBufferResetFlags flags)
2047 {
2048         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2049         return radv_reset_cmd_buffer(cmd_buffer);
2050 }
2051
2052 static void emit_gfx_buffer_state(struct radv_cmd_buffer *cmd_buffer)
2053 {
2054         struct radv_device *device = cmd_buffer->device;
2055         if (device->gfx_init) {
2056                 uint64_t va = radv_buffer_get_va(device->gfx_init);
2057                 radv_cs_add_buffer(device->ws, cmd_buffer->cs, device->gfx_init, 8);
2058                 radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2059                 radeon_emit(cmd_buffer->cs, va);
2060                 radeon_emit(cmd_buffer->cs, va >> 32);
2061                 radeon_emit(cmd_buffer->cs, device->gfx_init_size_dw & 0xffff);
2062         } else
2063                 si_init_config(cmd_buffer);
2064 }
2065
2066 VkResult radv_BeginCommandBuffer(
2067         VkCommandBuffer commandBuffer,
2068         const VkCommandBufferBeginInfo *pBeginInfo)
2069 {
2070         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2071         VkResult result = VK_SUCCESS;
2072
2073         if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {
2074                 /* If the command buffer has already been resetted with
2075                  * vkResetCommandBuffer, no need to do it again.
2076                  */
2077                 result = radv_reset_cmd_buffer(cmd_buffer);
2078                 if (result != VK_SUCCESS)
2079                         return result;
2080         }
2081
2082         memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
2083         cmd_buffer->state.last_primitive_reset_en = -1;
2084         cmd_buffer->state.last_index_type = -1;
2085         cmd_buffer->state.last_num_instances = -1;
2086         cmd_buffer->state.last_vertex_offset = -1;
2087         cmd_buffer->state.last_first_instance = -1;
2088         cmd_buffer->usage_flags = pBeginInfo->flags;
2089
2090         /* setup initial configuration into command buffer */
2091         if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
2092                 switch (cmd_buffer->queue_family_index) {
2093                 case RADV_QUEUE_GENERAL:
2094                         emit_gfx_buffer_state(cmd_buffer);
2095                         break;
2096                 case RADV_QUEUE_COMPUTE:
2097                         si_init_compute(cmd_buffer);
2098                         break;
2099                 case RADV_QUEUE_TRANSFER:
2100                 default:
2101                         break;
2102                 }
2103         }
2104
2105         if (pBeginInfo->flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) {
2106                 assert(pBeginInfo->pInheritanceInfo);
2107                 cmd_buffer->state.framebuffer = radv_framebuffer_from_handle(pBeginInfo->pInheritanceInfo->framebuffer);
2108                 cmd_buffer->state.pass = radv_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
2109
2110                 struct radv_subpass *subpass =
2111                         &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
2112
2113                 result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL);
2114                 if (result != VK_SUCCESS)
2115                         return result;
2116
2117                 radv_cmd_buffer_set_subpass(cmd_buffer, subpass, false);
2118         }
2119
2120         if (unlikely(cmd_buffer->device->trace_bo))
2121                 radv_cmd_buffer_trace_emit(cmd_buffer);
2122
2123         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
2124
2125         return result;
2126 }
2127
2128 void radv_CmdBindVertexBuffers(
2129         VkCommandBuffer                             commandBuffer,
2130         uint32_t                                    firstBinding,
2131         uint32_t                                    bindingCount,
2132         const VkBuffer*                             pBuffers,
2133         const VkDeviceSize*                         pOffsets)
2134 {
2135         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2136         struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
2137         bool changed = false;
2138
2139         /* We have to defer setting up vertex buffer since we need the buffer
2140          * stride from the pipeline. */
2141
2142         assert(firstBinding + bindingCount <= MAX_VBS);
2143         for (uint32_t i = 0; i < bindingCount; i++) {
2144                 uint32_t idx = firstBinding + i;
2145
2146                 if (!changed &&
2147                     (vb[idx].buffer != radv_buffer_from_handle(pBuffers[i]) ||
2148                      vb[idx].offset != pOffsets[i])) {
2149                         changed = true;
2150                 }
2151
2152                 vb[idx].buffer = radv_buffer_from_handle(pBuffers[i]);
2153                 vb[idx].offset = pOffsets[i];
2154
2155                 radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2156                                    vb[idx].buffer->bo, 8);
2157         }
2158
2159         if (!changed) {
2160                 /* No state changes. */
2161                 return;
2162         }
2163
2164         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER;
2165 }
2166
2167 void radv_CmdBindIndexBuffer(
2168         VkCommandBuffer                             commandBuffer,
2169         VkBuffer buffer,
2170         VkDeviceSize offset,
2171         VkIndexType indexType)
2172 {
2173         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2174         RADV_FROM_HANDLE(radv_buffer, index_buffer, buffer);
2175
2176         if (cmd_buffer->state.index_buffer == index_buffer &&
2177             cmd_buffer->state.index_offset == offset &&
2178             cmd_buffer->state.index_type == indexType) {
2179                 /* No state changes. */
2180                 return;
2181         }
2182
2183         cmd_buffer->state.index_buffer = index_buffer;
2184         cmd_buffer->state.index_offset = offset;
2185         cmd_buffer->state.index_type = indexType; /* vk matches hw */
2186         cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);
2187         cmd_buffer->state.index_va += index_buffer->offset + offset;
2188
2189         int index_size_shift = cmd_buffer->state.index_type ? 2 : 1;
2190         cmd_buffer->state.max_index_count = (index_buffer->size - offset) >> index_size_shift;
2191         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
2192         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo, 8);
2193 }
2194
2195
2196 static void
2197 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2198                          VkPipelineBindPoint bind_point,
2199                          struct radv_descriptor_set *set, unsigned idx)
2200 {
2201         struct radeon_winsys *ws = cmd_buffer->device->ws;
2202
2203         radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);
2204         if (!set)
2205                 return;
2206
2207         assert(!(set->layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR));
2208
2209         for (unsigned j = 0; j < set->layout->buffer_count; ++j)
2210                 if (set->descriptors[j])
2211                         radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j], 7);
2212
2213         if(set->bo)
2214                 radv_cs_add_buffer(ws, cmd_buffer->cs, set->bo, 8);
2215 }
2216
2217 void radv_CmdBindDescriptorSets(
2218         VkCommandBuffer                             commandBuffer,
2219         VkPipelineBindPoint                         pipelineBindPoint,
2220         VkPipelineLayout                            _layout,
2221         uint32_t                                    firstSet,
2222         uint32_t                                    descriptorSetCount,
2223         const VkDescriptorSet*                      pDescriptorSets,
2224         uint32_t                                    dynamicOffsetCount,
2225         const uint32_t*                             pDynamicOffsets)
2226 {
2227         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2228         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2229         unsigned dyn_idx = 0;
2230
2231         for (unsigned i = 0; i < descriptorSetCount; ++i) {
2232                 unsigned idx = i + firstSet;
2233                 RADV_FROM_HANDLE(radv_descriptor_set, set, pDescriptorSets[i]);
2234                 radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, idx);
2235
2236                 for(unsigned j = 0; j < set->layout->dynamic_offset_count; ++j, ++dyn_idx) {
2237                         unsigned idx = j + layout->set[i + firstSet].dynamic_offset_start;
2238                         uint32_t *dst = cmd_buffer->dynamic_buffers + idx * 4;
2239                         assert(dyn_idx < dynamicOffsetCount);
2240
2241                         struct radv_descriptor_range *range = set->dynamic_descriptors + j;
2242                         uint64_t va = range->va + pDynamicOffsets[dyn_idx];
2243                         dst[0] = va;
2244                         dst[1] = S_008F04_BASE_ADDRESS_HI(va >> 32);
2245                         dst[2] = range->size;
2246                         dst[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2247                                  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2248                                  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2249                                  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2250                                  S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2251                                  S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2252                         cmd_buffer->push_constant_stages |=
2253                                              set->layout->dynamic_shader_stages;
2254                 }
2255         }
2256 }
2257
2258 static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
2259                                           struct radv_descriptor_set *set,
2260                                           struct radv_descriptor_set_layout *layout,
2261                                           VkPipelineBindPoint bind_point)
2262 {
2263         struct radv_descriptor_state *descriptors_state =
2264                 radv_get_descriptors_state(cmd_buffer, bind_point);
2265         set->size = layout->size;
2266         set->layout = layout;
2267
2268         if (descriptors_state->push_set.capacity < set->size) {
2269                 size_t new_size = MAX2(set->size, 1024);
2270                 new_size = MAX2(new_size, 2 * descriptors_state->push_set.capacity);
2271                 new_size = MIN2(new_size, 96 * MAX_PUSH_DESCRIPTORS);
2272
2273                 free(set->mapped_ptr);
2274                 set->mapped_ptr = malloc(new_size);
2275
2276                 if (!set->mapped_ptr) {
2277                         descriptors_state->push_set.capacity = 0;
2278                         cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;
2279                         return false;
2280                 }
2281
2282                 descriptors_state->push_set.capacity = new_size;
2283         }
2284
2285         return true;
2286 }
2287
2288 void radv_meta_push_descriptor_set(
2289         struct radv_cmd_buffer*              cmd_buffer,
2290         VkPipelineBindPoint                  pipelineBindPoint,
2291         VkPipelineLayout                     _layout,
2292         uint32_t                             set,
2293         uint32_t                             descriptorWriteCount,
2294         const VkWriteDescriptorSet*          pDescriptorWrites)
2295 {
2296         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2297         struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors;
2298         unsigned bo_offset;
2299
2300         assert(set == 0);
2301         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2302
2303         push_set->size = layout->set[set].layout->size;
2304         push_set->layout = layout->set[set].layout;
2305
2306         if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32,
2307                                           &bo_offset,
2308                                           (void**) &push_set->mapped_ptr))
2309                 return;
2310
2311         push_set->va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
2312         push_set->va += bo_offset;
2313
2314         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2315                                     radv_descriptor_set_to_handle(push_set),
2316                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2317
2318         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2319 }
2320
2321 void radv_CmdPushDescriptorSetKHR(
2322         VkCommandBuffer                             commandBuffer,
2323         VkPipelineBindPoint                         pipelineBindPoint,
2324         VkPipelineLayout                            _layout,
2325         uint32_t                                    set,
2326         uint32_t                                    descriptorWriteCount,
2327         const VkWriteDescriptorSet*                 pDescriptorWrites)
2328 {
2329         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2330         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2331         struct radv_descriptor_state *descriptors_state =
2332                 radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);
2333         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2334
2335         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2336
2337         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2338                                            layout->set[set].layout,
2339                                            pipelineBindPoint))
2340                 return;
2341
2342         radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
2343                                     radv_descriptor_set_to_handle(push_set),
2344                                     descriptorWriteCount, pDescriptorWrites, 0, NULL);
2345
2346         radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);
2347         descriptors_state->push_dirty = true;
2348 }
2349
2350 void radv_CmdPushDescriptorSetWithTemplateKHR(
2351         VkCommandBuffer                             commandBuffer,
2352         VkDescriptorUpdateTemplateKHR               descriptorUpdateTemplate,
2353         VkPipelineLayout                            _layout,
2354         uint32_t                                    set,
2355         const void*                                 pData)
2356 {
2357         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2358         RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout);
2359         RADV_FROM_HANDLE(radv_descriptor_update_template, templ, descriptorUpdateTemplate);
2360         struct radv_descriptor_state *descriptors_state =
2361                 radv_get_descriptors_state(cmd_buffer, templ->bind_point);
2362         struct radv_descriptor_set *push_set = &descriptors_state->push_set.set;
2363
2364         assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR);
2365
2366         if (!radv_init_push_descriptor_set(cmd_buffer, push_set,
2367                                            layout->set[set].layout,
2368                                            templ->bind_point))
2369                 return;
2370
2371         radv_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,
2372                                                  descriptorUpdateTemplate, pData);
2373
2374         radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);
2375         descriptors_state->push_dirty = true;
2376 }
2377
2378 void radv_CmdPushConstants(VkCommandBuffer commandBuffer,
2379                            VkPipelineLayout layout,
2380                            VkShaderStageFlags stageFlags,
2381                            uint32_t offset,
2382                            uint32_t size,
2383                            const void* pValues)
2384 {
2385         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2386         memcpy(cmd_buffer->push_constants + offset, pValues, size);
2387         cmd_buffer->push_constant_stages |= stageFlags;
2388 }
2389
2390 VkResult radv_EndCommandBuffer(
2391         VkCommandBuffer                             commandBuffer)
2392 {
2393         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2394
2395         if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
2396                 if (cmd_buffer->device->physical_device->rad_info.chip_class == SI)
2397                         cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
2398                 si_emit_cache_flush(cmd_buffer);
2399         }
2400
2401         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
2402
2403         if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs))
2404                 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2405
2406         cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;
2407
2408         return cmd_buffer->record_result;
2409 }
2410
2411 static void
2412 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer)
2413 {
2414         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
2415
2416         if (!pipeline || pipeline == cmd_buffer->state.emitted_compute_pipeline)
2417                 return;
2418
2419         cmd_buffer->state.emitted_compute_pipeline = pipeline;
2420
2421         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);
2422         radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
2423
2424         cmd_buffer->compute_scratch_size_needed =
2425                                   MAX2(cmd_buffer->compute_scratch_size_needed,
2426                                        pipeline->max_waves * pipeline->scratch_bytes_per_wave);
2427
2428         radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
2429                            pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
2430
2431         if (unlikely(cmd_buffer->device->trace_bo))
2432                 radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
2433 }
2434
2435 static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer,
2436                                             VkPipelineBindPoint bind_point)
2437 {
2438         struct radv_descriptor_state *descriptors_state =
2439                 radv_get_descriptors_state(cmd_buffer, bind_point);
2440
2441         descriptors_state->dirty |= descriptors_state->valid;
2442 }
2443
2444 void radv_CmdBindPipeline(
2445         VkCommandBuffer                             commandBuffer,
2446         VkPipelineBindPoint                         pipelineBindPoint,
2447         VkPipeline                                  _pipeline)
2448 {
2449         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2450         RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
2451
2452         switch (pipelineBindPoint) {
2453         case VK_PIPELINE_BIND_POINT_COMPUTE:
2454                 if (cmd_buffer->state.compute_pipeline == pipeline)
2455                         return;
2456                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2457
2458                 cmd_buffer->state.compute_pipeline = pipeline;
2459                 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
2460                 break;
2461         case VK_PIPELINE_BIND_POINT_GRAPHICS:
2462                 if (cmd_buffer->state.pipeline == pipeline)
2463                         return;
2464                 radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);
2465
2466                 cmd_buffer->state.pipeline = pipeline;
2467                 if (!pipeline)
2468                         break;
2469
2470                 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
2471                 cmd_buffer->push_constant_stages |= pipeline->active_stages;
2472
2473                 /* the new vertex shader might not have the same user regs */
2474                 cmd_buffer->state.last_first_instance = -1;
2475                 cmd_buffer->state.last_vertex_offset = -1;
2476
2477                 /* Prefetch all pipeline shaders at first draw time. */
2478                 cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;
2479
2480                 radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);
2481
2482                 if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)
2483                         cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;
2484                 if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)
2485                         cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;
2486
2487                 if (radv_pipeline_has_tess(pipeline))
2488                         cmd_buffer->tess_rings_needed = true;
2489
2490                 if (radv_pipeline_has_gs(pipeline)) {
2491                         struct radv_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_GEOMETRY,
2492                                                                              AC_UD_SCRATCH_RING_OFFSETS);
2493                         if (cmd_buffer->ring_offsets_idx == -1)
2494                                 cmd_buffer->ring_offsets_idx = loc->sgpr_idx;
2495                         else if (loc->sgpr_idx != -1)
2496                                 assert(loc->sgpr_idx == cmd_buffer->ring_offsets_idx);
2497                 }
2498                 break;
2499         default:
2500                 assert(!"invalid bind point");
2501                 break;
2502         }
2503 }
2504
2505 void radv_CmdSetViewport(
2506         VkCommandBuffer                             commandBuffer,
2507         uint32_t                                    firstViewport,
2508         uint32_t                                    viewportCount,
2509         const VkViewport*                           pViewports)
2510 {
2511         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2512         struct radv_cmd_state *state = &cmd_buffer->state;
2513         MAYBE_UNUSED const uint32_t total_count = firstViewport + viewportCount;
2514
2515         assert(firstViewport < MAX_VIEWPORTS);
2516         assert(total_count >= 1 && total_count <= MAX_VIEWPORTS);
2517
2518         if (cmd_buffer->device->physical_device->has_scissor_bug) {
2519                 /* Try to skip unnecessary PS partial flushes when the viewports
2520                  * don't change.
2521                  */
2522                 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2523                                       RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2524                     !memcmp(state->dynamic.viewport.viewports + firstViewport,
2525                             pViewports, viewportCount * sizeof(*pViewports))) {
2526                         return;
2527                 }
2528         }
2529
2530         memcpy(state->dynamic.viewport.viewports + firstViewport, pViewports,
2531                viewportCount * sizeof(*pViewports));
2532
2533         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_VIEWPORT;
2534 }
2535
2536 void radv_CmdSetScissor(
2537         VkCommandBuffer                             commandBuffer,
2538         uint32_t                                    firstScissor,
2539         uint32_t                                    scissorCount,
2540         const VkRect2D*                             pScissors)
2541 {
2542         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2543         struct radv_cmd_state *state = &cmd_buffer->state;
2544         MAYBE_UNUSED const uint32_t total_count = firstScissor + scissorCount;
2545
2546         assert(firstScissor < MAX_SCISSORS);
2547         assert(total_count >= 1 && total_count <= MAX_SCISSORS);
2548
2549         if (cmd_buffer->device->physical_device->has_scissor_bug) {
2550                 /* Try to skip unnecessary PS partial flushes when the scissors
2551                  * don't change.
2552                  */
2553                 if (!(state->dirty & (RADV_CMD_DIRTY_DYNAMIC_VIEWPORT |
2554                                       RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) &&
2555                     !memcmp(state->dynamic.scissor.scissors + firstScissor,
2556                             pScissors, scissorCount * sizeof(*pScissors))) {
2557                         return;
2558                 }
2559         }
2560
2561         memcpy(state->dynamic.scissor.scissors + firstScissor, pScissors,
2562                scissorCount * sizeof(*pScissors));
2563
2564         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;
2565 }
2566
2567 void radv_CmdSetLineWidth(
2568         VkCommandBuffer                             commandBuffer,
2569         float                                       lineWidth)
2570 {
2571         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2572         cmd_buffer->state.dynamic.line_width = lineWidth;
2573         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
2574 }
2575
2576 void radv_CmdSetDepthBias(
2577         VkCommandBuffer                             commandBuffer,
2578         float                                       depthBiasConstantFactor,
2579         float                                       depthBiasClamp,
2580         float                                       depthBiasSlopeFactor)
2581 {
2582         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2583
2584         cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
2585         cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
2586         cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
2587
2588         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
2589 }
2590
2591 void radv_CmdSetBlendConstants(
2592         VkCommandBuffer                             commandBuffer,
2593         const float                                 blendConstants[4])
2594 {
2595         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2596
2597         memcpy(cmd_buffer->state.dynamic.blend_constants,
2598                blendConstants, sizeof(float) * 4);
2599
2600         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
2601 }
2602
2603 void radv_CmdSetDepthBounds(
2604         VkCommandBuffer                             commandBuffer,
2605         float                                       minDepthBounds,
2606         float                                       maxDepthBounds)
2607 {
2608         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2609
2610         cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
2611         cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
2612
2613         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
2614 }
2615
2616 void radv_CmdSetStencilCompareMask(
2617         VkCommandBuffer                             commandBuffer,
2618         VkStencilFaceFlags                          faceMask,
2619         uint32_t                                    compareMask)
2620 {
2621         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2622
2623         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2624                 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
2625         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2626                 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
2627
2628         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
2629 }
2630
2631 void radv_CmdSetStencilWriteMask(
2632         VkCommandBuffer                             commandBuffer,
2633         VkStencilFaceFlags                          faceMask,
2634         uint32_t                                    writeMask)
2635 {
2636         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2637
2638         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2639                 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
2640         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2641                 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
2642
2643         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
2644 }
2645
2646 void radv_CmdSetStencilReference(
2647         VkCommandBuffer                             commandBuffer,
2648         VkStencilFaceFlags                          faceMask,
2649         uint32_t                                    reference)
2650 {
2651         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2652
2653         if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
2654                 cmd_buffer->state.dynamic.stencil_reference.front = reference;
2655         if (faceMask & VK_STENCIL_FACE_BACK_BIT)
2656                 cmd_buffer->state.dynamic.stencil_reference.back = reference;
2657
2658         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
2659 }
2660
2661 void radv_CmdSetDiscardRectangleEXT(
2662         VkCommandBuffer                             commandBuffer,
2663         uint32_t                                    firstDiscardRectangle,
2664         uint32_t                                    discardRectangleCount,
2665         const VkRect2D*                             pDiscardRectangles)
2666 {
2667         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2668         struct radv_cmd_state *state = &cmd_buffer->state;
2669         MAYBE_UNUSED const uint32_t total_count = firstDiscardRectangle + discardRectangleCount;
2670
2671         assert(firstDiscardRectangle < MAX_DISCARD_RECTANGLES);
2672         assert(total_count >= 1 && total_count <= MAX_DISCARD_RECTANGLES);
2673
2674         typed_memcpy(&state->dynamic.discard_rectangle.rectangles[firstDiscardRectangle],
2675                      pDiscardRectangles, discardRectangleCount);
2676
2677         state->dirty |= RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE;
2678 }
2679
2680 void radv_CmdExecuteCommands(
2681         VkCommandBuffer                             commandBuffer,
2682         uint32_t                                    commandBufferCount,
2683         const VkCommandBuffer*                      pCmdBuffers)
2684 {
2685         RADV_FROM_HANDLE(radv_cmd_buffer, primary, commandBuffer);
2686
2687         assert(commandBufferCount > 0);
2688
2689         /* Emit pending flushes on primary prior to executing secondary */
2690         si_emit_cache_flush(primary);
2691
2692         for (uint32_t i = 0; i < commandBufferCount; i++) {
2693                 RADV_FROM_HANDLE(radv_cmd_buffer, secondary, pCmdBuffers[i]);
2694
2695                 primary->scratch_size_needed = MAX2(primary->scratch_size_needed,
2696                                                     secondary->scratch_size_needed);
2697                 primary->compute_scratch_size_needed = MAX2(primary->compute_scratch_size_needed,
2698                                                             secondary->compute_scratch_size_needed);
2699
2700                 if (secondary->esgs_ring_size_needed > primary->esgs_ring_size_needed)
2701                         primary->esgs_ring_size_needed = secondary->esgs_ring_size_needed;
2702                 if (secondary->gsvs_ring_size_needed > primary->gsvs_ring_size_needed)
2703                         primary->gsvs_ring_size_needed = secondary->gsvs_ring_size_needed;
2704                 if (secondary->tess_rings_needed)
2705                         primary->tess_rings_needed = true;
2706                 if (secondary->sample_positions_needed)
2707                         primary->sample_positions_needed = true;
2708
2709                 if (secondary->ring_offsets_idx != -1) {
2710                         if (primary->ring_offsets_idx == -1)
2711                                 primary->ring_offsets_idx = secondary->ring_offsets_idx;
2712                         else
2713                                 assert(secondary->ring_offsets_idx == primary->ring_offsets_idx);
2714                 }
2715                 primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
2716
2717
2718                 /* When the secondary command buffer is compute only we don't
2719                  * need to re-emit the current graphics pipeline.
2720                  */
2721                 if (secondary->state.emitted_pipeline) {
2722                         primary->state.emitted_pipeline =
2723                                 secondary->state.emitted_pipeline;
2724                 }
2725
2726                 /* When the secondary command buffer is graphics only we don't
2727                  * need to re-emit the current compute pipeline.
2728                  */
2729                 if (secondary->state.emitted_compute_pipeline) {
2730                         primary->state.emitted_compute_pipeline =
2731                                 secondary->state.emitted_compute_pipeline;
2732                 }
2733
2734                 /* Only re-emit the draw packets when needed. */
2735                 if (secondary->state.last_primitive_reset_en != -1) {
2736                         primary->state.last_primitive_reset_en =
2737                                 secondary->state.last_primitive_reset_en;
2738                 }
2739
2740                 if (secondary->state.last_primitive_reset_index) {
2741                         primary->state.last_primitive_reset_index =
2742                                 secondary->state.last_primitive_reset_index;
2743                 }
2744
2745                 if (secondary->state.last_ia_multi_vgt_param) {
2746                         primary->state.last_ia_multi_vgt_param =
2747                                 secondary->state.last_ia_multi_vgt_param;
2748                 }
2749
2750                 primary->state.last_first_instance = secondary->state.last_first_instance;
2751                 primary->state.last_num_instances = secondary->state.last_num_instances;
2752                 primary->state.last_vertex_offset = secondary->state.last_vertex_offset;
2753
2754                 if (secondary->state.last_index_type != -1) {
2755                         primary->state.last_index_type =
2756                                 secondary->state.last_index_type;
2757                 }
2758         }
2759
2760         /* After executing commands from secondary buffers we have to dirty
2761          * some states.
2762          */
2763         primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
2764                                 RADV_CMD_DIRTY_INDEX_BUFFER |
2765                                 RADV_CMD_DIRTY_DYNAMIC_ALL;
2766         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_GRAPHICS);
2767         radv_mark_descriptor_sets_dirty(primary, VK_PIPELINE_BIND_POINT_COMPUTE);
2768 }
2769
2770 VkResult radv_CreateCommandPool(
2771         VkDevice                                    _device,
2772         const VkCommandPoolCreateInfo*              pCreateInfo,
2773         const VkAllocationCallbacks*                pAllocator,
2774         VkCommandPool*                              pCmdPool)
2775 {
2776         RADV_FROM_HANDLE(radv_device, device, _device);
2777         struct radv_cmd_pool *pool;
2778
2779         pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
2780                            VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2781         if (pool == NULL)
2782                 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2783
2784         if (pAllocator)
2785                 pool->alloc = *pAllocator;
2786         else
2787                 pool->alloc = device->alloc;
2788
2789         list_inithead(&pool->cmd_buffers);
2790         list_inithead(&pool->free_cmd_buffers);
2791
2792         pool->queue_family_index = pCreateInfo->queueFamilyIndex;
2793
2794         *pCmdPool = radv_cmd_pool_to_handle(pool);
2795
2796         return VK_SUCCESS;
2797
2798 }
2799
2800 void radv_DestroyCommandPool(
2801         VkDevice                                    _device,
2802         VkCommandPool                               commandPool,
2803         const VkAllocationCallbacks*                pAllocator)
2804 {
2805         RADV_FROM_HANDLE(radv_device, device, _device);
2806         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2807
2808         if (!pool)
2809                 return;
2810
2811         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2812                                  &pool->cmd_buffers, pool_link) {
2813                 radv_cmd_buffer_destroy(cmd_buffer);
2814         }
2815
2816         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2817                                  &pool->free_cmd_buffers, pool_link) {
2818                 radv_cmd_buffer_destroy(cmd_buffer);
2819         }
2820
2821         vk_free2(&device->alloc, pAllocator, pool);
2822 }
2823
2824 VkResult radv_ResetCommandPool(
2825         VkDevice                                    device,
2826         VkCommandPool                               commandPool,
2827         VkCommandPoolResetFlags                     flags)
2828 {
2829         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2830         VkResult result;
2831
2832         list_for_each_entry(struct radv_cmd_buffer, cmd_buffer,
2833                             &pool->cmd_buffers, pool_link) {
2834                 result = radv_reset_cmd_buffer(cmd_buffer);
2835                 if (result != VK_SUCCESS)
2836                         return result;
2837         }
2838
2839         return VK_SUCCESS;
2840 }
2841
2842 void radv_TrimCommandPool(
2843     VkDevice                                    device,
2844     VkCommandPool                               commandPool,
2845     VkCommandPoolTrimFlagsKHR                   flags)
2846 {
2847         RADV_FROM_HANDLE(radv_cmd_pool, pool, commandPool);
2848
2849         if (!pool)
2850                 return;
2851
2852         list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer,
2853                                  &pool->free_cmd_buffers, pool_link) {
2854                 radv_cmd_buffer_destroy(cmd_buffer);
2855         }
2856 }
2857
2858 void radv_CmdBeginRenderPass(
2859         VkCommandBuffer                             commandBuffer,
2860         const VkRenderPassBeginInfo*                pRenderPassBegin,
2861         VkSubpassContents                           contents)
2862 {
2863         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2864         RADV_FROM_HANDLE(radv_render_pass, pass, pRenderPassBegin->renderPass);
2865         RADV_FROM_HANDLE(radv_framebuffer, framebuffer, pRenderPassBegin->framebuffer);
2866
2867         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws,
2868                                                            cmd_buffer->cs, 2048);
2869         MAYBE_UNUSED VkResult result;
2870
2871         cmd_buffer->state.framebuffer = framebuffer;
2872         cmd_buffer->state.pass = pass;
2873         cmd_buffer->state.render_area = pRenderPassBegin->renderArea;
2874
2875         result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin);
2876         if (result != VK_SUCCESS)
2877                 return;
2878
2879         radv_cmd_buffer_set_subpass(cmd_buffer, pass->subpasses, true);
2880         assert(cmd_buffer->cs->cdw <= cdw_max);
2881
2882         radv_cmd_buffer_clear_subpass(cmd_buffer);
2883 }
2884
2885 void radv_CmdNextSubpass(
2886     VkCommandBuffer                             commandBuffer,
2887     VkSubpassContents                           contents)
2888 {
2889         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
2890
2891         radv_cmd_buffer_resolve_subpass(cmd_buffer);
2892
2893         radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs,
2894                                               2048);
2895
2896         radv_cmd_buffer_set_subpass(cmd_buffer, cmd_buffer->state.subpass + 1, true);
2897         radv_cmd_buffer_clear_subpass(cmd_buffer);
2898 }
2899
2900 static void radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)
2901 {
2902         struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
2903         for (unsigned stage = 0; stage < MESA_SHADER_STAGES; ++stage) {
2904                 if (!pipeline->shaders[stage])
2905                         continue;
2906                 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, stage, AC_UD_VIEW_INDEX);
2907                 if (loc->sgpr_idx == -1)
2908                         continue;
2909                 uint32_t base_reg = pipeline->user_data_0[stage];
2910                 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2911
2912         }
2913         if (pipeline->gs_copy_shader) {
2914                 struct radv_userdata_info *loc = &pipeline->gs_copy_shader->info.user_sgprs_locs.shader_data[AC_UD_VIEW_INDEX];
2915                 if (loc->sgpr_idx != -1) {
2916                         uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2917                         radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);
2918                 }
2919         }
2920 }
2921
2922 static void
2923 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2924                          uint32_t vertex_count)
2925 {
2926         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
2927         radeon_emit(cmd_buffer->cs, vertex_count);
2928         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
2929                                     S_0287F0_USE_OPAQUE(0));
2930 }
2931
2932 static void
2933 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer,
2934                                  uint64_t index_va,
2935                                  uint32_t index_count)
2936 {
2937         radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, false));
2938         radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
2939         radeon_emit(cmd_buffer->cs, index_va);
2940         radeon_emit(cmd_buffer->cs, index_va >> 32);
2941         radeon_emit(cmd_buffer->cs, index_count);
2942         radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA);
2943 }
2944
2945 static void
2946 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer,
2947                                   bool indexed,
2948                                   uint32_t draw_count,
2949                                   uint64_t count_va,
2950                                   uint32_t stride)
2951 {
2952         struct radeon_winsys_cs *cs = cmd_buffer->cs;
2953         unsigned di_src_sel = indexed ? V_0287F0_DI_SRC_SEL_DMA
2954                                       : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
2955         bool draw_id_enable = radv_get_vertex_shader(cmd_buffer->state.pipeline)->info.info.vs.needs_draw_id;
2956         uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
2957         assert(base_reg);
2958
2959         /* just reset draw state for vertex data */
2960         cmd_buffer->state.last_first_instance = -1;
2961         cmd_buffer->state.last_num_instances = -1;
2962         cmd_buffer->state.last_vertex_offset = -1;
2963
2964         if (draw_count == 1 && !count_va && !draw_id_enable) {
2965                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT :
2966                                      PKT3_DRAW_INDIRECT, 3, false));
2967                 radeon_emit(cs, 0);
2968                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2969                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2970                 radeon_emit(cs, di_src_sel);
2971         } else {
2972                 radeon_emit(cs, PKT3(indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
2973                                      PKT3_DRAW_INDIRECT_MULTI,
2974                                      8, false));
2975                 radeon_emit(cs, 0);
2976                 radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
2977                 radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
2978                 radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
2979                             S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
2980                             S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
2981                 radeon_emit(cs, draw_count); /* count */
2982                 radeon_emit(cs, count_va); /* count_addr */
2983                 radeon_emit(cs, count_va >> 32);
2984                 radeon_emit(cs, stride); /* stride */
2985                 radeon_emit(cs, di_src_sel);
2986         }
2987 }
2988
2989 struct radv_draw_info {
2990         /**
2991          * Number of vertices.
2992          */
2993         uint32_t count;
2994
2995         /**
2996          * Index of the first vertex.
2997          */
2998         int32_t vertex_offset;
2999
3000         /**
3001          * First instance id.
3002          */
3003         uint32_t first_instance;
3004
3005         /**
3006          * Number of instances.
3007          */
3008         uint32_t instance_count;
3009
3010         /**
3011          * First index (indexed draws only).
3012          */
3013         uint32_t first_index;
3014
3015         /**
3016          * Whether it's an indexed draw.
3017          */
3018         bool indexed;
3019
3020         /**
3021          * Indirect draw parameters resource.
3022          */
3023         struct radv_buffer *indirect;
3024         uint64_t indirect_offset;
3025         uint32_t stride;
3026
3027         /**
3028          * Draw count parameters resource.
3029          */
3030         struct radv_buffer *count_buffer;
3031         uint64_t count_buffer_offset;
3032 };
3033
3034 static void
3035 radv_emit_draw_packets(struct radv_cmd_buffer *cmd_buffer,
3036                        const struct radv_draw_info *info)
3037 {
3038         struct radv_cmd_state *state = &cmd_buffer->state;
3039         struct radeon_winsys *ws = cmd_buffer->device->ws;
3040         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3041
3042         if (info->indirect) {
3043                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3044                 uint64_t count_va = 0;
3045
3046                 va += info->indirect->offset + info->indirect_offset;
3047
3048                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3049
3050                 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
3051                 radeon_emit(cs, 1);
3052                 radeon_emit(cs, va);
3053                 radeon_emit(cs, va >> 32);
3054
3055                 if (info->count_buffer) {
3056                         count_va = radv_buffer_get_va(info->count_buffer->bo);
3057                         count_va += info->count_buffer->offset +
3058                                     info->count_buffer_offset;
3059
3060                         radv_cs_add_buffer(ws, cs, info->count_buffer->bo, 8);
3061                 }
3062
3063                 if (!state->subpass->view_mask) {
3064                         radv_cs_emit_indirect_draw_packet(cmd_buffer,
3065                                                           info->indexed,
3066                                                           info->count,
3067                                                           count_va,
3068                                                           info->stride);
3069                 } else {
3070                         unsigned i;
3071                         for_each_bit(i, state->subpass->view_mask) {
3072                                 radv_emit_view_index(cmd_buffer, i);
3073
3074                                 radv_cs_emit_indirect_draw_packet(cmd_buffer,
3075                                                                   info->indexed,
3076                                                                   info->count,
3077                                                                   count_va,
3078                                                                   info->stride);
3079                         }
3080                 }
3081         } else {
3082                 assert(state->pipeline->graphics.vtx_base_sgpr);
3083
3084                 if (info->vertex_offset != state->last_vertex_offset ||
3085                     info->first_instance != state->last_first_instance) {
3086                         radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
3087                                               state->pipeline->graphics.vtx_emit_num);
3088
3089                         radeon_emit(cs, info->vertex_offset);
3090                         radeon_emit(cs, info->first_instance);
3091                         if (state->pipeline->graphics.vtx_emit_num == 3)
3092                                 radeon_emit(cs, 0);
3093                         state->last_first_instance = info->first_instance;
3094                         state->last_vertex_offset = info->vertex_offset;
3095                 }
3096
3097                 if (state->last_num_instances != info->instance_count) {
3098                         radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, false));
3099                         radeon_emit(cs, info->instance_count);
3100                         state->last_num_instances = info->instance_count;
3101                 }
3102
3103                 if (info->indexed) {
3104                         int index_size = state->index_type ? 4 : 2;
3105                         uint64_t index_va;
3106
3107                         index_va = state->index_va;
3108                         index_va += info->first_index * index_size;
3109
3110                         if (!state->subpass->view_mask) {
3111                                 radv_cs_emit_draw_indexed_packet(cmd_buffer,
3112                                                                  index_va,
3113                                                                  info->count);
3114                         } else {
3115                                 unsigned i;
3116                                 for_each_bit(i, state->subpass->view_mask) {
3117                                         radv_emit_view_index(cmd_buffer, i);
3118
3119                                         radv_cs_emit_draw_indexed_packet(cmd_buffer,
3120                                                                          index_va,
3121                                                                          info->count);
3122                                 }
3123                         }
3124                 } else {
3125                         if (!state->subpass->view_mask) {
3126                                 radv_cs_emit_draw_packet(cmd_buffer, info->count);
3127                         } else {
3128                                 unsigned i;
3129                                 for_each_bit(i, state->subpass->view_mask) {
3130                                         radv_emit_view_index(cmd_buffer, i);
3131
3132                                         radv_cs_emit_draw_packet(cmd_buffer,
3133                                                                  info->count);
3134                                 }
3135                         }
3136                 }
3137         }
3138 }
3139
3140 static void
3141 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
3142                               const struct radv_draw_info *info)
3143 {
3144         if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||
3145             cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)
3146                 radv_emit_rbplus_state(cmd_buffer);
3147
3148         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
3149                 radv_emit_graphics_pipeline(cmd_buffer);
3150
3151         if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)
3152                 radv_emit_framebuffer_state(cmd_buffer);
3153
3154         if (info->indexed) {
3155                 if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
3156                         radv_emit_index_buffer(cmd_buffer);
3157         } else {
3158                 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
3159                  * so the state must be re-emitted before the next indexed
3160                  * draw.
3161                  */
3162                 if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
3163                         cmd_buffer->state.last_index_type = -1;
3164                         cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
3165                 }
3166         }
3167
3168         radv_cmd_buffer_flush_dynamic_state(cmd_buffer);
3169
3170         radv_emit_draw_registers(cmd_buffer, info->indexed,
3171                                  info->instance_count > 1, info->indirect,
3172                                  info->indirect ? 0 : info->count);
3173 }
3174
3175 static void
3176 radv_draw(struct radv_cmd_buffer *cmd_buffer,
3177           const struct radv_draw_info *info)
3178 {
3179         bool has_prefetch =
3180                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3181         bool pipeline_is_dirty =
3182                 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
3183                 cmd_buffer->state.pipeline &&
3184                 cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;
3185
3186         MAYBE_UNUSED unsigned cdw_max =
3187                 radeon_check_space(cmd_buffer->device->ws,
3188                                    cmd_buffer->cs, 4096);
3189
3190         /* Use optimal packet order based on whether we need to sync the
3191          * pipeline.
3192          */
3193         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3194                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3195                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3196                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3197                 /* If we have to wait for idle, set all states first, so that
3198                  * all SET packets are processed in parallel with previous draw
3199                  * calls. Then upload descriptors, set shader pointers, and
3200                  * draw, and prefetch at the end. This ensures that the time
3201                  * the CUs are idle is very short. (there are only SET_SH
3202                  * packets between the wait and the draw)
3203                  */
3204                 radv_emit_all_graphics_states(cmd_buffer, info);
3205                 si_emit_cache_flush(cmd_buffer);
3206                 /* <-- CUs are idle here --> */
3207
3208                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3209
3210                 radv_emit_draw_packets(cmd_buffer, info);
3211                 /* <-- CUs are busy here --> */
3212
3213                 /* Start prefetches after the draw has been started. Both will
3214                  * run in parallel, but starting the draw first is more
3215                  * important.
3216                  */
3217                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3218                         radv_emit_prefetch_L2(cmd_buffer,
3219                                               cmd_buffer->state.pipeline, false);
3220                 }
3221         } else {
3222                 /* If we don't wait for idle, start prefetches first, then set
3223                  * states, and draw at the end.
3224                  */
3225                 si_emit_cache_flush(cmd_buffer);
3226
3227                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3228                         /* Only prefetch the vertex shader and VBO descriptors
3229                          * in order to start the draw as soon as possible.
3230                          */
3231                         radv_emit_prefetch_L2(cmd_buffer,
3232                                               cmd_buffer->state.pipeline, true);
3233                 }
3234
3235                 radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);
3236
3237                 radv_emit_all_graphics_states(cmd_buffer, info);
3238                 radv_emit_draw_packets(cmd_buffer, info);
3239
3240                 /* Prefetch the remaining shaders after the draw has been
3241                  * started.
3242                  */
3243                 if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {
3244                         radv_emit_prefetch_L2(cmd_buffer,
3245                                               cmd_buffer->state.pipeline, false);
3246                 }
3247         }
3248
3249         assert(cmd_buffer->cs->cdw <= cdw_max);
3250         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);
3251 }
3252
3253 void radv_CmdDraw(
3254         VkCommandBuffer                             commandBuffer,
3255         uint32_t                                    vertexCount,
3256         uint32_t                                    instanceCount,
3257         uint32_t                                    firstVertex,
3258         uint32_t                                    firstInstance)
3259 {
3260         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3261         struct radv_draw_info info = {};
3262
3263         info.count = vertexCount;
3264         info.instance_count = instanceCount;
3265         info.first_instance = firstInstance;
3266         info.vertex_offset = firstVertex;
3267
3268         radv_draw(cmd_buffer, &info);
3269 }
3270
3271 void radv_CmdDrawIndexed(
3272         VkCommandBuffer                             commandBuffer,
3273         uint32_t                                    indexCount,
3274         uint32_t                                    instanceCount,
3275         uint32_t                                    firstIndex,
3276         int32_t                                     vertexOffset,
3277         uint32_t                                    firstInstance)
3278 {
3279         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3280         struct radv_draw_info info = {};
3281
3282         info.indexed = true;
3283         info.count = indexCount;
3284         info.instance_count = instanceCount;
3285         info.first_index = firstIndex;
3286         info.vertex_offset = vertexOffset;
3287         info.first_instance = firstInstance;
3288
3289         radv_draw(cmd_buffer, &info);
3290 }
3291
3292 void radv_CmdDrawIndirect(
3293         VkCommandBuffer                             commandBuffer,
3294         VkBuffer                                    _buffer,
3295         VkDeviceSize                                offset,
3296         uint32_t                                    drawCount,
3297         uint32_t                                    stride)
3298 {
3299         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3300         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3301         struct radv_draw_info info = {};
3302
3303         info.count = drawCount;
3304         info.indirect = buffer;
3305         info.indirect_offset = offset;
3306         info.stride = stride;
3307
3308         radv_draw(cmd_buffer, &info);
3309 }
3310
3311 void radv_CmdDrawIndexedIndirect(
3312         VkCommandBuffer                             commandBuffer,
3313         VkBuffer                                    _buffer,
3314         VkDeviceSize                                offset,
3315         uint32_t                                    drawCount,
3316         uint32_t                                    stride)
3317 {
3318         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3319         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3320         struct radv_draw_info info = {};
3321
3322         info.indexed = true;
3323         info.count = drawCount;
3324         info.indirect = buffer;
3325         info.indirect_offset = offset;
3326         info.stride = stride;
3327
3328         radv_draw(cmd_buffer, &info);
3329 }
3330
3331 void radv_CmdDrawIndirectCountAMD(
3332         VkCommandBuffer                             commandBuffer,
3333         VkBuffer                                    _buffer,
3334         VkDeviceSize                                offset,
3335         VkBuffer                                    _countBuffer,
3336         VkDeviceSize                                countBufferOffset,
3337         uint32_t                                    maxDrawCount,
3338         uint32_t                                    stride)
3339 {
3340         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3341         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3342         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3343         struct radv_draw_info info = {};
3344
3345         info.count = maxDrawCount;
3346         info.indirect = buffer;
3347         info.indirect_offset = offset;
3348         info.count_buffer = count_buffer;
3349         info.count_buffer_offset = countBufferOffset;
3350         info.stride = stride;
3351
3352         radv_draw(cmd_buffer, &info);
3353 }
3354
3355 void radv_CmdDrawIndexedIndirectCountAMD(
3356         VkCommandBuffer                             commandBuffer,
3357         VkBuffer                                    _buffer,
3358         VkDeviceSize                                offset,
3359         VkBuffer                                    _countBuffer,
3360         VkDeviceSize                                countBufferOffset,
3361         uint32_t                                    maxDrawCount,
3362         uint32_t                                    stride)
3363 {
3364         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3365         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3366         RADV_FROM_HANDLE(radv_buffer, count_buffer, _countBuffer);
3367         struct radv_draw_info info = {};
3368
3369         info.indexed = true;
3370         info.count = maxDrawCount;
3371         info.indirect = buffer;
3372         info.indirect_offset = offset;
3373         info.count_buffer = count_buffer;
3374         info.count_buffer_offset = countBufferOffset;
3375         info.stride = stride;
3376
3377         radv_draw(cmd_buffer, &info);
3378 }
3379
3380 struct radv_dispatch_info {
3381         /**
3382          * Determine the layout of the grid (in block units) to be used.
3383          */
3384         uint32_t blocks[3];
3385
3386         /**
3387          * A starting offset for the grid. If unaligned is set, the offset
3388          * must still be aligned.
3389          */
3390         uint32_t offsets[3];
3391         /**
3392          * Whether it's an unaligned compute dispatch.
3393          */
3394         bool unaligned;
3395
3396         /**
3397          * Indirect compute parameters resource.
3398          */
3399         struct radv_buffer *indirect;
3400         uint64_t indirect_offset;
3401 };
3402
3403 static void
3404 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer,
3405                            const struct radv_dispatch_info *info)
3406 {
3407         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3408         struct radv_shader_variant *compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
3409         unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;
3410         struct radeon_winsys *ws = cmd_buffer->device->ws;
3411         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3412         struct radv_userdata_info *loc;
3413
3414         loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_COMPUTE,
3415                                     AC_UD_CS_GRID_SIZE);
3416
3417         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(ws, cs, 25);
3418
3419         if (info->indirect) {
3420                 uint64_t va = radv_buffer_get_va(info->indirect->bo);
3421
3422                 va += info->indirect->offset + info->indirect_offset;
3423
3424                 radv_cs_add_buffer(ws, cs, info->indirect->bo, 8);
3425
3426                 if (loc->sgpr_idx != -1) {
3427                         for (unsigned i = 0; i < 3; ++i) {
3428                                 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
3429                                 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
3430                                                 COPY_DATA_DST_SEL(COPY_DATA_REG));
3431                                 radeon_emit(cs, (va +  4 * i));
3432                                 radeon_emit(cs, (va + 4 * i) >> 32);
3433                                 radeon_emit(cs, ((R_00B900_COMPUTE_USER_DATA_0
3434                                                  + loc->sgpr_idx * 4) >> 2) + i);
3435                                 radeon_emit(cs, 0);
3436                         }
3437                 }
3438
3439                 if (radv_cmd_buffer_uses_mec(cmd_buffer)) {
3440                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 2, 0) |
3441                                         PKT3_SHADER_TYPE_S(1));
3442                         radeon_emit(cs, va);
3443                         radeon_emit(cs, va >> 32);
3444                         radeon_emit(cs, dispatch_initiator);
3445                 } else {
3446                         radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0) |
3447                                         PKT3_SHADER_TYPE_S(1));
3448                         radeon_emit(cs, 1);
3449                         radeon_emit(cs, va);
3450                         radeon_emit(cs, va >> 32);
3451
3452                         radeon_emit(cs, PKT3(PKT3_DISPATCH_INDIRECT, 1, 0) |
3453                                         PKT3_SHADER_TYPE_S(1));
3454                         radeon_emit(cs, 0);
3455                         radeon_emit(cs, dispatch_initiator);
3456                 }
3457         } else {
3458                 unsigned blocks[3] = { info->blocks[0], info->blocks[1], info->blocks[2] };
3459                 unsigned offsets[3] = { info->offsets[0], info->offsets[1], info->offsets[2] };
3460
3461                 if (info->unaligned) {
3462                         unsigned *cs_block_size = compute_shader->info.cs.block_size;
3463                         unsigned remainder[3];
3464
3465                         /* If aligned, these should be an entire block size,
3466                          * not 0.
3467                          */
3468                         remainder[0] = blocks[0] + cs_block_size[0] -
3469                                        align_u32_npot(blocks[0], cs_block_size[0]);
3470                         remainder[1] = blocks[1] + cs_block_size[1] -
3471                                        align_u32_npot(blocks[1], cs_block_size[1]);
3472                         remainder[2] = blocks[2] + cs_block_size[2] -
3473                                        align_u32_npot(blocks[2], cs_block_size[2]);
3474
3475                         blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
3476                         blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
3477                         blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
3478
3479                         for(unsigned i = 0; i < 3; ++i) {
3480                                 assert(offsets[i] % cs_block_size[i] == 0);
3481                                 offsets[i] /= cs_block_size[i];
3482                         }
3483
3484                         radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
3485                         radeon_emit(cs,
3486                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[0]) |
3487                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[0]));
3488                         radeon_emit(cs,
3489                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[1]) |
3490                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[1]));
3491                         radeon_emit(cs,
3492                                     S_00B81C_NUM_THREAD_FULL(cs_block_size[2]) |
3493                                     S_00B81C_NUM_THREAD_PARTIAL(remainder[2]));
3494
3495                         dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
3496                 }
3497
3498                 if (loc->sgpr_idx != -1) {
3499                         assert(!loc->indirect);
3500                         assert(loc->num_sgprs == 3);
3501
3502                         radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
3503                                                   loc->sgpr_idx * 4, 3);
3504                         radeon_emit(cs, blocks[0]);
3505                         radeon_emit(cs, blocks[1]);
3506                         radeon_emit(cs, blocks[2]);
3507                 }
3508
3509                 if (offsets[0] || offsets[1] || offsets[2]) {
3510                         radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
3511                         radeon_emit(cs, offsets[0]);
3512                         radeon_emit(cs, offsets[1]);
3513                         radeon_emit(cs, offsets[2]);
3514
3515                         /* The blocks in the packet are not counts but end values. */
3516                         for (unsigned i = 0; i < 3; ++i)
3517                                 blocks[i] += offsets[i];
3518                 } else {
3519                         dispatch_initiator |= S_00B800_FORCE_START_AT_000(1);
3520                 }
3521
3522                 radeon_emit(cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) |
3523                                 PKT3_SHADER_TYPE_S(1));
3524                 radeon_emit(cs, blocks[0]);
3525                 radeon_emit(cs, blocks[1]);
3526                 radeon_emit(cs, blocks[2]);
3527                 radeon_emit(cs, dispatch_initiator);
3528         }
3529
3530         assert(cmd_buffer->cs->cdw <= cdw_max);
3531 }
3532
3533 static void
3534 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer)
3535 {
3536         radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3537         radv_flush_constants(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT);
3538 }
3539
3540 static void
3541 radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
3542               const struct radv_dispatch_info *info)
3543 {
3544         struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
3545         bool has_prefetch =
3546                 cmd_buffer->device->physical_device->rad_info.chip_class >= CIK;
3547         bool pipeline_is_dirty = pipeline &&
3548                                  pipeline != cmd_buffer->state.emitted_compute_pipeline;
3549
3550         if (cmd_buffer->state.flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3551                                             RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3552                                             RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
3553                                             RADV_CMD_FLAG_CS_PARTIAL_FLUSH)) {
3554                 /* If we have to wait for idle, set all states first, so that
3555                  * all SET packets are processed in parallel with previous draw
3556                  * calls. Then upload descriptors, set shader pointers, and
3557                  * dispatch, and prefetch at the end. This ensures that the
3558                  * time the CUs are idle is very short. (there are only SET_SH
3559                  * packets between the wait and the draw)
3560                  */
3561                 radv_emit_compute_pipeline(cmd_buffer);
3562                 si_emit_cache_flush(cmd_buffer);
3563                 /* <-- CUs are idle here --> */
3564
3565                 radv_upload_compute_shader_descriptors(cmd_buffer);
3566
3567                 radv_emit_dispatch_packets(cmd_buffer, info);
3568                 /* <-- CUs are busy here --> */
3569
3570                 /* Start prefetches after the dispatch has been started. Both
3571                  * will run in parallel, but starting the dispatch first is
3572                  * more important.
3573                  */
3574                 if (has_prefetch && pipeline_is_dirty) {
3575                         radv_emit_shader_prefetch(cmd_buffer,
3576                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3577                 }
3578         } else {
3579                 /* If we don't wait for idle, start prefetches first, then set
3580                  * states, and dispatch at the end.
3581                  */
3582                 si_emit_cache_flush(cmd_buffer);
3583
3584                 if (has_prefetch && pipeline_is_dirty) {
3585                         radv_emit_shader_prefetch(cmd_buffer,
3586                                                   pipeline->shaders[MESA_SHADER_COMPUTE]);
3587                 }
3588
3589                 radv_upload_compute_shader_descriptors(cmd_buffer);
3590
3591                 radv_emit_compute_pipeline(cmd_buffer);
3592                 radv_emit_dispatch_packets(cmd_buffer, info);
3593         }
3594
3595         radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);
3596 }
3597
3598 void radv_CmdDispatchBase(
3599         VkCommandBuffer                             commandBuffer,
3600         uint32_t                                    base_x,
3601         uint32_t                                    base_y,
3602         uint32_t                                    base_z,
3603         uint32_t                                    x,
3604         uint32_t                                    y,
3605         uint32_t                                    z)
3606 {
3607         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3608         struct radv_dispatch_info info = {};
3609
3610         info.blocks[0] = x;
3611         info.blocks[1] = y;
3612         info.blocks[2] = z;
3613
3614         info.offsets[0] = base_x;
3615         info.offsets[1] = base_y;
3616         info.offsets[2] = base_z;
3617         radv_dispatch(cmd_buffer, &info);
3618 }
3619
3620 void radv_CmdDispatch(
3621         VkCommandBuffer                             commandBuffer,
3622         uint32_t                                    x,
3623         uint32_t                                    y,
3624         uint32_t                                    z)
3625 {
3626         radv_CmdDispatchBase(commandBuffer, 0, 0, 0, x, y, z);
3627 }
3628
3629 void radv_CmdDispatchIndirect(
3630         VkCommandBuffer                             commandBuffer,
3631         VkBuffer                                    _buffer,
3632         VkDeviceSize                                offset)
3633 {
3634         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3635         RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3636         struct radv_dispatch_info info = {};
3637
3638         info.indirect = buffer;
3639         info.indirect_offset = offset;
3640
3641         radv_dispatch(cmd_buffer, &info);
3642 }
3643
3644 void radv_unaligned_dispatch(
3645         struct radv_cmd_buffer                      *cmd_buffer,
3646         uint32_t                                    x,
3647         uint32_t                                    y,
3648         uint32_t                                    z)
3649 {
3650         struct radv_dispatch_info info = {};
3651
3652         info.blocks[0] = x;
3653         info.blocks[1] = y;
3654         info.blocks[2] = z;
3655         info.unaligned = 1;
3656
3657         radv_dispatch(cmd_buffer, &info);
3658 }
3659
3660 void radv_CmdEndRenderPass(
3661         VkCommandBuffer                             commandBuffer)
3662 {
3663         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3664
3665         radv_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);
3666
3667         radv_cmd_buffer_resolve_subpass(cmd_buffer);
3668
3669         for (unsigned i = 0; i < cmd_buffer->state.framebuffer->attachment_count; ++i) {
3670                 VkImageLayout layout = cmd_buffer->state.pass->attachments[i].final_layout;
3671                 radv_handle_subpass_image_transition(cmd_buffer,
3672                                       (VkAttachmentReference){i, layout});
3673         }
3674
3675         vk_free(&cmd_buffer->pool->alloc, cmd_buffer->state.attachments);
3676
3677         cmd_buffer->state.pass = NULL;
3678         cmd_buffer->state.subpass = NULL;
3679         cmd_buffer->state.attachments = NULL;
3680         cmd_buffer->state.framebuffer = NULL;
3681 }
3682
3683 /*
3684  * For HTILE we have the following interesting clear words:
3685  *   0xfffff30f: Uncompressed, full depth range, for depth+stencil HTILE
3686  *   0xfffc000f: Uncompressed, full depth range, for depth only HTILE.
3687  *   0xfffffff0: Clear depth to 1.0
3688  *   0x00000000: Clear depth to 0.0
3689  */
3690 static void radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer,
3691                                   struct radv_image *image,
3692                                   const VkImageSubresourceRange *range,
3693                                   uint32_t clear_word)
3694 {
3695         assert(range->baseMipLevel == 0);
3696         assert(range->levelCount == 1 || range->levelCount == VK_REMAINING_ARRAY_LAYERS);
3697         unsigned layer_count = radv_get_layerCount(image, range);
3698         uint64_t size = image->surface.htile_slice_size * layer_count;
3699         uint64_t offset = image->offset + image->htile_offset +
3700                           image->surface.htile_slice_size * range->baseArrayLayer;
3701         struct radv_cmd_state *state = &cmd_buffer->state;
3702
3703         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3704                              RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3705
3706         state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo, offset,
3707                                               size, clear_word);
3708
3709         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3710 }
3711
3712 static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer,
3713                                                struct radv_image *image,
3714                                                VkImageLayout src_layout,
3715                                                VkImageLayout dst_layout,
3716                                                unsigned src_queue_mask,
3717                                                unsigned dst_queue_mask,
3718                                                const VkImageSubresourceRange *range,
3719                                                VkImageAspectFlags pending_clears)
3720 {
3721         if (!radv_image_has_htile(image))
3722                 return;
3723
3724         if (dst_layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL &&
3725             (pending_clears & vk_format_aspects(image->vk_format)) == vk_format_aspects(image->vk_format) &&
3726             cmd_buffer->state.render_area.offset.x == 0 && cmd_buffer->state.render_area.offset.y == 0 &&
3727             cmd_buffer->state.render_area.extent.width == image->info.width &&
3728             cmd_buffer->state.render_area.extent.height == image->info.height) {
3729                 /* The clear will initialize htile. */
3730                 return;
3731         } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED &&
3732                    radv_layout_has_htile(image, dst_layout, dst_queue_mask)) {
3733                 /* TODO: merge with the clear if applicable */
3734                 radv_initialize_htile(cmd_buffer, image, range, 0);
3735         } else if (!radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3736                    radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3737                 uint32_t clear_value = vk_format_is_stencil(image->vk_format) ? 0xfffff30f : 0xfffc000f;
3738                 radv_initialize_htile(cmd_buffer, image, range, clear_value);
3739         } else if (radv_layout_is_htile_compressed(image, src_layout, src_queue_mask) &&
3740                    !radv_layout_is_htile_compressed(image, dst_layout, dst_queue_mask)) {
3741                 VkImageSubresourceRange local_range = *range;
3742                 local_range.aspectMask = VK_IMAGE_ASPECT_DEPTH_BIT;
3743                 local_range.baseMipLevel = 0;
3744                 local_range.levelCount = 1;
3745
3746                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3747                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3748
3749                 radv_decompress_depth_image_inplace(cmd_buffer, image, &local_range);
3750
3751                 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB |
3752                                                 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
3753         }
3754 }
3755
3756 static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
3757                                   struct radv_image *image, uint32_t value)
3758 {
3759         struct radv_cmd_state *state = &cmd_buffer->state;
3760
3761         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3762                             RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3763
3764         state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
3765
3766         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3767 }
3768
3769 static void radv_handle_cmask_image_transition(struct radv_cmd_buffer *cmd_buffer,
3770                                                struct radv_image *image,
3771                                                VkImageLayout src_layout,
3772                                                VkImageLayout dst_layout,
3773                                                unsigned src_queue_mask,
3774                                                unsigned dst_queue_mask,
3775                                                const VkImageSubresourceRange *range)
3776 {
3777         if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3778                 if (radv_image_has_fmask(image))
3779                         radv_initialise_cmask(cmd_buffer, image, 0xccccccccu);
3780                 else
3781                         radv_initialise_cmask(cmd_buffer, image, 0xffffffffu);
3782         } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3783                    !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3784                 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3785         }
3786 }
3787
3788 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
3789                          struct radv_image *image, uint32_t value)
3790 {
3791         struct radv_cmd_state *state = &cmd_buffer->state;
3792
3793         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3794                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3795
3796         state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
3797
3798         state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
3799                              RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
3800 }
3801
3802 static void radv_handle_dcc_image_transition(struct radv_cmd_buffer *cmd_buffer,
3803                                              struct radv_image *image,
3804                                              VkImageLayout src_layout,
3805                                              VkImageLayout dst_layout,
3806                                              unsigned src_queue_mask,
3807                                              unsigned dst_queue_mask,
3808                                              const VkImageSubresourceRange *range)
3809 {
3810         if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
3811                 radv_initialize_dcc(cmd_buffer, image, 0xffffffffu);
3812         } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
3813                 radv_initialize_dcc(cmd_buffer, image,
3814                                     radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask) ?
3815                                          0x20202020u : 0xffffffffu);
3816         } else if (radv_layout_dcc_compressed(image, src_layout, src_queue_mask) &&
3817                    !radv_layout_dcc_compressed(image, dst_layout, dst_queue_mask)) {
3818                 radv_decompress_dcc(cmd_buffer, image, range);
3819         } else if (radv_layout_can_fast_clear(image, src_layout, src_queue_mask) &&
3820                    !radv_layout_can_fast_clear(image, dst_layout, dst_queue_mask)) {
3821                 radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);
3822         }
3823 }
3824
3825 /**
3826  * Handle color image transitions for DCC/FMASK/CMASK.
3827  */
3828 static void radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer,
3829                                                struct radv_image *image,
3830                                                VkImageLayout src_layout,
3831                                                VkImageLayout dst_layout,
3832                                                unsigned src_queue_mask,
3833                                                unsigned dst_queue_mask,
3834                                                const VkImageSubresourceRange *range)
3835 {
3836         if (radv_image_has_dcc(image))
3837                 radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
3838                                                  dst_layout, src_queue_mask,
3839                                                  dst_queue_mask, range);
3840
3841         if (radv_image_has_cmask(image) || radv_image_has_fmask(image))
3842                 radv_handle_cmask_image_transition(cmd_buffer, image, src_layout,
3843                                                    dst_layout, src_queue_mask,
3844                                                    dst_queue_mask, range);
3845 }
3846
3847 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
3848                                          struct radv_image *image,
3849                                          VkImageLayout src_layout,
3850                                          VkImageLayout dst_layout,
3851                                          uint32_t src_family,
3852                                          uint32_t dst_family,
3853                                          const VkImageSubresourceRange *range,
3854                                          VkImageAspectFlags pending_clears)
3855 {
3856         if (image->exclusive && src_family != dst_family) {
3857                 /* This is an acquire or a release operation and there will be
3858                  * a corresponding release/acquire. Do the transition in the
3859                  * most flexible queue. */
3860
3861                 assert(src_family == cmd_buffer->queue_family_index ||
3862                        dst_family == cmd_buffer->queue_family_index);
3863
3864                 if (cmd_buffer->queue_family_index == RADV_QUEUE_TRANSFER)
3865                         return;
3866
3867                 if (cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
3868                     (src_family == RADV_QUEUE_GENERAL ||
3869                      dst_family == RADV_QUEUE_GENERAL))
3870                         return;
3871         }
3872
3873         unsigned src_queue_mask =
3874                 radv_image_queue_family_mask(image, src_family,
3875                                              cmd_buffer->queue_family_index);
3876         unsigned dst_queue_mask =
3877                 radv_image_queue_family_mask(image, dst_family,
3878                                              cmd_buffer->queue_family_index);
3879
3880         if (vk_format_is_depth(image->vk_format)) {
3881                 radv_handle_depth_image_transition(cmd_buffer, image,
3882                                                    src_layout, dst_layout,
3883                                                    src_queue_mask, dst_queue_mask,
3884                                                    range, pending_clears);
3885         } else {
3886                 radv_handle_color_image_transition(cmd_buffer, image,
3887                                                    src_layout, dst_layout,
3888                                                    src_queue_mask, dst_queue_mask,
3889                                                    range);
3890         }
3891 }
3892
3893 void radv_CmdPipelineBarrier(
3894         VkCommandBuffer                             commandBuffer,
3895         VkPipelineStageFlags                        srcStageMask,
3896         VkPipelineStageFlags                        destStageMask,
3897         VkBool32                                    byRegion,
3898         uint32_t                                    memoryBarrierCount,
3899         const VkMemoryBarrier*                      pMemoryBarriers,
3900         uint32_t                                    bufferMemoryBarrierCount,
3901         const VkBufferMemoryBarrier*                pBufferMemoryBarriers,
3902         uint32_t                                    imageMemoryBarrierCount,
3903         const VkImageMemoryBarrier*                 pImageMemoryBarriers)
3904 {
3905         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3906         enum radv_cmd_flush_bits src_flush_bits = 0;
3907         enum radv_cmd_flush_bits dst_flush_bits = 0;
3908
3909         for (uint32_t i = 0; i < memoryBarrierCount; i++) {
3910                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pMemoryBarriers[i].srcAccessMask);
3911                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pMemoryBarriers[i].dstAccessMask,
3912                                                         NULL);
3913         }
3914
3915         for (uint32_t i = 0; i < bufferMemoryBarrierCount; i++) {
3916                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pBufferMemoryBarriers[i].srcAccessMask);
3917                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pBufferMemoryBarriers[i].dstAccessMask,
3918                                                         NULL);
3919         }
3920
3921         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3922                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3923                 src_flush_bits |= radv_src_access_flush(cmd_buffer, pImageMemoryBarriers[i].srcAccessMask);
3924                 dst_flush_bits |= radv_dst_access_flush(cmd_buffer, pImageMemoryBarriers[i].dstAccessMask,
3925                                                         image);
3926         }
3927
3928         radv_stage_flush(cmd_buffer, srcStageMask);
3929         cmd_buffer->state.flush_bits |= src_flush_bits;
3930
3931         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
3932                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
3933                 radv_handle_image_transition(cmd_buffer, image,
3934                                              pImageMemoryBarriers[i].oldLayout,
3935                                              pImageMemoryBarriers[i].newLayout,
3936                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
3937                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
3938                                              &pImageMemoryBarriers[i].subresourceRange,
3939                                              0);
3940         }
3941
3942         cmd_buffer->state.flush_bits |= dst_flush_bits;
3943 }
3944
3945
3946 static void write_event(struct radv_cmd_buffer *cmd_buffer,
3947                         struct radv_event *event,
3948                         VkPipelineStageFlags stageMask,
3949                         unsigned value)
3950 {
3951         struct radeon_winsys_cs *cs = cmd_buffer->cs;
3952         uint64_t va = radv_buffer_get_va(event->bo);
3953
3954         radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
3955
3956         MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 18);
3957
3958         /* TODO: this is overkill. Probably should figure something out from
3959          * the stage mask. */
3960
3961         si_cs_emit_write_event_eop(cs,
3962                                    cmd_buffer->state.predicating,
3963                                    cmd_buffer->device->physical_device->rad_info.chip_class,
3964                                    radv_cmd_buffer_uses_mec(cmd_buffer),
3965                                    V_028A90_BOTTOM_OF_PIPE_TS, 0,
3966                                    1, va, 2, value);
3967
3968         assert(cmd_buffer->cs->cdw <= cdw_max);
3969 }
3970
3971 void radv_CmdSetEvent(VkCommandBuffer commandBuffer,
3972                       VkEvent _event,
3973                       VkPipelineStageFlags stageMask)
3974 {
3975         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3976         RADV_FROM_HANDLE(radv_event, event, _event);
3977
3978         write_event(cmd_buffer, event, stageMask, 1);
3979 }
3980
3981 void radv_CmdResetEvent(VkCommandBuffer commandBuffer,
3982                         VkEvent _event,
3983                         VkPipelineStageFlags stageMask)
3984 {
3985         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
3986         RADV_FROM_HANDLE(radv_event, event, _event);
3987
3988         write_event(cmd_buffer, event, stageMask, 0);
3989 }
3990
3991 void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
3992                         uint32_t eventCount,
3993                         const VkEvent* pEvents,
3994                         VkPipelineStageFlags srcStageMask,
3995                         VkPipelineStageFlags dstStageMask,
3996                         uint32_t memoryBarrierCount,
3997                         const VkMemoryBarrier* pMemoryBarriers,
3998                         uint32_t bufferMemoryBarrierCount,
3999                         const VkBufferMemoryBarrier* pBufferMemoryBarriers,
4000                         uint32_t imageMemoryBarrierCount,
4001                         const VkImageMemoryBarrier* pImageMemoryBarriers)
4002 {
4003         RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
4004         struct radeon_winsys_cs *cs = cmd_buffer->cs;
4005
4006         for (unsigned i = 0; i < eventCount; ++i) {
4007                 RADV_FROM_HANDLE(radv_event, event, pEvents[i]);
4008                 uint64_t va = radv_buffer_get_va(event->bo);
4009
4010                 radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo, 8);
4011
4012                 MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
4013
4014                 si_emit_wait_fence(cs, false, va, 1, 0xffffffff);
4015                 assert(cmd_buffer->cs->cdw <= cdw_max);
4016         }
4017
4018
4019         for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
4020                 RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
4021
4022                 radv_handle_image_transition(cmd_buffer, image,
4023                                              pImageMemoryBarriers[i].oldLayout,
4024                                              pImageMemoryBarriers[i].newLayout,
4025                                              pImageMemoryBarriers[i].srcQueueFamilyIndex,
4026                                              pImageMemoryBarriers[i].dstQueueFamilyIndex,
4027                                              &pImageMemoryBarriers[i].subresourceRange,
4028                                              0);
4029         }
4030
4031         /* TODO: figure out how to do memory barriers without waiting */
4032         cmd_buffer->state.flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER |
4033                                         RADV_CMD_FLAG_INV_GLOBAL_L2 |
4034                                         RADV_CMD_FLAG_INV_VMEM_L1 |
4035                                         RADV_CMD_FLAG_INV_SMEM_L1;
4036 }
4037
4038
4039 void radv_CmdSetDeviceMask(VkCommandBuffer commandBuffer,
4040                            uint32_t deviceMask)
4041 {
4042    /* No-op */
4043 }