src/amd/vulkan/radv_private.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_PRIVATE_H
  29 #define RADV_PRIVATE_H
  30
  31 #include <stdlib.h>
  32 #include <stdio.h>
  33 #include <stdbool.h>
  34 #include <pthread.h>
  35 #include <assert.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #ifdef HAVE_VALGRIND
  39 #include <valgrind.h>
  40 #include <memcheck.h>
  41 #define VG(x) x
  42 #else
  43 #define VG(x)
  44 #endif
  45
  46 #include <amdgpu.h>
  47 #include "compiler/shader_enums.h"
  48 #include "util/macros.h"
  49 #include "util/list.h"
  50 #include "util/vk_alloc.h"
  51 #include "main/macros.h"
  52
  53 #include "radv_radeon_winsys.h"
  54 #include "ac_binary.h"
  55 #include "ac_nir_to_llvm.h"
  56 #include "radv_debug.h"
  57 #include "radv_descriptor_set.h"
  58
  59 #include <llvm-c/TargetMachine.h>
  60
  61 /* Pre-declarations needed for WSI entrypoints */
  62 struct wl_surface;
  63 struct wl_display;
  64 typedef struct xcb_connection_t xcb_connection_t;
  65 typedef uint32_t xcb_visualid_t;
  66 typedef uint32_t xcb_window_t;
  67
  68 #include <vulkan/vulkan.h>
  69 #include <vulkan/vulkan_intel.h>
  70 #include <vulkan/vk_icd.h>
  71
  72 #include "radv_entrypoints.h"
  73
  74 #include "wsi_common.h"
  75
  76 #define MAX_VBS         32
  77 #define MAX_VERTEX_ATTRIBS 32
  78 #define MAX_RTS          8
  79 #define MAX_VIEWPORTS   16
  80 #define MAX_SCISSORS    16
  81 #define MAX_PUSH_CONSTANTS_SIZE 128
  82 #define MAX_DYNAMIC_BUFFERS 16
  83 #define MAX_SAMPLES_LOG2 4
  84 #define NUM_META_FS_KEYS 11
  85 #define RADV_MAX_DRM_DEVICES 8
  86
  87 #define NUM_DEPTH_CLEAR_PIPELINES 3
  88
  89 enum radv_mem_heap {
  90         RADV_MEM_HEAP_VRAM,
  91         RADV_MEM_HEAP_VRAM_CPU_ACCESS,
  92         RADV_MEM_HEAP_GTT,
  93         RADV_MEM_HEAP_COUNT
  94 };
  95
  96 enum radv_mem_type {
  97         RADV_MEM_TYPE_VRAM,
  98         RADV_MEM_TYPE_GTT_WRITE_COMBINE,
  99         RADV_MEM_TYPE_VRAM_CPU_ACCESS,
 100         RADV_MEM_TYPE_GTT_CACHED,
 101         RADV_MEM_TYPE_COUNT
 102 };
 103
 104 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
 105
 106 static inline uint32_t
 107 align_u32(uint32_t v, uint32_t a)
 108 {
 109         assert(a != 0 && a == (a & -a));
 110         return (v + a - 1) & ~(a - 1);
 111 }
 112
 113 static inline uint32_t
 114 align_u32_npot(uint32_t v, uint32_t a)
 115 {
 116         return (v + a - 1) / a * a;
 117 }
 118
 119 static inline uint64_t
 120 align_u64(uint64_t v, uint64_t a)
 121 {
 122         assert(a != 0 && a == (a & -a));
 123         return (v + a - 1) & ~(a - 1);
 124 }
 125
 126 static inline int32_t
 127 align_i32(int32_t v, int32_t a)
 128 {
 129         assert(a != 0 && a == (a & -a));
 130         return (v + a - 1) & ~(a - 1);
 131 }
 132
 133 /** Alignment must be a power of 2. */
 134 static inline bool
 135 radv_is_aligned(uintmax_t n, uintmax_t a)
 136 {
 137         assert(a == (a & -a));
 138         return (n & (a - 1)) == 0;
 139 }
 140
 141 static inline uint32_t
 142 round_up_u32(uint32_t v, uint32_t a)
 143 {
 144         return (v + a - 1) / a;
 145 }
 146
 147 static inline uint64_t
 148 round_up_u64(uint64_t v, uint64_t a)
 149 {
 150         return (v + a - 1) / a;
 151 }
 152
 153 static inline uint32_t
 154 radv_minify(uint32_t n, uint32_t levels)
 155 {
 156         if (unlikely(n == 0))
 157                 return 0;
 158         else
 159                 return MAX2(n >> levels, 1);
 160 }
 161 static inline float
 162 radv_clamp_f(float f, float min, float max)
 163 {
 164         assert(min < max);
 165
 166         if (f > max)
 167                 return max;
 168         else if (f < min)
 169                 return min;
 170         else
 171                 return f;
 172 }
 173
 174 static inline bool
 175 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
 176 {
 177         if (*inout_mask & clear_mask) {
 178                 *inout_mask &= ~clear_mask;
 179                 return true;
 180         } else {
 181                 return false;
 182         }
 183 }
 184
 185 #define for_each_bit(b, dword)                          \
 186         for (uint32_t __dword = (dword);                \
 187              (b) = __builtin_ffs(__dword) - 1, __dword; \
 188              __dword &= ~(1 << (b)))
 189
 190 #define typed_memcpy(dest, src, count) ({                               \
 191                         STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
 192                         memcpy((dest), (src), (count) * sizeof(*(src))); \
 193                 })
 194
 195 #define zero(x) (memset(&(x), 0, sizeof(x)))
 196
 197 /* Whenever we generate an error, pass it through this function. Useful for
 198  * debugging, where we can break on it. Only call at error site, not when
 199  * propagating errors. Might be useful to plug in a stack trace here.
 200  */
 201
 202 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
 203
 204 #ifdef DEBUG
 205 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
 206 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
 207 #else
 208 #define vk_error(error) error
 209 #define vk_errorf(error, format, ...) error
 210 #endif
 211
 212 void __radv_finishme(const char *file, int line, const char *format, ...)
 213         radv_printflike(3, 4);
 214 void radv_loge(const char *format, ...) radv_printflike(1, 2);
 215 void radv_loge_v(const char *format, va_list va);
 216
 217 /**
 218  * Print a FINISHME message, including its source location.
 219  */
 220 #define radv_finishme(format, ...)                                      \
 221         do { \
 222                 static bool reported = false; \
 223                 if (!reported) { \
 224                         __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
 225                         reported = true; \
 226                 } \
 227         } while (0)
 228
 229 /* A non-fatal assert.  Useful for debugging. */
 230 #ifdef DEBUG
 231 #define radv_assert(x) ({                                               \
 232                         if (unlikely(!(x)))                             \
 233                                 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
 234                 })
 235 #else
 236 #define radv_assert(x)
 237 #endif
 238
 239 #define stub_return(v)                                  \
 240         do {                                            \
 241                 radv_finishme("stub %s", __func__);     \
 242                 return (v);                             \
 243         } while (0)
 244
 245 #define stub()                                          \
 246         do {                                            \
 247                 radv_finishme("stub %s", __func__);     \
 248                 return;                                 \
 249         } while (0)
 250
 251 void *radv_lookup_entrypoint(const char *name);
 252
 253 struct radv_extensions {
 254         VkExtensionProperties       *ext_array;
 255         uint32_t                    num_ext;
 256 };
 257
 258 struct radv_physical_device {
 259         VK_LOADER_DATA                              _loader_data;
 260
 261         struct radv_instance *                       instance;
 262
 263         struct radeon_winsys *ws;
 264         struct radeon_info rad_info;
 265         char                                        path[20];
 266         const char *                                name;
 267         uint8_t                                     uuid[VK_UUID_SIZE];
 268
 269         int local_fd;
 270         struct wsi_device                       wsi_device;
 271         struct radv_extensions                      extensions;
 272 };
 273
 274 struct radv_instance {
 275         VK_LOADER_DATA                              _loader_data;
 276
 277         VkAllocationCallbacks                       alloc;
 278
 279         uint32_t                                    apiVersion;
 280         int                                         physicalDeviceCount;
 281         struct radv_physical_device                 physicalDevices[RADV_MAX_DRM_DEVICES];
 282
 283         uint64_t debug_flags;
 284 };
 285
 286 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
 287 void radv_finish_wsi(struct radv_physical_device *physical_device);
 288
 289 struct cache_entry;
 290
 291 struct radv_pipeline_cache {
 292         struct radv_device *                          device;
 293         pthread_mutex_t                              mutex;
 294
 295         uint32_t                                     total_size;
 296         uint32_t                                     table_size;
 297         uint32_t                                     kernel_count;
 298         struct cache_entry **                        hash_table;
 299         bool                                         modified;
 300
 301         VkAllocationCallbacks                        alloc;
 302 };
 303
 304 void
 305 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
 306                          struct radv_device *device);
 307 void
 308 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
 309 void
 310 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
 311                          const void *data, size_t size);
 312
 313 struct radv_shader_variant *
 314 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
 315                                                struct radv_pipeline_cache *cache,
 316                                                const unsigned char *sha1);
 317
 318 struct radv_shader_variant *
 319 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
 320                                   const unsigned char *sha1,
 321                                   struct radv_shader_variant *variant,
 322                                   const void *code, unsigned code_size);
 323
 324 void radv_shader_variant_destroy(struct radv_device *device,
 325                                  struct radv_shader_variant *variant);
 326
 327 struct radv_meta_state {
 328         VkAllocationCallbacks alloc;
 329
 330         struct radv_pipeline_cache cache;
 331
 332         /**
 333          * Use array element `i` for images with `2^i` samples.
 334          */
 335         struct {
 336                 VkRenderPass render_pass[NUM_META_FS_KEYS];
 337                 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
 338
 339                 VkRenderPass depthstencil_rp;
 340                 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 341                 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 342                 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 343         } clear[1 + MAX_SAMPLES_LOG2];
 344
 345         struct {
 346                 VkRenderPass render_pass[NUM_META_FS_KEYS];
 347
 348                 /** Pipeline that blits from a 1D image. */
 349                 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
 350
 351                 /** Pipeline that blits from a 2D image. */
 352                 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
 353
 354                 /** Pipeline that blits from a 3D image. */
 355                 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
 356
 357                 VkRenderPass depth_only_rp;
 358                 VkPipeline depth_only_1d_pipeline;
 359                 VkPipeline depth_only_2d_pipeline;
 360                 VkPipeline depth_only_3d_pipeline;
 361
 362                 VkRenderPass stencil_only_rp;
 363                 VkPipeline stencil_only_1d_pipeline;
 364                 VkPipeline stencil_only_2d_pipeline;
 365                 VkPipeline stencil_only_3d_pipeline;
 366                 VkPipelineLayout                          pipeline_layout;
 367                 VkDescriptorSetLayout                     ds_layout;
 368         } blit;
 369
 370         struct {
 371                 VkRenderPass render_passes[NUM_META_FS_KEYS];
 372
 373                 VkPipelineLayout p_layouts[2];
 374                 VkDescriptorSetLayout ds_layouts[2];
 375                 VkPipeline pipelines[2][NUM_META_FS_KEYS];
 376
 377                 VkRenderPass depth_only_rp;
 378                 VkPipeline depth_only_pipeline[2];
 379
 380                 VkRenderPass stencil_only_rp;
 381                 VkPipeline stencil_only_pipeline[2];
 382         } blit2d;
 383
 384         struct {
 385                 VkPipelineLayout                          img_p_layout;
 386                 VkDescriptorSetLayout                     img_ds_layout;
 387                 VkPipeline pipeline;
 388         } itob;
 389         struct {
 390                 VkRenderPass render_pass;
 391                 VkPipelineLayout                          img_p_layout;
 392                 VkDescriptorSetLayout                     img_ds_layout;
 393                 VkPipeline pipeline;
 394         } btoi;
 395         struct {
 396                 VkPipelineLayout                          img_p_layout;
 397                 VkDescriptorSetLayout                     img_ds_layout;
 398                 VkPipeline pipeline;
 399         } itoi;
 400         struct {
 401                 VkPipelineLayout                          img_p_layout;
 402                 VkDescriptorSetLayout                     img_ds_layout;
 403                 VkPipeline pipeline;
 404         } cleari;
 405
 406         struct {
 407                 VkPipeline                                pipeline;
 408                 VkRenderPass                              pass;
 409         } resolve;
 410
 411         struct {
 412                 VkDescriptorSetLayout                     ds_layout;
 413                 VkPipelineLayout                          p_layout;
 414                 struct {
 415                         VkPipeline                                pipeline;
 416                         VkPipeline                                i_pipeline;
 417                 } rc[MAX_SAMPLES_LOG2];
 418         } resolve_compute;
 419
 420         struct {
 421                 VkPipeline                                decompress_pipeline;
 422                 VkPipeline                                resummarize_pipeline;
 423                 VkRenderPass                              pass;
 424         } depth_decomp;
 425
 426         struct {
 427                 VkPipeline                                cmask_eliminate_pipeline;
 428                 VkPipeline                                fmask_decompress_pipeline;
 429                 VkRenderPass                              pass;
 430         } fast_clear_flush;
 431
 432         struct {
 433                 VkPipelineLayout fill_p_layout;
 434                 VkPipelineLayout copy_p_layout;
 435                 VkDescriptorSetLayout fill_ds_layout;
 436                 VkDescriptorSetLayout copy_ds_layout;
 437                 VkPipeline fill_pipeline;
 438                 VkPipeline copy_pipeline;
 439         } buffer;
 440 };
 441
 442 /* queue types */
 443 #define RADV_QUEUE_GENERAL 0
 444 #define RADV_QUEUE_COMPUTE 1
 445 #define RADV_QUEUE_TRANSFER 2
 446
 447 #define RADV_MAX_QUEUE_FAMILIES 3
 448
 449 enum ring_type radv_queue_family_to_ring(int f);
 450
 451 struct radv_queue {
 452         VK_LOADER_DATA                              _loader_data;
 453         struct radv_device *                         device;
 454         struct radeon_winsys_ctx                    *hw_ctx;
 455         int queue_family_index;
 456         int queue_idx;
 457
 458         uint32_t scratch_size;
 459         uint32_t compute_scratch_size;
 460         uint32_t esgs_ring_size;
 461         uint32_t gsvs_ring_size;
 462
 463         struct radeon_winsys_bo *scratch_bo;
 464         struct radeon_winsys_bo *descriptor_bo;
 465         struct radeon_winsys_bo *compute_scratch_bo;
 466         struct radeon_winsys_bo *esgs_ring_bo;
 467         struct radeon_winsys_bo *gsvs_ring_bo;
 468         struct radeon_winsys_cs *initial_preamble_cs;
 469         struct radeon_winsys_cs *continue_preamble_cs;
 470 };
 471
 472 struct radv_device {
 473         VK_LOADER_DATA                              _loader_data;
 474
 475         VkAllocationCallbacks                       alloc;
 476
 477         struct radv_instance *                       instance;
 478         struct radeon_winsys *ws;
 479
 480         struct radv_meta_state                       meta_state;
 481
 482         struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
 483         int queue_count[RADV_MAX_QUEUE_FAMILIES];
 484         struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
 485         struct radeon_winsys_cs *flush_cs[RADV_MAX_QUEUE_FAMILIES];
 486
 487         uint64_t debug_flags;
 488
 489         bool llvm_supports_spill;
 490         uint32_t scratch_waves;
 491
 492         uint32_t gs_table_depth;
 493
 494         /* MSAA sample locations.
 495          * The first index is the sample index.
 496          * The second index is the coordinate: X, Y. */
 497         float sample_locations_1x[1][2];
 498         float sample_locations_2x[2][2];
 499         float sample_locations_4x[4][2];
 500         float sample_locations_8x[8][2];
 501         float sample_locations_16x[16][2];
 502
 503         /* CIK and later */
 504         uint32_t gfx_init_size_dw;
 505         struct radeon_winsys_bo                      *gfx_init;
 506
 507         struct radeon_winsys_bo                      *trace_bo;
 508         uint32_t                                     *trace_id_ptr;
 509
 510         struct radv_physical_device                  *physical_device;
 511
 512         /* Backup in-memory cache to be used if the app doesn't provide one */
 513         struct radv_pipeline_cache *                mem_cache;
 514 };
 515
 516 struct radv_device_memory {
 517         struct radeon_winsys_bo                      *bo;
 518         /* for dedicated allocations */
 519         struct radv_image                            *image;
 520         struct radv_buffer                           *buffer;
 521         uint32_t                                     type_index;
 522         VkDeviceSize                                 map_size;
 523         void *                                       map;
 524 };
 525
 526
 527 struct radv_descriptor_range {
 528         uint64_t va;
 529         uint32_t size;
 530 };
 531
 532 struct radv_descriptor_set {
 533         const struct radv_descriptor_set_layout *layout;
 534         uint32_t size;
 535
 536         struct radeon_winsys_bo *bo;
 537         uint64_t va;
 538         uint32_t *mapped_ptr;
 539         struct radv_descriptor_range *dynamic_descriptors;
 540
 541         struct list_head vram_list;
 542
 543         struct radeon_winsys_bo *descriptors[0];
 544 };
 545
 546 struct radv_descriptor_pool {
 547         struct radeon_winsys_bo *bo;
 548         uint8_t *mapped_ptr;
 549         uint64_t current_offset;
 550         uint64_t size;
 551
 552         struct list_head vram_list;
 553 };
 554
 555 struct radv_buffer {
 556         struct radv_device *                          device;
 557         VkDeviceSize                                 size;
 558
 559         VkBufferUsageFlags                           usage;
 560
 561         /* Set when bound */
 562         struct radeon_winsys_bo *                      bo;
 563         VkDeviceSize                                 offset;
 564 };
 565
 566
 567 enum radv_cmd_dirty_bits {
 568         RADV_CMD_DIRTY_DYNAMIC_VIEWPORT                  = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
 569         RADV_CMD_DIRTY_DYNAMIC_SCISSOR                   = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
 570         RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH                = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
 571         RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS                = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
 572         RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS           = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
 573         RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS              = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
 574         RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK      = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
 575         RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK        = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
 576         RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE         = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
 577         RADV_CMD_DIRTY_DYNAMIC_ALL                       = (1 << 9) - 1,
 578         RADV_CMD_DIRTY_PIPELINE                          = 1 << 9,
 579         RADV_CMD_DIRTY_INDEX_BUFFER                      = 1 << 10,
 580         RADV_CMD_DIRTY_RENDER_TARGETS                    = 1 << 11,
 581 };
 582 typedef uint32_t radv_cmd_dirty_mask_t;
 583
 584 enum radv_cmd_flush_bits {
 585         RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
 586         /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
 587         RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
 588         /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
 589         RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
 590         /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
 591         RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
 592         /* Same as above, but only writes back and doesn't invalidate */
 593         RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
 594         /* Framebuffer caches */
 595         RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
 596         RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
 597         RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
 598         RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
 599         /* Engine synchronization. */
 600         RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
 601         RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
 602         RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
 603         RADV_CMD_FLAG_VGT_FLUSH        = 1 << 12,
 604
 605         RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
 606                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
 607                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB |
 608                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
 609 };
 610
 611 struct radv_vertex_binding {
 612         struct radv_buffer *                          buffer;
 613         VkDeviceSize                                 offset;
 614 };
 615
 616 struct radv_dynamic_state {
 617         struct {
 618                 uint32_t                                  count;
 619                 VkViewport                                viewports[MAX_VIEWPORTS];
 620         } viewport;
 621
 622         struct {
 623                 uint32_t                                  count;
 624                 VkRect2D                                  scissors[MAX_SCISSORS];
 625         } scissor;
 626
 627         float                                        line_width;
 628
 629         struct {
 630                 float                                     bias;
 631                 float                                     clamp;
 632                 float                                     slope;
 633         } depth_bias;
 634
 635         float                                        blend_constants[4];
 636
 637         struct {
 638                 float                                     min;
 639                 float                                     max;
 640         } depth_bounds;
 641
 642         struct {
 643                 uint32_t                                  front;
 644                 uint32_t                                  back;
 645         } stencil_compare_mask;
 646
 647         struct {
 648                 uint32_t                                  front;
 649                 uint32_t                                  back;
 650         } stencil_write_mask;
 651
 652         struct {
 653                 uint32_t                                  front;
 654                 uint32_t                                  back;
 655         } stencil_reference;
 656 };
 657
 658 extern const struct radv_dynamic_state default_dynamic_state;
 659
 660 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
 661                              const struct radv_dynamic_state *src,
 662                              uint32_t copy_mask);
 663 /**
 664  * Attachment state when recording a renderpass instance.
 665  *
 666  * The clear value is valid only if there exists a pending clear.
 667  */
 668 struct radv_attachment_state {
 669         VkImageAspectFlags                           pending_clear_aspects;
 670         VkClearValue                                 clear_value;
 671         VkImageLayout                                current_layout;
 672 };
 673
 674 struct radv_cmd_state {
 675         uint32_t                                      vb_dirty;
 676         radv_cmd_dirty_mask_t                         dirty;
 677         bool                                          vertex_descriptors_dirty;
 678
 679         struct radv_pipeline *                        pipeline;
 680         struct radv_pipeline *                        emitted_pipeline;
 681         struct radv_pipeline *                        compute_pipeline;
 682         struct radv_pipeline *                        emitted_compute_pipeline;
 683         struct radv_framebuffer *                     framebuffer;
 684         struct radv_render_pass *                     pass;
 685         const struct radv_subpass *                         subpass;
 686         struct radv_dynamic_state                     dynamic;
 687         struct radv_vertex_binding                    vertex_bindings[MAX_VBS];
 688         struct radv_descriptor_set *                  descriptors[MAX_SETS];
 689         struct radv_attachment_state *                attachments;
 690         VkRect2D                                     render_area;
 691         struct radv_buffer *                         index_buffer;
 692         uint32_t                                     index_type;
 693         uint32_t                                     index_offset;
 694         uint32_t                                     last_primitive_reset_index;
 695         enum radv_cmd_flush_bits                     flush_bits;
 696         unsigned                                     active_occlusion_queries;
 697         float                                        offset_scale;
 698         uint32_t                                      descriptors_dirty;
 699         uint32_t                                      trace_id;
 700         uint32_t                                      last_ia_multi_vgt_param;
 701 };
 702
 703 struct radv_cmd_pool {
 704         VkAllocationCallbacks                        alloc;
 705         struct list_head                             cmd_buffers;
 706         struct list_head                             free_cmd_buffers;
 707         uint32_t queue_family_index;
 708 };
 709
 710 struct radv_cmd_buffer_upload {
 711         uint8_t *map;
 712         unsigned offset;
 713         uint64_t size;
 714         struct radeon_winsys_bo *upload_bo;
 715         struct list_head list;
 716 };
 717
 718 struct radv_cmd_buffer {
 719         VK_LOADER_DATA                               _loader_data;
 720
 721         struct radv_device *                          device;
 722
 723         struct radv_cmd_pool *                        pool;
 724         struct list_head                             pool_link;
 725
 726         VkCommandBufferUsageFlags                    usage_flags;
 727         VkCommandBufferLevel                         level;
 728         struct radeon_winsys_cs *cs;
 729         struct radv_cmd_state state;
 730         uint32_t queue_family_index;
 731
 732         uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
 733         uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
 734         VkShaderStageFlags push_constant_stages;
 735
 736         struct radv_cmd_buffer_upload upload;
 737
 738         bool record_fail;
 739
 740         uint32_t scratch_size_needed;
 741         uint32_t compute_scratch_size_needed;
 742         uint32_t esgs_ring_size_needed;
 743         uint32_t gsvs_ring_size_needed;
 744
 745         int ring_offsets_idx; /* just used for verification */
 746 };
 747
 748 struct radv_image;
 749
 750 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
 751
 752 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
 753 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
 754
 755 void cik_create_gfx_config(struct radv_device *device);
 756
 757 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
 758                        int count, const VkViewport *viewports);
 759 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
 760                        int count, const VkRect2D *scissors);
 761 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
 762                                    bool instanced_draw, bool indirect_draw,
 763                                    uint32_t draw_vertex_count);
 764 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
 765                             enum chip_class chip_class,
 766                             bool is_mec,
 767                             enum radv_cmd_flush_bits flush_bits);
 768 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
 769                             enum chip_class chip_class,
 770                             bool is_mec,
 771                             enum radv_cmd_flush_bits flush_bits);
 772 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
 773 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
 774                            uint64_t src_va, uint64_t dest_va,
 775                            uint64_t size);
 776 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
 777                             uint64_t size, unsigned value);
 778 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
 779 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 780                               struct radv_descriptor_set *set,
 781                               unsigned idx);
 782 bool
 783 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
 784                              unsigned size,
 785                              unsigned alignment,
 786                              unsigned *out_offset,
 787                              void **ptr);
 788 void
 789 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
 790                             const struct radv_subpass *subpass,
 791                             bool transitions);
 792 bool
 793 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
 794                             unsigned size, unsigned alignmnet,
 795                             const void *data, unsigned *out_offset);
 796 void
 797 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
 798 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
 799 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
 800 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 801 unsigned radv_cayman_get_maxdist(int log_samples);
 802 void radv_device_init_msaa(struct radv_device *device);
 803 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
 804                                struct radv_image *image,
 805                                VkClearDepthStencilValue ds_clear_value,
 806                                VkImageAspectFlags aspects);
 807 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
 808                                struct radv_image *image,
 809                                int idx,
 810                                uint32_t color_values[2]);
 811 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
 812                       struct radeon_winsys_bo *bo,
 813                       uint64_t offset, uint64_t size, uint32_t value);
 814 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
 815 bool radv_get_memory_fd(struct radv_device *device,
 816                         struct radv_device_memory *memory,
 817                         int *pFD);
 818 /*
 819  * Takes x,y,z as exact numbers of invocations, instead of blocks.
 820  *
 821  * Limitations: Can't call normal dispatch functions without binding or rebinding
 822  *              the compute pipeline.
 823  */
 824 void radv_unaligned_dispatch(
 825         struct radv_cmd_buffer                      *cmd_buffer,
 826         uint32_t                                    x,
 827         uint32_t                                    y,
 828         uint32_t                                    z);
 829
 830 struct radv_event {
 831         struct radeon_winsys_bo *bo;
 832         uint64_t *map;
 833 };
 834
 835 struct nir_shader;
 836
 837 struct radv_shader_module {
 838         struct nir_shader *                          nir;
 839         unsigned char                                sha1[20];
 840         uint32_t                                     size;
 841         char                                         data[0];
 842 };
 843
 844 union ac_shader_variant_key;
 845
 846 void
 847 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
 848                  const char *entrypoint,
 849                  const VkSpecializationInfo *spec_info,
 850                  const struct radv_pipeline_layout *layout,
 851                  const union ac_shader_variant_key *key,
 852                  uint32_t is_geom_copy_shader);
 853
 854 static inline gl_shader_stage
 855 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
 856 {
 857         assert(__builtin_popcount(vk_stage) == 1);
 858         return ffs(vk_stage) - 1;
 859 }
 860
 861 static inline VkShaderStageFlagBits
 862 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
 863 {
 864         return (1 << mesa_stage);
 865 }
 866
 867 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
 868
 869 #define radv_foreach_stage(stage, stage_bits)                           \
 870         for (gl_shader_stage stage,                                     \
 871                      __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
 872              stage = __builtin_ffs(__tmp) - 1, __tmp;                   \
 873              __tmp &= ~(1 << (stage)))
 874
 875 struct radv_shader_variant {
 876         uint32_t ref_count;
 877
 878         struct radeon_winsys_bo *bo;
 879         struct ac_shader_config config;
 880         struct ac_shader_variant_info info;
 881         unsigned rsrc1;
 882         unsigned rsrc2;
 883         uint32_t code_size;
 884 };
 885
 886 struct radv_depth_stencil_state {
 887         uint32_t db_depth_control;
 888         uint32_t db_stencil_control;
 889         uint32_t db_render_control;
 890         uint32_t db_render_override2;
 891 };
 892
 893 struct radv_blend_state {
 894         uint32_t cb_color_control;
 895         uint32_t cb_target_mask;
 896         uint32_t sx_mrt0_blend_opt[8];
 897         uint32_t cb_blend_control[8];
 898
 899         uint32_t spi_shader_col_format;
 900         uint32_t cb_shader_mask;
 901         uint32_t db_alpha_to_mask;
 902 };
 903
 904 unsigned radv_format_meta_fs_key(VkFormat format);
 905
 906 struct radv_raster_state {
 907         uint32_t pa_cl_clip_cntl;
 908         uint32_t pa_cl_vs_out_cntl;
 909         uint32_t spi_interp_control;
 910         uint32_t pa_su_point_size;
 911         uint32_t pa_su_point_minmax;
 912         uint32_t pa_su_line_cntl;
 913         uint32_t pa_su_vtx_cntl;
 914         uint32_t pa_su_sc_mode_cntl;
 915 };
 916
 917 struct radv_multisample_state {
 918         uint32_t db_eqaa;
 919         uint32_t pa_sc_line_cntl;
 920         uint32_t pa_sc_mode_cntl_0;
 921         uint32_t pa_sc_mode_cntl_1;
 922         uint32_t pa_sc_aa_config;
 923         uint32_t pa_sc_aa_mask[2];
 924         unsigned num_samples;
 925 };
 926
 927 struct radv_prim_vertex_count {
 928         uint8_t min;
 929         uint8_t incr;
 930 };
 931
 932 struct radv_pipeline {
 933         struct radv_device *                          device;
 934         uint32_t                                     dynamic_state_mask;
 935         struct radv_dynamic_state                     dynamic_state;
 936
 937         struct radv_pipeline_layout *                 layout;
 938
 939         bool                                         needs_data_cache;
 940
 941         struct radv_shader_variant *                 shaders[MESA_SHADER_STAGES];
 942         struct radv_shader_variant *gs_copy_shader;
 943         VkShaderStageFlags                           active_stages;
 944
 945         uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
 946         uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
 947         uint32_t va_binding[MAX_VERTEX_ATTRIBS];
 948         uint32_t va_offset[MAX_VERTEX_ATTRIBS];
 949         uint32_t num_vertex_attribs;
 950         uint32_t                                     binding_stride[MAX_VBS];
 951
 952         union {
 953                 struct {
 954                         struct radv_blend_state blend;
 955                         struct radv_depth_stencil_state ds;
 956                         struct radv_raster_state raster;
 957                         struct radv_multisample_state ms;
 958                         unsigned prim;
 959                         unsigned gs_out;
 960                         bool prim_restart_enable;
 961                         unsigned esgs_ring_size;
 962                         unsigned gsvs_ring_size;
 963                         struct radv_prim_vertex_count prim_vertex_count;
 964                 } graphics;
 965         };
 966
 967         unsigned max_waves;
 968         unsigned scratch_bytes_per_wave;
 969 };
 970
 971 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
 972 {
 973         return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
 974 }
 975
 976 struct radv_graphics_pipeline_create_info {
 977         bool use_rectlist;
 978         bool db_depth_clear;
 979         bool db_stencil_clear;
 980         bool db_depth_disable_expclear;
 981         bool db_stencil_disable_expclear;
 982         bool db_flush_depth_inplace;
 983         bool db_flush_stencil_inplace;
 984         bool db_resummarize;
 985         uint32_t custom_blend_mode;
 986 };
 987
 988 VkResult
 989 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
 990                    struct radv_pipeline_cache *cache,
 991                    const VkGraphicsPipelineCreateInfo *pCreateInfo,
 992                    const struct radv_graphics_pipeline_create_info *extra,
 993                    const VkAllocationCallbacks *alloc);
 994
 995 VkResult
 996 radv_graphics_pipeline_create(VkDevice device,
 997                               VkPipelineCache cache,
 998                               const VkGraphicsPipelineCreateInfo *pCreateInfo,
 999                               const struct radv_graphics_pipeline_create_info *extra,
1000                               const VkAllocationCallbacks *alloc,
1001                               VkPipeline *pPipeline);
1002
1003 struct vk_format_description;
1004 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1005                                           int first_non_void);
1006 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1007                                          int first_non_void);
1008 uint32_t radv_translate_colorformat(VkFormat format);
1009 uint32_t radv_translate_color_numformat(VkFormat format,
1010                                         const struct vk_format_description *desc,
1011                                         int first_non_void);
1012 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1013 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1014 uint32_t radv_translate_dbformat(VkFormat format);
1015 uint32_t radv_translate_tex_dataformat(VkFormat format,
1016                                        const struct vk_format_description *desc,
1017                                        int first_non_void);
1018 uint32_t radv_translate_tex_numformat(VkFormat format,
1019                                       const struct vk_format_description *desc,
1020                                       int first_non_void);
1021 bool radv_format_pack_clear_color(VkFormat format,
1022                                   uint32_t clear_vals[2],
1023                                   VkClearColorValue *value);
1024 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1025
1026 struct radv_fmask_info {
1027         uint64_t offset;
1028         uint64_t size;
1029         unsigned alignment;
1030         unsigned pitch_in_pixels;
1031         unsigned bank_height;
1032         unsigned slice_tile_max;
1033         unsigned tile_mode_index;
1034 };
1035
1036 struct radv_cmask_info {
1037         uint64_t offset;
1038         uint64_t size;
1039         unsigned alignment;
1040         unsigned slice_tile_max;
1041         unsigned base_address_reg;
1042 };
1043
1044 struct r600_htile_info {
1045         uint64_t offset;
1046         uint64_t size;
1047         unsigned pitch;
1048         unsigned height;
1049         unsigned xalign;
1050         unsigned yalign;
1051 };
1052
1053 struct radv_image {
1054         VkImageType type;
1055         /* The original VkFormat provided by the client.  This may not match any
1056          * of the actual surface formats.
1057          */
1058         VkFormat vk_format;
1059         VkImageAspectFlags aspects;
1060         VkExtent3D extent;
1061         uint32_t levels;
1062         uint32_t array_size;
1063         uint32_t samples; /**< VkImageCreateInfo::samples */
1064         VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1065         VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1066
1067         VkDeviceSize size;
1068         uint32_t alignment;
1069
1070         bool exclusive;
1071         unsigned queue_family_mask;
1072
1073         /* Set when bound */
1074         struct radeon_winsys_bo *bo;
1075         VkDeviceSize offset;
1076         uint32_t dcc_offset;
1077         uint32_t htile_offset;
1078         struct radeon_surf surface;
1079
1080         struct radv_fmask_info fmask;
1081         struct radv_cmask_info cmask;
1082         uint32_t clear_value_offset;
1083 };
1084
1085 bool radv_layout_has_htile(const struct radv_image *image,
1086                            VkImageLayout layout);
1087 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1088                                      VkImageLayout layout);
1089 bool radv_layout_can_expclear(const struct radv_image *image,
1090                               VkImageLayout layout);
1091 bool radv_layout_can_fast_clear(const struct radv_image *image,
1092                                 VkImageLayout layout,
1093                                 unsigned queue_mask);
1094
1095
1096 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1097
1098 static inline uint32_t
1099 radv_get_layerCount(const struct radv_image *image,
1100                     const VkImageSubresourceRange *range)
1101 {
1102         return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1103                 image->array_size - range->baseArrayLayer : range->layerCount;
1104 }
1105
1106 static inline uint32_t
1107 radv_get_levelCount(const struct radv_image *image,
1108                     const VkImageSubresourceRange *range)
1109 {
1110         return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1111                 image->levels - range->baseMipLevel : range->levelCount;
1112 }
1113
1114 struct radeon_bo_metadata;
1115 void
1116 radv_init_metadata(struct radv_device *device,
1117                    struct radv_image *image,
1118                    struct radeon_bo_metadata *metadata);
1119
1120 struct radv_image_view {
1121         struct radv_image *image; /**< VkImageViewCreateInfo::image */
1122         struct radeon_winsys_bo *bo;
1123
1124         VkImageViewType type;
1125         VkImageAspectFlags aspect_mask;
1126         VkFormat vk_format;
1127         uint32_t base_layer;
1128         uint32_t layer_count;
1129         uint32_t base_mip;
1130         VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1131
1132         uint32_t descriptor[8];
1133         uint32_t fmask_descriptor[8];
1134 };
1135
1136 struct radv_image_create_info {
1137         const VkImageCreateInfo *vk_info;
1138         uint32_t stride;
1139         bool scanout;
1140 };
1141
1142 VkResult radv_image_create(VkDevice _device,
1143                            const struct radv_image_create_info *info,
1144                            const VkAllocationCallbacks* alloc,
1145                            VkImage *pImage);
1146
1147 void radv_image_view_init(struct radv_image_view *view,
1148                           struct radv_device *device,
1149                           const VkImageViewCreateInfo* pCreateInfo,
1150                           struct radv_cmd_buffer *cmd_buffer,
1151                           VkImageUsageFlags usage_mask);
1152 void radv_image_set_optimal_micro_tile_mode(struct radv_device *device,
1153                                             struct radv_image *image, uint32_t micro_tile_mode);
1154 struct radv_buffer_view {
1155         struct radeon_winsys_bo *bo;
1156         VkFormat vk_format;
1157         uint64_t range; /**< VkBufferViewCreateInfo::range */
1158         uint32_t state[4];
1159 };
1160 void radv_buffer_view_init(struct radv_buffer_view *view,
1161                            struct radv_device *device,
1162                            const VkBufferViewCreateInfo* pCreateInfo,
1163                            struct radv_cmd_buffer *cmd_buffer);
1164
1165 static inline struct VkExtent3D
1166 radv_sanitize_image_extent(const VkImageType imageType,
1167                            const struct VkExtent3D imageExtent)
1168 {
1169         switch (imageType) {
1170         case VK_IMAGE_TYPE_1D:
1171                 return (VkExtent3D) { imageExtent.width, 1, 1 };
1172         case VK_IMAGE_TYPE_2D:
1173                 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1174         case VK_IMAGE_TYPE_3D:
1175                 return imageExtent;
1176         default:
1177                 unreachable("invalid image type");
1178         }
1179 }
1180
1181 static inline struct VkOffset3D
1182 radv_sanitize_image_offset(const VkImageType imageType,
1183                            const struct VkOffset3D imageOffset)
1184 {
1185         switch (imageType) {
1186         case VK_IMAGE_TYPE_1D:
1187                 return (VkOffset3D) { imageOffset.x, 0, 0 };
1188         case VK_IMAGE_TYPE_2D:
1189                 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1190         case VK_IMAGE_TYPE_3D:
1191                 return imageOffset;
1192         default:
1193                 unreachable("invalid image type");
1194         }
1195 }
1196
1197 struct radv_sampler {
1198         uint32_t state[4];
1199 };
1200
1201 struct radv_color_buffer_info {
1202         uint32_t cb_color_base;
1203         uint32_t cb_color_pitch;
1204         uint32_t cb_color_slice;
1205         uint32_t cb_color_view;
1206         uint32_t cb_color_info;
1207         uint32_t cb_color_attrib;
1208         uint32_t cb_dcc_control;
1209         uint32_t cb_color_cmask;
1210         uint32_t cb_color_cmask_slice;
1211         uint32_t cb_color_fmask;
1212         uint32_t cb_color_fmask_slice;
1213         uint32_t cb_clear_value0;
1214         uint32_t cb_clear_value1;
1215         uint32_t cb_dcc_base;
1216         uint32_t micro_tile_mode;
1217 };
1218
1219 struct radv_ds_buffer_info {
1220         uint32_t db_depth_info;
1221         uint32_t db_z_info;
1222         uint32_t db_stencil_info;
1223         uint32_t db_z_read_base;
1224         uint32_t db_stencil_read_base;
1225         uint32_t db_z_write_base;
1226         uint32_t db_stencil_write_base;
1227         uint32_t db_depth_view;
1228         uint32_t db_depth_size;
1229         uint32_t db_depth_slice;
1230         uint32_t db_htile_surface;
1231         uint32_t db_htile_data_base;
1232         uint32_t pa_su_poly_offset_db_fmt_cntl;
1233         float offset_scale;
1234 };
1235
1236 struct radv_attachment_info {
1237         union {
1238                 struct radv_color_buffer_info cb;
1239                 struct radv_ds_buffer_info ds;
1240         };
1241         struct radv_image_view *attachment;
1242 };
1243
1244 struct radv_framebuffer {
1245         uint32_t                                     width;
1246         uint32_t                                     height;
1247         uint32_t                                     layers;
1248
1249         uint32_t                                     attachment_count;
1250         struct radv_attachment_info                  attachments[0];
1251 };
1252
1253 struct radv_subpass_barrier {
1254         VkPipelineStageFlags src_stage_mask;
1255         VkAccessFlags        src_access_mask;
1256         VkAccessFlags        dst_access_mask;
1257 };
1258
1259 struct radv_subpass {
1260         uint32_t                                     input_count;
1261         VkAttachmentReference *                      input_attachments;
1262         uint32_t                                     color_count;
1263         VkAttachmentReference *                      color_attachments;
1264         VkAttachmentReference *                      resolve_attachments;
1265         VkAttachmentReference                        depth_stencil_attachment;
1266
1267         /** Subpass has at least one resolve attachment */
1268         bool                                         has_resolve;
1269
1270         struct radv_subpass_barrier                  start_barrier;
1271 };
1272
1273 struct radv_render_pass_attachment {
1274         VkFormat                                     format;
1275         uint32_t                                     samples;
1276         VkAttachmentLoadOp                           load_op;
1277         VkAttachmentLoadOp                           stencil_load_op;
1278         VkImageLayout                                initial_layout;
1279         VkImageLayout                                final_layout;
1280 };
1281
1282 struct radv_render_pass {
1283         uint32_t                                     attachment_count;
1284         uint32_t                                     subpass_count;
1285         VkAttachmentReference *                      subpass_attachments;
1286         struct radv_render_pass_attachment *         attachments;
1287         struct radv_subpass_barrier                  end_barrier;
1288         struct radv_subpass                          subpasses[0];
1289 };
1290
1291 VkResult radv_device_init_meta(struct radv_device *device);
1292 void radv_device_finish_meta(struct radv_device *device);
1293
1294 struct radv_query_pool {
1295         struct radeon_winsys_bo *bo;
1296         uint32_t stride;
1297         uint32_t availability_offset;
1298         char *ptr;
1299         VkQueryType type;
1300 };
1301
1302 VkResult
1303 radv_temp_descriptor_set_create(struct radv_device *device,
1304                                 struct radv_cmd_buffer *cmd_buffer,
1305                                 VkDescriptorSetLayout _layout,
1306                                 VkDescriptorSet *_set);
1307
1308 void
1309 radv_temp_descriptor_set_destroy(struct radv_device *device,
1310                                  VkDescriptorSet _set);
1311 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1312                            struct radv_image *image, uint32_t value);
1313 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1314                          struct radv_image *image, uint32_t value);
1315
1316 struct radv_fence {
1317         struct radeon_winsys_fence *fence;
1318         bool submitted;
1319         bool signalled;
1320 };
1321
1322 struct radeon_winsys_sem;
1323
1324 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType)         \
1325                                                                 \
1326         static inline struct __radv_type *                      \
1327         __radv_type ## _from_handle(__VkType _handle)           \
1328         {                                                       \
1329                 return (struct __radv_type *) _handle;          \
1330         }                                                       \
1331                                                                 \
1332         static inline __VkType                                  \
1333         __radv_type ## _to_handle(struct __radv_type *_obj)     \
1334         {                                                       \
1335                 return (__VkType) _obj;                         \
1336         }
1337
1338 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType)         \
1339                                                                         \
1340         static inline struct __radv_type *                              \
1341         __radv_type ## _from_handle(__VkType _handle)                   \
1342         {                                                               \
1343                 return (struct __radv_type *)(uintptr_t) _handle;       \
1344         }                                                               \
1345                                                                         \
1346         static inline __VkType                                          \
1347         __radv_type ## _to_handle(struct __radv_type *_obj)             \
1348         {                                                               \
1349                 return (__VkType)(uintptr_t) _obj;                      \
1350         }
1351
1352 #define RADV_FROM_HANDLE(__radv_type, __name, __handle)                 \
1353         struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1354
1355 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1356 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1357 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1358 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1359 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1360
1361 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1362 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1363 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1364 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1365 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1366 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1367 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1368 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1369 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1370 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1371 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1372 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1373 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1374 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1375 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1376 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1377 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1378 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1379 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1380 RADV_DEFINE_NONDISP_HANDLE_CASTS(radeon_winsys_sem, VkSemaphore)
1381
1382 #endif /* RADV_PRIVATE_H */