src/amd/vulkan/radv_private.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_PRIVATE_H
  29 #define RADV_PRIVATE_H
  30
  31 #include <stdlib.h>
  32 #include <stdio.h>
  33 #include <stdbool.h>
  34 #include <pthread.h>
  35 #include <assert.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #ifdef HAVE_VALGRIND
  39 #include <valgrind.h>
  40 #include <memcheck.h>
  41 #define VG(x) x
  42 #else
  43 #define VG(x)
  44 #endif
  45
  46 #include <amdgpu.h>
  47 #include "compiler/shader_enums.h"
  48 #include "util/macros.h"
  49 #include "util/list.h"
  50 #include "main/macros.h"
  51 #include "vk_alloc.h"
  52
  53 #include "radv_radeon_winsys.h"
  54 #include "ac_binary.h"
  55 #include "ac_nir_to_llvm.h"
  56 #include "ac_gpu_info.h"
  57 #include "ac_surface.h"
  58 #include "radv_debug.h"
  59 #include "radv_descriptor_set.h"
  60
  61 #include <llvm-c/TargetMachine.h>
  62
  63 /* Pre-declarations needed for WSI entrypoints */
  64 struct wl_surface;
  65 struct wl_display;
  66 typedef struct xcb_connection_t xcb_connection_t;
  67 typedef uint32_t xcb_visualid_t;
  68 typedef uint32_t xcb_window_t;
  69
  70 #include <vulkan/vulkan.h>
  71 #include <vulkan/vulkan_intel.h>
  72 #include <vulkan/vk_icd.h>
  73
  74 #include "radv_entrypoints.h"
  75
  76 #include "wsi_common.h"
  77
  78 #define MAX_VBS         32
  79 #define MAX_VERTEX_ATTRIBS 32
  80 #define MAX_RTS          8
  81 #define MAX_VIEWPORTS   16
  82 #define MAX_SCISSORS    16
  83 #define MAX_PUSH_CONSTANTS_SIZE 128
  84 #define MAX_PUSH_DESCRIPTORS 32
  85 #define MAX_DYNAMIC_BUFFERS 16
  86 #define MAX_SAMPLES_LOG2 4
  87 #define NUM_META_FS_KEYS 11
  88 #define RADV_MAX_DRM_DEVICES 8
  89
  90 #define NUM_DEPTH_CLEAR_PIPELINES 3
  91
  92 enum radv_mem_heap {
  93         RADV_MEM_HEAP_VRAM,
  94         RADV_MEM_HEAP_VRAM_CPU_ACCESS,
  95         RADV_MEM_HEAP_GTT,
  96         RADV_MEM_HEAP_COUNT
  97 };
  98
  99 enum radv_mem_type {
 100         RADV_MEM_TYPE_VRAM,
 101         RADV_MEM_TYPE_GTT_WRITE_COMBINE,
 102         RADV_MEM_TYPE_VRAM_CPU_ACCESS,
 103         RADV_MEM_TYPE_GTT_CACHED,
 104         RADV_MEM_TYPE_COUNT
 105 };
 106
 107 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
 108
 109 static inline uint32_t
 110 align_u32(uint32_t v, uint32_t a)
 111 {
 112         assert(a != 0 && a == (a & -a));
 113         return (v + a - 1) & ~(a - 1);
 114 }
 115
 116 static inline uint32_t
 117 align_u32_npot(uint32_t v, uint32_t a)
 118 {
 119         return (v + a - 1) / a * a;
 120 }
 121
 122 static inline uint64_t
 123 align_u64(uint64_t v, uint64_t a)
 124 {
 125         assert(a != 0 && a == (a & -a));
 126         return (v + a - 1) & ~(a - 1);
 127 }
 128
 129 static inline int32_t
 130 align_i32(int32_t v, int32_t a)
 131 {
 132         assert(a != 0 && a == (a & -a));
 133         return (v + a - 1) & ~(a - 1);
 134 }
 135
 136 /** Alignment must be a power of 2. */
 137 static inline bool
 138 radv_is_aligned(uintmax_t n, uintmax_t a)
 139 {
 140         assert(a == (a & -a));
 141         return (n & (a - 1)) == 0;
 142 }
 143
 144 static inline uint32_t
 145 round_up_u32(uint32_t v, uint32_t a)
 146 {
 147         return (v + a - 1) / a;
 148 }
 149
 150 static inline uint64_t
 151 round_up_u64(uint64_t v, uint64_t a)
 152 {
 153         return (v + a - 1) / a;
 154 }
 155
 156 static inline uint32_t
 157 radv_minify(uint32_t n, uint32_t levels)
 158 {
 159         if (unlikely(n == 0))
 160                 return 0;
 161         else
 162                 return MAX2(n >> levels, 1);
 163 }
 164 static inline float
 165 radv_clamp_f(float f, float min, float max)
 166 {
 167         assert(min < max);
 168
 169         if (f > max)
 170                 return max;
 171         else if (f < min)
 172                 return min;
 173         else
 174                 return f;
 175 }
 176
 177 static inline bool
 178 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
 179 {
 180         if (*inout_mask & clear_mask) {
 181                 *inout_mask &= ~clear_mask;
 182                 return true;
 183         } else {
 184                 return false;
 185         }
 186 }
 187
 188 #define for_each_bit(b, dword)                          \
 189         for (uint32_t __dword = (dword);                \
 190              (b) = __builtin_ffs(__dword) - 1, __dword; \
 191              __dword &= ~(1 << (b)))
 192
 193 #define typed_memcpy(dest, src, count) ({                               \
 194                         STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
 195                         memcpy((dest), (src), (count) * sizeof(*(src))); \
 196                 })
 197
 198 #define zero(x) (memset(&(x), 0, sizeof(x)))
 199
 200 /* Whenever we generate an error, pass it through this function. Useful for
 201  * debugging, where we can break on it. Only call at error site, not when
 202  * propagating errors. Might be useful to plug in a stack trace here.
 203  */
 204
 205 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
 206
 207 #ifdef DEBUG
 208 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
 209 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
 210 #else
 211 #define vk_error(error) error
 212 #define vk_errorf(error, format, ...) error
 213 #endif
 214
 215 void __radv_finishme(const char *file, int line, const char *format, ...)
 216         radv_printflike(3, 4);
 217 void radv_loge(const char *format, ...) radv_printflike(1, 2);
 218 void radv_loge_v(const char *format, va_list va);
 219
 220 /**
 221  * Print a FINISHME message, including its source location.
 222  */
 223 #define radv_finishme(format, ...)                                      \
 224         do { \
 225                 static bool reported = false; \
 226                 if (!reported) { \
 227                         __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
 228                         reported = true; \
 229                 } \
 230         } while (0)
 231
 232 /* A non-fatal assert.  Useful for debugging. */
 233 #ifdef DEBUG
 234 #define radv_assert(x) ({                                               \
 235                         if (unlikely(!(x)))                             \
 236                                 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
 237                 })
 238 #else
 239 #define radv_assert(x)
 240 #endif
 241
 242 #define stub_return(v)                                  \
 243         do {                                            \
 244                 radv_finishme("stub %s", __func__);     \
 245                 return (v);                             \
 246         } while (0)
 247
 248 #define stub()                                          \
 249         do {                                            \
 250                 radv_finishme("stub %s", __func__);     \
 251                 return;                                 \
 252         } while (0)
 253
 254 void *radv_lookup_entrypoint(const char *name);
 255
 256 struct radv_extensions {
 257         VkExtensionProperties       *ext_array;
 258         uint32_t                    num_ext;
 259 };
 260
 261 struct radv_physical_device {
 262         VK_LOADER_DATA                              _loader_data;
 263
 264         struct radv_instance *                       instance;
 265
 266         struct radeon_winsys *ws;
 267         struct radeon_info rad_info;
 268         char                                        path[20];
 269         const char *                                name;
 270         uint8_t                                     uuid[VK_UUID_SIZE];
 271         uint8_t                                     device_uuid[VK_UUID_SIZE];
 272
 273         int local_fd;
 274         struct wsi_device                       wsi_device;
 275         struct radv_extensions                      extensions;
 276
 277         bool has_rbplus; /* if RB+ register exist */
 278         bool rbplus_allowed; /* if RB+ is allowed */
 279 };
 280
 281 struct radv_instance {
 282         VK_LOADER_DATA                              _loader_data;
 283
 284         VkAllocationCallbacks                       alloc;
 285
 286         uint32_t                                    apiVersion;
 287         int                                         physicalDeviceCount;
 288         struct radv_physical_device                 physicalDevices[RADV_MAX_DRM_DEVICES];
 289
 290         uint64_t debug_flags;
 291 };
 292
 293 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
 294 void radv_finish_wsi(struct radv_physical_device *physical_device);
 295
 296 struct cache_entry;
 297
 298 struct radv_pipeline_cache {
 299         struct radv_device *                          device;
 300         pthread_mutex_t                              mutex;
 301
 302         uint32_t                                     total_size;
 303         uint32_t                                     table_size;
 304         uint32_t                                     kernel_count;
 305         struct cache_entry **                        hash_table;
 306         bool                                         modified;
 307
 308         VkAllocationCallbacks                        alloc;
 309 };
 310
 311 void
 312 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
 313                          struct radv_device *device);
 314 void
 315 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
 316 void
 317 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
 318                          const void *data, size_t size);
 319
 320 struct radv_shader_variant *
 321 radv_create_shader_variant_from_pipeline_cache(struct radv_device *device,
 322                                                struct radv_pipeline_cache *cache,
 323                                                const unsigned char *sha1);
 324
 325 struct radv_shader_variant *
 326 radv_pipeline_cache_insert_shader(struct radv_pipeline_cache *cache,
 327                                   const unsigned char *sha1,
 328                                   struct radv_shader_variant *variant,
 329                                   const void *code, unsigned code_size);
 330
 331 void radv_shader_variant_destroy(struct radv_device *device,
 332                                  struct radv_shader_variant *variant);
 333
 334 struct radv_meta_state {
 335         VkAllocationCallbacks alloc;
 336
 337         struct radv_pipeline_cache cache;
 338
 339         /**
 340          * Use array element `i` for images with `2^i` samples.
 341          */
 342         struct {
 343                 VkRenderPass render_pass[NUM_META_FS_KEYS];
 344                 struct radv_pipeline *color_pipelines[NUM_META_FS_KEYS];
 345
 346                 VkRenderPass depthstencil_rp;
 347                 struct radv_pipeline *depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 348                 struct radv_pipeline *stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 349                 struct radv_pipeline *depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 350         } clear[1 + MAX_SAMPLES_LOG2];
 351
 352         VkPipelineLayout                          clear_color_p_layout;
 353         VkPipelineLayout                          clear_depth_p_layout;
 354         struct {
 355                 VkRenderPass render_pass[NUM_META_FS_KEYS];
 356
 357                 /** Pipeline that blits from a 1D image. */
 358                 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
 359
 360                 /** Pipeline that blits from a 2D image. */
 361                 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
 362
 363                 /** Pipeline that blits from a 3D image. */
 364                 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
 365
 366                 VkRenderPass depth_only_rp;
 367                 VkPipeline depth_only_1d_pipeline;
 368                 VkPipeline depth_only_2d_pipeline;
 369                 VkPipeline depth_only_3d_pipeline;
 370
 371                 VkRenderPass stencil_only_rp;
 372                 VkPipeline stencil_only_1d_pipeline;
 373                 VkPipeline stencil_only_2d_pipeline;
 374                 VkPipeline stencil_only_3d_pipeline;
 375                 VkPipelineLayout                          pipeline_layout;
 376                 VkDescriptorSetLayout                     ds_layout;
 377         } blit;
 378
 379         struct {
 380                 VkRenderPass render_passes[NUM_META_FS_KEYS];
 381
 382                 VkPipelineLayout p_layouts[2];
 383                 VkDescriptorSetLayout ds_layouts[2];
 384                 VkPipeline pipelines[2][NUM_META_FS_KEYS];
 385
 386                 VkRenderPass depth_only_rp;
 387                 VkPipeline depth_only_pipeline[2];
 388
 389                 VkRenderPass stencil_only_rp;
 390                 VkPipeline stencil_only_pipeline[2];
 391         } blit2d;
 392
 393         struct {
 394                 VkPipelineLayout                          img_p_layout;
 395                 VkDescriptorSetLayout                     img_ds_layout;
 396                 VkPipeline pipeline;
 397         } itob;
 398         struct {
 399                 VkRenderPass render_pass;
 400                 VkPipelineLayout                          img_p_layout;
 401                 VkDescriptorSetLayout                     img_ds_layout;
 402                 VkPipeline pipeline;
 403         } btoi;
 404         struct {
 405                 VkPipelineLayout                          img_p_layout;
 406                 VkDescriptorSetLayout                     img_ds_layout;
 407                 VkPipeline pipeline;
 408         } itoi;
 409         struct {
 410                 VkPipelineLayout                          img_p_layout;
 411                 VkDescriptorSetLayout                     img_ds_layout;
 412                 VkPipeline pipeline;
 413         } cleari;
 414
 415         struct {
 416                 VkPipeline                                pipeline;
 417                 VkRenderPass                              pass;
 418         } resolve;
 419
 420         struct {
 421                 VkDescriptorSetLayout                     ds_layout;
 422                 VkPipelineLayout                          p_layout;
 423                 struct {
 424                         VkPipeline                                pipeline;
 425                         VkPipeline                                i_pipeline;
 426                         VkPipeline                                srgb_pipeline;
 427                 } rc[MAX_SAMPLES_LOG2];
 428         } resolve_compute;
 429
 430         struct {
 431                 VkDescriptorSetLayout                     ds_layout;
 432                 VkPipelineLayout                          p_layout;
 433
 434                 struct {
 435                         VkRenderPass srgb_render_pass;
 436                         VkPipeline   srgb_pipeline;
 437                         VkRenderPass render_pass[NUM_META_FS_KEYS];
 438                         VkPipeline   pipeline[NUM_META_FS_KEYS];
 439                 } rc[MAX_SAMPLES_LOG2];
 440         } resolve_fragment;
 441
 442         struct {
 443                 VkPipeline                                decompress_pipeline;
 444                 VkPipeline                                resummarize_pipeline;
 445                 VkRenderPass                              pass;
 446         } depth_decomp;
 447
 448         struct {
 449                 VkPipeline                                cmask_eliminate_pipeline;
 450                 VkPipeline                                fmask_decompress_pipeline;
 451                 VkRenderPass                              pass;
 452         } fast_clear_flush;
 453
 454         struct {
 455                 VkPipelineLayout fill_p_layout;
 456                 VkPipelineLayout copy_p_layout;
 457                 VkDescriptorSetLayout fill_ds_layout;
 458                 VkDescriptorSetLayout copy_ds_layout;
 459                 VkPipeline fill_pipeline;
 460                 VkPipeline copy_pipeline;
 461         } buffer;
 462
 463         struct {
 464                 VkDescriptorSetLayout ds_layout;
 465                 VkPipelineLayout p_layout;
 466                 VkPipeline occlusion_query_pipeline;
 467                 VkPipeline pipeline_statistics_query_pipeline;
 468         } query;
 469 };
 470
 471 /* queue types */
 472 #define RADV_QUEUE_GENERAL 0
 473 #define RADV_QUEUE_COMPUTE 1
 474 #define RADV_QUEUE_TRANSFER 2
 475
 476 #define RADV_MAX_QUEUE_FAMILIES 3
 477
 478 enum ring_type radv_queue_family_to_ring(int f);
 479
 480 struct radv_queue {
 481         VK_LOADER_DATA                              _loader_data;
 482         struct radv_device *                         device;
 483         struct radeon_winsys_ctx                    *hw_ctx;
 484         int queue_family_index;
 485         int queue_idx;
 486
 487         uint32_t scratch_size;
 488         uint32_t compute_scratch_size;
 489         uint32_t esgs_ring_size;
 490         uint32_t gsvs_ring_size;
 491         bool has_tess_rings;
 492         bool has_sample_positions;
 493
 494         struct radeon_winsys_bo *scratch_bo;
 495         struct radeon_winsys_bo *descriptor_bo;
 496         struct radeon_winsys_bo *compute_scratch_bo;
 497         struct radeon_winsys_bo *esgs_ring_bo;
 498         struct radeon_winsys_bo *gsvs_ring_bo;
 499         struct radeon_winsys_bo *tess_factor_ring_bo;
 500         struct radeon_winsys_bo *tess_offchip_ring_bo;
 501         struct radeon_winsys_cs *initial_preamble_cs;
 502         struct radeon_winsys_cs *continue_preamble_cs;
 503 };
 504
 505 struct radv_device {
 506         VK_LOADER_DATA                              _loader_data;
 507
 508         VkAllocationCallbacks                       alloc;
 509
 510         struct radv_instance *                       instance;
 511         struct radeon_winsys *ws;
 512
 513         struct radv_meta_state                       meta_state;
 514
 515         struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
 516         int queue_count[RADV_MAX_QUEUE_FAMILIES];
 517         struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
 518         struct radeon_winsys_cs *flush_cs[RADV_MAX_QUEUE_FAMILIES];
 519         struct radeon_winsys_cs *flush_shader_cs[RADV_MAX_QUEUE_FAMILIES];
 520         uint64_t debug_flags;
 521
 522         bool llvm_supports_spill;
 523         bool has_distributed_tess;
 524         uint32_t tess_offchip_block_dw_size;
 525         uint32_t scratch_waves;
 526
 527         uint32_t gs_table_depth;
 528
 529         /* MSAA sample locations.
 530          * The first index is the sample index.
 531          * The second index is the coordinate: X, Y. */
 532         float sample_locations_1x[1][2];
 533         float sample_locations_2x[2][2];
 534         float sample_locations_4x[4][2];
 535         float sample_locations_8x[8][2];
 536         float sample_locations_16x[16][2];
 537
 538         /* CIK and later */
 539         uint32_t gfx_init_size_dw;
 540         struct radeon_winsys_bo                      *gfx_init;
 541
 542         struct radeon_winsys_bo                      *trace_bo;
 543         uint32_t                                     *trace_id_ptr;
 544
 545         struct radv_physical_device                  *physical_device;
 546
 547         /* Backup in-memory cache to be used if the app doesn't provide one */
 548         struct radv_pipeline_cache *                mem_cache;
 549 };
 550
 551 struct radv_device_memory {
 552         struct radeon_winsys_bo                      *bo;
 553         /* for dedicated allocations */
 554         struct radv_image                            *image;
 555         struct radv_buffer                           *buffer;
 556         uint32_t                                     type_index;
 557         VkDeviceSize                                 map_size;
 558         void *                                       map;
 559 };
 560
 561
 562 struct radv_descriptor_range {
 563         uint64_t va;
 564         uint32_t size;
 565 };
 566
 567 struct radv_descriptor_set {
 568         const struct radv_descriptor_set_layout *layout;
 569         uint32_t size;
 570
 571         struct radeon_winsys_bo *bo;
 572         uint64_t va;
 573         uint32_t *mapped_ptr;
 574         struct radv_descriptor_range *dynamic_descriptors;
 575
 576         struct list_head vram_list;
 577
 578         struct radeon_winsys_bo *descriptors[0];
 579 };
 580
 581 struct radv_push_descriptor_set
 582 {
 583         struct radv_descriptor_set set;
 584         uint32_t capacity;
 585 };
 586
 587 struct radv_descriptor_pool {
 588         struct radeon_winsys_bo *bo;
 589         uint8_t *mapped_ptr;
 590         uint64_t current_offset;
 591         uint64_t size;
 592
 593         struct list_head vram_list;
 594
 595         uint8_t *host_memory_base;
 596         uint8_t *host_memory_ptr;
 597         uint8_t *host_memory_end;
 598 };
 599
 600 struct radv_descriptor_update_template_entry {
 601         VkDescriptorType descriptor_type;
 602
 603         /* The number of descriptors to update */
 604         uint32_t descriptor_count;
 605
 606         /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
 607         uint32_t dst_offset;
 608
 609         /* In dwords. Not valid/used for dynamic descriptors */
 610         uint32_t dst_stride;
 611
 612         uint32_t buffer_offset;
 613
 614         /* Only valid for combined image samplers and samplers */
 615         uint16_t has_sampler;
 616
 617         /* In bytes */
 618         size_t src_offset;
 619         size_t src_stride;
 620
 621         /* For push descriptors */
 622         const uint32_t *immutable_samplers;
 623 };
 624
 625 struct radv_descriptor_update_template {
 626         uint32_t entry_count;
 627         struct radv_descriptor_update_template_entry entry[0];
 628 };
 629
 630 struct radv_buffer {
 631         struct radv_device *                          device;
 632         VkDeviceSize                                 size;
 633
 634         VkBufferUsageFlags                           usage;
 635         VkBufferCreateFlags                          flags;
 636
 637         /* Set when bound */
 638         struct radeon_winsys_bo *                      bo;
 639         VkDeviceSize                                 offset;
 640 };
 641
 642
 643 enum radv_cmd_dirty_bits {
 644         RADV_CMD_DIRTY_DYNAMIC_VIEWPORT                  = 1 << 0, /* VK_DYNAMIC_STATE_VIEWPORT */
 645         RADV_CMD_DIRTY_DYNAMIC_SCISSOR                   = 1 << 1, /* VK_DYNAMIC_STATE_SCISSOR */
 646         RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH                = 1 << 2, /* VK_DYNAMIC_STATE_LINE_WIDTH */
 647         RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS                = 1 << 3, /* VK_DYNAMIC_STATE_DEPTH_BIAS */
 648         RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS           = 1 << 4, /* VK_DYNAMIC_STATE_BLEND_CONSTANTS */
 649         RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS              = 1 << 5, /* VK_DYNAMIC_STATE_DEPTH_BOUNDS */
 650         RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK      = 1 << 6, /* VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK */
 651         RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK        = 1 << 7, /* VK_DYNAMIC_STATE_STENCIL_WRITE_MASK */
 652         RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE         = 1 << 8, /* VK_DYNAMIC_STATE_STENCIL_REFERENCE */
 653         RADV_CMD_DIRTY_DYNAMIC_ALL                       = (1 << 9) - 1,
 654         RADV_CMD_DIRTY_PIPELINE                          = 1 << 9,
 655         RADV_CMD_DIRTY_INDEX_BUFFER                      = 1 << 10,
 656         RADV_CMD_DIRTY_RENDER_TARGETS                    = 1 << 11,
 657 };
 658 typedef uint32_t radv_cmd_dirty_mask_t;
 659
 660 enum radv_cmd_flush_bits {
 661         RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
 662         /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
 663         RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
 664         /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
 665         RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
 666         /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
 667         RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
 668         /* Same as above, but only writes back and doesn't invalidate */
 669         RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
 670         /* Framebuffer caches */
 671         RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
 672         RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
 673         RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
 674         RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
 675         /* Engine synchronization. */
 676         RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
 677         RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
 678         RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
 679         RADV_CMD_FLAG_VGT_FLUSH        = 1 << 12,
 680
 681         RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
 682                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
 683                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB |
 684                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
 685 };
 686
 687 struct radv_vertex_binding {
 688         struct radv_buffer *                          buffer;
 689         VkDeviceSize                                 offset;
 690 };
 691
 692 struct radv_dynamic_state {
 693         struct {
 694                 uint32_t                                  count;
 695                 VkViewport                                viewports[MAX_VIEWPORTS];
 696         } viewport;
 697
 698         struct {
 699                 uint32_t                                  count;
 700                 VkRect2D                                  scissors[MAX_SCISSORS];
 701         } scissor;
 702
 703         float                                        line_width;
 704
 705         struct {
 706                 float                                     bias;
 707                 float                                     clamp;
 708                 float                                     slope;
 709         } depth_bias;
 710
 711         float                                        blend_constants[4];
 712
 713         struct {
 714                 float                                     min;
 715                 float                                     max;
 716         } depth_bounds;
 717
 718         struct {
 719                 uint32_t                                  front;
 720                 uint32_t                                  back;
 721         } stencil_compare_mask;
 722
 723         struct {
 724                 uint32_t                                  front;
 725                 uint32_t                                  back;
 726         } stencil_write_mask;
 727
 728         struct {
 729                 uint32_t                                  front;
 730                 uint32_t                                  back;
 731         } stencil_reference;
 732 };
 733
 734 extern const struct radv_dynamic_state default_dynamic_state;
 735
 736 void radv_dynamic_state_copy(struct radv_dynamic_state *dest,
 737                              const struct radv_dynamic_state *src,
 738                              uint32_t copy_mask);
 739 /**
 740  * Attachment state when recording a renderpass instance.
 741  *
 742  * The clear value is valid only if there exists a pending clear.
 743  */
 744 struct radv_attachment_state {
 745         VkImageAspectFlags                           pending_clear_aspects;
 746         VkClearValue                                 clear_value;
 747         VkImageLayout                                current_layout;
 748 };
 749
 750 struct radv_cmd_state {
 751         uint32_t                                      vb_dirty;
 752         radv_cmd_dirty_mask_t                         dirty;
 753         bool                                          vertex_descriptors_dirty;
 754         bool                                          push_descriptors_dirty;
 755
 756         struct radv_pipeline *                        pipeline;
 757         struct radv_pipeline *                        emitted_pipeline;
 758         struct radv_pipeline *                        compute_pipeline;
 759         struct radv_pipeline *                        emitted_compute_pipeline;
 760         struct radv_framebuffer *                     framebuffer;
 761         struct radv_render_pass *                     pass;
 762         const struct radv_subpass *                         subpass;
 763         struct radv_dynamic_state                     dynamic;
 764         struct radv_vertex_binding                    vertex_bindings[MAX_VBS];
 765         struct radv_descriptor_set *                  descriptors[MAX_SETS];
 766         struct radv_attachment_state *                attachments;
 767         VkRect2D                                     render_area;
 768         struct radv_buffer *                         index_buffer;
 769         uint32_t                                     index_type;
 770         uint32_t                                     index_offset;
 771         int32_t                                      last_primitive_reset_en;
 772         uint32_t                                     last_primitive_reset_index;
 773         enum radv_cmd_flush_bits                     flush_bits;
 774         unsigned                                     active_occlusion_queries;
 775         float                                        offset_scale;
 776         uint32_t                                      descriptors_dirty;
 777         uint32_t                                      trace_id;
 778         uint32_t                                      last_ia_multi_vgt_param;
 779 };
 780
 781 struct radv_cmd_pool {
 782         VkAllocationCallbacks                        alloc;
 783         struct list_head                             cmd_buffers;
 784         struct list_head                             free_cmd_buffers;
 785         uint32_t queue_family_index;
 786 };
 787
 788 struct radv_cmd_buffer_upload {
 789         uint8_t *map;
 790         unsigned offset;
 791         uint64_t size;
 792         struct radeon_winsys_bo *upload_bo;
 793         struct list_head list;
 794 };
 795
 796 struct radv_cmd_buffer {
 797         VK_LOADER_DATA                               _loader_data;
 798
 799         struct radv_device *                          device;
 800
 801         struct radv_cmd_pool *                        pool;
 802         struct list_head                             pool_link;
 803
 804         VkCommandBufferUsageFlags                    usage_flags;
 805         VkCommandBufferLevel                         level;
 806         struct radeon_winsys_cs *cs;
 807         struct radv_cmd_state state;
 808         uint32_t queue_family_index;
 809
 810         uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
 811         uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
 812         VkShaderStageFlags push_constant_stages;
 813         struct radv_push_descriptor_set push_descriptors;
 814         struct radv_descriptor_set meta_push_descriptors;
 815
 816         struct radv_cmd_buffer_upload upload;
 817
 818         uint32_t scratch_size_needed;
 819         uint32_t compute_scratch_size_needed;
 820         uint32_t esgs_ring_size_needed;
 821         uint32_t gsvs_ring_size_needed;
 822         bool tess_rings_needed;
 823         bool sample_positions_needed;
 824
 825         bool record_fail;
 826
 827         int ring_offsets_idx; /* just used for verification */
 828         uint32_t gfx9_fence_offset;
 829         struct radeon_winsys_bo *gfx9_fence_bo;
 830         uint32_t gfx9_fence_idx;
 831 };
 832
 833 struct radv_image;
 834
 835 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
 836
 837 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
 838 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
 839
 840 void cik_create_gfx_config(struct radv_device *device);
 841
 842 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
 843                        int count, const VkViewport *viewports);
 844 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
 845                        int count, const VkRect2D *scissors,
 846                        const VkViewport *viewports, bool can_use_guardband);
 847 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
 848                                    bool instanced_draw, bool indirect_draw,
 849                                    uint32_t draw_vertex_count);
 850 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
 851                                 enum chip_class chip_class,
 852                                 bool is_mec,
 853                                 unsigned event, unsigned event_flags,
 854                                 unsigned data_sel,
 855                                 uint64_t va,
 856                                 uint32_t old_fence,
 857                                 uint32_t new_fence);
 858
 859 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
 860                         uint64_t va, uint32_t ref,
 861                         uint32_t mask);
 862 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
 863                             enum chip_class chip_class,
 864                             uint32_t *fence_ptr, uint64_t va,
 865                             bool is_mec,
 866                             enum radv_cmd_flush_bits flush_bits);
 867 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
 868 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
 869                            uint64_t src_va, uint64_t dest_va,
 870                            uint64_t size);
 871 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
 872                         unsigned size);
 873 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
 874                             uint64_t size, unsigned value);
 875 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
 876 void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
 877                               struct radv_descriptor_set *set,
 878                               unsigned idx);
 879 bool
 880 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
 881                              unsigned size,
 882                              unsigned alignment,
 883                              unsigned *out_offset,
 884                              void **ptr);
 885 void
 886 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
 887                             const struct radv_subpass *subpass,
 888                             bool transitions);
 889 bool
 890 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
 891                             unsigned size, unsigned alignmnet,
 892                             const void *data, unsigned *out_offset);
 893 void
 894 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer);
 895 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
 896 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
 897 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
 898 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
 899 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
 900 unsigned radv_cayman_get_maxdist(int log_samples);
 901 void radv_device_init_msaa(struct radv_device *device);
 902 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
 903                                struct radv_image *image,
 904                                VkClearDepthStencilValue ds_clear_value,
 905                                VkImageAspectFlags aspects);
 906 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
 907                                struct radv_image *image,
 908                                int idx,
 909                                uint32_t color_values[2]);
 910 void radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
 911                       struct radeon_winsys_bo *bo,
 912                       uint64_t offset, uint64_t size, uint32_t value);
 913 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
 914 bool radv_get_memory_fd(struct radv_device *device,
 915                         struct radv_device_memory *memory,
 916                         int *pFD);
 917 /*
 918  * Takes x,y,z as exact numbers of invocations, instead of blocks.
 919  *
 920  * Limitations: Can't call normal dispatch functions without binding or rebinding
 921  *              the compute pipeline.
 922  */
 923 void radv_unaligned_dispatch(
 924         struct radv_cmd_buffer                      *cmd_buffer,
 925         uint32_t                                    x,
 926         uint32_t                                    y,
 927         uint32_t                                    z);
 928
 929 struct radv_event {
 930         struct radeon_winsys_bo *bo;
 931         uint64_t *map;
 932 };
 933
 934 struct nir_shader;
 935
 936 struct radv_shader_module {
 937         struct nir_shader *                          nir;
 938         unsigned char                                sha1[20];
 939         uint32_t                                     size;
 940         char                                         data[0];
 941 };
 942
 943 union ac_shader_variant_key;
 944
 945 void
 946 radv_hash_shader(unsigned char *hash, struct radv_shader_module *module,
 947                  const char *entrypoint,
 948                  const VkSpecializationInfo *spec_info,
 949                  const struct radv_pipeline_layout *layout,
 950                  const union ac_shader_variant_key *key,
 951                  uint32_t is_geom_copy_shader);
 952
 953 static inline gl_shader_stage
 954 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
 955 {
 956         assert(__builtin_popcount(vk_stage) == 1);
 957         return ffs(vk_stage) - 1;
 958 }
 959
 960 static inline VkShaderStageFlagBits
 961 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
 962 {
 963         return (1 << mesa_stage);
 964 }
 965
 966 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
 967
 968 #define radv_foreach_stage(stage, stage_bits)                           \
 969         for (gl_shader_stage stage,                                     \
 970                      __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
 971              stage = __builtin_ffs(__tmp) - 1, __tmp;                   \
 972              __tmp &= ~(1 << (stage)))
 973
 974 struct radv_shader_variant {
 975         uint32_t ref_count;
 976
 977         struct radeon_winsys_bo *bo;
 978         struct ac_shader_config config;
 979         struct ac_shader_variant_info info;
 980         unsigned rsrc1;
 981         unsigned rsrc2;
 982         uint32_t code_size;
 983 };
 984
 985 struct radv_depth_stencil_state {
 986         uint32_t db_depth_control;
 987         uint32_t db_stencil_control;
 988         uint32_t db_render_control;
 989         uint32_t db_render_override2;
 990 };
 991
 992 struct radv_blend_state {
 993         uint32_t cb_color_control;
 994         uint32_t cb_target_mask;
 995         uint32_t sx_mrt0_blend_opt[8];
 996         uint32_t cb_blend_control[8];
 997
 998         uint32_t spi_shader_col_format;
 999         uint32_t cb_shader_mask;
1000         uint32_t db_alpha_to_mask;
1001 };
1002
1003 unsigned radv_format_meta_fs_key(VkFormat format);
1004
1005 struct radv_raster_state {
1006         uint32_t pa_cl_clip_cntl;
1007         uint32_t spi_interp_control;
1008         uint32_t pa_su_point_size;
1009         uint32_t pa_su_point_minmax;
1010         uint32_t pa_su_line_cntl;
1011         uint32_t pa_su_vtx_cntl;
1012         uint32_t pa_su_sc_mode_cntl;
1013 };
1014
1015 struct radv_multisample_state {
1016         uint32_t db_eqaa;
1017         uint32_t pa_sc_line_cntl;
1018         uint32_t pa_sc_mode_cntl_0;
1019         uint32_t pa_sc_mode_cntl_1;
1020         uint32_t pa_sc_aa_config;
1021         uint32_t pa_sc_aa_mask[2];
1022         unsigned num_samples;
1023 };
1024
1025 struct radv_prim_vertex_count {
1026         uint8_t min;
1027         uint8_t incr;
1028 };
1029
1030 struct radv_tessellation_state {
1031         uint32_t ls_hs_config;
1032         uint32_t tcs_in_layout;
1033         uint32_t tcs_out_layout;
1034         uint32_t tcs_out_offsets;
1035         uint32_t offchip_layout;
1036         unsigned num_patches;
1037         unsigned lds_size;
1038         unsigned num_tcs_input_cp;
1039         uint32_t tf_param;
1040 };
1041
1042 struct radv_pipeline {
1043         struct radv_device *                          device;
1044         uint32_t                                     dynamic_state_mask;
1045         struct radv_dynamic_state                     dynamic_state;
1046
1047         struct radv_pipeline_layout *                 layout;
1048
1049         bool                                         needs_data_cache;
1050         bool                                         need_indirect_descriptor_sets;
1051         struct radv_shader_variant *                 shaders[MESA_SHADER_STAGES];
1052         struct radv_shader_variant *gs_copy_shader;
1053         VkShaderStageFlags                           active_stages;
1054
1055         uint32_t va_rsrc_word3[MAX_VERTEX_ATTRIBS];
1056         uint32_t va_format_size[MAX_VERTEX_ATTRIBS];
1057         uint32_t va_binding[MAX_VERTEX_ATTRIBS];
1058         uint32_t va_offset[MAX_VERTEX_ATTRIBS];
1059         uint32_t num_vertex_attribs;
1060         uint32_t                                     binding_stride[MAX_VBS];
1061
1062         union {
1063                 struct {
1064                         struct radv_blend_state blend;
1065                         struct radv_depth_stencil_state ds;
1066                         struct radv_raster_state raster;
1067                         struct radv_multisample_state ms;
1068                         struct radv_tessellation_state tess;
1069                         uint32_t db_shader_control;
1070                         uint32_t shader_z_format;
1071                         unsigned prim;
1072                         unsigned gs_out;
1073                         uint32_t vgt_gs_mode;
1074                         bool prim_restart_enable;
1075                         unsigned esgs_ring_size;
1076                         unsigned gsvs_ring_size;
1077                         uint32_t ps_input_cntl[32];
1078                         uint32_t ps_input_cntl_num;
1079                         uint32_t pa_cl_vs_out_cntl;
1080                         uint32_t vgt_shader_stages_en;
1081                         struct radv_prim_vertex_count prim_vertex_count;
1082                         bool can_use_guardband;
1083                 } graphics;
1084         };
1085
1086         unsigned max_waves;
1087         unsigned scratch_bytes_per_wave;
1088 };
1089
1090 static inline bool radv_pipeline_has_gs(struct radv_pipeline *pipeline)
1091 {
1092         return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1093 }
1094
1095 static inline bool radv_pipeline_has_tess(struct radv_pipeline *pipeline)
1096 {
1097         return pipeline->shaders[MESA_SHADER_TESS_EVAL] ? true : false;
1098 }
1099
1100 struct radv_graphics_pipeline_create_info {
1101         bool use_rectlist;
1102         bool db_depth_clear;
1103         bool db_stencil_clear;
1104         bool db_depth_disable_expclear;
1105         bool db_stencil_disable_expclear;
1106         bool db_flush_depth_inplace;
1107         bool db_flush_stencil_inplace;
1108         bool db_resummarize;
1109         uint32_t custom_blend_mode;
1110 };
1111
1112 VkResult
1113 radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
1114                    struct radv_pipeline_cache *cache,
1115                    const VkGraphicsPipelineCreateInfo *pCreateInfo,
1116                    const struct radv_graphics_pipeline_create_info *extra,
1117                    const VkAllocationCallbacks *alloc);
1118
1119 VkResult
1120 radv_graphics_pipeline_create(VkDevice device,
1121                               VkPipelineCache cache,
1122                               const VkGraphicsPipelineCreateInfo *pCreateInfo,
1123                               const struct radv_graphics_pipeline_create_info *extra,
1124                               const VkAllocationCallbacks *alloc,
1125                               VkPipeline *pPipeline);
1126
1127 struct vk_format_description;
1128 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1129                                           int first_non_void);
1130 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1131                                          int first_non_void);
1132 uint32_t radv_translate_colorformat(VkFormat format);
1133 uint32_t radv_translate_color_numformat(VkFormat format,
1134                                         const struct vk_format_description *desc,
1135                                         int first_non_void);
1136 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1137 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1138 uint32_t radv_translate_dbformat(VkFormat format);
1139 uint32_t radv_translate_tex_dataformat(VkFormat format,
1140                                        const struct vk_format_description *desc,
1141                                        int first_non_void);
1142 uint32_t radv_translate_tex_numformat(VkFormat format,
1143                                       const struct vk_format_description *desc,
1144                                       int first_non_void);
1145 bool radv_format_pack_clear_color(VkFormat format,
1146                                   uint32_t clear_vals[2],
1147                                   VkClearColorValue *value);
1148 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1149
1150 struct radv_fmask_info {
1151         uint64_t offset;
1152         uint64_t size;
1153         unsigned alignment;
1154         unsigned pitch_in_pixels;
1155         unsigned bank_height;
1156         unsigned slice_tile_max;
1157         unsigned tile_mode_index;
1158 };
1159
1160 struct radv_cmask_info {
1161         uint64_t offset;
1162         uint64_t size;
1163         unsigned alignment;
1164         unsigned slice_tile_max;
1165         unsigned base_address_reg;
1166 };
1167
1168 struct r600_htile_info {
1169         uint64_t offset;
1170         uint64_t size;
1171         unsigned pitch;
1172         unsigned height;
1173         unsigned xalign;
1174         unsigned yalign;
1175 };
1176
1177 struct radv_image {
1178         VkImageType type;
1179         /* The original VkFormat provided by the client.  This may not match any
1180          * of the actual surface formats.
1181          */
1182         VkFormat vk_format;
1183         VkImageAspectFlags aspects;
1184         struct ac_surf_info info;
1185         VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1186         VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1187         VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1188
1189         VkDeviceSize size;
1190         uint32_t alignment;
1191
1192         bool exclusive;
1193         unsigned queue_family_mask;
1194
1195         /* Set when bound */
1196         struct radeon_winsys_bo *bo;
1197         VkDeviceSize offset;
1198         uint32_t dcc_offset;
1199         uint32_t htile_offset;
1200         struct radeon_surf surface;
1201
1202         struct radv_fmask_info fmask;
1203         struct radv_cmask_info cmask;
1204         uint32_t clear_value_offset;
1205 };
1206
1207 /* Whether the image has a htile that is known consistent with the contents of
1208  * the image. */
1209 bool radv_layout_has_htile(const struct radv_image *image,
1210                            VkImageLayout layout,
1211                            unsigned queue_mask);
1212
1213 /* Whether the image has a htile  that is known consistent with the contents of
1214  * the image and is allowed to be in compressed form.
1215  *
1216  * If this is false reads that don't use the htile should be able to return
1217  * correct results.
1218  */
1219 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1220                                      VkImageLayout layout,
1221                                      unsigned queue_mask);
1222
1223 bool radv_layout_can_fast_clear(const struct radv_image *image,
1224                                 VkImageLayout layout,
1225                                 unsigned queue_mask);
1226
1227
1228 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1229
1230 static inline uint32_t
1231 radv_get_layerCount(const struct radv_image *image,
1232                     const VkImageSubresourceRange *range)
1233 {
1234         return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1235                 image->info.array_size - range->baseArrayLayer : range->layerCount;
1236 }
1237
1238 static inline uint32_t
1239 radv_get_levelCount(const struct radv_image *image,
1240                     const VkImageSubresourceRange *range)
1241 {
1242         return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1243                 image->info.levels - range->baseMipLevel : range->levelCount;
1244 }
1245
1246 struct radeon_bo_metadata;
1247 void
1248 radv_init_metadata(struct radv_device *device,
1249                    struct radv_image *image,
1250                    struct radeon_bo_metadata *metadata);
1251
1252 struct radv_image_view {
1253         struct radv_image *image; /**< VkImageViewCreateInfo::image */
1254         struct radeon_winsys_bo *bo;
1255
1256         VkImageViewType type;
1257         VkImageAspectFlags aspect_mask;
1258         VkFormat vk_format;
1259         uint32_t base_layer;
1260         uint32_t layer_count;
1261         uint32_t base_mip;
1262         VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1263
1264         uint32_t descriptor[8];
1265         uint32_t fmask_descriptor[8];
1266 };
1267
1268 struct radv_image_create_info {
1269         const VkImageCreateInfo *vk_info;
1270         bool scanout;
1271 };
1272
1273 VkResult radv_image_create(VkDevice _device,
1274                            const struct radv_image_create_info *info,
1275                            const VkAllocationCallbacks* alloc,
1276                            VkImage *pImage);
1277
1278 void radv_image_view_init(struct radv_image_view *view,
1279                           struct radv_device *device,
1280                           const VkImageViewCreateInfo* pCreateInfo,
1281                           struct radv_cmd_buffer *cmd_buffer,
1282                           VkImageUsageFlags usage_mask);
1283
1284 struct radv_buffer_view {
1285         struct radeon_winsys_bo *bo;
1286         VkFormat vk_format;
1287         uint64_t range; /**< VkBufferViewCreateInfo::range */
1288         uint32_t state[4];
1289 };
1290 void radv_buffer_view_init(struct radv_buffer_view *view,
1291                            struct radv_device *device,
1292                            const VkBufferViewCreateInfo* pCreateInfo,
1293                            struct radv_cmd_buffer *cmd_buffer);
1294
1295 static inline struct VkExtent3D
1296 radv_sanitize_image_extent(const VkImageType imageType,
1297                            const struct VkExtent3D imageExtent)
1298 {
1299         switch (imageType) {
1300         case VK_IMAGE_TYPE_1D:
1301                 return (VkExtent3D) { imageExtent.width, 1, 1 };
1302         case VK_IMAGE_TYPE_2D:
1303                 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1304         case VK_IMAGE_TYPE_3D:
1305                 return imageExtent;
1306         default:
1307                 unreachable("invalid image type");
1308         }
1309 }
1310
1311 static inline struct VkOffset3D
1312 radv_sanitize_image_offset(const VkImageType imageType,
1313                            const struct VkOffset3D imageOffset)
1314 {
1315         switch (imageType) {
1316         case VK_IMAGE_TYPE_1D:
1317                 return (VkOffset3D) { imageOffset.x, 0, 0 };
1318         case VK_IMAGE_TYPE_2D:
1319                 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1320         case VK_IMAGE_TYPE_3D:
1321                 return imageOffset;
1322         default:
1323                 unreachable("invalid image type");
1324         }
1325 }
1326
1327 static inline bool
1328 radv_image_extent_compare(const struct radv_image *image,
1329                           const VkExtent3D *extent)
1330 {
1331         if (extent->width != image->info.width ||
1332             extent->height != image->info.height ||
1333             extent->depth != image->info.depth)
1334                 return false;
1335         return true;
1336 }
1337
1338 struct radv_sampler {
1339         uint32_t state[4];
1340 };
1341
1342 struct radv_color_buffer_info {
1343         uint64_t cb_color_base;
1344         uint64_t cb_color_cmask;
1345         uint64_t cb_color_fmask;
1346         uint64_t cb_dcc_base;
1347         uint32_t cb_color_pitch;
1348         uint32_t cb_color_slice;
1349         uint32_t cb_color_view;
1350         uint32_t cb_color_info;
1351         uint32_t cb_color_attrib;
1352         uint32_t cb_color_attrib2;
1353         uint32_t cb_dcc_control;
1354         uint32_t cb_color_cmask_slice;
1355         uint32_t cb_color_fmask_slice;
1356         uint32_t cb_clear_value0;
1357         uint32_t cb_clear_value1;
1358         uint32_t micro_tile_mode;
1359         uint32_t gfx9_epitch;
1360 };
1361
1362 struct radv_ds_buffer_info {
1363         uint64_t db_z_read_base;
1364         uint64_t db_stencil_read_base;
1365         uint64_t db_z_write_base;
1366         uint64_t db_stencil_write_base;
1367         uint64_t db_htile_data_base;
1368         uint32_t db_depth_info;
1369         uint32_t db_z_info;
1370         uint32_t db_stencil_info;
1371         uint32_t db_depth_view;
1372         uint32_t db_depth_size;
1373         uint32_t db_depth_slice;
1374         uint32_t db_htile_surface;
1375         uint32_t pa_su_poly_offset_db_fmt_cntl;
1376         uint32_t db_z_info2;
1377         uint32_t db_stencil_info2;
1378         float offset_scale;
1379 };
1380
1381 struct radv_attachment_info {
1382         union {
1383                 struct radv_color_buffer_info cb;
1384                 struct radv_ds_buffer_info ds;
1385         };
1386         struct radv_image_view *attachment;
1387 };
1388
1389 struct radv_framebuffer {
1390         uint32_t                                     width;
1391         uint32_t                                     height;
1392         uint32_t                                     layers;
1393
1394         uint32_t                                     attachment_count;
1395         struct radv_attachment_info                  attachments[0];
1396 };
1397
1398 struct radv_subpass_barrier {
1399         VkPipelineStageFlags src_stage_mask;
1400         VkAccessFlags        src_access_mask;
1401         VkAccessFlags        dst_access_mask;
1402 };
1403
1404 struct radv_subpass {
1405         uint32_t                                     input_count;
1406         uint32_t                                     color_count;
1407         VkAttachmentReference *                      input_attachments;
1408         VkAttachmentReference *                      color_attachments;
1409         VkAttachmentReference *                      resolve_attachments;
1410         VkAttachmentReference                        depth_stencil_attachment;
1411
1412         /** Subpass has at least one resolve attachment */
1413         bool                                         has_resolve;
1414
1415         struct radv_subpass_barrier                  start_barrier;
1416 };
1417
1418 struct radv_render_pass_attachment {
1419         VkFormat                                     format;
1420         uint32_t                                     samples;
1421         VkAttachmentLoadOp                           load_op;
1422         VkAttachmentLoadOp                           stencil_load_op;
1423         VkImageLayout                                initial_layout;
1424         VkImageLayout                                final_layout;
1425 };
1426
1427 struct radv_render_pass {
1428         uint32_t                                     attachment_count;
1429         uint32_t                                     subpass_count;
1430         VkAttachmentReference *                      subpass_attachments;
1431         struct radv_render_pass_attachment *         attachments;
1432         struct radv_subpass_barrier                  end_barrier;
1433         struct radv_subpass                          subpasses[0];
1434 };
1435
1436 VkResult radv_device_init_meta(struct radv_device *device);
1437 void radv_device_finish_meta(struct radv_device *device);
1438
1439 struct radv_query_pool {
1440         struct radeon_winsys_bo *bo;
1441         uint32_t stride;
1442         uint32_t availability_offset;
1443         char *ptr;
1444         VkQueryType type;
1445         uint32_t pipeline_stats_mask;
1446 };
1447
1448 void
1449 radv_update_descriptor_sets(struct radv_device *device,
1450                             struct radv_cmd_buffer *cmd_buffer,
1451                             VkDescriptorSet overrideSet,
1452                             uint32_t descriptorWriteCount,
1453                             const VkWriteDescriptorSet *pDescriptorWrites,
1454                             uint32_t descriptorCopyCount,
1455                             const VkCopyDescriptorSet *pDescriptorCopies);
1456
1457 void
1458 radv_update_descriptor_set_with_template(struct radv_device *device,
1459                                          struct radv_cmd_buffer *cmd_buffer,
1460                                          struct radv_descriptor_set *set,
1461                                          VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1462                                          const void *pData);
1463
1464 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1465                                    VkPipelineBindPoint pipelineBindPoint,
1466                                    VkPipelineLayout _layout,
1467                                    uint32_t set,
1468                                    uint32_t descriptorWriteCount,
1469                                    const VkWriteDescriptorSet *pDescriptorWrites);
1470
1471 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1472                            struct radv_image *image, uint32_t value);
1473 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1474                          struct radv_image *image, uint32_t value);
1475
1476 struct radv_fence {
1477         struct radeon_winsys_fence *fence;
1478         bool submitted;
1479         bool signalled;
1480 };
1481
1482 struct radeon_winsys_sem;
1483
1484 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType)         \
1485                                                                 \
1486         static inline struct __radv_type *                      \
1487         __radv_type ## _from_handle(__VkType _handle)           \
1488         {                                                       \
1489                 return (struct __radv_type *) _handle;          \
1490         }                                                       \
1491                                                                 \
1492         static inline __VkType                                  \
1493         __radv_type ## _to_handle(struct __radv_type *_obj)     \
1494         {                                                       \
1495                 return (__VkType) _obj;                         \
1496         }
1497
1498 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType)         \
1499                                                                         \
1500         static inline struct __radv_type *                              \
1501         __radv_type ## _from_handle(__VkType _handle)                   \
1502         {                                                               \
1503                 return (struct __radv_type *)(uintptr_t) _handle;       \
1504         }                                                               \
1505                                                                         \
1506         static inline __VkType                                          \
1507         __radv_type ## _to_handle(struct __radv_type *_obj)             \
1508         {                                                               \
1509                 return (__VkType)(uintptr_t) _obj;                      \
1510         }
1511
1512 #define RADV_FROM_HANDLE(__radv_type, __name, __handle)                 \
1513         struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1514
1515 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1516 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1517 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1518 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1519 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1520
1521 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1522 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1523 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1524 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1525 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1526 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1527 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1528 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1529 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1530 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1531 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1532 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1533 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1534 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1535 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1536 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1537 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1538 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1539 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1540 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1541 RADV_DEFINE_NONDISP_HANDLE_CASTS(radeon_winsys_sem, VkSemaphore)
1542
1543 #endif /* RADV_PRIVATE_H */