src/amd/vulkan/radv_private.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_PRIVATE_H
  29 #define RADV_PRIVATE_H
  30
  31 #include <stdlib.h>
  32 #include <stdio.h>
  33 #include <stdbool.h>
  34 #include <pthread.h>
  35 #include <assert.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #ifdef HAVE_VALGRIND
  39 #include <valgrind.h>
  40 #include <memcheck.h>
  41 #define VG(x) x
  42 #else
  43 #define VG(x)
  44 #endif
  45
  46 #include <amdgpu.h>
  47 #include "compiler/shader_enums.h"
  48 #include "util/macros.h"
  49 #include "util/list.h"
  50 #include "main/macros.h"
  51 #include "vk_alloc.h"
  52 #include "vk_debug_report.h"
  53
  54 #include "radv_radeon_winsys.h"
  55 #include "ac_binary.h"
  56 #include "ac_nir_to_llvm.h"
  57 #include "ac_gpu_info.h"
  58 #include "ac_surface.h"
  59 #include "radv_descriptor_set.h"
  60 #include "radv_extensions.h"
  61
  62 #include <llvm-c/TargetMachine.h>
  63
  64 /* Pre-declarations needed for WSI entrypoints */
  65 struct wl_surface;
  66 struct wl_display;
  67 typedef struct xcb_connection_t xcb_connection_t;
  68 typedef uint32_t xcb_visualid_t;
  69 typedef uint32_t xcb_window_t;
  70
  71 #include <vulkan/vulkan.h>
  72 #include <vulkan/vulkan_intel.h>
  73 #include <vulkan/vk_icd.h>
  74 #include <vulkan/vk_android_native_buffer.h>
  75
  76 #include "radv_entrypoints.h"
  77
  78 #include "wsi_common.h"
  79
  80 #define ATI_VENDOR_ID 0x1002
  81
  82 #define MAX_VBS         32
  83 #define MAX_VERTEX_ATTRIBS 32
  84 #define MAX_RTS          8
  85 #define MAX_VIEWPORTS   16
  86 #define MAX_SCISSORS    16
  87 #define MAX_DISCARD_RECTANGLES 4
  88 #define MAX_PUSH_CONSTANTS_SIZE 128
  89 #define MAX_PUSH_DESCRIPTORS 32
  90 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
  91 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
  92 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
  93 #define MAX_SAMPLES_LOG2 4
  94 #define NUM_META_FS_KEYS 13
  95 #define RADV_MAX_DRM_DEVICES 8
  96 #define MAX_VIEWS        8
  97
  98 #define NUM_DEPTH_CLEAR_PIPELINES 3
  99
 100 /*
 101  * This is the point we switch from using CP to compute shader
 102  * for certain buffer operations.
 103  */
 104 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
 105
 106 enum radv_mem_heap {
 107         RADV_MEM_HEAP_VRAM,
 108         RADV_MEM_HEAP_VRAM_CPU_ACCESS,
 109         RADV_MEM_HEAP_GTT,
 110         RADV_MEM_HEAP_COUNT
 111 };
 112
 113 enum radv_mem_type {
 114         RADV_MEM_TYPE_VRAM,
 115         RADV_MEM_TYPE_GTT_WRITE_COMBINE,
 116         RADV_MEM_TYPE_VRAM_CPU_ACCESS,
 117         RADV_MEM_TYPE_GTT_CACHED,
 118         RADV_MEM_TYPE_COUNT
 119 };
 120
 121 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
 122
 123 static inline uint32_t
 124 align_u32(uint32_t v, uint32_t a)
 125 {
 126         assert(a != 0 && a == (a & -a));
 127         return (v + a - 1) & ~(a - 1);
 128 }
 129
 130 static inline uint32_t
 131 align_u32_npot(uint32_t v, uint32_t a)
 132 {
 133         return (v + a - 1) / a * a;
 134 }
 135
 136 static inline uint64_t
 137 align_u64(uint64_t v, uint64_t a)
 138 {
 139         assert(a != 0 && a == (a & -a));
 140         return (v + a - 1) & ~(a - 1);
 141 }
 142
 143 static inline int32_t
 144 align_i32(int32_t v, int32_t a)
 145 {
 146         assert(a != 0 && a == (a & -a));
 147         return (v + a - 1) & ~(a - 1);
 148 }
 149
 150 /** Alignment must be a power of 2. */
 151 static inline bool
 152 radv_is_aligned(uintmax_t n, uintmax_t a)
 153 {
 154         assert(a == (a & -a));
 155         return (n & (a - 1)) == 0;
 156 }
 157
 158 static inline uint32_t
 159 round_up_u32(uint32_t v, uint32_t a)
 160 {
 161         return (v + a - 1) / a;
 162 }
 163
 164 static inline uint64_t
 165 round_up_u64(uint64_t v, uint64_t a)
 166 {
 167         return (v + a - 1) / a;
 168 }
 169
 170 static inline uint32_t
 171 radv_minify(uint32_t n, uint32_t levels)
 172 {
 173         if (unlikely(n == 0))
 174                 return 0;
 175         else
 176                 return MAX2(n >> levels, 1);
 177 }
 178 static inline float
 179 radv_clamp_f(float f, float min, float max)
 180 {
 181         assert(min < max);
 182
 183         if (f > max)
 184                 return max;
 185         else if (f < min)
 186                 return min;
 187         else
 188                 return f;
 189 }
 190
 191 static inline bool
 192 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
 193 {
 194         if (*inout_mask & clear_mask) {
 195                 *inout_mask &= ~clear_mask;
 196                 return true;
 197         } else {
 198                 return false;
 199         }
 200 }
 201
 202 #define for_each_bit(b, dword)                          \
 203         for (uint32_t __dword = (dword);                \
 204              (b) = __builtin_ffs(__dword) - 1, __dword; \
 205              __dword &= ~(1 << (b)))
 206
 207 #define typed_memcpy(dest, src, count) ({                               \
 208                         STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
 209                         memcpy((dest), (src), (count) * sizeof(*(src))); \
 210                 })
 211
 212 /* Whenever we generate an error, pass it through this function. Useful for
 213  * debugging, where we can break on it. Only call at error site, not when
 214  * propagating errors. Might be useful to plug in a stack trace here.
 215  */
 216
 217 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
 218
 219 #ifdef DEBUG
 220 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
 221 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
 222 #else
 223 #define vk_error(error) error
 224 #define vk_errorf(error, format, ...) error
 225 #endif
 226
 227 void __radv_finishme(const char *file, int line, const char *format, ...)
 228         radv_printflike(3, 4);
 229 void radv_loge(const char *format, ...) radv_printflike(1, 2);
 230 void radv_loge_v(const char *format, va_list va);
 231
 232 /**
 233  * Print a FINISHME message, including its source location.
 234  */
 235 #define radv_finishme(format, ...)                                      \
 236         do { \
 237                 static bool reported = false; \
 238                 if (!reported) { \
 239                         __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
 240                         reported = true; \
 241                 } \
 242         } while (0)
 243
 244 /* A non-fatal assert.  Useful for debugging. */
 245 #ifdef DEBUG
 246 #define radv_assert(x) ({                                               \
 247                         if (unlikely(!(x)))                             \
 248                                 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
 249                 })
 250 #else
 251 #define radv_assert(x)
 252 #endif
 253
 254 #define stub_return(v)                                  \
 255         do {                                            \
 256                 radv_finishme("stub %s", __func__);     \
 257                 return (v);                             \
 258         } while (0)
 259
 260 #define stub()                                          \
 261         do {                                            \
 262                 radv_finishme("stub %s", __func__);     \
 263                 return;                                 \
 264         } while (0)
 265
 266 void *radv_lookup_entrypoint_unchecked(const char *name);
 267 void *radv_lookup_entrypoint_checked(const char *name,
 268                                     uint32_t core_version,
 269                                     const struct radv_instance_extension_table *instance,
 270                                     const struct radv_device_extension_table *device);
 271
 272 struct radv_physical_device {
 273         VK_LOADER_DATA                              _loader_data;
 274
 275         struct radv_instance *                       instance;
 276
 277         struct radeon_winsys *ws;
 278         struct radeon_info rad_info;
 279         char                                        path[20];
 280         char                                        name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
 281         uint8_t                                     driver_uuid[VK_UUID_SIZE];
 282         uint8_t                                     device_uuid[VK_UUID_SIZE];
 283         uint8_t                                     cache_uuid[VK_UUID_SIZE];
 284
 285         int local_fd;
 286         struct wsi_device                       wsi_device;
 287
 288         bool has_rbplus; /* if RB+ register exist */
 289         bool rbplus_allowed; /* if RB+ is allowed */
 290         bool has_clear_state;
 291         bool cpdma_prefetch_writes_memory;
 292         bool has_scissor_bug;
 293
 294         bool has_out_of_order_rast;
 295         bool out_of_order_rast_allowed;
 296
 297         /* This is the drivers on-disk cache used as a fallback as opposed to
 298          * the pipeline cache defined by apps.
 299          */
 300         struct disk_cache *                          disk_cache;
 301
 302         VkPhysicalDeviceMemoryProperties memory_properties;
 303         enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
 304
 305         struct radv_device_extension_table supported_extensions;
 306 };
 307
 308 struct radv_instance {
 309         VK_LOADER_DATA                              _loader_data;
 310
 311         VkAllocationCallbacks                       alloc;
 312
 313         uint32_t                                    apiVersion;
 314         int                                         physicalDeviceCount;
 315         struct radv_physical_device                 physicalDevices[RADV_MAX_DRM_DEVICES];
 316
 317         uint64_t debug_flags;
 318         uint64_t perftest_flags;
 319
 320         struct vk_debug_report_instance             debug_report_callbacks;
 321
 322         struct radv_instance_extension_table enabled_extensions;
 323 };
 324
 325 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
 326 void radv_finish_wsi(struct radv_physical_device *physical_device);
 327
 328 bool radv_instance_extension_supported(const char *name);
 329 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
 330 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
 331                                               const char *name);
 332
 333 struct cache_entry;
 334
 335 struct radv_pipeline_cache {
 336         struct radv_device *                          device;
 337         pthread_mutex_t                              mutex;
 338
 339         uint32_t                                     total_size;
 340         uint32_t                                     table_size;
 341         uint32_t                                     kernel_count;
 342         struct cache_entry **                        hash_table;
 343         bool                                         modified;
 344
 345         VkAllocationCallbacks                        alloc;
 346 };
 347
 348 struct radv_pipeline_key {
 349         uint32_t instance_rate_inputs;
 350         unsigned tess_input_vertices;
 351         uint32_t col_format;
 352         uint32_t is_int8;
 353         uint32_t is_int10;
 354         uint8_t log2_ps_iter_samples;
 355         uint8_t log2_num_samples;
 356         uint32_t multisample : 1;
 357         uint32_t has_multiview_view_index : 1;
 358 };
 359
 360 void
 361 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
 362                          struct radv_device *device);
 363 void
 364 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
 365 void
 366 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
 367                          const void *data, size_t size);
 368
 369 struct radv_shader_variant;
 370
 371 bool
 372 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
 373                                                 struct radv_pipeline_cache *cache,
 374                                                 const unsigned char *sha1,
 375                                                 struct radv_shader_variant **variants);
 376
 377 void
 378 radv_pipeline_cache_insert_shaders(struct radv_device *device,
 379                                    struct radv_pipeline_cache *cache,
 380                                    const unsigned char *sha1,
 381                                    struct radv_shader_variant **variants,
 382                                    const void *const *codes,
 383                                    const unsigned *code_sizes);
 384
 385 enum radv_blit_ds_layout {
 386         RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
 387         RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
 388         RADV_BLIT_DS_LAYOUT_COUNT,
 389 };
 390
 391 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
 392 {
 393         return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
 394 }
 395
 396 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
 397 {
 398         return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
 399 }
 400
 401 enum radv_meta_dst_layout {
 402         RADV_META_DST_LAYOUT_GENERAL,
 403         RADV_META_DST_LAYOUT_OPTIMAL,
 404         RADV_META_DST_LAYOUT_COUNT,
 405 };
 406
 407 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
 408 {
 409         return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
 410 }
 411
 412 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
 413 {
 414         return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
 415 }
 416
 417 struct radv_meta_state {
 418         VkAllocationCallbacks alloc;
 419
 420         struct radv_pipeline_cache cache;
 421
 422         /**
 423          * Use array element `i` for images with `2^i` samples.
 424          */
 425         struct {
 426                 VkRenderPass render_pass[NUM_META_FS_KEYS];
 427                 VkPipeline color_pipelines[NUM_META_FS_KEYS];
 428
 429                 VkRenderPass depthstencil_rp;
 430                 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 431                 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 432                 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 433         } clear[1 + MAX_SAMPLES_LOG2];
 434
 435         VkPipelineLayout                          clear_color_p_layout;
 436         VkPipelineLayout                          clear_depth_p_layout;
 437         struct {
 438                 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
 439
 440                 /** Pipeline that blits from a 1D image. */
 441                 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
 442
 443                 /** Pipeline that blits from a 2D image. */
 444                 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
 445
 446                 /** Pipeline that blits from a 3D image. */
 447                 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
 448
 449                 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
 450                 VkPipeline depth_only_1d_pipeline;
 451                 VkPipeline depth_only_2d_pipeline;
 452                 VkPipeline depth_only_3d_pipeline;
 453
 454                 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
 455                 VkPipeline stencil_only_1d_pipeline;
 456                 VkPipeline stencil_only_2d_pipeline;
 457                 VkPipeline stencil_only_3d_pipeline;
 458                 VkPipelineLayout                          pipeline_layout;
 459                 VkDescriptorSetLayout                     ds_layout;
 460         } blit;
 461
 462         struct {
 463                 VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
 464
 465                 VkPipelineLayout p_layouts[3];
 466                 VkDescriptorSetLayout ds_layouts[3];
 467                 VkPipeline pipelines[3][NUM_META_FS_KEYS];
 468
 469                 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
 470                 VkPipeline depth_only_pipeline[3];
 471
 472                 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
 473                 VkPipeline stencil_only_pipeline[3];
 474         } blit2d;
 475
 476         struct {
 477                 VkPipelineLayout                          img_p_layout;
 478                 VkDescriptorSetLayout                     img_ds_layout;
 479                 VkPipeline pipeline;
 480                 VkPipeline pipeline_3d;
 481         } itob;
 482         struct {
 483                 VkPipelineLayout                          img_p_layout;
 484                 VkDescriptorSetLayout                     img_ds_layout;
 485                 VkPipeline pipeline;
 486                 VkPipeline pipeline_3d;
 487         } btoi;
 488         struct {
 489                 VkPipelineLayout                          img_p_layout;
 490                 VkDescriptorSetLayout                     img_ds_layout;
 491                 VkPipeline pipeline;
 492                 VkPipeline pipeline_3d;
 493         } itoi;
 494         struct {
 495                 VkPipelineLayout                          img_p_layout;
 496                 VkDescriptorSetLayout                     img_ds_layout;
 497                 VkPipeline pipeline;
 498                 VkPipeline pipeline_3d;
 499         } cleari;
 500
 501         struct {
 502                 VkPipelineLayout                          p_layout;
 503                 VkPipeline                                pipeline[NUM_META_FS_KEYS];
 504                 VkRenderPass                              pass[NUM_META_FS_KEYS];
 505         } resolve;
 506
 507         struct {
 508                 VkDescriptorSetLayout                     ds_layout;
 509                 VkPipelineLayout                          p_layout;
 510                 struct {
 511                         VkPipeline                                pipeline;
 512                         VkPipeline                                i_pipeline;
 513                         VkPipeline                                srgb_pipeline;
 514                 } rc[MAX_SAMPLES_LOG2];
 515         } resolve_compute;
 516
 517         struct {
 518                 VkDescriptorSetLayout                     ds_layout;
 519                 VkPipelineLayout                          p_layout;
 520
 521                 struct {
 522                         VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
 523                         VkPipeline   pipeline[NUM_META_FS_KEYS];
 524                 } rc[MAX_SAMPLES_LOG2];
 525         } resolve_fragment;
 526
 527         struct {
 528                 VkPipelineLayout                          p_layout;
 529                 VkPipeline                                decompress_pipeline;
 530                 VkPipeline                                resummarize_pipeline;
 531                 VkRenderPass                              pass;
 532         } depth_decomp[1 + MAX_SAMPLES_LOG2];
 533
 534         struct {
 535                 VkPipelineLayout                          p_layout;
 536                 VkPipeline                                cmask_eliminate_pipeline;
 537                 VkPipeline                                fmask_decompress_pipeline;
 538                 VkPipeline                                dcc_decompress_pipeline;
 539                 VkRenderPass                              pass;
 540
 541                 VkDescriptorSetLayout                     dcc_decompress_compute_ds_layout;
 542                 VkPipelineLayout                          dcc_decompress_compute_p_layout;
 543                 VkPipeline                                dcc_decompress_compute_pipeline;
 544         } fast_clear_flush;
 545
 546         struct {
 547                 VkPipelineLayout fill_p_layout;
 548                 VkPipelineLayout copy_p_layout;
 549                 VkDescriptorSetLayout fill_ds_layout;
 550                 VkDescriptorSetLayout copy_ds_layout;
 551                 VkPipeline fill_pipeline;
 552                 VkPipeline copy_pipeline;
 553         } buffer;
 554
 555         struct {
 556                 VkDescriptorSetLayout ds_layout;
 557                 VkPipelineLayout p_layout;
 558                 VkPipeline occlusion_query_pipeline;
 559                 VkPipeline pipeline_statistics_query_pipeline;
 560         } query;
 561 };
 562
 563 /* queue types */
 564 #define RADV_QUEUE_GENERAL 0
 565 #define RADV_QUEUE_COMPUTE 1
 566 #define RADV_QUEUE_TRANSFER 2
 567
 568 #define RADV_MAX_QUEUE_FAMILIES 3
 569
 570 enum ring_type radv_queue_family_to_ring(int f);
 571
 572 struct radv_queue {
 573         VK_LOADER_DATA                              _loader_data;
 574         struct radv_device *                         device;
 575         struct radeon_winsys_ctx                    *hw_ctx;
 576         enum radeon_ctx_priority                     priority;
 577         uint32_t queue_family_index;
 578         int queue_idx;
 579         VkDeviceQueueCreateFlags flags;
 580
 581         uint32_t scratch_size;
 582         uint32_t compute_scratch_size;
 583         uint32_t esgs_ring_size;
 584         uint32_t gsvs_ring_size;
 585         bool has_tess_rings;
 586         bool has_sample_positions;
 587
 588         struct radeon_winsys_bo *scratch_bo;
 589         struct radeon_winsys_bo *descriptor_bo;
 590         struct radeon_winsys_bo *compute_scratch_bo;
 591         struct radeon_winsys_bo *esgs_ring_bo;
 592         struct radeon_winsys_bo *gsvs_ring_bo;
 593         struct radeon_winsys_bo *tess_rings_bo;
 594         struct radeon_winsys_cs *initial_preamble_cs;
 595         struct radeon_winsys_cs *initial_full_flush_preamble_cs;
 596         struct radeon_winsys_cs *continue_preamble_cs;
 597 };
 598
 599 struct radv_device {
 600         VK_LOADER_DATA                              _loader_data;
 601
 602         VkAllocationCallbacks                       alloc;
 603
 604         struct radv_instance *                       instance;
 605         struct radeon_winsys *ws;
 606
 607         struct radv_meta_state                       meta_state;
 608
 609         struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
 610         int queue_count[RADV_MAX_QUEUE_FAMILIES];
 611         struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
 612
 613         bool always_use_syncobj;
 614         bool llvm_supports_spill;
 615         bool has_distributed_tess;
 616         bool pbb_allowed;
 617         bool dfsm_allowed;
 618         uint32_t tess_offchip_block_dw_size;
 619         uint32_t scratch_waves;
 620         uint32_t dispatch_initiator;
 621
 622         uint32_t gs_table_depth;
 623
 624         /* MSAA sample locations.
 625          * The first index is the sample index.
 626          * The second index is the coordinate: X, Y. */
 627         float sample_locations_1x[1][2];
 628         float sample_locations_2x[2][2];
 629         float sample_locations_4x[4][2];
 630         float sample_locations_8x[8][2];
 631         float sample_locations_16x[16][2];
 632
 633         /* CIK and later */
 634         uint32_t gfx_init_size_dw;
 635         struct radeon_winsys_bo                      *gfx_init;
 636
 637         struct radeon_winsys_bo                      *trace_bo;
 638         uint32_t                                     *trace_id_ptr;
 639
 640         /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
 641         bool                                         keep_shader_info;
 642
 643         struct radv_physical_device                  *physical_device;
 644
 645         /* Backup in-memory cache to be used if the app doesn't provide one */
 646         struct radv_pipeline_cache *                mem_cache;
 647
 648         /*
 649          * use different counters so MSAA MRTs get consecutive surface indices,
 650          * even if MASK is allocated in between.
 651          */
 652         uint32_t image_mrt_offset_counter;
 653         uint32_t fmask_mrt_offset_counter;
 654         struct list_head shader_slabs;
 655         mtx_t shader_slab_mutex;
 656
 657         /* For detecting VM faults reported by dmesg. */
 658         uint64_t dmesg_timestamp;
 659
 660         struct radv_device_extension_table enabled_extensions;
 661 };
 662
 663 struct radv_device_memory {
 664         struct radeon_winsys_bo                      *bo;
 665         /* for dedicated allocations */
 666         struct radv_image                            *image;
 667         struct radv_buffer                           *buffer;
 668         uint32_t                                     type_index;
 669         VkDeviceSize                                 map_size;
 670         void *                                       map;
 671         void *                                       user_ptr;
 672 };
 673
 674
 675 struct radv_descriptor_range {
 676         uint64_t va;
 677         uint32_t size;
 678 };
 679
 680 struct radv_descriptor_set {
 681         const struct radv_descriptor_set_layout *layout;
 682         uint32_t size;
 683
 684         struct radeon_winsys_bo *bo;
 685         uint64_t va;
 686         uint32_t *mapped_ptr;
 687         struct radv_descriptor_range *dynamic_descriptors;
 688
 689         struct radeon_winsys_bo *descriptors[0];
 690 };
 691
 692 struct radv_push_descriptor_set
 693 {
 694         struct radv_descriptor_set set;
 695         uint32_t capacity;
 696 };
 697
 698 struct radv_descriptor_pool_entry {
 699         uint32_t offset;
 700         uint32_t size;
 701         struct radv_descriptor_set *set;
 702 };
 703
 704 struct radv_descriptor_pool {
 705         struct radeon_winsys_bo *bo;
 706         uint8_t *mapped_ptr;
 707         uint64_t current_offset;
 708         uint64_t size;
 709
 710         uint8_t *host_memory_base;
 711         uint8_t *host_memory_ptr;
 712         uint8_t *host_memory_end;
 713
 714         uint32_t entry_count;
 715         uint32_t max_entry_count;
 716         struct radv_descriptor_pool_entry entries[0];
 717 };
 718
 719 struct radv_descriptor_update_template_entry {
 720         VkDescriptorType descriptor_type;
 721
 722         /* The number of descriptors to update */
 723         uint32_t descriptor_count;
 724
 725         /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
 726         uint32_t dst_offset;
 727
 728         /* In dwords. Not valid/used for dynamic descriptors */
 729         uint32_t dst_stride;
 730
 731         uint32_t buffer_offset;
 732
 733         /* Only valid for combined image samplers and samplers */
 734         uint16_t has_sampler;
 735
 736         /* In bytes */
 737         size_t src_offset;
 738         size_t src_stride;
 739
 740         /* For push descriptors */
 741         const uint32_t *immutable_samplers;
 742 };
 743
 744 struct radv_descriptor_update_template {
 745         uint32_t entry_count;
 746         VkPipelineBindPoint bind_point;
 747         struct radv_descriptor_update_template_entry entry[0];
 748 };
 749
 750 struct radv_buffer {
 751         VkDeviceSize                                 size;
 752
 753         VkBufferUsageFlags                           usage;
 754         VkBufferCreateFlags                          flags;
 755
 756         /* Set when bound */
 757         struct radeon_winsys_bo *                      bo;
 758         VkDeviceSize                                 offset;
 759
 760         bool shareable;
 761 };
 762
 763 enum radv_dynamic_state_bits {
 764         RADV_DYNAMIC_VIEWPORT             = 1 << 0,
 765         RADV_DYNAMIC_SCISSOR              = 1 << 1,
 766         RADV_DYNAMIC_LINE_WIDTH           = 1 << 2,
 767         RADV_DYNAMIC_DEPTH_BIAS           = 1 << 3,
 768         RADV_DYNAMIC_BLEND_CONSTANTS      = 1 << 4,
 769         RADV_DYNAMIC_DEPTH_BOUNDS         = 1 << 5,
 770         RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
 771         RADV_DYNAMIC_STENCIL_WRITE_MASK   = 1 << 7,
 772         RADV_DYNAMIC_STENCIL_REFERENCE    = 1 << 8,
 773         RADV_DYNAMIC_DISCARD_RECTANGLE    = 1 << 9,
 774         RADV_DYNAMIC_ALL                  = (1 << 10) - 1,
 775 };
 776
 777 enum radv_cmd_dirty_bits {
 778         /* Keep the dynamic state dirty bits in sync with
 779          * enum radv_dynamic_state_bits */
 780         RADV_CMD_DIRTY_DYNAMIC_VIEWPORT                  = 1 << 0,
 781         RADV_CMD_DIRTY_DYNAMIC_SCISSOR                   = 1 << 1,
 782         RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH                = 1 << 2,
 783         RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS                = 1 << 3,
 784         RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS           = 1 << 4,
 785         RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS              = 1 << 5,
 786         RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK      = 1 << 6,
 787         RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK        = 1 << 7,
 788         RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE         = 1 << 8,
 789         RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE         = 1 << 9,
 790         RADV_CMD_DIRTY_DYNAMIC_ALL                       = (1 << 10) - 1,
 791         RADV_CMD_DIRTY_PIPELINE                          = 1 << 10,
 792         RADV_CMD_DIRTY_INDEX_BUFFER                      = 1 << 11,
 793         RADV_CMD_DIRTY_FRAMEBUFFER                       = 1 << 12,
 794         RADV_CMD_DIRTY_VERTEX_BUFFER                     = 1 << 13,
 795 };
 796
 797 enum radv_cmd_flush_bits {
 798         RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
 799         /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
 800         RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
 801         /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
 802         RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
 803         /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
 804         RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
 805         /* Same as above, but only writes back and doesn't invalidate */
 806         RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
 807         /* Framebuffer caches */
 808         RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
 809         RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
 810         RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
 811         RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
 812         /* Engine synchronization. */
 813         RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
 814         RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
 815         RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
 816         RADV_CMD_FLAG_VGT_FLUSH        = 1 << 12,
 817
 818         RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
 819                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
 820                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB |
 821                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
 822 };
 823
 824 struct radv_vertex_binding {
 825         struct radv_buffer *                          buffer;
 826         VkDeviceSize                                 offset;
 827 };
 828
 829 struct radv_viewport_state {
 830         uint32_t                                          count;
 831         VkViewport                                        viewports[MAX_VIEWPORTS];
 832 };
 833
 834 struct radv_scissor_state {
 835         uint32_t                                          count;
 836         VkRect2D                                          scissors[MAX_SCISSORS];
 837 };
 838
 839 struct radv_discard_rectangle_state {
 840         uint32_t                                          count;
 841         VkRect2D                                          rectangles[MAX_DISCARD_RECTANGLES];
 842 };
 843
 844 struct radv_dynamic_state {
 845         /**
 846          * Bitmask of (1 << VK_DYNAMIC_STATE_*).
 847          * Defines the set of saved dynamic state.
 848          */
 849         uint32_t mask;
 850
 851         struct radv_viewport_state                        viewport;
 852
 853         struct radv_scissor_state                         scissor;
 854
 855         float                                        line_width;
 856
 857         struct {
 858                 float                                     bias;
 859                 float                                     clamp;
 860                 float                                     slope;
 861         } depth_bias;
 862
 863         float                                        blend_constants[4];
 864
 865         struct {
 866                 float                                     min;
 867                 float                                     max;
 868         } depth_bounds;
 869
 870         struct {
 871                 uint32_t                                  front;
 872                 uint32_t                                  back;
 873         } stencil_compare_mask;
 874
 875         struct {
 876                 uint32_t                                  front;
 877                 uint32_t                                  back;
 878         } stencil_write_mask;
 879
 880         struct {
 881                 uint32_t                                  front;
 882                 uint32_t                                  back;
 883         } stencil_reference;
 884
 885         struct radv_discard_rectangle_state               discard_rectangle;
 886 };
 887
 888 extern const struct radv_dynamic_state default_dynamic_state;
 889
 890 const char *
 891 radv_get_debug_option_name(int id);
 892
 893 const char *
 894 radv_get_perftest_option_name(int id);
 895
 896 /**
 897  * Attachment state when recording a renderpass instance.
 898  *
 899  * The clear value is valid only if there exists a pending clear.
 900  */
 901 struct radv_attachment_state {
 902         VkImageAspectFlags                           pending_clear_aspects;
 903         uint32_t                                     cleared_views;
 904         VkClearValue                                 clear_value;
 905         VkImageLayout                                current_layout;
 906 };
 907
 908 struct radv_descriptor_state {
 909         struct radv_descriptor_set *sets[MAX_SETS];
 910         uint32_t dirty;
 911         uint32_t valid;
 912         struct radv_push_descriptor_set push_set;
 913         bool push_dirty;
 914 };
 915
 916 struct radv_cmd_state {
 917         /* Vertex descriptors */
 918         uint64_t                                      vb_va;
 919         unsigned                                      vb_size;
 920
 921         bool predicating;
 922         uint32_t                                      dirty;
 923
 924         uint32_t                                      prefetch_L2_mask;
 925
 926         struct radv_pipeline *                        pipeline;
 927         struct radv_pipeline *                        emitted_pipeline;
 928         struct radv_pipeline *                        compute_pipeline;
 929         struct radv_pipeline *                        emitted_compute_pipeline;
 930         struct radv_framebuffer *                     framebuffer;
 931         struct radv_render_pass *                     pass;
 932         const struct radv_subpass *                         subpass;
 933         struct radv_dynamic_state                     dynamic;
 934         struct radv_attachment_state *                attachments;
 935         VkRect2D                                     render_area;
 936
 937         /* Index buffer */
 938         struct radv_buffer                           *index_buffer;
 939         uint64_t                                     index_offset;
 940         uint32_t                                     index_type;
 941         uint32_t                                     max_index_count;
 942         uint64_t                                     index_va;
 943         int32_t                                      last_index_type;
 944
 945         int32_t                                      last_primitive_reset_en;
 946         uint32_t                                     last_primitive_reset_index;
 947         enum radv_cmd_flush_bits                     flush_bits;
 948         unsigned                                     active_occlusion_queries;
 949         bool                                         perfect_occlusion_queries_enabled;
 950         float                                        offset_scale;
 951         uint32_t                                      trace_id;
 952         uint32_t                                      last_ia_multi_vgt_param;
 953
 954         uint32_t last_num_instances;
 955         uint32_t last_first_instance;
 956         uint32_t last_vertex_offset;
 957 };
 958
 959 struct radv_cmd_pool {
 960         VkAllocationCallbacks                        alloc;
 961         struct list_head                             cmd_buffers;
 962         struct list_head                             free_cmd_buffers;
 963         uint32_t queue_family_index;
 964 };
 965
 966 struct radv_cmd_buffer_upload {
 967         uint8_t *map;
 968         unsigned offset;
 969         uint64_t size;
 970         struct radeon_winsys_bo *upload_bo;
 971         struct list_head list;
 972 };
 973
 974 enum radv_cmd_buffer_status {
 975         RADV_CMD_BUFFER_STATUS_INVALID,
 976         RADV_CMD_BUFFER_STATUS_INITIAL,
 977         RADV_CMD_BUFFER_STATUS_RECORDING,
 978         RADV_CMD_BUFFER_STATUS_EXECUTABLE,
 979         RADV_CMD_BUFFER_STATUS_PENDING,
 980 };
 981
 982 struct radv_cmd_buffer {
 983         VK_LOADER_DATA                               _loader_data;
 984
 985         struct radv_device *                          device;
 986
 987         struct radv_cmd_pool *                        pool;
 988         struct list_head                             pool_link;
 989
 990         VkCommandBufferUsageFlags                    usage_flags;
 991         VkCommandBufferLevel                         level;
 992         enum radv_cmd_buffer_status status;
 993         struct radeon_winsys_cs *cs;
 994         struct radv_cmd_state state;
 995         struct radv_vertex_binding                   vertex_bindings[MAX_VBS];
 996         uint32_t queue_family_index;
 997
 998         uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
 999         uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1000         VkShaderStageFlags push_constant_stages;
1001         struct radv_descriptor_set meta_push_descriptors;
1002
1003         struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1004
1005         struct radv_cmd_buffer_upload upload;
1006
1007         uint32_t scratch_size_needed;
1008         uint32_t compute_scratch_size_needed;
1009         uint32_t esgs_ring_size_needed;
1010         uint32_t gsvs_ring_size_needed;
1011         bool tess_rings_needed;
1012         bool sample_positions_needed;
1013
1014         VkResult record_result;
1015
1016         int ring_offsets_idx; /* just used for verification */
1017         uint32_t gfx9_fence_offset;
1018         struct radeon_winsys_bo *gfx9_fence_bo;
1019         uint32_t gfx9_fence_idx;
1020
1021         /**
1022          * Whether a query pool has been resetted and we have to flush caches.
1023          */
1024         bool pending_reset_query;
1025 };
1026
1027 struct radv_image;
1028
1029 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1030
1031 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1032 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1033
1034 void cik_create_gfx_config(struct radv_device *device);
1035
1036 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
1037                        int count, const VkViewport *viewports);
1038 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
1039                        int count, const VkRect2D *scissors,
1040                        const VkViewport *viewports, bool can_use_guardband);
1041 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1042                                    bool instanced_draw, bool indirect_draw,
1043                                    uint32_t draw_vertex_count);
1044 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
1045                                 bool predicated,
1046                                 enum chip_class chip_class,
1047                                 bool is_mec,
1048                                 unsigned event, unsigned event_flags,
1049                                 unsigned data_sel,
1050                                 uint64_t va,
1051                                 uint32_t old_fence,
1052                                 uint32_t new_fence);
1053
1054 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1055                         bool predicated,
1056                         uint64_t va, uint32_t ref,
1057                         uint32_t mask);
1058 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1059                             enum chip_class chip_class,
1060                             uint32_t *fence_ptr, uint64_t va,
1061                             bool is_mec,
1062                             enum radv_cmd_flush_bits flush_bits);
1063 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1064 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1065 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1066                            uint64_t src_va, uint64_t dest_va,
1067                            uint64_t size);
1068 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1069                         unsigned size);
1070 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1071                             uint64_t size, unsigned value);
1072 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1073 bool
1074 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1075                              unsigned size,
1076                              unsigned alignment,
1077                              unsigned *out_offset,
1078                              void **ptr);
1079 void
1080 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1081                             const struct radv_subpass *subpass,
1082                             bool transitions);
1083 bool
1084 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1085                             unsigned size, unsigned alignmnet,
1086                             const void *data, unsigned *out_offset);
1087
1088 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1089 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1090 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1091 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1092 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1093 unsigned radv_cayman_get_maxdist(int log_samples);
1094 void radv_device_init_msaa(struct radv_device *device);
1095 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1096                                struct radv_image *image,
1097                                VkClearDepthStencilValue ds_clear_value,
1098                                VkImageAspectFlags aspects);
1099 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1100                                struct radv_image *image,
1101                                int idx,
1102                                uint32_t color_values[2]);
1103 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1104                                        struct radv_image *image,
1105                                        bool value);
1106 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1107                           struct radeon_winsys_bo *bo,
1108                           uint64_t offset, uint64_t size, uint32_t value);
1109 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1110 bool radv_get_memory_fd(struct radv_device *device,
1111                         struct radv_device_memory *memory,
1112                         int *pFD);
1113
1114 static inline struct radv_descriptor_state *
1115 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1116                            VkPipelineBindPoint bind_point)
1117 {
1118         assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1119                bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1120         return &cmd_buffer->descriptors[bind_point];
1121 }
1122
1123 /*
1124  * Takes x,y,z as exact numbers of invocations, instead of blocks.
1125  *
1126  * Limitations: Can't call normal dispatch functions without binding or rebinding
1127  *              the compute pipeline.
1128  */
1129 void radv_unaligned_dispatch(
1130         struct radv_cmd_buffer                      *cmd_buffer,
1131         uint32_t                                    x,
1132         uint32_t                                    y,
1133         uint32_t                                    z);
1134
1135 struct radv_event {
1136         struct radeon_winsys_bo *bo;
1137         uint64_t *map;
1138 };
1139
1140 struct radv_shader_module;
1141
1142 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1143 #define RADV_HASH_SHADER_SISCHED             (1 << 1)
1144 #define RADV_HASH_SHADER_UNSAFE_MATH         (1 << 2)
1145 void
1146 radv_hash_shaders(unsigned char *hash,
1147                   const VkPipelineShaderStageCreateInfo **stages,
1148                   const struct radv_pipeline_layout *layout,
1149                   const struct radv_pipeline_key *key,
1150                   uint32_t flags);
1151
1152 static inline gl_shader_stage
1153 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1154 {
1155         assert(__builtin_popcount(vk_stage) == 1);
1156         return ffs(vk_stage) - 1;
1157 }
1158
1159 static inline VkShaderStageFlagBits
1160 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1161 {
1162         return (1 << mesa_stage);
1163 }
1164
1165 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1166
1167 #define radv_foreach_stage(stage, stage_bits)                           \
1168         for (gl_shader_stage stage,                                     \
1169                      __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1170              stage = __builtin_ffs(__tmp) - 1, __tmp;                   \
1171              __tmp &= ~(1 << (stage)))
1172
1173 unsigned radv_format_meta_fs_key(VkFormat format);
1174
1175 struct radv_multisample_state {
1176         uint32_t db_eqaa;
1177         uint32_t pa_sc_line_cntl;
1178         uint32_t pa_sc_mode_cntl_0;
1179         uint32_t pa_sc_mode_cntl_1;
1180         uint32_t pa_sc_aa_config;
1181         uint32_t pa_sc_aa_mask[2];
1182         unsigned num_samples;
1183 };
1184
1185 struct radv_prim_vertex_count {
1186         uint8_t min;
1187         uint8_t incr;
1188 };
1189
1190 struct radv_vertex_elements_info {
1191         uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1192         uint32_t format_size[MAX_VERTEX_ATTRIBS];
1193         uint32_t binding[MAX_VERTEX_ATTRIBS];
1194         uint32_t offset[MAX_VERTEX_ATTRIBS];
1195         uint32_t count;
1196 };
1197
1198 struct radv_ia_multi_vgt_param_helpers {
1199         uint32_t base;
1200         bool partial_es_wave;
1201         uint8_t primgroup_size;
1202         bool wd_switch_on_eop;
1203         bool ia_switch_on_eoi;
1204         bool partial_vs_wave;
1205 };
1206
1207 #define SI_GS_PER_ES 128
1208
1209 struct radv_pipeline {
1210         struct radv_device *                          device;
1211         struct radv_dynamic_state                     dynamic_state;
1212
1213         struct radv_pipeline_layout *                 layout;
1214
1215         bool                                         need_indirect_descriptor_sets;
1216         struct radv_shader_variant *                 shaders[MESA_SHADER_STAGES];
1217         struct radv_shader_variant *gs_copy_shader;
1218         VkShaderStageFlags                           active_stages;
1219
1220         struct radeon_winsys_cs                      cs;
1221
1222         struct radv_vertex_elements_info             vertex_elements;
1223
1224         uint32_t                                     binding_stride[MAX_VBS];
1225
1226         uint32_t user_data_0[MESA_SHADER_STAGES];
1227         union {
1228                 struct {
1229                         struct radv_multisample_state ms;
1230                         uint32_t spi_baryc_cntl;
1231                         bool prim_restart_enable;
1232                         unsigned esgs_ring_size;
1233                         unsigned gsvs_ring_size;
1234                         uint32_t vtx_base_sgpr;
1235                         struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1236                         uint8_t vtx_emit_num;
1237                         struct radv_prim_vertex_count prim_vertex_count;
1238                         bool can_use_guardband;
1239                         uint32_t needed_dynamic_state;
1240                         bool disable_out_of_order_rast_for_occlusion;
1241                 } graphics;
1242         };
1243
1244         unsigned max_waves;
1245         unsigned scratch_bytes_per_wave;
1246 };
1247
1248 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1249 {
1250         return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1251 }
1252
1253 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1254 {
1255         return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1256 }
1257
1258 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1259                                                  gl_shader_stage stage,
1260                                                  int idx);
1261
1262 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1263
1264 struct radv_graphics_pipeline_create_info {
1265         bool use_rectlist;
1266         bool db_depth_clear;
1267         bool db_stencil_clear;
1268         bool db_depth_disable_expclear;
1269         bool db_stencil_disable_expclear;
1270         bool db_flush_depth_inplace;
1271         bool db_flush_stencil_inplace;
1272         bool db_resummarize;
1273         uint32_t custom_blend_mode;
1274 };
1275
1276 VkResult
1277 radv_graphics_pipeline_create(VkDevice device,
1278                               VkPipelineCache cache,
1279                               const VkGraphicsPipelineCreateInfo *pCreateInfo,
1280                               const struct radv_graphics_pipeline_create_info *extra,
1281                               const VkAllocationCallbacks *alloc,
1282                               VkPipeline *pPipeline);
1283
1284 struct vk_format_description;
1285 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1286                                           int first_non_void);
1287 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1288                                          int first_non_void);
1289 uint32_t radv_translate_colorformat(VkFormat format);
1290 uint32_t radv_translate_color_numformat(VkFormat format,
1291                                         const struct vk_format_description *desc,
1292                                         int first_non_void);
1293 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1294 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1295 uint32_t radv_translate_dbformat(VkFormat format);
1296 uint32_t radv_translate_tex_dataformat(VkFormat format,
1297                                        const struct vk_format_description *desc,
1298                                        int first_non_void);
1299 uint32_t radv_translate_tex_numformat(VkFormat format,
1300                                       const struct vk_format_description *desc,
1301                                       int first_non_void);
1302 bool radv_format_pack_clear_color(VkFormat format,
1303                                   uint32_t clear_vals[2],
1304                                   VkClearColorValue *value);
1305 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1306 bool radv_dcc_formats_compatible(VkFormat format1,
1307                                  VkFormat format2);
1308
1309 struct radv_fmask_info {
1310         uint64_t offset;
1311         uint64_t size;
1312         unsigned alignment;
1313         unsigned pitch_in_pixels;
1314         unsigned bank_height;
1315         unsigned slice_tile_max;
1316         unsigned tile_mode_index;
1317         unsigned tile_swizzle;
1318 };
1319
1320 struct radv_cmask_info {
1321         uint64_t offset;
1322         uint64_t size;
1323         unsigned alignment;
1324         unsigned slice_tile_max;
1325 };
1326
1327 struct radv_image {
1328         VkImageType type;
1329         /* The original VkFormat provided by the client.  This may not match any
1330          * of the actual surface formats.
1331          */
1332         VkFormat vk_format;
1333         VkImageAspectFlags aspects;
1334         VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1335         struct ac_surf_info info;
1336         VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1337         VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1338
1339         VkDeviceSize size;
1340         uint32_t alignment;
1341
1342         unsigned queue_family_mask;
1343         bool exclusive;
1344         bool shareable;
1345
1346         /* Set when bound */
1347         struct radeon_winsys_bo *bo;
1348         VkDeviceSize offset;
1349         uint64_t dcc_offset;
1350         uint64_t htile_offset;
1351         bool tc_compatible_htile;
1352         struct radeon_surf surface;
1353
1354         struct radv_fmask_info fmask;
1355         struct radv_cmask_info cmask;
1356         uint64_t clear_value_offset;
1357         uint64_t dcc_pred_offset;
1358
1359         /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1360         VkDeviceMemory owned_memory;
1361 };
1362
1363 /* Whether the image has a htile that is known consistent with the contents of
1364  * the image. */
1365 bool radv_layout_has_htile(const struct radv_image *image,
1366                            VkImageLayout layout,
1367                            unsigned queue_mask);
1368
1369 /* Whether the image has a htile  that is known consistent with the contents of
1370  * the image and is allowed to be in compressed form.
1371  *
1372  * If this is false reads that don't use the htile should be able to return
1373  * correct results.
1374  */
1375 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1376                                      VkImageLayout layout,
1377                                      unsigned queue_mask);
1378
1379 bool radv_layout_can_fast_clear(const struct radv_image *image,
1380                                 VkImageLayout layout,
1381                                 unsigned queue_mask);
1382
1383 bool radv_layout_dcc_compressed(const struct radv_image *image,
1384                                 VkImageLayout layout,
1385                                 unsigned queue_mask);
1386
1387 static inline bool
1388 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1389 {
1390         return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1391 }
1392
1393 static inline bool
1394 radv_htile_enabled(const struct radv_image *image, unsigned level)
1395 {
1396         return image->surface.htile_size && level == 0;
1397 }
1398
1399 /**
1400  * Return whether the image has CMASK metadata for color surfaces.
1401  */
1402 static inline bool
1403 radv_image_has_cmask(const struct radv_image *image)
1404 {
1405         return image->cmask.size;
1406 }
1407
1408 /**
1409  * Return whether the image has FMASK metadata for color surfaces.
1410  */
1411 static inline bool
1412 radv_image_has_fmask(const struct radv_image *image)
1413 {
1414         return image->fmask.size;
1415 }
1416
1417 /**
1418  * Return whether the image has DCC metadata for color surfaces.
1419  */
1420 static inline bool
1421 radv_image_has_dcc(const struct radv_image *image)
1422 {
1423         return image->surface.dcc_size;
1424 }
1425
1426 /**
1427  * Return whether the image has HTILE metadata for depth surfaces.
1428  */
1429 static inline bool
1430 radv_image_has_htile(const struct radv_image *image)
1431 {
1432         return image->surface.htile_size;
1433 }
1434
1435 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1436
1437 static inline uint32_t
1438 radv_get_layerCount(const struct radv_image *image,
1439                     const VkImageSubresourceRange *range)
1440 {
1441         return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1442                 image->info.array_size - range->baseArrayLayer : range->layerCount;
1443 }
1444
1445 static inline uint32_t
1446 radv_get_levelCount(const struct radv_image *image,
1447                     const VkImageSubresourceRange *range)
1448 {
1449         return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1450                 image->info.levels - range->baseMipLevel : range->levelCount;
1451 }
1452
1453 struct radeon_bo_metadata;
1454 void
1455 radv_init_metadata(struct radv_device *device,
1456                    struct radv_image *image,
1457                    struct radeon_bo_metadata *metadata);
1458
1459 struct radv_image_view {
1460         struct radv_image *image; /**< VkImageViewCreateInfo::image */
1461         struct radeon_winsys_bo *bo;
1462
1463         VkImageViewType type;
1464         VkImageAspectFlags aspect_mask;
1465         VkFormat vk_format;
1466         uint32_t base_layer;
1467         uint32_t layer_count;
1468         uint32_t base_mip;
1469         uint32_t level_count;
1470         VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1471
1472         uint32_t descriptor[16];
1473
1474         /* Descriptor for use as a storage image as opposed to a sampled image.
1475          * This has a few differences for cube maps (e.g. type).
1476          */
1477         uint32_t storage_descriptor[16];
1478 };
1479
1480 struct radv_image_create_info {
1481         const VkImageCreateInfo *vk_info;
1482         bool scanout;
1483         bool no_metadata_planes;
1484 };
1485
1486 VkResult radv_image_create(VkDevice _device,
1487                            const struct radv_image_create_info *info,
1488                            const VkAllocationCallbacks* alloc,
1489                            VkImage *pImage);
1490
1491 VkResult
1492 radv_image_from_gralloc(VkDevice device_h,
1493                        const VkImageCreateInfo *base_info,
1494                        const VkNativeBufferANDROID *gralloc_info,
1495                        const VkAllocationCallbacks *alloc,
1496                        VkImage *out_image_h);
1497
1498 void radv_image_view_init(struct radv_image_view *view,
1499                           struct radv_device *device,
1500                           const VkImageViewCreateInfo* pCreateInfo);
1501
1502 struct radv_buffer_view {
1503         struct radeon_winsys_bo *bo;
1504         VkFormat vk_format;
1505         uint64_t range; /**< VkBufferViewCreateInfo::range */
1506         uint32_t state[4];
1507 };
1508 void radv_buffer_view_init(struct radv_buffer_view *view,
1509                            struct radv_device *device,
1510                            const VkBufferViewCreateInfo* pCreateInfo);
1511
1512 static inline struct VkExtent3D
1513 radv_sanitize_image_extent(const VkImageType imageType,
1514                            const struct VkExtent3D imageExtent)
1515 {
1516         switch (imageType) {
1517         case VK_IMAGE_TYPE_1D:
1518                 return (VkExtent3D) { imageExtent.width, 1, 1 };
1519         case VK_IMAGE_TYPE_2D:
1520                 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1521         case VK_IMAGE_TYPE_3D:
1522                 return imageExtent;
1523         default:
1524                 unreachable("invalid image type");
1525         }
1526 }
1527
1528 static inline struct VkOffset3D
1529 radv_sanitize_image_offset(const VkImageType imageType,
1530                            const struct VkOffset3D imageOffset)
1531 {
1532         switch (imageType) {
1533         case VK_IMAGE_TYPE_1D:
1534                 return (VkOffset3D) { imageOffset.x, 0, 0 };
1535         case VK_IMAGE_TYPE_2D:
1536                 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1537         case VK_IMAGE_TYPE_3D:
1538                 return imageOffset;
1539         default:
1540                 unreachable("invalid image type");
1541         }
1542 }
1543
1544 static inline bool
1545 radv_image_extent_compare(const struct radv_image *image,
1546                           const VkExtent3D *extent)
1547 {
1548         if (extent->width != image->info.width ||
1549             extent->height != image->info.height ||
1550             extent->depth != image->info.depth)
1551                 return false;
1552         return true;
1553 }
1554
1555 struct radv_sampler {
1556         uint32_t state[4];
1557 };
1558
1559 struct radv_color_buffer_info {
1560         uint64_t cb_color_base;
1561         uint64_t cb_color_cmask;
1562         uint64_t cb_color_fmask;
1563         uint64_t cb_dcc_base;
1564         uint32_t cb_color_pitch;
1565         uint32_t cb_color_slice;
1566         uint32_t cb_color_view;
1567         uint32_t cb_color_info;
1568         uint32_t cb_color_attrib;
1569         uint32_t cb_color_attrib2;
1570         uint32_t cb_dcc_control;
1571         uint32_t cb_color_cmask_slice;
1572         uint32_t cb_color_fmask_slice;
1573 };
1574
1575 struct radv_ds_buffer_info {
1576         uint64_t db_z_read_base;
1577         uint64_t db_stencil_read_base;
1578         uint64_t db_z_write_base;
1579         uint64_t db_stencil_write_base;
1580         uint64_t db_htile_data_base;
1581         uint32_t db_depth_info;
1582         uint32_t db_z_info;
1583         uint32_t db_stencil_info;
1584         uint32_t db_depth_view;
1585         uint32_t db_depth_size;
1586         uint32_t db_depth_slice;
1587         uint32_t db_htile_surface;
1588         uint32_t pa_su_poly_offset_db_fmt_cntl;
1589         uint32_t db_z_info2;
1590         uint32_t db_stencil_info2;
1591         float offset_scale;
1592 };
1593
1594 struct radv_attachment_info {
1595         union {
1596                 struct radv_color_buffer_info cb;
1597                 struct radv_ds_buffer_info ds;
1598         };
1599         struct radv_image_view *attachment;
1600 };
1601
1602 struct radv_framebuffer {
1603         uint32_t                                     width;
1604         uint32_t                                     height;
1605         uint32_t                                     layers;
1606
1607         uint32_t                                     attachment_count;
1608         struct radv_attachment_info                  attachments[0];
1609 };
1610
1611 struct radv_subpass_barrier {
1612         VkPipelineStageFlags src_stage_mask;
1613         VkAccessFlags        src_access_mask;
1614         VkAccessFlags        dst_access_mask;
1615 };
1616
1617 struct radv_subpass {
1618         uint32_t                                     input_count;
1619         uint32_t                                     color_count;
1620         VkAttachmentReference *                      input_attachments;
1621         VkAttachmentReference *                      color_attachments;
1622         VkAttachmentReference *                      resolve_attachments;
1623         VkAttachmentReference                        depth_stencil_attachment;
1624
1625         /** Subpass has at least one resolve attachment */
1626         bool                                         has_resolve;
1627
1628         struct radv_subpass_barrier                  start_barrier;
1629
1630         uint32_t                                     view_mask;
1631         VkSampleCountFlagBits                        max_sample_count;
1632 };
1633
1634 struct radv_render_pass_attachment {
1635         VkFormat                                     format;
1636         uint32_t                                     samples;
1637         VkAttachmentLoadOp                           load_op;
1638         VkAttachmentLoadOp                           stencil_load_op;
1639         VkImageLayout                                initial_layout;
1640         VkImageLayout                                final_layout;
1641         uint32_t                                     view_mask;
1642 };
1643
1644 struct radv_render_pass {
1645         uint32_t                                     attachment_count;
1646         uint32_t                                     subpass_count;
1647         VkAttachmentReference *                      subpass_attachments;
1648         struct radv_render_pass_attachment *         attachments;
1649         struct radv_subpass_barrier                  end_barrier;
1650         struct radv_subpass                          subpasses[0];
1651 };
1652
1653 VkResult radv_device_init_meta(struct radv_device *device);
1654 void radv_device_finish_meta(struct radv_device *device);
1655
1656 struct radv_query_pool {
1657         struct radeon_winsys_bo *bo;
1658         uint32_t stride;
1659         uint32_t availability_offset;
1660         uint64_t size;
1661         char *ptr;
1662         VkQueryType type;
1663         uint32_t pipeline_stats_mask;
1664 };
1665
1666 struct radv_semaphore {
1667         /* use a winsys sem for non-exportable */
1668         struct radeon_winsys_sem *sem;
1669         uint32_t syncobj;
1670         uint32_t temp_syncobj;
1671 };
1672
1673 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1674                              int num_wait_sems,
1675                              const VkSemaphore *wait_sems,
1676                              int num_signal_sems,
1677                              const VkSemaphore *signal_sems,
1678                              VkFence fence);
1679 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1680
1681 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1682                              VkPipelineBindPoint bind_point,
1683                              struct radv_descriptor_set *set,
1684                              unsigned idx);
1685
1686 void
1687 radv_update_descriptor_sets(struct radv_device *device,
1688                             struct radv_cmd_buffer *cmd_buffer,
1689                             VkDescriptorSet overrideSet,
1690                             uint32_t descriptorWriteCount,
1691                             const VkWriteDescriptorSet *pDescriptorWrites,
1692                             uint32_t descriptorCopyCount,
1693                             const VkCopyDescriptorSet *pDescriptorCopies);
1694
1695 void
1696 radv_update_descriptor_set_with_template(struct radv_device *device,
1697                                          struct radv_cmd_buffer *cmd_buffer,
1698                                          struct radv_descriptor_set *set,
1699                                          VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1700                                          const void *pData);
1701
1702 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1703                                    VkPipelineBindPoint pipelineBindPoint,
1704                                    VkPipelineLayout _layout,
1705                                    uint32_t set,
1706                                    uint32_t descriptorWriteCount,
1707                                    const VkWriteDescriptorSet *pDescriptorWrites);
1708
1709 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1710                            struct radv_image *image, uint32_t value);
1711 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1712                          struct radv_image *image, uint32_t value);
1713
1714 struct radv_fence {
1715         struct radeon_winsys_fence *fence;
1716         bool submitted;
1717         bool signalled;
1718
1719         uint32_t syncobj;
1720         uint32_t temp_syncobj;
1721 };
1722
1723 /* radv_nir_to_llvm.c */
1724 struct radv_shader_variant_info;
1725 struct radv_nir_compiler_options;
1726
1727 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
1728                                  struct nir_shader *geom_shader,
1729                                  struct ac_shader_binary *binary,
1730                                  struct ac_shader_config *config,
1731                                  struct radv_shader_variant_info *shader_info,
1732                                  const struct radv_nir_compiler_options *option);
1733
1734 void radv_compile_nir_shader(LLVMTargetMachineRef tm,
1735                              struct ac_shader_binary *binary,
1736                              struct ac_shader_config *config,
1737                              struct radv_shader_variant_info *shader_info,
1738                              struct nir_shader *const *nir,
1739                              int nir_count,
1740                              const struct radv_nir_compiler_options *options);
1741
1742 /* radv_shader_info.h */
1743 struct radv_shader_info;
1744
1745 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1746                                const struct radv_nir_compiler_options *options,
1747                                struct radv_shader_info *info);
1748
1749 struct radeon_winsys_sem;
1750
1751 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType)         \
1752                                                                 \
1753         static inline struct __radv_type *                      \
1754         __radv_type ## _from_handle(__VkType _handle)           \
1755         {                                                       \
1756                 return (struct __radv_type *) _handle;          \
1757         }                                                       \
1758                                                                 \
1759         static inline __VkType                                  \
1760         __radv_type ## _to_handle(struct __radv_type *_obj)     \
1761         {                                                       \
1762                 return (__VkType) _obj;                         \
1763         }
1764
1765 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType)         \
1766                                                                         \
1767         static inline struct __radv_type *                              \
1768         __radv_type ## _from_handle(__VkType _handle)                   \
1769         {                                                               \
1770                 return (struct __radv_type *)(uintptr_t) _handle;       \
1771         }                                                               \
1772                                                                         \
1773         static inline __VkType                                          \
1774         __radv_type ## _to_handle(struct __radv_type *_obj)             \
1775         {                                                               \
1776                 return (__VkType)(uintptr_t) _obj;                      \
1777         }
1778
1779 #define RADV_FROM_HANDLE(__radv_type, __name, __handle)                 \
1780         struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1781
1782 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1783 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1784 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1785 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1786 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1787
1788 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1789 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1790 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1791 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1792 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1793 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1794 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1795 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1796 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1797 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1798 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1799 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1800 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1801 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1802 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1803 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1804 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1805 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1806 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1807 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1808 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1809
1810 #endif /* RADV_PRIVATE_H */