src/amd/vulkan/radv_private.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_PRIVATE_H
  29 #define RADV_PRIVATE_H
  30
  31 #include <stdlib.h>
  32 #include <stdio.h>
  33 #include <stdbool.h>
  34 #include <pthread.h>
  35 #include <assert.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #ifdef HAVE_VALGRIND
  39 #include <valgrind.h>
  40 #include <memcheck.h>
  41 #define VG(x) x
  42 #else
  43 #define VG(x)
  44 #endif
  45
  46 #include "c11/threads.h"
  47 #include <amdgpu.h>
  48 #include "compiler/shader_enums.h"
  49 #include "util/macros.h"
  50 #include "util/list.h"
  51 #include "main/macros.h"
  52 #include "vk_alloc.h"
  53 #include "vk_debug_report.h"
  54
  55 #include "radv_radeon_winsys.h"
  56 #include "ac_binary.h"
  57 #include "ac_nir_to_llvm.h"
  58 #include "ac_gpu_info.h"
  59 #include "ac_surface.h"
  60 #include "radv_descriptor_set.h"
  61 #include "radv_extensions.h"
  62
  63 #include <llvm-c/TargetMachine.h>
  64
  65 /* Pre-declarations needed for WSI entrypoints */
  66 struct wl_surface;
  67 struct wl_display;
  68 typedef struct xcb_connection_t xcb_connection_t;
  69 typedef uint32_t xcb_visualid_t;
  70 typedef uint32_t xcb_window_t;
  71
  72 #include <vulkan/vulkan.h>
  73 #include <vulkan/vulkan_intel.h>
  74 #include <vulkan/vk_icd.h>
  75 #include <vulkan/vk_android_native_buffer.h>
  76
  77 #include "radv_entrypoints.h"
  78
  79 #include "wsi_common.h"
  80
  81 #define ATI_VENDOR_ID 0x1002
  82
  83 #define MAX_VBS         32
  84 #define MAX_VERTEX_ATTRIBS 32
  85 #define MAX_RTS          8
  86 #define MAX_VIEWPORTS   16
  87 #define MAX_SCISSORS    16
  88 #define MAX_DISCARD_RECTANGLES 4
  89 #define MAX_PUSH_CONSTANTS_SIZE 128
  90 #define MAX_PUSH_DESCRIPTORS 32
  91 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
  92 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
  93 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
  94 #define MAX_SAMPLES_LOG2 4
  95 #define NUM_META_FS_KEYS 13
  96 #define RADV_MAX_DRM_DEVICES 8
  97 #define MAX_VIEWS        8
  98
  99 #define NUM_DEPTH_CLEAR_PIPELINES 3
 100
 101 /*
 102  * This is the point we switch from using CP to compute shader
 103  * for certain buffer operations.
 104  */
 105 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
 106
 107 enum radv_mem_heap {
 108         RADV_MEM_HEAP_VRAM,
 109         RADV_MEM_HEAP_VRAM_CPU_ACCESS,
 110         RADV_MEM_HEAP_GTT,
 111         RADV_MEM_HEAP_COUNT
 112 };
 113
 114 enum radv_mem_type {
 115         RADV_MEM_TYPE_VRAM,
 116         RADV_MEM_TYPE_GTT_WRITE_COMBINE,
 117         RADV_MEM_TYPE_VRAM_CPU_ACCESS,
 118         RADV_MEM_TYPE_GTT_CACHED,
 119         RADV_MEM_TYPE_COUNT
 120 };
 121
 122 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
 123
 124 static inline uint32_t
 125 align_u32(uint32_t v, uint32_t a)
 126 {
 127         assert(a != 0 && a == (a & -a));
 128         return (v + a - 1) & ~(a - 1);
 129 }
 130
 131 static inline uint32_t
 132 align_u32_npot(uint32_t v, uint32_t a)
 133 {
 134         return (v + a - 1) / a * a;
 135 }
 136
 137 static inline uint64_t
 138 align_u64(uint64_t v, uint64_t a)
 139 {
 140         assert(a != 0 && a == (a & -a));
 141         return (v + a - 1) & ~(a - 1);
 142 }
 143
 144 static inline int32_t
 145 align_i32(int32_t v, int32_t a)
 146 {
 147         assert(a != 0 && a == (a & -a));
 148         return (v + a - 1) & ~(a - 1);
 149 }
 150
 151 /** Alignment must be a power of 2. */
 152 static inline bool
 153 radv_is_aligned(uintmax_t n, uintmax_t a)
 154 {
 155         assert(a == (a & -a));
 156         return (n & (a - 1)) == 0;
 157 }
 158
 159 static inline uint32_t
 160 round_up_u32(uint32_t v, uint32_t a)
 161 {
 162         return (v + a - 1) / a;
 163 }
 164
 165 static inline uint64_t
 166 round_up_u64(uint64_t v, uint64_t a)
 167 {
 168         return (v + a - 1) / a;
 169 }
 170
 171 static inline uint32_t
 172 radv_minify(uint32_t n, uint32_t levels)
 173 {
 174         if (unlikely(n == 0))
 175                 return 0;
 176         else
 177                 return MAX2(n >> levels, 1);
 178 }
 179 static inline float
 180 radv_clamp_f(float f, float min, float max)
 181 {
 182         assert(min < max);
 183
 184         if (f > max)
 185                 return max;
 186         else if (f < min)
 187                 return min;
 188         else
 189                 return f;
 190 }
 191
 192 static inline bool
 193 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
 194 {
 195         if (*inout_mask & clear_mask) {
 196                 *inout_mask &= ~clear_mask;
 197                 return true;
 198         } else {
 199                 return false;
 200         }
 201 }
 202
 203 #define for_each_bit(b, dword)                          \
 204         for (uint32_t __dword = (dword);                \
 205              (b) = __builtin_ffs(__dword) - 1, __dword; \
 206              __dword &= ~(1 << (b)))
 207
 208 #define typed_memcpy(dest, src, count) ({                               \
 209                         STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
 210                         memcpy((dest), (src), (count) * sizeof(*(src))); \
 211                 })
 212
 213 /* Whenever we generate an error, pass it through this function. Useful for
 214  * debugging, where we can break on it. Only call at error site, not when
 215  * propagating errors. Might be useful to plug in a stack trace here.
 216  */
 217
 218 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
 219
 220 #ifdef DEBUG
 221 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
 222 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
 223 #else
 224 #define vk_error(error) error
 225 #define vk_errorf(error, format, ...) error
 226 #endif
 227
 228 void __radv_finishme(const char *file, int line, const char *format, ...)
 229         radv_printflike(3, 4);
 230 void radv_loge(const char *format, ...) radv_printflike(1, 2);
 231 void radv_loge_v(const char *format, va_list va);
 232
 233 /**
 234  * Print a FINISHME message, including its source location.
 235  */
 236 #define radv_finishme(format, ...)                                      \
 237         do { \
 238                 static bool reported = false; \
 239                 if (!reported) { \
 240                         __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
 241                         reported = true; \
 242                 } \
 243         } while (0)
 244
 245 /* A non-fatal assert.  Useful for debugging. */
 246 #ifdef DEBUG
 247 #define radv_assert(x) ({                                               \
 248                         if (unlikely(!(x)))                             \
 249                                 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
 250                 })
 251 #else
 252 #define radv_assert(x)
 253 #endif
 254
 255 #define stub_return(v)                                  \
 256         do {                                            \
 257                 radv_finishme("stub %s", __func__);     \
 258                 return (v);                             \
 259         } while (0)
 260
 261 #define stub()                                          \
 262         do {                                            \
 263                 radv_finishme("stub %s", __func__);     \
 264                 return;                                 \
 265         } while (0)
 266
 267 void *radv_lookup_entrypoint_unchecked(const char *name);
 268 void *radv_lookup_entrypoint_checked(const char *name,
 269                                     uint32_t core_version,
 270                                     const struct radv_instance_extension_table *instance,
 271                                     const struct radv_device_extension_table *device);
 272
 273 struct radv_physical_device {
 274         VK_LOADER_DATA                              _loader_data;
 275
 276         struct radv_instance *                       instance;
 277
 278         struct radeon_winsys *ws;
 279         struct radeon_info rad_info;
 280         char                                        path[20];
 281         char                                        name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
 282         uint8_t                                     driver_uuid[VK_UUID_SIZE];
 283         uint8_t                                     device_uuid[VK_UUID_SIZE];
 284         uint8_t                                     cache_uuid[VK_UUID_SIZE];
 285
 286         int local_fd;
 287         struct wsi_device                       wsi_device;
 288
 289         bool has_rbplus; /* if RB+ register exist */
 290         bool rbplus_allowed; /* if RB+ is allowed */
 291         bool has_clear_state;
 292         bool cpdma_prefetch_writes_memory;
 293         bool has_scissor_bug;
 294
 295         bool has_out_of_order_rast;
 296         bool out_of_order_rast_allowed;
 297
 298         /* Whether DCC should be enabled for MSAA textures. */
 299         bool dcc_msaa_allowed;
 300
 301         /* This is the drivers on-disk cache used as a fallback as opposed to
 302          * the pipeline cache defined by apps.
 303          */
 304         struct disk_cache *                          disk_cache;
 305
 306         VkPhysicalDeviceMemoryProperties memory_properties;
 307         enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
 308
 309         struct radv_device_extension_table supported_extensions;
 310 };
 311
 312 struct radv_instance {
 313         VK_LOADER_DATA                              _loader_data;
 314
 315         VkAllocationCallbacks                       alloc;
 316
 317         uint32_t                                    apiVersion;
 318         int                                         physicalDeviceCount;
 319         struct radv_physical_device                 physicalDevices[RADV_MAX_DRM_DEVICES];
 320
 321         uint64_t debug_flags;
 322         uint64_t perftest_flags;
 323
 324         struct vk_debug_report_instance             debug_report_callbacks;
 325
 326         struct radv_instance_extension_table enabled_extensions;
 327 };
 328
 329 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
 330 void radv_finish_wsi(struct radv_physical_device *physical_device);
 331
 332 bool radv_instance_extension_supported(const char *name);
 333 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
 334 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
 335                                               const char *name);
 336
 337 struct cache_entry;
 338
 339 struct radv_pipeline_cache {
 340         struct radv_device *                          device;
 341         pthread_mutex_t                              mutex;
 342
 343         uint32_t                                     total_size;
 344         uint32_t                                     table_size;
 345         uint32_t                                     kernel_count;
 346         struct cache_entry **                        hash_table;
 347         bool                                         modified;
 348
 349         VkAllocationCallbacks                        alloc;
 350 };
 351
 352 struct radv_pipeline_key {
 353         uint32_t instance_rate_inputs;
 354         uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
 355         unsigned tess_input_vertices;
 356         uint32_t col_format;
 357         uint32_t is_int8;
 358         uint32_t is_int10;
 359         uint8_t log2_ps_iter_samples;
 360         uint8_t log2_num_samples;
 361         uint32_t multisample : 1;
 362         uint32_t has_multiview_view_index : 1;
 363 };
 364
 365 void
 366 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
 367                          struct radv_device *device);
 368 void
 369 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
 370 void
 371 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
 372                          const void *data, size_t size);
 373
 374 struct radv_shader_variant;
 375
 376 bool
 377 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
 378                                                 struct radv_pipeline_cache *cache,
 379                                                 const unsigned char *sha1,
 380                                                 struct radv_shader_variant **variants);
 381
 382 void
 383 radv_pipeline_cache_insert_shaders(struct radv_device *device,
 384                                    struct radv_pipeline_cache *cache,
 385                                    const unsigned char *sha1,
 386                                    struct radv_shader_variant **variants,
 387                                    const void *const *codes,
 388                                    const unsigned *code_sizes);
 389
 390 enum radv_blit_ds_layout {
 391         RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
 392         RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
 393         RADV_BLIT_DS_LAYOUT_COUNT,
 394 };
 395
 396 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
 397 {
 398         return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
 399 }
 400
 401 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
 402 {
 403         return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
 404 }
 405
 406 enum radv_meta_dst_layout {
 407         RADV_META_DST_LAYOUT_GENERAL,
 408         RADV_META_DST_LAYOUT_OPTIMAL,
 409         RADV_META_DST_LAYOUT_COUNT,
 410 };
 411
 412 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
 413 {
 414         return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
 415 }
 416
 417 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
 418 {
 419         return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
 420 }
 421
 422 struct radv_meta_state {
 423         VkAllocationCallbacks alloc;
 424
 425         struct radv_pipeline_cache cache;
 426
 427         /**
 428          * Use array element `i` for images with `2^i` samples.
 429          */
 430         struct {
 431                 VkRenderPass render_pass[NUM_META_FS_KEYS];
 432                 VkPipeline color_pipelines[NUM_META_FS_KEYS];
 433
 434                 VkRenderPass depthstencil_rp;
 435                 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 436                 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 437                 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 438         } clear[1 + MAX_SAMPLES_LOG2];
 439
 440         VkPipelineLayout                          clear_color_p_layout;
 441         VkPipelineLayout                          clear_depth_p_layout;
 442         struct {
 443                 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
 444
 445                 /** Pipeline that blits from a 1D image. */
 446                 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
 447
 448                 /** Pipeline that blits from a 2D image. */
 449                 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
 450
 451                 /** Pipeline that blits from a 3D image. */
 452                 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
 453
 454                 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
 455                 VkPipeline depth_only_1d_pipeline;
 456                 VkPipeline depth_only_2d_pipeline;
 457                 VkPipeline depth_only_3d_pipeline;
 458
 459                 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
 460                 VkPipeline stencil_only_1d_pipeline;
 461                 VkPipeline stencil_only_2d_pipeline;
 462                 VkPipeline stencil_only_3d_pipeline;
 463                 VkPipelineLayout                          pipeline_layout;
 464                 VkDescriptorSetLayout                     ds_layout;
 465         } blit;
 466
 467         struct {
 468                 VkPipelineLayout p_layouts[5];
 469                 VkDescriptorSetLayout ds_layouts[5];
 470                 VkPipeline pipelines[5][NUM_META_FS_KEYS];
 471
 472                 VkPipeline depth_only_pipeline[5];
 473
 474                 VkPipeline stencil_only_pipeline[5];
 475         } blit2d[1 + MAX_SAMPLES_LOG2];
 476
 477         VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
 478         VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
 479         VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
 480
 481         struct {
 482                 VkPipelineLayout                          img_p_layout;
 483                 VkDescriptorSetLayout                     img_ds_layout;
 484                 VkPipeline pipeline;
 485                 VkPipeline pipeline_3d;
 486         } itob;
 487         struct {
 488                 VkPipelineLayout                          img_p_layout;
 489                 VkDescriptorSetLayout                     img_ds_layout;
 490                 VkPipeline pipeline;
 491                 VkPipeline pipeline_3d;
 492         } btoi;
 493         struct {
 494                 VkPipelineLayout                          img_p_layout;
 495                 VkDescriptorSetLayout                     img_ds_layout;
 496                 VkPipeline pipeline;
 497                 VkPipeline pipeline_3d;
 498         } itoi;
 499         struct {
 500                 VkPipelineLayout                          img_p_layout;
 501                 VkDescriptorSetLayout                     img_ds_layout;
 502                 VkPipeline pipeline;
 503                 VkPipeline pipeline_3d;
 504         } cleari;
 505
 506         struct {
 507                 VkPipelineLayout                          p_layout;
 508                 VkPipeline                                pipeline[NUM_META_FS_KEYS];
 509                 VkRenderPass                              pass[NUM_META_FS_KEYS];
 510         } resolve;
 511
 512         struct {
 513                 VkDescriptorSetLayout                     ds_layout;
 514                 VkPipelineLayout                          p_layout;
 515                 struct {
 516                         VkPipeline                                pipeline;
 517                         VkPipeline                                i_pipeline;
 518                         VkPipeline                                srgb_pipeline;
 519                 } rc[MAX_SAMPLES_LOG2];
 520         } resolve_compute;
 521
 522         struct {
 523                 VkDescriptorSetLayout                     ds_layout;
 524                 VkPipelineLayout                          p_layout;
 525
 526                 struct {
 527                         VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
 528                         VkPipeline   pipeline[NUM_META_FS_KEYS];
 529                 } rc[MAX_SAMPLES_LOG2];
 530         } resolve_fragment;
 531
 532         struct {
 533                 VkPipelineLayout                          p_layout;
 534                 VkPipeline                                decompress_pipeline;
 535                 VkPipeline                                resummarize_pipeline;
 536                 VkRenderPass                              pass;
 537         } depth_decomp[1 + MAX_SAMPLES_LOG2];
 538
 539         struct {
 540                 VkPipelineLayout                          p_layout;
 541                 VkPipeline                                cmask_eliminate_pipeline;
 542                 VkPipeline                                fmask_decompress_pipeline;
 543                 VkPipeline                                dcc_decompress_pipeline;
 544                 VkRenderPass                              pass;
 545
 546                 VkDescriptorSetLayout                     dcc_decompress_compute_ds_layout;
 547                 VkPipelineLayout                          dcc_decompress_compute_p_layout;
 548                 VkPipeline                                dcc_decompress_compute_pipeline;
 549         } fast_clear_flush;
 550
 551         struct {
 552                 VkPipelineLayout fill_p_layout;
 553                 VkPipelineLayout copy_p_layout;
 554                 VkDescriptorSetLayout fill_ds_layout;
 555                 VkDescriptorSetLayout copy_ds_layout;
 556                 VkPipeline fill_pipeline;
 557                 VkPipeline copy_pipeline;
 558         } buffer;
 559
 560         struct {
 561                 VkDescriptorSetLayout ds_layout;
 562                 VkPipelineLayout p_layout;
 563                 VkPipeline occlusion_query_pipeline;
 564                 VkPipeline pipeline_statistics_query_pipeline;
 565         } query;
 566 };
 567
 568 /* queue types */
 569 #define RADV_QUEUE_GENERAL 0
 570 #define RADV_QUEUE_COMPUTE 1
 571 #define RADV_QUEUE_TRANSFER 2
 572
 573 #define RADV_MAX_QUEUE_FAMILIES 3
 574
 575 enum ring_type radv_queue_family_to_ring(int f);
 576
 577 struct radv_queue {
 578         VK_LOADER_DATA                              _loader_data;
 579         struct radv_device *                         device;
 580         struct radeon_winsys_ctx                    *hw_ctx;
 581         enum radeon_ctx_priority                     priority;
 582         uint32_t queue_family_index;
 583         int queue_idx;
 584         VkDeviceQueueCreateFlags flags;
 585
 586         uint32_t scratch_size;
 587         uint32_t compute_scratch_size;
 588         uint32_t esgs_ring_size;
 589         uint32_t gsvs_ring_size;
 590         bool has_tess_rings;
 591         bool has_sample_positions;
 592
 593         struct radeon_winsys_bo *scratch_bo;
 594         struct radeon_winsys_bo *descriptor_bo;
 595         struct radeon_winsys_bo *compute_scratch_bo;
 596         struct radeon_winsys_bo *esgs_ring_bo;
 597         struct radeon_winsys_bo *gsvs_ring_bo;
 598         struct radeon_winsys_bo *tess_rings_bo;
 599         struct radeon_winsys_cs *initial_preamble_cs;
 600         struct radeon_winsys_cs *initial_full_flush_preamble_cs;
 601         struct radeon_winsys_cs *continue_preamble_cs;
 602 };
 603
 604 struct radv_bo_list {
 605         struct radv_winsys_bo_list list;
 606         unsigned capacity;
 607         pthread_mutex_t mutex;
 608 };
 609
 610 struct radv_device {
 611         VK_LOADER_DATA                              _loader_data;
 612
 613         VkAllocationCallbacks                       alloc;
 614
 615         struct radv_instance *                       instance;
 616         struct radeon_winsys *ws;
 617
 618         struct radv_meta_state                       meta_state;
 619
 620         struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
 621         int queue_count[RADV_MAX_QUEUE_FAMILIES];
 622         struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
 623
 624         bool always_use_syncobj;
 625         bool llvm_supports_spill;
 626         bool has_distributed_tess;
 627         bool pbb_allowed;
 628         bool dfsm_allowed;
 629         uint32_t tess_offchip_block_dw_size;
 630         uint32_t scratch_waves;
 631         uint32_t dispatch_initiator;
 632
 633         uint32_t gs_table_depth;
 634
 635         /* MSAA sample locations.
 636          * The first index is the sample index.
 637          * The second index is the coordinate: X, Y. */
 638         float sample_locations_1x[1][2];
 639         float sample_locations_2x[2][2];
 640         float sample_locations_4x[4][2];
 641         float sample_locations_8x[8][2];
 642         float sample_locations_16x[16][2];
 643
 644         /* CIK and later */
 645         uint32_t gfx_init_size_dw;
 646         struct radeon_winsys_bo                      *gfx_init;
 647
 648         struct radeon_winsys_bo                      *trace_bo;
 649         uint32_t                                     *trace_id_ptr;
 650
 651         /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
 652         bool                                         keep_shader_info;
 653
 654         struct radv_physical_device                  *physical_device;
 655
 656         /* Backup in-memory cache to be used if the app doesn't provide one */
 657         struct radv_pipeline_cache *                mem_cache;
 658
 659         /*
 660          * use different counters so MSAA MRTs get consecutive surface indices,
 661          * even if MASK is allocated in between.
 662          */
 663         uint32_t image_mrt_offset_counter;
 664         uint32_t fmask_mrt_offset_counter;
 665         struct list_head shader_slabs;
 666         mtx_t shader_slab_mutex;
 667
 668         /* For detecting VM faults reported by dmesg. */
 669         uint64_t dmesg_timestamp;
 670
 671         struct radv_device_extension_table enabled_extensions;
 672
 673         /* Whether the driver uses a global BO list. */
 674         bool use_global_bo_list;
 675
 676         struct radv_bo_list bo_list;
 677 };
 678
 679 struct radv_device_memory {
 680         struct radeon_winsys_bo                      *bo;
 681         /* for dedicated allocations */
 682         struct radv_image                            *image;
 683         struct radv_buffer                           *buffer;
 684         uint32_t                                     type_index;
 685         VkDeviceSize                                 map_size;
 686         void *                                       map;
 687         void *                                       user_ptr;
 688 };
 689
 690
 691 struct radv_descriptor_range {
 692         uint64_t va;
 693         uint32_t size;
 694 };
 695
 696 struct radv_descriptor_set {
 697         const struct radv_descriptor_set_layout *layout;
 698         uint32_t size;
 699
 700         struct radeon_winsys_bo *bo;
 701         uint64_t va;
 702         uint32_t *mapped_ptr;
 703         struct radv_descriptor_range *dynamic_descriptors;
 704
 705         struct radeon_winsys_bo *descriptors[0];
 706 };
 707
 708 struct radv_push_descriptor_set
 709 {
 710         struct radv_descriptor_set set;
 711         uint32_t capacity;
 712 };
 713
 714 struct radv_descriptor_pool_entry {
 715         uint32_t offset;
 716         uint32_t size;
 717         struct radv_descriptor_set *set;
 718 };
 719
 720 struct radv_descriptor_pool {
 721         struct radeon_winsys_bo *bo;
 722         uint8_t *mapped_ptr;
 723         uint64_t current_offset;
 724         uint64_t size;
 725
 726         uint8_t *host_memory_base;
 727         uint8_t *host_memory_ptr;
 728         uint8_t *host_memory_end;
 729
 730         uint32_t entry_count;
 731         uint32_t max_entry_count;
 732         struct radv_descriptor_pool_entry entries[0];
 733 };
 734
 735 struct radv_descriptor_update_template_entry {
 736         VkDescriptorType descriptor_type;
 737
 738         /* The number of descriptors to update */
 739         uint32_t descriptor_count;
 740
 741         /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
 742         uint32_t dst_offset;
 743
 744         /* In dwords. Not valid/used for dynamic descriptors */
 745         uint32_t dst_stride;
 746
 747         uint32_t buffer_offset;
 748
 749         /* Only valid for combined image samplers and samplers */
 750         uint16_t has_sampler;
 751
 752         /* In bytes */
 753         size_t src_offset;
 754         size_t src_stride;
 755
 756         /* For push descriptors */
 757         const uint32_t *immutable_samplers;
 758 };
 759
 760 struct radv_descriptor_update_template {
 761         uint32_t entry_count;
 762         VkPipelineBindPoint bind_point;
 763         struct radv_descriptor_update_template_entry entry[0];
 764 };
 765
 766 struct radv_buffer {
 767         VkDeviceSize                                 size;
 768
 769         VkBufferUsageFlags                           usage;
 770         VkBufferCreateFlags                          flags;
 771
 772         /* Set when bound */
 773         struct radeon_winsys_bo *                      bo;
 774         VkDeviceSize                                 offset;
 775
 776         bool shareable;
 777 };
 778
 779 enum radv_dynamic_state_bits {
 780         RADV_DYNAMIC_VIEWPORT             = 1 << 0,
 781         RADV_DYNAMIC_SCISSOR              = 1 << 1,
 782         RADV_DYNAMIC_LINE_WIDTH           = 1 << 2,
 783         RADV_DYNAMIC_DEPTH_BIAS           = 1 << 3,
 784         RADV_DYNAMIC_BLEND_CONSTANTS      = 1 << 4,
 785         RADV_DYNAMIC_DEPTH_BOUNDS         = 1 << 5,
 786         RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
 787         RADV_DYNAMIC_STENCIL_WRITE_MASK   = 1 << 7,
 788         RADV_DYNAMIC_STENCIL_REFERENCE    = 1 << 8,
 789         RADV_DYNAMIC_DISCARD_RECTANGLE    = 1 << 9,
 790         RADV_DYNAMIC_ALL                  = (1 << 10) - 1,
 791 };
 792
 793 enum radv_cmd_dirty_bits {
 794         /* Keep the dynamic state dirty bits in sync with
 795          * enum radv_dynamic_state_bits */
 796         RADV_CMD_DIRTY_DYNAMIC_VIEWPORT                  = 1 << 0,
 797         RADV_CMD_DIRTY_DYNAMIC_SCISSOR                   = 1 << 1,
 798         RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH                = 1 << 2,
 799         RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS                = 1 << 3,
 800         RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS           = 1 << 4,
 801         RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS              = 1 << 5,
 802         RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK      = 1 << 6,
 803         RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK        = 1 << 7,
 804         RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE         = 1 << 8,
 805         RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE         = 1 << 9,
 806         RADV_CMD_DIRTY_DYNAMIC_ALL                       = (1 << 10) - 1,
 807         RADV_CMD_DIRTY_PIPELINE                          = 1 << 10,
 808         RADV_CMD_DIRTY_INDEX_BUFFER                      = 1 << 11,
 809         RADV_CMD_DIRTY_FRAMEBUFFER                       = 1 << 12,
 810         RADV_CMD_DIRTY_VERTEX_BUFFER                     = 1 << 13,
 811 };
 812
 813 enum radv_cmd_flush_bits {
 814         RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
 815         /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
 816         RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
 817         /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
 818         RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
 819         /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
 820         RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
 821         /* Same as above, but only writes back and doesn't invalidate */
 822         RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
 823         /* Framebuffer caches */
 824         RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
 825         RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
 826         RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
 827         RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
 828         /* Engine synchronization. */
 829         RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
 830         RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
 831         RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
 832         RADV_CMD_FLAG_VGT_FLUSH        = 1 << 12,
 833
 834         RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
 835                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
 836                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB |
 837                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
 838 };
 839
 840 struct radv_vertex_binding {
 841         struct radv_buffer *                          buffer;
 842         VkDeviceSize                                 offset;
 843 };
 844
 845 struct radv_viewport_state {
 846         uint32_t                                          count;
 847         VkViewport                                        viewports[MAX_VIEWPORTS];
 848 };
 849
 850 struct radv_scissor_state {
 851         uint32_t                                          count;
 852         VkRect2D                                          scissors[MAX_SCISSORS];
 853 };
 854
 855 struct radv_discard_rectangle_state {
 856         uint32_t                                          count;
 857         VkRect2D                                          rectangles[MAX_DISCARD_RECTANGLES];
 858 };
 859
 860 struct radv_dynamic_state {
 861         /**
 862          * Bitmask of (1 << VK_DYNAMIC_STATE_*).
 863          * Defines the set of saved dynamic state.
 864          */
 865         uint32_t mask;
 866
 867         struct radv_viewport_state                        viewport;
 868
 869         struct radv_scissor_state                         scissor;
 870
 871         float                                        line_width;
 872
 873         struct {
 874                 float                                     bias;
 875                 float                                     clamp;
 876                 float                                     slope;
 877         } depth_bias;
 878
 879         float                                        blend_constants[4];
 880
 881         struct {
 882                 float                                     min;
 883                 float                                     max;
 884         } depth_bounds;
 885
 886         struct {
 887                 uint32_t                                  front;
 888                 uint32_t                                  back;
 889         } stencil_compare_mask;
 890
 891         struct {
 892                 uint32_t                                  front;
 893                 uint32_t                                  back;
 894         } stencil_write_mask;
 895
 896         struct {
 897                 uint32_t                                  front;
 898                 uint32_t                                  back;
 899         } stencil_reference;
 900
 901         struct radv_discard_rectangle_state               discard_rectangle;
 902 };
 903
 904 extern const struct radv_dynamic_state default_dynamic_state;
 905
 906 const char *
 907 radv_get_debug_option_name(int id);
 908
 909 const char *
 910 radv_get_perftest_option_name(int id);
 911
 912 /**
 913  * Attachment state when recording a renderpass instance.
 914  *
 915  * The clear value is valid only if there exists a pending clear.
 916  */
 917 struct radv_attachment_state {
 918         VkImageAspectFlags                           pending_clear_aspects;
 919         uint32_t                                     cleared_views;
 920         VkClearValue                                 clear_value;
 921         VkImageLayout                                current_layout;
 922 };
 923
 924 struct radv_descriptor_state {
 925         struct radv_descriptor_set *sets[MAX_SETS];
 926         uint32_t dirty;
 927         uint32_t valid;
 928         struct radv_push_descriptor_set push_set;
 929         bool push_dirty;
 930 };
 931
 932 struct radv_cmd_state {
 933         /* Vertex descriptors */
 934         uint64_t                                      vb_va;
 935         unsigned                                      vb_size;
 936
 937         bool predicating;
 938         uint32_t                                      dirty;
 939
 940         uint32_t                                      prefetch_L2_mask;
 941
 942         struct radv_pipeline *                        pipeline;
 943         struct radv_pipeline *                        emitted_pipeline;
 944         struct radv_pipeline *                        compute_pipeline;
 945         struct radv_pipeline *                        emitted_compute_pipeline;
 946         struct radv_framebuffer *                     framebuffer;
 947         struct radv_render_pass *                     pass;
 948         const struct radv_subpass *                         subpass;
 949         struct radv_dynamic_state                     dynamic;
 950         struct radv_attachment_state *                attachments;
 951         VkRect2D                                     render_area;
 952
 953         /* Index buffer */
 954         struct radv_buffer                           *index_buffer;
 955         uint64_t                                     index_offset;
 956         uint32_t                                     index_type;
 957         uint32_t                                     max_index_count;
 958         uint64_t                                     index_va;
 959         int32_t                                      last_index_type;
 960
 961         int32_t                                      last_primitive_reset_en;
 962         uint32_t                                     last_primitive_reset_index;
 963         enum radv_cmd_flush_bits                     flush_bits;
 964         unsigned                                     active_occlusion_queries;
 965         bool                                         perfect_occlusion_queries_enabled;
 966         float                                        offset_scale;
 967         uint32_t                                      trace_id;
 968         uint32_t                                      last_ia_multi_vgt_param;
 969
 970         uint32_t last_num_instances;
 971         uint32_t last_first_instance;
 972         uint32_t last_vertex_offset;
 973 };
 974
 975 struct radv_cmd_pool {
 976         VkAllocationCallbacks                        alloc;
 977         struct list_head                             cmd_buffers;
 978         struct list_head                             free_cmd_buffers;
 979         uint32_t queue_family_index;
 980 };
 981
 982 struct radv_cmd_buffer_upload {
 983         uint8_t *map;
 984         unsigned offset;
 985         uint64_t size;
 986         struct radeon_winsys_bo *upload_bo;
 987         struct list_head list;
 988 };
 989
 990 enum radv_cmd_buffer_status {
 991         RADV_CMD_BUFFER_STATUS_INVALID,
 992         RADV_CMD_BUFFER_STATUS_INITIAL,
 993         RADV_CMD_BUFFER_STATUS_RECORDING,
 994         RADV_CMD_BUFFER_STATUS_EXECUTABLE,
 995         RADV_CMD_BUFFER_STATUS_PENDING,
 996 };
 997
 998 struct radv_cmd_buffer {
 999         VK_LOADER_DATA                               _loader_data;
1000
1001         struct radv_device *                          device;
1002
1003         struct radv_cmd_pool *                        pool;
1004         struct list_head                             pool_link;
1005
1006         VkCommandBufferUsageFlags                    usage_flags;
1007         VkCommandBufferLevel                         level;
1008         enum radv_cmd_buffer_status status;
1009         struct radeon_winsys_cs *cs;
1010         struct radv_cmd_state state;
1011         struct radv_vertex_binding                   vertex_bindings[MAX_VBS];
1012         uint32_t queue_family_index;
1013
1014         uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1015         uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1016         VkShaderStageFlags push_constant_stages;
1017         struct radv_descriptor_set meta_push_descriptors;
1018
1019         struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1020
1021         struct radv_cmd_buffer_upload upload;
1022
1023         uint32_t scratch_size_needed;
1024         uint32_t compute_scratch_size_needed;
1025         uint32_t esgs_ring_size_needed;
1026         uint32_t gsvs_ring_size_needed;
1027         bool tess_rings_needed;
1028         bool sample_positions_needed;
1029
1030         VkResult record_result;
1031
1032         int ring_offsets_idx; /* just used for verification */
1033         uint32_t gfx9_fence_offset;
1034         struct radeon_winsys_bo *gfx9_fence_bo;
1035         uint32_t gfx9_fence_idx;
1036
1037         /**
1038          * Whether a query pool has been resetted and we have to flush caches.
1039          */
1040         bool pending_reset_query;
1041 };
1042
1043 struct radv_image;
1044
1045 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1046
1047 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1048 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1049
1050 void cik_create_gfx_config(struct radv_device *device);
1051
1052 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
1053                        int count, const VkViewport *viewports);
1054 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
1055                        int count, const VkRect2D *scissors,
1056                        const VkViewport *viewports, bool can_use_guardband);
1057 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1058                                    bool instanced_draw, bool indirect_draw,
1059                                    uint32_t draw_vertex_count);
1060 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
1061                                 bool predicated,
1062                                 enum chip_class chip_class,
1063                                 bool is_mec,
1064                                 unsigned event, unsigned event_flags,
1065                                 unsigned data_sel,
1066                                 uint64_t va,
1067                                 uint32_t old_fence,
1068                                 uint32_t new_fence);
1069
1070 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1071                         bool predicated,
1072                         uint64_t va, uint32_t ref,
1073                         uint32_t mask);
1074 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1075                             enum chip_class chip_class,
1076                             uint32_t *fence_ptr, uint64_t va,
1077                             bool is_mec,
1078                             enum radv_cmd_flush_bits flush_bits);
1079 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1080 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1081 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1082                            uint64_t src_va, uint64_t dest_va,
1083                            uint64_t size);
1084 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1085                         unsigned size);
1086 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1087                             uint64_t size, unsigned value);
1088 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1089 bool
1090 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1091                              unsigned size,
1092                              unsigned alignment,
1093                              unsigned *out_offset,
1094                              void **ptr);
1095 void
1096 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1097                             const struct radv_subpass *subpass,
1098                             bool transitions);
1099 bool
1100 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1101                             unsigned size, unsigned alignmnet,
1102                             const void *data, unsigned *out_offset);
1103
1104 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1105 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1106 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1107 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1108 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1109 unsigned radv_cayman_get_maxdist(int log_samples);
1110 void radv_device_init_msaa(struct radv_device *device);
1111 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1112                                struct radv_image *image,
1113                                VkClearDepthStencilValue ds_clear_value,
1114                                VkImageAspectFlags aspects);
1115 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1116                                struct radv_image *image,
1117                                int idx,
1118                                uint32_t color_values[2]);
1119 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1120                                        struct radv_image *image,
1121                                        bool value);
1122 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1123                           struct radeon_winsys_bo *bo,
1124                           uint64_t offset, uint64_t size, uint32_t value);
1125 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1126 bool radv_get_memory_fd(struct radv_device *device,
1127                         struct radv_device_memory *memory,
1128                         int *pFD);
1129
1130 static inline struct radv_descriptor_state *
1131 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1132                            VkPipelineBindPoint bind_point)
1133 {
1134         assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1135                bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1136         return &cmd_buffer->descriptors[bind_point];
1137 }
1138
1139 /*
1140  * Takes x,y,z as exact numbers of invocations, instead of blocks.
1141  *
1142  * Limitations: Can't call normal dispatch functions without binding or rebinding
1143  *              the compute pipeline.
1144  */
1145 void radv_unaligned_dispatch(
1146         struct radv_cmd_buffer                      *cmd_buffer,
1147         uint32_t                                    x,
1148         uint32_t                                    y,
1149         uint32_t                                    z);
1150
1151 struct radv_event {
1152         struct radeon_winsys_bo *bo;
1153         uint64_t *map;
1154 };
1155
1156 struct radv_shader_module;
1157
1158 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1159 #define RADV_HASH_SHADER_SISCHED             (1 << 1)
1160 #define RADV_HASH_SHADER_UNSAFE_MATH         (1 << 2)
1161 void
1162 radv_hash_shaders(unsigned char *hash,
1163                   const VkPipelineShaderStageCreateInfo **stages,
1164                   const struct radv_pipeline_layout *layout,
1165                   const struct radv_pipeline_key *key,
1166                   uint32_t flags);
1167
1168 static inline gl_shader_stage
1169 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1170 {
1171         assert(__builtin_popcount(vk_stage) == 1);
1172         return ffs(vk_stage) - 1;
1173 }
1174
1175 static inline VkShaderStageFlagBits
1176 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1177 {
1178         return (1 << mesa_stage);
1179 }
1180
1181 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1182
1183 #define radv_foreach_stage(stage, stage_bits)                           \
1184         for (gl_shader_stage stage,                                     \
1185                      __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1186              stage = __builtin_ffs(__tmp) - 1, __tmp;                   \
1187              __tmp &= ~(1 << (stage)))
1188
1189 unsigned radv_format_meta_fs_key(VkFormat format);
1190
1191 struct radv_multisample_state {
1192         uint32_t db_eqaa;
1193         uint32_t pa_sc_line_cntl;
1194         uint32_t pa_sc_mode_cntl_0;
1195         uint32_t pa_sc_mode_cntl_1;
1196         uint32_t pa_sc_aa_config;
1197         uint32_t pa_sc_aa_mask[2];
1198         unsigned num_samples;
1199 };
1200
1201 struct radv_prim_vertex_count {
1202         uint8_t min;
1203         uint8_t incr;
1204 };
1205
1206 struct radv_vertex_elements_info {
1207         uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1208         uint32_t format_size[MAX_VERTEX_ATTRIBS];
1209         uint32_t binding[MAX_VERTEX_ATTRIBS];
1210         uint32_t offset[MAX_VERTEX_ATTRIBS];
1211         uint32_t count;
1212 };
1213
1214 struct radv_ia_multi_vgt_param_helpers {
1215         uint32_t base;
1216         bool partial_es_wave;
1217         uint8_t primgroup_size;
1218         bool wd_switch_on_eop;
1219         bool ia_switch_on_eoi;
1220         bool partial_vs_wave;
1221 };
1222
1223 #define SI_GS_PER_ES 128
1224
1225 struct radv_pipeline {
1226         struct radv_device *                          device;
1227         struct radv_dynamic_state                     dynamic_state;
1228
1229         struct radv_pipeline_layout *                 layout;
1230
1231         bool                                         need_indirect_descriptor_sets;
1232         struct radv_shader_variant *                 shaders[MESA_SHADER_STAGES];
1233         struct radv_shader_variant *gs_copy_shader;
1234         VkShaderStageFlags                           active_stages;
1235
1236         struct radeon_winsys_cs                      cs;
1237
1238         struct radv_vertex_elements_info             vertex_elements;
1239
1240         uint32_t                                     binding_stride[MAX_VBS];
1241
1242         uint32_t user_data_0[MESA_SHADER_STAGES];
1243         union {
1244                 struct {
1245                         struct radv_multisample_state ms;
1246                         uint32_t spi_baryc_cntl;
1247                         bool prim_restart_enable;
1248                         unsigned esgs_ring_size;
1249                         unsigned gsvs_ring_size;
1250                         uint32_t vtx_base_sgpr;
1251                         struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1252                         uint8_t vtx_emit_num;
1253                         struct radv_prim_vertex_count prim_vertex_count;
1254                         bool can_use_guardband;
1255                         uint32_t needed_dynamic_state;
1256                         bool disable_out_of_order_rast_for_occlusion;
1257
1258                         /* Used for rbplus */
1259                         uint32_t col_format;
1260                         uint32_t cb_target_mask;
1261                 } graphics;
1262         };
1263
1264         unsigned max_waves;
1265         unsigned scratch_bytes_per_wave;
1266 };
1267
1268 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1269 {
1270         return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1271 }
1272
1273 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1274 {
1275         return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1276 }
1277
1278 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1279                                                  gl_shader_stage stage,
1280                                                  int idx);
1281
1282 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1283
1284 struct radv_graphics_pipeline_create_info {
1285         bool use_rectlist;
1286         bool db_depth_clear;
1287         bool db_stencil_clear;
1288         bool db_depth_disable_expclear;
1289         bool db_stencil_disable_expclear;
1290         bool db_flush_depth_inplace;
1291         bool db_flush_stencil_inplace;
1292         bool db_resummarize;
1293         uint32_t custom_blend_mode;
1294 };
1295
1296 VkResult
1297 radv_graphics_pipeline_create(VkDevice device,
1298                               VkPipelineCache cache,
1299                               const VkGraphicsPipelineCreateInfo *pCreateInfo,
1300                               const struct radv_graphics_pipeline_create_info *extra,
1301                               const VkAllocationCallbacks *alloc,
1302                               VkPipeline *pPipeline);
1303
1304 struct vk_format_description;
1305 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1306                                           int first_non_void);
1307 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1308                                          int first_non_void);
1309 uint32_t radv_translate_colorformat(VkFormat format);
1310 uint32_t radv_translate_color_numformat(VkFormat format,
1311                                         const struct vk_format_description *desc,
1312                                         int first_non_void);
1313 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1314 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1315 uint32_t radv_translate_dbformat(VkFormat format);
1316 uint32_t radv_translate_tex_dataformat(VkFormat format,
1317                                        const struct vk_format_description *desc,
1318                                        int first_non_void);
1319 uint32_t radv_translate_tex_numformat(VkFormat format,
1320                                       const struct vk_format_description *desc,
1321                                       int first_non_void);
1322 bool radv_format_pack_clear_color(VkFormat format,
1323                                   uint32_t clear_vals[2],
1324                                   VkClearColorValue *value);
1325 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1326 bool radv_dcc_formats_compatible(VkFormat format1,
1327                                  VkFormat format2);
1328
1329 struct radv_fmask_info {
1330         uint64_t offset;
1331         uint64_t size;
1332         unsigned alignment;
1333         unsigned pitch_in_pixels;
1334         unsigned bank_height;
1335         unsigned slice_tile_max;
1336         unsigned tile_mode_index;
1337         unsigned tile_swizzle;
1338 };
1339
1340 struct radv_cmask_info {
1341         uint64_t offset;
1342         uint64_t size;
1343         unsigned alignment;
1344         unsigned slice_tile_max;
1345 };
1346
1347 struct radv_image {
1348         VkImageType type;
1349         /* The original VkFormat provided by the client.  This may not match any
1350          * of the actual surface formats.
1351          */
1352         VkFormat vk_format;
1353         VkImageAspectFlags aspects;
1354         VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1355         struct ac_surf_info info;
1356         VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1357         VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1358
1359         VkDeviceSize size;
1360         uint32_t alignment;
1361
1362         unsigned queue_family_mask;
1363         bool exclusive;
1364         bool shareable;
1365
1366         /* Set when bound */
1367         struct radeon_winsys_bo *bo;
1368         VkDeviceSize offset;
1369         uint64_t dcc_offset;
1370         uint64_t htile_offset;
1371         bool tc_compatible_htile;
1372         struct radeon_surf surface;
1373
1374         struct radv_fmask_info fmask;
1375         struct radv_cmask_info cmask;
1376         uint64_t clear_value_offset;
1377         uint64_t dcc_pred_offset;
1378
1379         /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1380         VkDeviceMemory owned_memory;
1381 };
1382
1383 /* Whether the image has a htile that is known consistent with the contents of
1384  * the image. */
1385 bool radv_layout_has_htile(const struct radv_image *image,
1386                            VkImageLayout layout,
1387                            unsigned queue_mask);
1388
1389 /* Whether the image has a htile  that is known consistent with the contents of
1390  * the image and is allowed to be in compressed form.
1391  *
1392  * If this is false reads that don't use the htile should be able to return
1393  * correct results.
1394  */
1395 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1396                                      VkImageLayout layout,
1397                                      unsigned queue_mask);
1398
1399 bool radv_layout_can_fast_clear(const struct radv_image *image,
1400                                 VkImageLayout layout,
1401                                 unsigned queue_mask);
1402
1403 bool radv_layout_dcc_compressed(const struct radv_image *image,
1404                                 VkImageLayout layout,
1405                                 unsigned queue_mask);
1406
1407 /**
1408  * Return whether the image has CMASK metadata for color surfaces.
1409  */
1410 static inline bool
1411 radv_image_has_cmask(const struct radv_image *image)
1412 {
1413         return image->cmask.size;
1414 }
1415
1416 /**
1417  * Return whether the image has FMASK metadata for color surfaces.
1418  */
1419 static inline bool
1420 radv_image_has_fmask(const struct radv_image *image)
1421 {
1422         return image->fmask.size;
1423 }
1424
1425 /**
1426  * Return whether the image has DCC metadata for color surfaces.
1427  */
1428 static inline bool
1429 radv_image_has_dcc(const struct radv_image *image)
1430 {
1431         return image->surface.dcc_size;
1432 }
1433
1434 /**
1435  * Return whether DCC metadata is enabled for a level.
1436  */
1437 static inline bool
1438 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1439 {
1440         return radv_image_has_dcc(image) &&
1441                level < image->surface.num_dcc_levels;
1442 }
1443
1444 /**
1445  * Return whether the image has HTILE metadata for depth surfaces.
1446  */
1447 static inline bool
1448 radv_image_has_htile(const struct radv_image *image)
1449 {
1450         return image->surface.htile_size;
1451 }
1452
1453 /**
1454  * Return whether HTILE metadata is enabled for a level.
1455  */
1456 static inline bool
1457 radv_htile_enabled(const struct radv_image *image, unsigned level)
1458 {
1459         return radv_image_has_htile(image) && level == 0;
1460 }
1461
1462 /**
1463  * Return whether the image is TC-compatible HTILE.
1464  */
1465 static inline bool
1466 radv_image_is_tc_compat_htile(const struct radv_image *image)
1467 {
1468         return radv_image_has_htile(image) && image->tc_compatible_htile;
1469 }
1470
1471 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1472
1473 static inline uint32_t
1474 radv_get_layerCount(const struct radv_image *image,
1475                     const VkImageSubresourceRange *range)
1476 {
1477         return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1478                 image->info.array_size - range->baseArrayLayer : range->layerCount;
1479 }
1480
1481 static inline uint32_t
1482 radv_get_levelCount(const struct radv_image *image,
1483                     const VkImageSubresourceRange *range)
1484 {
1485         return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1486                 image->info.levels - range->baseMipLevel : range->levelCount;
1487 }
1488
1489 struct radeon_bo_metadata;
1490 void
1491 radv_init_metadata(struct radv_device *device,
1492                    struct radv_image *image,
1493                    struct radeon_bo_metadata *metadata);
1494
1495 struct radv_image_view {
1496         struct radv_image *image; /**< VkImageViewCreateInfo::image */
1497         struct radeon_winsys_bo *bo;
1498
1499         VkImageViewType type;
1500         VkImageAspectFlags aspect_mask;
1501         VkFormat vk_format;
1502         uint32_t base_layer;
1503         uint32_t layer_count;
1504         uint32_t base_mip;
1505         uint32_t level_count;
1506         VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1507
1508         uint32_t descriptor[16];
1509
1510         /* Descriptor for use as a storage image as opposed to a sampled image.
1511          * This has a few differences for cube maps (e.g. type).
1512          */
1513         uint32_t storage_descriptor[16];
1514 };
1515
1516 struct radv_image_create_info {
1517         const VkImageCreateInfo *vk_info;
1518         bool scanout;
1519         bool no_metadata_planes;
1520 };
1521
1522 VkResult radv_image_create(VkDevice _device,
1523                            const struct radv_image_create_info *info,
1524                            const VkAllocationCallbacks* alloc,
1525                            VkImage *pImage);
1526
1527 VkResult
1528 radv_image_from_gralloc(VkDevice device_h,
1529                        const VkImageCreateInfo *base_info,
1530                        const VkNativeBufferANDROID *gralloc_info,
1531                        const VkAllocationCallbacks *alloc,
1532                        VkImage *out_image_h);
1533
1534 void radv_image_view_init(struct radv_image_view *view,
1535                           struct radv_device *device,
1536                           const VkImageViewCreateInfo* pCreateInfo);
1537
1538 struct radv_buffer_view {
1539         struct radeon_winsys_bo *bo;
1540         VkFormat vk_format;
1541         uint64_t range; /**< VkBufferViewCreateInfo::range */
1542         uint32_t state[4];
1543 };
1544 void radv_buffer_view_init(struct radv_buffer_view *view,
1545                            struct radv_device *device,
1546                            const VkBufferViewCreateInfo* pCreateInfo);
1547
1548 static inline struct VkExtent3D
1549 radv_sanitize_image_extent(const VkImageType imageType,
1550                            const struct VkExtent3D imageExtent)
1551 {
1552         switch (imageType) {
1553         case VK_IMAGE_TYPE_1D:
1554                 return (VkExtent3D) { imageExtent.width, 1, 1 };
1555         case VK_IMAGE_TYPE_2D:
1556                 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1557         case VK_IMAGE_TYPE_3D:
1558                 return imageExtent;
1559         default:
1560                 unreachable("invalid image type");
1561         }
1562 }
1563
1564 static inline struct VkOffset3D
1565 radv_sanitize_image_offset(const VkImageType imageType,
1566                            const struct VkOffset3D imageOffset)
1567 {
1568         switch (imageType) {
1569         case VK_IMAGE_TYPE_1D:
1570                 return (VkOffset3D) { imageOffset.x, 0, 0 };
1571         case VK_IMAGE_TYPE_2D:
1572                 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1573         case VK_IMAGE_TYPE_3D:
1574                 return imageOffset;
1575         default:
1576                 unreachable("invalid image type");
1577         }
1578 }
1579
1580 static inline bool
1581 radv_image_extent_compare(const struct radv_image *image,
1582                           const VkExtent3D *extent)
1583 {
1584         if (extent->width != image->info.width ||
1585             extent->height != image->info.height ||
1586             extent->depth != image->info.depth)
1587                 return false;
1588         return true;
1589 }
1590
1591 struct radv_sampler {
1592         uint32_t state[4];
1593 };
1594
1595 struct radv_color_buffer_info {
1596         uint64_t cb_color_base;
1597         uint64_t cb_color_cmask;
1598         uint64_t cb_color_fmask;
1599         uint64_t cb_dcc_base;
1600         uint32_t cb_color_pitch;
1601         uint32_t cb_color_slice;
1602         uint32_t cb_color_view;
1603         uint32_t cb_color_info;
1604         uint32_t cb_color_attrib;
1605         uint32_t cb_color_attrib2;
1606         uint32_t cb_dcc_control;
1607         uint32_t cb_color_cmask_slice;
1608         uint32_t cb_color_fmask_slice;
1609 };
1610
1611 struct radv_ds_buffer_info {
1612         uint64_t db_z_read_base;
1613         uint64_t db_stencil_read_base;
1614         uint64_t db_z_write_base;
1615         uint64_t db_stencil_write_base;
1616         uint64_t db_htile_data_base;
1617         uint32_t db_depth_info;
1618         uint32_t db_z_info;
1619         uint32_t db_stencil_info;
1620         uint32_t db_depth_view;
1621         uint32_t db_depth_size;
1622         uint32_t db_depth_slice;
1623         uint32_t db_htile_surface;
1624         uint32_t pa_su_poly_offset_db_fmt_cntl;
1625         uint32_t db_z_info2;
1626         uint32_t db_stencil_info2;
1627         float offset_scale;
1628 };
1629
1630 struct radv_attachment_info {
1631         union {
1632                 struct radv_color_buffer_info cb;
1633                 struct radv_ds_buffer_info ds;
1634         };
1635         struct radv_image_view *attachment;
1636 };
1637
1638 struct radv_framebuffer {
1639         uint32_t                                     width;
1640         uint32_t                                     height;
1641         uint32_t                                     layers;
1642
1643         uint32_t                                     attachment_count;
1644         struct radv_attachment_info                  attachments[0];
1645 };
1646
1647 struct radv_subpass_barrier {
1648         VkPipelineStageFlags src_stage_mask;
1649         VkAccessFlags        src_access_mask;
1650         VkAccessFlags        dst_access_mask;
1651 };
1652
1653 struct radv_subpass {
1654         uint32_t                                     input_count;
1655         uint32_t                                     color_count;
1656         VkAttachmentReference *                      input_attachments;
1657         VkAttachmentReference *                      color_attachments;
1658         VkAttachmentReference *                      resolve_attachments;
1659         VkAttachmentReference                        depth_stencil_attachment;
1660
1661         /** Subpass has at least one resolve attachment */
1662         bool                                         has_resolve;
1663
1664         struct radv_subpass_barrier                  start_barrier;
1665
1666         uint32_t                                     view_mask;
1667         VkSampleCountFlagBits                        max_sample_count;
1668 };
1669
1670 struct radv_render_pass_attachment {
1671         VkFormat                                     format;
1672         uint32_t                                     samples;
1673         VkAttachmentLoadOp                           load_op;
1674         VkAttachmentLoadOp                           stencil_load_op;
1675         VkImageLayout                                initial_layout;
1676         VkImageLayout                                final_layout;
1677         uint32_t                                     view_mask;
1678 };
1679
1680 struct radv_render_pass {
1681         uint32_t                                     attachment_count;
1682         uint32_t                                     subpass_count;
1683         VkAttachmentReference *                      subpass_attachments;
1684         struct radv_render_pass_attachment *         attachments;
1685         struct radv_subpass_barrier                  end_barrier;
1686         struct radv_subpass                          subpasses[0];
1687 };
1688
1689 VkResult radv_device_init_meta(struct radv_device *device);
1690 void radv_device_finish_meta(struct radv_device *device);
1691
1692 struct radv_query_pool {
1693         struct radeon_winsys_bo *bo;
1694         uint32_t stride;
1695         uint32_t availability_offset;
1696         uint64_t size;
1697         char *ptr;
1698         VkQueryType type;
1699         uint32_t pipeline_stats_mask;
1700 };
1701
1702 struct radv_semaphore {
1703         /* use a winsys sem for non-exportable */
1704         struct radeon_winsys_sem *sem;
1705         uint32_t syncobj;
1706         uint32_t temp_syncobj;
1707 };
1708
1709 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1710                              int num_wait_sems,
1711                              const VkSemaphore *wait_sems,
1712                              int num_signal_sems,
1713                              const VkSemaphore *signal_sems,
1714                              VkFence fence);
1715 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1716
1717 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1718                              VkPipelineBindPoint bind_point,
1719                              struct radv_descriptor_set *set,
1720                              unsigned idx);
1721
1722 void
1723 radv_update_descriptor_sets(struct radv_device *device,
1724                             struct radv_cmd_buffer *cmd_buffer,
1725                             VkDescriptorSet overrideSet,
1726                             uint32_t descriptorWriteCount,
1727                             const VkWriteDescriptorSet *pDescriptorWrites,
1728                             uint32_t descriptorCopyCount,
1729                             const VkCopyDescriptorSet *pDescriptorCopies);
1730
1731 void
1732 radv_update_descriptor_set_with_template(struct radv_device *device,
1733                                          struct radv_cmd_buffer *cmd_buffer,
1734                                          struct radv_descriptor_set *set,
1735                                          VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1736                                          const void *pData);
1737
1738 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1739                                    VkPipelineBindPoint pipelineBindPoint,
1740                                    VkPipelineLayout _layout,
1741                                    uint32_t set,
1742                                    uint32_t descriptorWriteCount,
1743                                    const VkWriteDescriptorSet *pDescriptorWrites);
1744
1745 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1746                          struct radv_image *image, uint32_t value);
1747
1748 struct radv_fence {
1749         struct radeon_winsys_fence *fence;
1750         bool submitted;
1751         bool signalled;
1752
1753         uint32_t syncobj;
1754         uint32_t temp_syncobj;
1755 };
1756
1757 /* radv_nir_to_llvm.c */
1758 struct radv_shader_variant_info;
1759 struct radv_nir_compiler_options;
1760
1761 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
1762                                  struct nir_shader *geom_shader,
1763                                  struct ac_shader_binary *binary,
1764                                  struct ac_shader_config *config,
1765                                  struct radv_shader_variant_info *shader_info,
1766                                  const struct radv_nir_compiler_options *option);
1767
1768 void radv_compile_nir_shader(LLVMTargetMachineRef tm,
1769                              struct ac_shader_binary *binary,
1770                              struct ac_shader_config *config,
1771                              struct radv_shader_variant_info *shader_info,
1772                              struct nir_shader *const *nir,
1773                              int nir_count,
1774                              const struct radv_nir_compiler_options *options);
1775
1776 /* radv_shader_info.h */
1777 struct radv_shader_info;
1778
1779 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1780                                const struct radv_nir_compiler_options *options,
1781                                struct radv_shader_info *info);
1782
1783 struct radeon_winsys_sem;
1784
1785 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType)         \
1786                                                                 \
1787         static inline struct __radv_type *                      \
1788         __radv_type ## _from_handle(__VkType _handle)           \
1789         {                                                       \
1790                 return (struct __radv_type *) _handle;          \
1791         }                                                       \
1792                                                                 \
1793         static inline __VkType                                  \
1794         __radv_type ## _to_handle(struct __radv_type *_obj)     \
1795         {                                                       \
1796                 return (__VkType) _obj;                         \
1797         }
1798
1799 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType)         \
1800                                                                         \
1801         static inline struct __radv_type *                              \
1802         __radv_type ## _from_handle(__VkType _handle)                   \
1803         {                                                               \
1804                 return (struct __radv_type *)(uintptr_t) _handle;       \
1805         }                                                               \
1806                                                                         \
1807         static inline __VkType                                          \
1808         __radv_type ## _to_handle(struct __radv_type *_obj)             \
1809         {                                                               \
1810                 return (__VkType)(uintptr_t) _obj;                      \
1811         }
1812
1813 #define RADV_FROM_HANDLE(__radv_type, __name, __handle)                 \
1814         struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1815
1816 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1817 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1818 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1819 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1820 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1821
1822 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1823 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1824 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1825 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1826 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1827 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1828 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1829 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1830 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1831 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1832 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1833 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1834 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1835 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1836 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1837 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1838 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1839 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1840 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1841 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1842 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1843
1844 #endif /* RADV_PRIVATE_H */