src/amd/vulkan/radv_private.h

   1 /*
   2  * Copyright © 2016 Red Hat.
   3  * Copyright © 2016 Bas Nieuwenhuizen
   4  *
   5  * based in part on anv driver which is:
   6  * Copyright © 2015 Intel Corporation
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  25  * IN THE SOFTWARE.
  26  */
  27
  28 #ifndef RADV_PRIVATE_H
  29 #define RADV_PRIVATE_H
  30
  31 #include <stdlib.h>
  32 #include <stdio.h>
  33 #include <stdbool.h>
  34 #include <pthread.h>
  35 #include <assert.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #ifdef HAVE_VALGRIND
  39 #include <valgrind.h>
  40 #include <memcheck.h>
  41 #define VG(x) x
  42 #else
  43 #define VG(x)
  44 #endif
  45
  46 #include <amdgpu.h>
  47 #include "compiler/shader_enums.h"
  48 #include "util/macros.h"
  49 #include "util/list.h"
  50 #include "main/macros.h"
  51 #include "vk_alloc.h"
  52 #include "vk_debug_report.h"
  53
  54 #include "radv_radeon_winsys.h"
  55 #include "ac_binary.h"
  56 #include "ac_nir_to_llvm.h"
  57 #include "ac_gpu_info.h"
  58 #include "ac_surface.h"
  59 #include "radv_descriptor_set.h"
  60 #include "radv_extensions.h"
  61
  62 #include <llvm-c/TargetMachine.h>
  63
  64 /* Pre-declarations needed for WSI entrypoints */
  65 struct wl_surface;
  66 struct wl_display;
  67 typedef struct xcb_connection_t xcb_connection_t;
  68 typedef uint32_t xcb_visualid_t;
  69 typedef uint32_t xcb_window_t;
  70
  71 #include <vulkan/vulkan.h>
  72 #include <vulkan/vulkan_intel.h>
  73 #include <vulkan/vk_icd.h>
  74 #include <vulkan/vk_android_native_buffer.h>
  75
  76 #include "radv_entrypoints.h"
  77
  78 #include "wsi_common.h"
  79
  80 #define ATI_VENDOR_ID 0x1002
  81
  82 #define MAX_VBS         32
  83 #define MAX_VERTEX_ATTRIBS 32
  84 #define MAX_RTS          8
  85 #define MAX_VIEWPORTS   16
  86 #define MAX_SCISSORS    16
  87 #define MAX_DISCARD_RECTANGLES 4
  88 #define MAX_PUSH_CONSTANTS_SIZE 128
  89 #define MAX_PUSH_DESCRIPTORS 32
  90 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
  91 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
  92 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
  93 #define MAX_SAMPLES_LOG2 4
  94 #define NUM_META_FS_KEYS 13
  95 #define RADV_MAX_DRM_DEVICES 8
  96 #define MAX_VIEWS        8
  97
  98 #define NUM_DEPTH_CLEAR_PIPELINES 3
  99
 100 /*
 101  * This is the point we switch from using CP to compute shader
 102  * for certain buffer operations.
 103  */
 104 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
 105
 106 enum radv_mem_heap {
 107         RADV_MEM_HEAP_VRAM,
 108         RADV_MEM_HEAP_VRAM_CPU_ACCESS,
 109         RADV_MEM_HEAP_GTT,
 110         RADV_MEM_HEAP_COUNT
 111 };
 112
 113 enum radv_mem_type {
 114         RADV_MEM_TYPE_VRAM,
 115         RADV_MEM_TYPE_GTT_WRITE_COMBINE,
 116         RADV_MEM_TYPE_VRAM_CPU_ACCESS,
 117         RADV_MEM_TYPE_GTT_CACHED,
 118         RADV_MEM_TYPE_COUNT
 119 };
 120
 121 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
 122
 123 static inline uint32_t
 124 align_u32(uint32_t v, uint32_t a)
 125 {
 126         assert(a != 0 && a == (a & -a));
 127         return (v + a - 1) & ~(a - 1);
 128 }
 129
 130 static inline uint32_t
 131 align_u32_npot(uint32_t v, uint32_t a)
 132 {
 133         return (v + a - 1) / a * a;
 134 }
 135
 136 static inline uint64_t
 137 align_u64(uint64_t v, uint64_t a)
 138 {
 139         assert(a != 0 && a == (a & -a));
 140         return (v + a - 1) & ~(a - 1);
 141 }
 142
 143 static inline int32_t
 144 align_i32(int32_t v, int32_t a)
 145 {
 146         assert(a != 0 && a == (a & -a));
 147         return (v + a - 1) & ~(a - 1);
 148 }
 149
 150 /** Alignment must be a power of 2. */
 151 static inline bool
 152 radv_is_aligned(uintmax_t n, uintmax_t a)
 153 {
 154         assert(a == (a & -a));
 155         return (n & (a - 1)) == 0;
 156 }
 157
 158 static inline uint32_t
 159 round_up_u32(uint32_t v, uint32_t a)
 160 {
 161         return (v + a - 1) / a;
 162 }
 163
 164 static inline uint64_t
 165 round_up_u64(uint64_t v, uint64_t a)
 166 {
 167         return (v + a - 1) / a;
 168 }
 169
 170 static inline uint32_t
 171 radv_minify(uint32_t n, uint32_t levels)
 172 {
 173         if (unlikely(n == 0))
 174                 return 0;
 175         else
 176                 return MAX2(n >> levels, 1);
 177 }
 178 static inline float
 179 radv_clamp_f(float f, float min, float max)
 180 {
 181         assert(min < max);
 182
 183         if (f > max)
 184                 return max;
 185         else if (f < min)
 186                 return min;
 187         else
 188                 return f;
 189 }
 190
 191 static inline bool
 192 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
 193 {
 194         if (*inout_mask & clear_mask) {
 195                 *inout_mask &= ~clear_mask;
 196                 return true;
 197         } else {
 198                 return false;
 199         }
 200 }
 201
 202 #define for_each_bit(b, dword)                          \
 203         for (uint32_t __dword = (dword);                \
 204              (b) = __builtin_ffs(__dword) - 1, __dword; \
 205              __dword &= ~(1 << (b)))
 206
 207 #define typed_memcpy(dest, src, count) ({                               \
 208                         STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
 209                         memcpy((dest), (src), (count) * sizeof(*(src))); \
 210                 })
 211
 212 /* Whenever we generate an error, pass it through this function. Useful for
 213  * debugging, where we can break on it. Only call at error site, not when
 214  * propagating errors. Might be useful to plug in a stack trace here.
 215  */
 216
 217 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
 218
 219 #ifdef DEBUG
 220 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
 221 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
 222 #else
 223 #define vk_error(error) error
 224 #define vk_errorf(error, format, ...) error
 225 #endif
 226
 227 void __radv_finishme(const char *file, int line, const char *format, ...)
 228         radv_printflike(3, 4);
 229 void radv_loge(const char *format, ...) radv_printflike(1, 2);
 230 void radv_loge_v(const char *format, va_list va);
 231
 232 /**
 233  * Print a FINISHME message, including its source location.
 234  */
 235 #define radv_finishme(format, ...)                                      \
 236         do { \
 237                 static bool reported = false; \
 238                 if (!reported) { \
 239                         __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
 240                         reported = true; \
 241                 } \
 242         } while (0)
 243
 244 /* A non-fatal assert.  Useful for debugging. */
 245 #ifdef DEBUG
 246 #define radv_assert(x) ({                                               \
 247                         if (unlikely(!(x)))                             \
 248                                 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
 249                 })
 250 #else
 251 #define radv_assert(x)
 252 #endif
 253
 254 #define stub_return(v)                                  \
 255         do {                                            \
 256                 radv_finishme("stub %s", __func__);     \
 257                 return (v);                             \
 258         } while (0)
 259
 260 #define stub()                                          \
 261         do {                                            \
 262                 radv_finishme("stub %s", __func__);     \
 263                 return;                                 \
 264         } while (0)
 265
 266 void *radv_lookup_entrypoint_unchecked(const char *name);
 267 void *radv_lookup_entrypoint_checked(const char *name,
 268                                     uint32_t core_version,
 269                                     const struct radv_instance_extension_table *instance,
 270                                     const struct radv_device_extension_table *device);
 271
 272 struct radv_physical_device {
 273         VK_LOADER_DATA                              _loader_data;
 274
 275         struct radv_instance *                       instance;
 276
 277         struct radeon_winsys *ws;
 278         struct radeon_info rad_info;
 279         char                                        path[20];
 280         char                                        name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
 281         uint8_t                                     driver_uuid[VK_UUID_SIZE];
 282         uint8_t                                     device_uuid[VK_UUID_SIZE];
 283         uint8_t                                     cache_uuid[VK_UUID_SIZE];
 284
 285         int local_fd;
 286         struct wsi_device                       wsi_device;
 287
 288         bool has_rbplus; /* if RB+ register exist */
 289         bool rbplus_allowed; /* if RB+ is allowed */
 290         bool has_clear_state;
 291         bool cpdma_prefetch_writes_memory;
 292         bool has_scissor_bug;
 293
 294         /* This is the drivers on-disk cache used as a fallback as opposed to
 295          * the pipeline cache defined by apps.
 296          */
 297         struct disk_cache *                          disk_cache;
 298
 299         VkPhysicalDeviceMemoryProperties memory_properties;
 300         enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
 301
 302         struct radv_device_extension_table supported_extensions;
 303 };
 304
 305 struct radv_instance {
 306         VK_LOADER_DATA                              _loader_data;
 307
 308         VkAllocationCallbacks                       alloc;
 309
 310         uint32_t                                    apiVersion;
 311         int                                         physicalDeviceCount;
 312         struct radv_physical_device                 physicalDevices[RADV_MAX_DRM_DEVICES];
 313
 314         uint64_t debug_flags;
 315         uint64_t perftest_flags;
 316
 317         struct vk_debug_report_instance             debug_report_callbacks;
 318
 319         struct radv_instance_extension_table enabled_extensions;
 320 };
 321
 322 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
 323 void radv_finish_wsi(struct radv_physical_device *physical_device);
 324
 325 bool radv_instance_extension_supported(const char *name);
 326 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
 327 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
 328                                               const char *name);
 329
 330 struct cache_entry;
 331
 332 struct radv_pipeline_cache {
 333         struct radv_device *                          device;
 334         pthread_mutex_t                              mutex;
 335
 336         uint32_t                                     total_size;
 337         uint32_t                                     table_size;
 338         uint32_t                                     kernel_count;
 339         struct cache_entry **                        hash_table;
 340         bool                                         modified;
 341
 342         VkAllocationCallbacks                        alloc;
 343 };
 344
 345 struct radv_pipeline_key {
 346         uint32_t instance_rate_inputs;
 347         unsigned tess_input_vertices;
 348         uint32_t col_format;
 349         uint32_t is_int8;
 350         uint32_t is_int10;
 351         uint8_t log2_ps_iter_samples;
 352         uint8_t log2_num_samples;
 353         uint32_t multisample : 1;
 354         uint32_t has_multiview_view_index : 1;
 355 };
 356
 357 void
 358 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
 359                          struct radv_device *device);
 360 void
 361 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
 362 void
 363 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
 364                          const void *data, size_t size);
 365
 366 struct radv_shader_variant;
 367
 368 bool
 369 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
 370                                                 struct radv_pipeline_cache *cache,
 371                                                 const unsigned char *sha1,
 372                                                 struct radv_shader_variant **variants);
 373
 374 void
 375 radv_pipeline_cache_insert_shaders(struct radv_device *device,
 376                                    struct radv_pipeline_cache *cache,
 377                                    const unsigned char *sha1,
 378                                    struct radv_shader_variant **variants,
 379                                    const void *const *codes,
 380                                    const unsigned *code_sizes);
 381
 382 enum radv_blit_ds_layout {
 383         RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
 384         RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
 385         RADV_BLIT_DS_LAYOUT_COUNT,
 386 };
 387
 388 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
 389 {
 390         return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
 391 }
 392
 393 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
 394 {
 395         return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
 396 }
 397
 398 enum radv_meta_dst_layout {
 399         RADV_META_DST_LAYOUT_GENERAL,
 400         RADV_META_DST_LAYOUT_OPTIMAL,
 401         RADV_META_DST_LAYOUT_COUNT,
 402 };
 403
 404 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
 405 {
 406         return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
 407 }
 408
 409 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
 410 {
 411         return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
 412 }
 413
 414 struct radv_meta_state {
 415         VkAllocationCallbacks alloc;
 416
 417         struct radv_pipeline_cache cache;
 418
 419         /**
 420          * Use array element `i` for images with `2^i` samples.
 421          */
 422         struct {
 423                 VkRenderPass render_pass[NUM_META_FS_KEYS];
 424                 VkPipeline color_pipelines[NUM_META_FS_KEYS];
 425
 426                 VkRenderPass depthstencil_rp;
 427                 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 428                 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 429                 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
 430         } clear[1 + MAX_SAMPLES_LOG2];
 431
 432         VkPipelineLayout                          clear_color_p_layout;
 433         VkPipelineLayout                          clear_depth_p_layout;
 434         struct {
 435                 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
 436
 437                 /** Pipeline that blits from a 1D image. */
 438                 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
 439
 440                 /** Pipeline that blits from a 2D image. */
 441                 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
 442
 443                 /** Pipeline that blits from a 3D image. */
 444                 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
 445
 446                 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
 447                 VkPipeline depth_only_1d_pipeline;
 448                 VkPipeline depth_only_2d_pipeline;
 449                 VkPipeline depth_only_3d_pipeline;
 450
 451                 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
 452                 VkPipeline stencil_only_1d_pipeline;
 453                 VkPipeline stencil_only_2d_pipeline;
 454                 VkPipeline stencil_only_3d_pipeline;
 455                 VkPipelineLayout                          pipeline_layout;
 456                 VkDescriptorSetLayout                     ds_layout;
 457         } blit;
 458
 459         struct {
 460                 VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
 461
 462                 VkPipelineLayout p_layouts[3];
 463                 VkDescriptorSetLayout ds_layouts[3];
 464                 VkPipeline pipelines[3][NUM_META_FS_KEYS];
 465
 466                 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
 467                 VkPipeline depth_only_pipeline[3];
 468
 469                 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
 470                 VkPipeline stencil_only_pipeline[3];
 471         } blit2d;
 472
 473         struct {
 474                 VkPipelineLayout                          img_p_layout;
 475                 VkDescriptorSetLayout                     img_ds_layout;
 476                 VkPipeline pipeline;
 477                 VkPipeline pipeline_3d;
 478         } itob;
 479         struct {
 480                 VkPipelineLayout                          img_p_layout;
 481                 VkDescriptorSetLayout                     img_ds_layout;
 482                 VkPipeline pipeline;
 483                 VkPipeline pipeline_3d;
 484         } btoi;
 485         struct {
 486                 VkPipelineLayout                          img_p_layout;
 487                 VkDescriptorSetLayout                     img_ds_layout;
 488                 VkPipeline pipeline;
 489                 VkPipeline pipeline_3d;
 490         } itoi;
 491         struct {
 492                 VkPipelineLayout                          img_p_layout;
 493                 VkDescriptorSetLayout                     img_ds_layout;
 494                 VkPipeline pipeline;
 495                 VkPipeline pipeline_3d;
 496         } cleari;
 497
 498         struct {
 499                 VkPipelineLayout                          p_layout;
 500                 VkPipeline                                pipeline[NUM_META_FS_KEYS];
 501                 VkRenderPass                              pass[NUM_META_FS_KEYS];
 502         } resolve;
 503
 504         struct {
 505                 VkDescriptorSetLayout                     ds_layout;
 506                 VkPipelineLayout                          p_layout;
 507                 struct {
 508                         VkPipeline                                pipeline;
 509                         VkPipeline                                i_pipeline;
 510                         VkPipeline                                srgb_pipeline;
 511                 } rc[MAX_SAMPLES_LOG2];
 512         } resolve_compute;
 513
 514         struct {
 515                 VkDescriptorSetLayout                     ds_layout;
 516                 VkPipelineLayout                          p_layout;
 517
 518                 struct {
 519                         VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
 520                         VkPipeline   pipeline[NUM_META_FS_KEYS];
 521                 } rc[MAX_SAMPLES_LOG2];
 522         } resolve_fragment;
 523
 524         struct {
 525                 VkPipelineLayout                          p_layout;
 526                 VkPipeline                                decompress_pipeline;
 527                 VkPipeline                                resummarize_pipeline;
 528                 VkRenderPass                              pass;
 529         } depth_decomp[1 + MAX_SAMPLES_LOG2];
 530
 531         struct {
 532                 VkPipelineLayout                          p_layout;
 533                 VkPipeline                                cmask_eliminate_pipeline;
 534                 VkPipeline                                fmask_decompress_pipeline;
 535                 VkPipeline                                dcc_decompress_pipeline;
 536                 VkRenderPass                              pass;
 537
 538                 VkDescriptorSetLayout                     dcc_decompress_compute_ds_layout;
 539                 VkPipelineLayout                          dcc_decompress_compute_p_layout;
 540                 VkPipeline                                dcc_decompress_compute_pipeline;
 541         } fast_clear_flush;
 542
 543         struct {
 544                 VkPipelineLayout fill_p_layout;
 545                 VkPipelineLayout copy_p_layout;
 546                 VkDescriptorSetLayout fill_ds_layout;
 547                 VkDescriptorSetLayout copy_ds_layout;
 548                 VkPipeline fill_pipeline;
 549                 VkPipeline copy_pipeline;
 550         } buffer;
 551
 552         struct {
 553                 VkDescriptorSetLayout ds_layout;
 554                 VkPipelineLayout p_layout;
 555                 VkPipeline occlusion_query_pipeline;
 556                 VkPipeline pipeline_statistics_query_pipeline;
 557         } query;
 558 };
 559
 560 /* queue types */
 561 #define RADV_QUEUE_GENERAL 0
 562 #define RADV_QUEUE_COMPUTE 1
 563 #define RADV_QUEUE_TRANSFER 2
 564
 565 #define RADV_MAX_QUEUE_FAMILIES 3
 566
 567 enum ring_type radv_queue_family_to_ring(int f);
 568
 569 struct radv_queue {
 570         VK_LOADER_DATA                              _loader_data;
 571         struct radv_device *                         device;
 572         struct radeon_winsys_ctx                    *hw_ctx;
 573         enum radeon_ctx_priority                     priority;
 574         uint32_t queue_family_index;
 575         int queue_idx;
 576
 577         uint32_t scratch_size;
 578         uint32_t compute_scratch_size;
 579         uint32_t esgs_ring_size;
 580         uint32_t gsvs_ring_size;
 581         bool has_tess_rings;
 582         bool has_sample_positions;
 583
 584         struct radeon_winsys_bo *scratch_bo;
 585         struct radeon_winsys_bo *descriptor_bo;
 586         struct radeon_winsys_bo *compute_scratch_bo;
 587         struct radeon_winsys_bo *esgs_ring_bo;
 588         struct radeon_winsys_bo *gsvs_ring_bo;
 589         struct radeon_winsys_bo *tess_rings_bo;
 590         struct radeon_winsys_cs *initial_preamble_cs;
 591         struct radeon_winsys_cs *initial_full_flush_preamble_cs;
 592         struct radeon_winsys_cs *continue_preamble_cs;
 593 };
 594
 595 struct radv_device {
 596         VK_LOADER_DATA                              _loader_data;
 597
 598         VkAllocationCallbacks                       alloc;
 599
 600         struct radv_instance *                       instance;
 601         struct radeon_winsys *ws;
 602
 603         struct radv_meta_state                       meta_state;
 604
 605         struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
 606         int queue_count[RADV_MAX_QUEUE_FAMILIES];
 607         struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
 608
 609         bool always_use_syncobj;
 610         bool llvm_supports_spill;
 611         bool has_distributed_tess;
 612         bool pbb_allowed;
 613         bool dfsm_allowed;
 614         uint32_t tess_offchip_block_dw_size;
 615         uint32_t scratch_waves;
 616         uint32_t dispatch_initiator;
 617
 618         uint32_t gs_table_depth;
 619
 620         /* MSAA sample locations.
 621          * The first index is the sample index.
 622          * The second index is the coordinate: X, Y. */
 623         float sample_locations_1x[1][2];
 624         float sample_locations_2x[2][2];
 625         float sample_locations_4x[4][2];
 626         float sample_locations_8x[8][2];
 627         float sample_locations_16x[16][2];
 628
 629         /* CIK and later */
 630         uint32_t gfx_init_size_dw;
 631         struct radeon_winsys_bo                      *gfx_init;
 632
 633         struct radeon_winsys_bo                      *trace_bo;
 634         uint32_t                                     *trace_id_ptr;
 635
 636         /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
 637         bool                                         keep_shader_info;
 638
 639         struct radv_physical_device                  *physical_device;
 640
 641         /* Backup in-memory cache to be used if the app doesn't provide one */
 642         struct radv_pipeline_cache *                mem_cache;
 643
 644         /*
 645          * use different counters so MSAA MRTs get consecutive surface indices,
 646          * even if MASK is allocated in between.
 647          */
 648         uint32_t image_mrt_offset_counter;
 649         uint32_t fmask_mrt_offset_counter;
 650         struct list_head shader_slabs;
 651         mtx_t shader_slab_mutex;
 652
 653         /* For detecting VM faults reported by dmesg. */
 654         uint64_t dmesg_timestamp;
 655
 656         struct radv_device_extension_table enabled_extensions;
 657 };
 658
 659 struct radv_device_memory {
 660         struct radeon_winsys_bo                      *bo;
 661         /* for dedicated allocations */
 662         struct radv_image                            *image;
 663         struct radv_buffer                           *buffer;
 664         uint32_t                                     type_index;
 665         VkDeviceSize                                 map_size;
 666         void *                                       map;
 667         void *                                       user_ptr;
 668 };
 669
 670
 671 struct radv_descriptor_range {
 672         uint64_t va;
 673         uint32_t size;
 674 };
 675
 676 struct radv_descriptor_set {
 677         const struct radv_descriptor_set_layout *layout;
 678         uint32_t size;
 679
 680         struct radeon_winsys_bo *bo;
 681         uint64_t va;
 682         uint32_t *mapped_ptr;
 683         struct radv_descriptor_range *dynamic_descriptors;
 684
 685         struct radeon_winsys_bo *descriptors[0];
 686 };
 687
 688 struct radv_push_descriptor_set
 689 {
 690         struct radv_descriptor_set set;
 691         uint32_t capacity;
 692 };
 693
 694 struct radv_descriptor_pool_entry {
 695         uint32_t offset;
 696         uint32_t size;
 697         struct radv_descriptor_set *set;
 698 };
 699
 700 struct radv_descriptor_pool {
 701         struct radeon_winsys_bo *bo;
 702         uint8_t *mapped_ptr;
 703         uint64_t current_offset;
 704         uint64_t size;
 705
 706         uint8_t *host_memory_base;
 707         uint8_t *host_memory_ptr;
 708         uint8_t *host_memory_end;
 709
 710         uint32_t entry_count;
 711         uint32_t max_entry_count;
 712         struct radv_descriptor_pool_entry entries[0];
 713 };
 714
 715 struct radv_descriptor_update_template_entry {
 716         VkDescriptorType descriptor_type;
 717
 718         /* The number of descriptors to update */
 719         uint32_t descriptor_count;
 720
 721         /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
 722         uint32_t dst_offset;
 723
 724         /* In dwords. Not valid/used for dynamic descriptors */
 725         uint32_t dst_stride;
 726
 727         uint32_t buffer_offset;
 728
 729         /* Only valid for combined image samplers and samplers */
 730         uint16_t has_sampler;
 731
 732         /* In bytes */
 733         size_t src_offset;
 734         size_t src_stride;
 735
 736         /* For push descriptors */
 737         const uint32_t *immutable_samplers;
 738 };
 739
 740 struct radv_descriptor_update_template {
 741         uint32_t entry_count;
 742         VkPipelineBindPoint bind_point;
 743         struct radv_descriptor_update_template_entry entry[0];
 744 };
 745
 746 struct radv_buffer {
 747         VkDeviceSize                                 size;
 748
 749         VkBufferUsageFlags                           usage;
 750         VkBufferCreateFlags                          flags;
 751
 752         /* Set when bound */
 753         struct radeon_winsys_bo *                      bo;
 754         VkDeviceSize                                 offset;
 755
 756         bool shareable;
 757 };
 758
 759 enum radv_dynamic_state_bits {
 760         RADV_DYNAMIC_VIEWPORT             = 1 << 0,
 761         RADV_DYNAMIC_SCISSOR              = 1 << 1,
 762         RADV_DYNAMIC_LINE_WIDTH           = 1 << 2,
 763         RADV_DYNAMIC_DEPTH_BIAS           = 1 << 3,
 764         RADV_DYNAMIC_BLEND_CONSTANTS      = 1 << 4,
 765         RADV_DYNAMIC_DEPTH_BOUNDS         = 1 << 5,
 766         RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
 767         RADV_DYNAMIC_STENCIL_WRITE_MASK   = 1 << 7,
 768         RADV_DYNAMIC_STENCIL_REFERENCE    = 1 << 8,
 769         RADV_DYNAMIC_DISCARD_RECTANGLE    = 1 << 9,
 770         RADV_DYNAMIC_ALL                  = (1 << 10) - 1,
 771 };
 772
 773 enum radv_cmd_dirty_bits {
 774         /* Keep the dynamic state dirty bits in sync with
 775          * enum radv_dynamic_state_bits */
 776         RADV_CMD_DIRTY_DYNAMIC_VIEWPORT                  = 1 << 0,
 777         RADV_CMD_DIRTY_DYNAMIC_SCISSOR                   = 1 << 1,
 778         RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH                = 1 << 2,
 779         RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS                = 1 << 3,
 780         RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS           = 1 << 4,
 781         RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS              = 1 << 5,
 782         RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK      = 1 << 6,
 783         RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK        = 1 << 7,
 784         RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE         = 1 << 8,
 785         RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE         = 1 << 9,
 786         RADV_CMD_DIRTY_DYNAMIC_ALL                       = (1 << 10) - 1,
 787         RADV_CMD_DIRTY_PIPELINE                          = 1 << 10,
 788         RADV_CMD_DIRTY_INDEX_BUFFER                      = 1 << 11,
 789         RADV_CMD_DIRTY_FRAMEBUFFER                       = 1 << 12,
 790         RADV_CMD_DIRTY_VERTEX_BUFFER                     = 1 << 13,
 791 };
 792
 793 enum radv_cmd_flush_bits {
 794         RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
 795         /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
 796         RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
 797         /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
 798         RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
 799         /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
 800         RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
 801         /* Same as above, but only writes back and doesn't invalidate */
 802         RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
 803         /* Framebuffer caches */
 804         RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
 805         RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
 806         RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
 807         RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
 808         /* Engine synchronization. */
 809         RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
 810         RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
 811         RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
 812         RADV_CMD_FLAG_VGT_FLUSH        = 1 << 12,
 813
 814         RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
 815                                               RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
 816                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB |
 817                                               RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
 818 };
 819
 820 struct radv_vertex_binding {
 821         struct radv_buffer *                          buffer;
 822         VkDeviceSize                                 offset;
 823 };
 824
 825 struct radv_viewport_state {
 826         uint32_t                                          count;
 827         VkViewport                                        viewports[MAX_VIEWPORTS];
 828 };
 829
 830 struct radv_scissor_state {
 831         uint32_t                                          count;
 832         VkRect2D                                          scissors[MAX_SCISSORS];
 833 };
 834
 835 struct radv_discard_rectangle_state {
 836         uint32_t                                          count;
 837         VkRect2D                                          rectangles[MAX_DISCARD_RECTANGLES];
 838 };
 839
 840 struct radv_dynamic_state {
 841         /**
 842          * Bitmask of (1 << VK_DYNAMIC_STATE_*).
 843          * Defines the set of saved dynamic state.
 844          */
 845         uint32_t mask;
 846
 847         struct radv_viewport_state                        viewport;
 848
 849         struct radv_scissor_state                         scissor;
 850
 851         float                                        line_width;
 852
 853         struct {
 854                 float                                     bias;
 855                 float                                     clamp;
 856                 float                                     slope;
 857         } depth_bias;
 858
 859         float                                        blend_constants[4];
 860
 861         struct {
 862                 float                                     min;
 863                 float                                     max;
 864         } depth_bounds;
 865
 866         struct {
 867                 uint32_t                                  front;
 868                 uint32_t                                  back;
 869         } stencil_compare_mask;
 870
 871         struct {
 872                 uint32_t                                  front;
 873                 uint32_t                                  back;
 874         } stencil_write_mask;
 875
 876         struct {
 877                 uint32_t                                  front;
 878                 uint32_t                                  back;
 879         } stencil_reference;
 880
 881         struct radv_discard_rectangle_state               discard_rectangle;
 882 };
 883
 884 extern const struct radv_dynamic_state default_dynamic_state;
 885
 886 const char *
 887 radv_get_debug_option_name(int id);
 888
 889 const char *
 890 radv_get_perftest_option_name(int id);
 891
 892 /**
 893  * Attachment state when recording a renderpass instance.
 894  *
 895  * The clear value is valid only if there exists a pending clear.
 896  */
 897 struct radv_attachment_state {
 898         VkImageAspectFlags                           pending_clear_aspects;
 899         uint32_t                                     cleared_views;
 900         VkClearValue                                 clear_value;
 901         VkImageLayout                                current_layout;
 902 };
 903
 904 struct radv_descriptor_state {
 905         struct radv_descriptor_set *sets[MAX_SETS];
 906         uint32_t dirty;
 907         uint32_t valid;
 908         struct radv_push_descriptor_set push_set;
 909         bool push_dirty;
 910 };
 911
 912 struct radv_cmd_state {
 913         /* Vertex descriptors */
 914         bool                                          vb_prefetch_dirty;
 915         uint64_t                                      vb_va;
 916         unsigned                                      vb_size;
 917
 918         bool predicating;
 919         uint32_t                                      dirty;
 920
 921         struct radv_pipeline *                        pipeline;
 922         struct radv_pipeline *                        emitted_pipeline;
 923         struct radv_pipeline *                        compute_pipeline;
 924         struct radv_pipeline *                        emitted_compute_pipeline;
 925         struct radv_framebuffer *                     framebuffer;
 926         struct radv_render_pass *                     pass;
 927         const struct radv_subpass *                         subpass;
 928         struct radv_dynamic_state                     dynamic;
 929         struct radv_attachment_state *                attachments;
 930         VkRect2D                                     render_area;
 931
 932         /* Index buffer */
 933         struct radv_buffer                           *index_buffer;
 934         uint64_t                                     index_offset;
 935         uint32_t                                     index_type;
 936         uint32_t                                     max_index_count;
 937         uint64_t                                     index_va;
 938         int32_t                                      last_index_type;
 939
 940         int32_t                                      last_primitive_reset_en;
 941         uint32_t                                     last_primitive_reset_index;
 942         enum radv_cmd_flush_bits                     flush_bits;
 943         unsigned                                     active_occlusion_queries;
 944         float                                        offset_scale;
 945         uint32_t                                      trace_id;
 946         uint32_t                                      last_ia_multi_vgt_param;
 947
 948         uint32_t last_num_instances;
 949         uint32_t last_first_instance;
 950         uint32_t last_vertex_offset;
 951 };
 952
 953 struct radv_cmd_pool {
 954         VkAllocationCallbacks                        alloc;
 955         struct list_head                             cmd_buffers;
 956         struct list_head                             free_cmd_buffers;
 957         uint32_t queue_family_index;
 958 };
 959
 960 struct radv_cmd_buffer_upload {
 961         uint8_t *map;
 962         unsigned offset;
 963         uint64_t size;
 964         struct radeon_winsys_bo *upload_bo;
 965         struct list_head list;
 966 };
 967
 968 enum radv_cmd_buffer_status {
 969         RADV_CMD_BUFFER_STATUS_INVALID,
 970         RADV_CMD_BUFFER_STATUS_INITIAL,
 971         RADV_CMD_BUFFER_STATUS_RECORDING,
 972         RADV_CMD_BUFFER_STATUS_EXECUTABLE,
 973         RADV_CMD_BUFFER_STATUS_PENDING,
 974 };
 975
 976 struct radv_cmd_buffer {
 977         VK_LOADER_DATA                               _loader_data;
 978
 979         struct radv_device *                          device;
 980
 981         struct radv_cmd_pool *                        pool;
 982         struct list_head                             pool_link;
 983
 984         VkCommandBufferUsageFlags                    usage_flags;
 985         VkCommandBufferLevel                         level;
 986         enum radv_cmd_buffer_status status;
 987         struct radeon_winsys_cs *cs;
 988         struct radv_cmd_state state;
 989         struct radv_vertex_binding                   vertex_bindings[MAX_VBS];
 990         uint32_t queue_family_index;
 991
 992         uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
 993         uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
 994         VkShaderStageFlags push_constant_stages;
 995         struct radv_descriptor_set meta_push_descriptors;
 996
 997         struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
 998
 999         struct radv_cmd_buffer_upload upload;
1000
1001         uint32_t scratch_size_needed;
1002         uint32_t compute_scratch_size_needed;
1003         uint32_t esgs_ring_size_needed;
1004         uint32_t gsvs_ring_size_needed;
1005         bool tess_rings_needed;
1006         bool sample_positions_needed;
1007
1008         VkResult record_result;
1009
1010         int ring_offsets_idx; /* just used for verification */
1011         uint32_t gfx9_fence_offset;
1012         struct radeon_winsys_bo *gfx9_fence_bo;
1013         uint32_t gfx9_fence_idx;
1014
1015         /**
1016          * Whether a query pool has been resetted and we have to flush caches.
1017          */
1018         bool pending_reset_query;
1019 };
1020
1021 struct radv_image;
1022
1023 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1024
1025 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1026 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1027
1028 void cik_create_gfx_config(struct radv_device *device);
1029
1030 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
1031                        int count, const VkViewport *viewports);
1032 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
1033                        int count, const VkRect2D *scissors,
1034                        const VkViewport *viewports, bool can_use_guardband);
1035 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1036                                    bool instanced_draw, bool indirect_draw,
1037                                    uint32_t draw_vertex_count);
1038 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
1039                                 bool predicated,
1040                                 enum chip_class chip_class,
1041                                 bool is_mec,
1042                                 unsigned event, unsigned event_flags,
1043                                 unsigned data_sel,
1044                                 uint64_t va,
1045                                 uint32_t old_fence,
1046                                 uint32_t new_fence);
1047
1048 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1049                         bool predicated,
1050                         uint64_t va, uint32_t ref,
1051                         uint32_t mask);
1052 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1053                             enum chip_class chip_class,
1054                             uint32_t *fence_ptr, uint64_t va,
1055                             bool is_mec,
1056                             enum radv_cmd_flush_bits flush_bits);
1057 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1058 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1059 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1060                            uint64_t src_va, uint64_t dest_va,
1061                            uint64_t size);
1062 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1063                         unsigned size);
1064 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1065                             uint64_t size, unsigned value);
1066 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1067 bool
1068 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1069                              unsigned size,
1070                              unsigned alignment,
1071                              unsigned *out_offset,
1072                              void **ptr);
1073 void
1074 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1075                             const struct radv_subpass *subpass,
1076                             bool transitions);
1077 bool
1078 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1079                             unsigned size, unsigned alignmnet,
1080                             const void *data, unsigned *out_offset);
1081
1082 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1083 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1084 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1085 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1086 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1087 unsigned radv_cayman_get_maxdist(int log_samples);
1088 void radv_device_init_msaa(struct radv_device *device);
1089 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1090                                struct radv_image *image,
1091                                VkClearDepthStencilValue ds_clear_value,
1092                                VkImageAspectFlags aspects);
1093 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1094                                struct radv_image *image,
1095                                int idx,
1096                                uint32_t color_values[2]);
1097 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1098                                        struct radv_image *image,
1099                                        bool value);
1100 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1101                           struct radeon_winsys_bo *bo,
1102                           uint64_t offset, uint64_t size, uint32_t value);
1103 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1104 bool radv_get_memory_fd(struct radv_device *device,
1105                         struct radv_device_memory *memory,
1106                         int *pFD);
1107
1108 static inline struct radv_descriptor_state *
1109 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1110                            VkPipelineBindPoint bind_point)
1111 {
1112         assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1113                bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1114         return &cmd_buffer->descriptors[bind_point];
1115 }
1116
1117 /*
1118  * Takes x,y,z as exact numbers of invocations, instead of blocks.
1119  *
1120  * Limitations: Can't call normal dispatch functions without binding or rebinding
1121  *              the compute pipeline.
1122  */
1123 void radv_unaligned_dispatch(
1124         struct radv_cmd_buffer                      *cmd_buffer,
1125         uint32_t                                    x,
1126         uint32_t                                    y,
1127         uint32_t                                    z);
1128
1129 struct radv_event {
1130         struct radeon_winsys_bo *bo;
1131         uint64_t *map;
1132 };
1133
1134 struct radv_shader_module;
1135
1136 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1137 #define RADV_HASH_SHADER_SISCHED             (1 << 1)
1138 #define RADV_HASH_SHADER_UNSAFE_MATH         (1 << 2)
1139 void
1140 radv_hash_shaders(unsigned char *hash,
1141                   const VkPipelineShaderStageCreateInfo **stages,
1142                   const struct radv_pipeline_layout *layout,
1143                   const struct radv_pipeline_key *key,
1144                   uint32_t flags);
1145
1146 static inline gl_shader_stage
1147 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1148 {
1149         assert(__builtin_popcount(vk_stage) == 1);
1150         return ffs(vk_stage) - 1;
1151 }
1152
1153 static inline VkShaderStageFlagBits
1154 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1155 {
1156         return (1 << mesa_stage);
1157 }
1158
1159 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1160
1161 #define radv_foreach_stage(stage, stage_bits)                           \
1162         for (gl_shader_stage stage,                                     \
1163                      __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1164              stage = __builtin_ffs(__tmp) - 1, __tmp;                   \
1165              __tmp &= ~(1 << (stage)))
1166
1167 unsigned radv_format_meta_fs_key(VkFormat format);
1168
1169 struct radv_multisample_state {
1170         uint32_t db_eqaa;
1171         uint32_t pa_sc_line_cntl;
1172         uint32_t pa_sc_mode_cntl_0;
1173         uint32_t pa_sc_mode_cntl_1;
1174         uint32_t pa_sc_aa_config;
1175         uint32_t pa_sc_aa_mask[2];
1176         unsigned num_samples;
1177 };
1178
1179 struct radv_prim_vertex_count {
1180         uint8_t min;
1181         uint8_t incr;
1182 };
1183
1184 struct radv_vertex_elements_info {
1185         uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1186         uint32_t format_size[MAX_VERTEX_ATTRIBS];
1187         uint32_t binding[MAX_VERTEX_ATTRIBS];
1188         uint32_t offset[MAX_VERTEX_ATTRIBS];
1189         uint32_t count;
1190 };
1191
1192 struct radv_ia_multi_vgt_param_helpers {
1193         uint32_t base;
1194         bool partial_es_wave;
1195         uint8_t primgroup_size;
1196         bool wd_switch_on_eop;
1197         bool ia_switch_on_eoi;
1198         bool partial_vs_wave;
1199 };
1200
1201 #define SI_GS_PER_ES 128
1202
1203 struct radv_pipeline {
1204         struct radv_device *                          device;
1205         struct radv_dynamic_state                     dynamic_state;
1206
1207         struct radv_pipeline_layout *                 layout;
1208
1209         bool                                         needs_data_cache;
1210         bool                                         need_indirect_descriptor_sets;
1211         struct radv_shader_variant *                 shaders[MESA_SHADER_STAGES];
1212         struct radv_shader_variant *gs_copy_shader;
1213         VkShaderStageFlags                           active_stages;
1214
1215         struct radeon_winsys_cs                      cs;
1216
1217         struct radv_vertex_elements_info             vertex_elements;
1218
1219         uint32_t                                     binding_stride[MAX_VBS];
1220
1221         uint32_t user_data_0[MESA_SHADER_STAGES];
1222         union {
1223                 struct {
1224                         struct radv_multisample_state ms;
1225                         uint32_t spi_baryc_cntl;
1226                         bool prim_restart_enable;
1227                         unsigned esgs_ring_size;
1228                         unsigned gsvs_ring_size;
1229                         uint32_t vtx_base_sgpr;
1230                         struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1231                         uint8_t vtx_emit_num;
1232                         struct radv_prim_vertex_count prim_vertex_count;
1233                         bool can_use_guardband;
1234                         uint32_t needed_dynamic_state;
1235                 } graphics;
1236         };
1237
1238         unsigned max_waves;
1239         unsigned scratch_bytes_per_wave;
1240 };
1241
1242 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1243 {
1244         return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1245 }
1246
1247 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1248 {
1249         return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1250 }
1251
1252 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1253                                                gl_shader_stage stage,
1254                                                int idx);
1255
1256 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1257
1258 struct radv_graphics_pipeline_create_info {
1259         bool use_rectlist;
1260         bool db_depth_clear;
1261         bool db_stencil_clear;
1262         bool db_depth_disable_expclear;
1263         bool db_stencil_disable_expclear;
1264         bool db_flush_depth_inplace;
1265         bool db_flush_stencil_inplace;
1266         bool db_resummarize;
1267         uint32_t custom_blend_mode;
1268 };
1269
1270 VkResult
1271 radv_graphics_pipeline_create(VkDevice device,
1272                               VkPipelineCache cache,
1273                               const VkGraphicsPipelineCreateInfo *pCreateInfo,
1274                               const struct radv_graphics_pipeline_create_info *extra,
1275                               const VkAllocationCallbacks *alloc,
1276                               VkPipeline *pPipeline);
1277
1278 struct vk_format_description;
1279 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1280                                           int first_non_void);
1281 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1282                                          int first_non_void);
1283 uint32_t radv_translate_colorformat(VkFormat format);
1284 uint32_t radv_translate_color_numformat(VkFormat format,
1285                                         const struct vk_format_description *desc,
1286                                         int first_non_void);
1287 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1288 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1289 uint32_t radv_translate_dbformat(VkFormat format);
1290 uint32_t radv_translate_tex_dataformat(VkFormat format,
1291                                        const struct vk_format_description *desc,
1292                                        int first_non_void);
1293 uint32_t radv_translate_tex_numformat(VkFormat format,
1294                                       const struct vk_format_description *desc,
1295                                       int first_non_void);
1296 bool radv_format_pack_clear_color(VkFormat format,
1297                                   uint32_t clear_vals[2],
1298                                   VkClearColorValue *value);
1299 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1300 bool radv_dcc_formats_compatible(VkFormat format1,
1301                                  VkFormat format2);
1302
1303 struct radv_fmask_info {
1304         uint64_t offset;
1305         uint64_t size;
1306         unsigned alignment;
1307         unsigned pitch_in_pixels;
1308         unsigned bank_height;
1309         unsigned slice_tile_max;
1310         unsigned tile_mode_index;
1311         unsigned tile_swizzle;
1312 };
1313
1314 struct radv_cmask_info {
1315         uint64_t offset;
1316         uint64_t size;
1317         unsigned alignment;
1318         unsigned slice_tile_max;
1319 };
1320
1321 struct radv_image {
1322         VkImageType type;
1323         /* The original VkFormat provided by the client.  This may not match any
1324          * of the actual surface formats.
1325          */
1326         VkFormat vk_format;
1327         VkImageAspectFlags aspects;
1328         VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1329         struct ac_surf_info info;
1330         VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1331         VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1332
1333         VkDeviceSize size;
1334         uint32_t alignment;
1335
1336         unsigned queue_family_mask;
1337         bool exclusive;
1338         bool shareable;
1339
1340         /* Set when bound */
1341         struct radeon_winsys_bo *bo;
1342         VkDeviceSize offset;
1343         uint64_t dcc_offset;
1344         uint64_t htile_offset;
1345         bool tc_compatible_htile;
1346         struct radeon_surf surface;
1347
1348         struct radv_fmask_info fmask;
1349         struct radv_cmask_info cmask;
1350         uint64_t clear_value_offset;
1351         uint64_t dcc_pred_offset;
1352
1353         /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1354         VkDeviceMemory owned_memory;
1355 };
1356
1357 /* Whether the image has a htile that is known consistent with the contents of
1358  * the image. */
1359 bool radv_layout_has_htile(const struct radv_image *image,
1360                            VkImageLayout layout,
1361                            unsigned queue_mask);
1362
1363 /* Whether the image has a htile  that is known consistent with the contents of
1364  * the image and is allowed to be in compressed form.
1365  *
1366  * If this is false reads that don't use the htile should be able to return
1367  * correct results.
1368  */
1369 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1370                                      VkImageLayout layout,
1371                                      unsigned queue_mask);
1372
1373 bool radv_layout_can_fast_clear(const struct radv_image *image,
1374                                 VkImageLayout layout,
1375                                 unsigned queue_mask);
1376
1377 bool radv_layout_dcc_compressed(const struct radv_image *image,
1378                                 VkImageLayout layout,
1379                                 unsigned queue_mask);
1380
1381 static inline bool
1382 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1383 {
1384         return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1385 }
1386
1387 static inline bool
1388 radv_htile_enabled(const struct radv_image *image, unsigned level)
1389 {
1390         return image->surface.htile_size && level == 0;
1391 }
1392
1393 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1394
1395 static inline uint32_t
1396 radv_get_layerCount(const struct radv_image *image,
1397                     const VkImageSubresourceRange *range)
1398 {
1399         return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1400                 image->info.array_size - range->baseArrayLayer : range->layerCount;
1401 }
1402
1403 static inline uint32_t
1404 radv_get_levelCount(const struct radv_image *image,
1405                     const VkImageSubresourceRange *range)
1406 {
1407         return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1408                 image->info.levels - range->baseMipLevel : range->levelCount;
1409 }
1410
1411 struct radeon_bo_metadata;
1412 void
1413 radv_init_metadata(struct radv_device *device,
1414                    struct radv_image *image,
1415                    struct radeon_bo_metadata *metadata);
1416
1417 struct radv_image_view {
1418         struct radv_image *image; /**< VkImageViewCreateInfo::image */
1419         struct radeon_winsys_bo *bo;
1420
1421         VkImageViewType type;
1422         VkImageAspectFlags aspect_mask;
1423         VkFormat vk_format;
1424         uint32_t base_layer;
1425         uint32_t layer_count;
1426         uint32_t base_mip;
1427         uint32_t level_count;
1428         VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1429
1430         uint32_t descriptor[16];
1431
1432         /* Descriptor for use as a storage image as opposed to a sampled image.
1433          * This has a few differences for cube maps (e.g. type).
1434          */
1435         uint32_t storage_descriptor[16];
1436 };
1437
1438 struct radv_image_create_info {
1439         const VkImageCreateInfo *vk_info;
1440         bool scanout;
1441         bool no_metadata_planes;
1442 };
1443
1444 VkResult radv_image_create(VkDevice _device,
1445                            const struct radv_image_create_info *info,
1446                            const VkAllocationCallbacks* alloc,
1447                            VkImage *pImage);
1448
1449 VkResult
1450 radv_image_from_gralloc(VkDevice device_h,
1451                        const VkImageCreateInfo *base_info,
1452                        const VkNativeBufferANDROID *gralloc_info,
1453                        const VkAllocationCallbacks *alloc,
1454                        VkImage *out_image_h);
1455
1456 void radv_image_view_init(struct radv_image_view *view,
1457                           struct radv_device *device,
1458                           const VkImageViewCreateInfo* pCreateInfo);
1459
1460 struct radv_buffer_view {
1461         struct radeon_winsys_bo *bo;
1462         VkFormat vk_format;
1463         uint64_t range; /**< VkBufferViewCreateInfo::range */
1464         uint32_t state[4];
1465 };
1466 void radv_buffer_view_init(struct radv_buffer_view *view,
1467                            struct radv_device *device,
1468                            const VkBufferViewCreateInfo* pCreateInfo);
1469
1470 static inline struct VkExtent3D
1471 radv_sanitize_image_extent(const VkImageType imageType,
1472                            const struct VkExtent3D imageExtent)
1473 {
1474         switch (imageType) {
1475         case VK_IMAGE_TYPE_1D:
1476                 return (VkExtent3D) { imageExtent.width, 1, 1 };
1477         case VK_IMAGE_TYPE_2D:
1478                 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1479         case VK_IMAGE_TYPE_3D:
1480                 return imageExtent;
1481         default:
1482                 unreachable("invalid image type");
1483         }
1484 }
1485
1486 static inline struct VkOffset3D
1487 radv_sanitize_image_offset(const VkImageType imageType,
1488                            const struct VkOffset3D imageOffset)
1489 {
1490         switch (imageType) {
1491         case VK_IMAGE_TYPE_1D:
1492                 return (VkOffset3D) { imageOffset.x, 0, 0 };
1493         case VK_IMAGE_TYPE_2D:
1494                 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1495         case VK_IMAGE_TYPE_3D:
1496                 return imageOffset;
1497         default:
1498                 unreachable("invalid image type");
1499         }
1500 }
1501
1502 static inline bool
1503 radv_image_extent_compare(const struct radv_image *image,
1504                           const VkExtent3D *extent)
1505 {
1506         if (extent->width != image->info.width ||
1507             extent->height != image->info.height ||
1508             extent->depth != image->info.depth)
1509                 return false;
1510         return true;
1511 }
1512
1513 struct radv_sampler {
1514         uint32_t state[4];
1515 };
1516
1517 struct radv_color_buffer_info {
1518         uint64_t cb_color_base;
1519         uint64_t cb_color_cmask;
1520         uint64_t cb_color_fmask;
1521         uint64_t cb_dcc_base;
1522         uint32_t cb_color_pitch;
1523         uint32_t cb_color_slice;
1524         uint32_t cb_color_view;
1525         uint32_t cb_color_info;
1526         uint32_t cb_color_attrib;
1527         uint32_t cb_color_attrib2;
1528         uint32_t cb_dcc_control;
1529         uint32_t cb_color_cmask_slice;
1530         uint32_t cb_color_fmask_slice;
1531 };
1532
1533 struct radv_ds_buffer_info {
1534         uint64_t db_z_read_base;
1535         uint64_t db_stencil_read_base;
1536         uint64_t db_z_write_base;
1537         uint64_t db_stencil_write_base;
1538         uint64_t db_htile_data_base;
1539         uint32_t db_depth_info;
1540         uint32_t db_z_info;
1541         uint32_t db_stencil_info;
1542         uint32_t db_depth_view;
1543         uint32_t db_depth_size;
1544         uint32_t db_depth_slice;
1545         uint32_t db_htile_surface;
1546         uint32_t pa_su_poly_offset_db_fmt_cntl;
1547         uint32_t db_z_info2;
1548         uint32_t db_stencil_info2;
1549         float offset_scale;
1550 };
1551
1552 struct radv_attachment_info {
1553         union {
1554                 struct radv_color_buffer_info cb;
1555                 struct radv_ds_buffer_info ds;
1556         };
1557         struct radv_image_view *attachment;
1558 };
1559
1560 struct radv_framebuffer {
1561         uint32_t                                     width;
1562         uint32_t                                     height;
1563         uint32_t                                     layers;
1564
1565         uint32_t                                     attachment_count;
1566         struct radv_attachment_info                  attachments[0];
1567 };
1568
1569 struct radv_subpass_barrier {
1570         VkPipelineStageFlags src_stage_mask;
1571         VkAccessFlags        src_access_mask;
1572         VkAccessFlags        dst_access_mask;
1573 };
1574
1575 struct radv_subpass {
1576         uint32_t                                     input_count;
1577         uint32_t                                     color_count;
1578         VkAttachmentReference *                      input_attachments;
1579         VkAttachmentReference *                      color_attachments;
1580         VkAttachmentReference *                      resolve_attachments;
1581         VkAttachmentReference                        depth_stencil_attachment;
1582
1583         /** Subpass has at least one resolve attachment */
1584         bool                                         has_resolve;
1585
1586         struct radv_subpass_barrier                  start_barrier;
1587
1588         uint32_t                                     view_mask;
1589 };
1590
1591 struct radv_render_pass_attachment {
1592         VkFormat                                     format;
1593         uint32_t                                     samples;
1594         VkAttachmentLoadOp                           load_op;
1595         VkAttachmentLoadOp                           stencil_load_op;
1596         VkImageLayout                                initial_layout;
1597         VkImageLayout                                final_layout;
1598         uint32_t                                     view_mask;
1599 };
1600
1601 struct radv_render_pass {
1602         uint32_t                                     attachment_count;
1603         uint32_t                                     subpass_count;
1604         VkAttachmentReference *                      subpass_attachments;
1605         struct radv_render_pass_attachment *         attachments;
1606         struct radv_subpass_barrier                  end_barrier;
1607         struct radv_subpass                          subpasses[0];
1608 };
1609
1610 VkResult radv_device_init_meta(struct radv_device *device);
1611 void radv_device_finish_meta(struct radv_device *device);
1612
1613 struct radv_query_pool {
1614         struct radeon_winsys_bo *bo;
1615         uint32_t stride;
1616         uint32_t availability_offset;
1617         uint64_t size;
1618         char *ptr;
1619         VkQueryType type;
1620         uint32_t pipeline_stats_mask;
1621 };
1622
1623 struct radv_semaphore {
1624         /* use a winsys sem for non-exportable */
1625         struct radeon_winsys_sem *sem;
1626         uint32_t syncobj;
1627         uint32_t temp_syncobj;
1628 };
1629
1630 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1631                              int num_wait_sems,
1632                              const VkSemaphore *wait_sems,
1633                              int num_signal_sems,
1634                              const VkSemaphore *signal_sems,
1635                              VkFence fence);
1636 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1637
1638 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1639                              VkPipelineBindPoint bind_point,
1640                              struct radv_descriptor_set *set,
1641                              unsigned idx);
1642
1643 void
1644 radv_update_descriptor_sets(struct radv_device *device,
1645                             struct radv_cmd_buffer *cmd_buffer,
1646                             VkDescriptorSet overrideSet,
1647                             uint32_t descriptorWriteCount,
1648                             const VkWriteDescriptorSet *pDescriptorWrites,
1649                             uint32_t descriptorCopyCount,
1650                             const VkCopyDescriptorSet *pDescriptorCopies);
1651
1652 void
1653 radv_update_descriptor_set_with_template(struct radv_device *device,
1654                                          struct radv_cmd_buffer *cmd_buffer,
1655                                          struct radv_descriptor_set *set,
1656                                          VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1657                                          const void *pData);
1658
1659 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1660                                    VkPipelineBindPoint pipelineBindPoint,
1661                                    VkPipelineLayout _layout,
1662                                    uint32_t set,
1663                                    uint32_t descriptorWriteCount,
1664                                    const VkWriteDescriptorSet *pDescriptorWrites);
1665
1666 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1667                            struct radv_image *image, uint32_t value);
1668 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1669                          struct radv_image *image, uint32_t value);
1670
1671 struct radv_fence {
1672         struct radeon_winsys_fence *fence;
1673         bool submitted;
1674         bool signalled;
1675
1676         uint32_t syncobj;
1677         uint32_t temp_syncobj;
1678 };
1679
1680 /* radv_nir_to_llvm.c */
1681 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
1682                                  struct nir_shader *geom_shader,
1683                                  struct ac_shader_binary *binary,
1684                                  struct ac_shader_config *config,
1685                                  struct ac_shader_variant_info *shader_info,
1686                                  const struct ac_nir_compiler_options *options,
1687                                  bool dump_shader);
1688
1689 void radv_compile_nir_shader(LLVMTargetMachineRef tm,
1690                              struct ac_shader_binary *binary,
1691                              struct ac_shader_config *config,
1692                              struct ac_shader_variant_info *shader_info,
1693                              struct nir_shader *const *nir,
1694                              int nir_count,
1695                              const struct ac_nir_compiler_options *options,
1696                              bool dump_shader);
1697
1698 struct radeon_winsys_sem;
1699
1700 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType)         \
1701                                                                 \
1702         static inline struct __radv_type *                      \
1703         __radv_type ## _from_handle(__VkType _handle)           \
1704         {                                                       \
1705                 return (struct __radv_type *) _handle;          \
1706         }                                                       \
1707                                                                 \
1708         static inline __VkType                                  \
1709         __radv_type ## _to_handle(struct __radv_type *_obj)     \
1710         {                                                       \
1711                 return (__VkType) _obj;                         \
1712         }
1713
1714 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType)         \
1715                                                                         \
1716         static inline struct __radv_type *                              \
1717         __radv_type ## _from_handle(__VkType _handle)                   \
1718         {                                                               \
1719                 return (struct __radv_type *)(uintptr_t) _handle;       \
1720         }                                                               \
1721                                                                         \
1722         static inline __VkType                                          \
1723         __radv_type ## _to_handle(struct __radv_type *_obj)             \
1724         {                                                               \
1725                 return (__VkType)(uintptr_t) _obj;                      \
1726         }
1727
1728 #define RADV_FROM_HANDLE(__radv_type, __name, __handle)                 \
1729         struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1730
1731 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1732 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1733 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1734 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1735 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1736
1737 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1738 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1739 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1740 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1741 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1742 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1743 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1744 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1745 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1746 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1747 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1748 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1749 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1750 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1751 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1752 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1753 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1754 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1755 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1756 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1757 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1758
1759 #endif /* RADV_PRIVATE_H */