2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
46 #include "c11/threads.h"
48 #include "compiler/shader_enums.h"
49 #include "util/macros.h"
50 #include "util/list.h"
51 #include "main/macros.h"
53 #include "vk_debug_report.h"
55 #include "radv_radeon_winsys.h"
56 #include "ac_binary.h"
57 #include "ac_nir_to_llvm.h"
58 #include "ac_gpu_info.h"
59 #include "ac_surface.h"
60 #include "radv_descriptor_set.h"
61 #include "radv_extensions.h"
63 #include <llvm-c/TargetMachine.h>
65 /* Pre-declarations needed for WSI entrypoints */
68 typedef struct xcb_connection_t xcb_connection_t;
69 typedef uint32_t xcb_visualid_t;
70 typedef uint32_t xcb_window_t;
72 #include <vulkan/vulkan.h>
73 #include <vulkan/vulkan_intel.h>
74 #include <vulkan/vk_icd.h>
75 #include <vulkan/vk_android_native_buffer.h>
77 #include "radv_entrypoints.h"
79 #include "wsi_common.h"
81 #define ATI_VENDOR_ID 0x1002
84 #define MAX_VERTEX_ATTRIBS 32
86 #define MAX_VIEWPORTS 16
87 #define MAX_SCISSORS 16
88 #define MAX_DISCARD_RECTANGLES 4
89 #define MAX_PUSH_CONSTANTS_SIZE 128
90 #define MAX_PUSH_DESCRIPTORS 32
91 #define MAX_DYNAMIC_UNIFORM_BUFFERS 16
92 #define MAX_DYNAMIC_STORAGE_BUFFERS 8
93 #define MAX_DYNAMIC_BUFFERS (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
94 #define MAX_SAMPLES_LOG2 4
95 #define NUM_META_FS_KEYS 13
96 #define RADV_MAX_DRM_DEVICES 8
99 #define NUM_DEPTH_CLEAR_PIPELINES 3
102 * This is the point we switch from using CP to compute shader
103 * for certain buffer operations.
105 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
109 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
116 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
117 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
118 RADV_MEM_TYPE_GTT_CACHED,
122 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
124 static inline uint32_t
125 align_u32(uint32_t v, uint32_t a)
127 assert(a != 0 && a == (a & -a));
128 return (v + a - 1) & ~(a - 1);
131 static inline uint32_t
132 align_u32_npot(uint32_t v, uint32_t a)
134 return (v + a - 1) / a * a;
137 static inline uint64_t
138 align_u64(uint64_t v, uint64_t a)
140 assert(a != 0 && a == (a & -a));
141 return (v + a - 1) & ~(a - 1);
144 static inline int32_t
145 align_i32(int32_t v, int32_t a)
147 assert(a != 0 && a == (a & -a));
148 return (v + a - 1) & ~(a - 1);
151 /** Alignment must be a power of 2. */
153 radv_is_aligned(uintmax_t n, uintmax_t a)
155 assert(a == (a & -a));
156 return (n & (a - 1)) == 0;
159 static inline uint32_t
160 round_up_u32(uint32_t v, uint32_t a)
162 return (v + a - 1) / a;
165 static inline uint64_t
166 round_up_u64(uint64_t v, uint64_t a)
168 return (v + a - 1) / a;
171 static inline uint32_t
172 radv_minify(uint32_t n, uint32_t levels)
174 if (unlikely(n == 0))
177 return MAX2(n >> levels, 1);
180 radv_clamp_f(float f, float min, float max)
193 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
195 if (*inout_mask & clear_mask) {
196 *inout_mask &= ~clear_mask;
203 #define for_each_bit(b, dword) \
204 for (uint32_t __dword = (dword); \
205 (b) = __builtin_ffs(__dword) - 1, __dword; \
206 __dword &= ~(1 << (b)))
208 #define typed_memcpy(dest, src, count) ({ \
209 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
210 memcpy((dest), (src), (count) * sizeof(*(src))); \
213 /* Whenever we generate an error, pass it through this function. Useful for
214 * debugging, where we can break on it. Only call at error site, not when
215 * propagating errors. Might be useful to plug in a stack trace here.
218 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
221 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
222 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
224 #define vk_error(error) error
225 #define vk_errorf(error, format, ...) error
228 void __radv_finishme(const char *file, int line, const char *format, ...)
229 radv_printflike(3, 4);
230 void radv_loge(const char *format, ...) radv_printflike(1, 2);
231 void radv_loge_v(const char *format, va_list va);
234 * Print a FINISHME message, including its source location.
236 #define radv_finishme(format, ...) \
238 static bool reported = false; \
240 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
245 /* A non-fatal assert. Useful for debugging. */
247 #define radv_assert(x) ({ \
248 if (unlikely(!(x))) \
249 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
252 #define radv_assert(x)
255 #define stub_return(v) \
257 radv_finishme("stub %s", __func__); \
263 radv_finishme("stub %s", __func__); \
267 void *radv_lookup_entrypoint_unchecked(const char *name);
268 void *radv_lookup_entrypoint_checked(const char *name,
269 uint32_t core_version,
270 const struct radv_instance_extension_table *instance,
271 const struct radv_device_extension_table *device);
273 struct radv_physical_device {
274 VK_LOADER_DATA _loader_data;
276 struct radv_instance * instance;
278 struct radeon_winsys *ws;
279 struct radeon_info rad_info;
281 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
282 uint8_t driver_uuid[VK_UUID_SIZE];
283 uint8_t device_uuid[VK_UUID_SIZE];
284 uint8_t cache_uuid[VK_UUID_SIZE];
287 struct wsi_device wsi_device;
289 bool has_rbplus; /* if RB+ register exist */
290 bool rbplus_allowed; /* if RB+ is allowed */
291 bool has_clear_state;
292 bool cpdma_prefetch_writes_memory;
293 bool has_scissor_bug;
295 bool has_out_of_order_rast;
296 bool out_of_order_rast_allowed;
298 /* Whether DCC should be enabled for MSAA textures. */
299 bool dcc_msaa_allowed;
301 /* This is the drivers on-disk cache used as a fallback as opposed to
302 * the pipeline cache defined by apps.
304 struct disk_cache * disk_cache;
306 VkPhysicalDeviceMemoryProperties memory_properties;
307 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
309 struct radv_device_extension_table supported_extensions;
312 struct radv_instance {
313 VK_LOADER_DATA _loader_data;
315 VkAllocationCallbacks alloc;
318 int physicalDeviceCount;
319 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
321 uint64_t debug_flags;
322 uint64_t perftest_flags;
324 struct vk_debug_report_instance debug_report_callbacks;
326 struct radv_instance_extension_table enabled_extensions;
329 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
330 void radv_finish_wsi(struct radv_physical_device *physical_device);
332 bool radv_instance_extension_supported(const char *name);
333 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
334 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
339 struct radv_pipeline_cache {
340 struct radv_device * device;
341 pthread_mutex_t mutex;
345 uint32_t kernel_count;
346 struct cache_entry ** hash_table;
349 VkAllocationCallbacks alloc;
352 struct radv_pipeline_key {
353 uint32_t instance_rate_inputs;
354 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
355 unsigned tess_input_vertices;
359 uint8_t log2_ps_iter_samples;
360 uint8_t log2_num_samples;
361 uint32_t multisample : 1;
362 uint32_t has_multiview_view_index : 1;
363 uint32_t optimisations_disabled : 1;
367 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
368 struct radv_device *device);
370 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
372 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
373 const void *data, size_t size);
375 struct radv_shader_variant;
378 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
379 struct radv_pipeline_cache *cache,
380 const unsigned char *sha1,
381 struct radv_shader_variant **variants);
384 radv_pipeline_cache_insert_shaders(struct radv_device *device,
385 struct radv_pipeline_cache *cache,
386 const unsigned char *sha1,
387 struct radv_shader_variant **variants,
388 const void *const *codes,
389 const unsigned *code_sizes);
391 enum radv_blit_ds_layout {
392 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
393 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
394 RADV_BLIT_DS_LAYOUT_COUNT,
397 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
399 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
402 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
404 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
407 enum radv_meta_dst_layout {
408 RADV_META_DST_LAYOUT_GENERAL,
409 RADV_META_DST_LAYOUT_OPTIMAL,
410 RADV_META_DST_LAYOUT_COUNT,
413 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
415 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
418 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
420 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
423 struct radv_meta_state {
424 VkAllocationCallbacks alloc;
426 struct radv_pipeline_cache cache;
429 * Use array element `i` for images with `2^i` samples.
432 VkRenderPass render_pass[NUM_META_FS_KEYS];
433 VkPipeline color_pipelines[NUM_META_FS_KEYS];
435 VkRenderPass depthstencil_rp;
436 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
437 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
438 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
439 } clear[1 + MAX_SAMPLES_LOG2];
441 VkPipelineLayout clear_color_p_layout;
442 VkPipelineLayout clear_depth_p_layout;
444 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
446 /** Pipeline that blits from a 1D image. */
447 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
449 /** Pipeline that blits from a 2D image. */
450 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
452 /** Pipeline that blits from a 3D image. */
453 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
455 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
456 VkPipeline depth_only_1d_pipeline;
457 VkPipeline depth_only_2d_pipeline;
458 VkPipeline depth_only_3d_pipeline;
460 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
461 VkPipeline stencil_only_1d_pipeline;
462 VkPipeline stencil_only_2d_pipeline;
463 VkPipeline stencil_only_3d_pipeline;
464 VkPipelineLayout pipeline_layout;
465 VkDescriptorSetLayout ds_layout;
469 VkPipelineLayout p_layouts[5];
470 VkDescriptorSetLayout ds_layouts[5];
471 VkPipeline pipelines[5][NUM_META_FS_KEYS];
473 VkPipeline depth_only_pipeline[5];
475 VkPipeline stencil_only_pipeline[5];
476 } blit2d[1 + MAX_SAMPLES_LOG2];
478 VkRenderPass blit2d_render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
479 VkRenderPass blit2d_depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
480 VkRenderPass blit2d_stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
483 VkPipelineLayout img_p_layout;
484 VkDescriptorSetLayout img_ds_layout;
486 VkPipeline pipeline_3d;
489 VkPipelineLayout img_p_layout;
490 VkDescriptorSetLayout img_ds_layout;
492 VkPipeline pipeline_3d;
495 VkPipelineLayout img_p_layout;
496 VkDescriptorSetLayout img_ds_layout;
498 VkPipeline pipeline_3d;
501 VkPipelineLayout img_p_layout;
502 VkDescriptorSetLayout img_ds_layout;
504 VkPipeline pipeline_3d;
508 VkPipelineLayout p_layout;
509 VkPipeline pipeline[NUM_META_FS_KEYS];
510 VkRenderPass pass[NUM_META_FS_KEYS];
514 VkDescriptorSetLayout ds_layout;
515 VkPipelineLayout p_layout;
518 VkPipeline i_pipeline;
519 VkPipeline srgb_pipeline;
520 } rc[MAX_SAMPLES_LOG2];
524 VkDescriptorSetLayout ds_layout;
525 VkPipelineLayout p_layout;
528 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
529 VkPipeline pipeline[NUM_META_FS_KEYS];
530 } rc[MAX_SAMPLES_LOG2];
534 VkPipelineLayout p_layout;
535 VkPipeline decompress_pipeline;
536 VkPipeline resummarize_pipeline;
538 } depth_decomp[1 + MAX_SAMPLES_LOG2];
541 VkPipelineLayout p_layout;
542 VkPipeline cmask_eliminate_pipeline;
543 VkPipeline fmask_decompress_pipeline;
544 VkPipeline dcc_decompress_pipeline;
547 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
548 VkPipelineLayout dcc_decompress_compute_p_layout;
549 VkPipeline dcc_decompress_compute_pipeline;
553 VkPipelineLayout fill_p_layout;
554 VkPipelineLayout copy_p_layout;
555 VkDescriptorSetLayout fill_ds_layout;
556 VkDescriptorSetLayout copy_ds_layout;
557 VkPipeline fill_pipeline;
558 VkPipeline copy_pipeline;
562 VkDescriptorSetLayout ds_layout;
563 VkPipelineLayout p_layout;
564 VkPipeline occlusion_query_pipeline;
565 VkPipeline pipeline_statistics_query_pipeline;
570 #define RADV_QUEUE_GENERAL 0
571 #define RADV_QUEUE_COMPUTE 1
572 #define RADV_QUEUE_TRANSFER 2
574 #define RADV_MAX_QUEUE_FAMILIES 3
576 enum ring_type radv_queue_family_to_ring(int f);
579 VK_LOADER_DATA _loader_data;
580 struct radv_device * device;
581 struct radeon_winsys_ctx *hw_ctx;
582 enum radeon_ctx_priority priority;
583 uint32_t queue_family_index;
585 VkDeviceQueueCreateFlags flags;
587 uint32_t scratch_size;
588 uint32_t compute_scratch_size;
589 uint32_t esgs_ring_size;
590 uint32_t gsvs_ring_size;
592 bool has_sample_positions;
594 struct radeon_winsys_bo *scratch_bo;
595 struct radeon_winsys_bo *descriptor_bo;
596 struct radeon_winsys_bo *compute_scratch_bo;
597 struct radeon_winsys_bo *esgs_ring_bo;
598 struct radeon_winsys_bo *gsvs_ring_bo;
599 struct radeon_winsys_bo *tess_rings_bo;
600 struct radeon_winsys_cs *initial_preamble_cs;
601 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
602 struct radeon_winsys_cs *continue_preamble_cs;
605 struct radv_bo_list {
606 struct radv_winsys_bo_list list;
608 pthread_mutex_t mutex;
612 VK_LOADER_DATA _loader_data;
614 VkAllocationCallbacks alloc;
616 struct radv_instance * instance;
617 struct radeon_winsys *ws;
619 struct radv_meta_state meta_state;
621 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
622 int queue_count[RADV_MAX_QUEUE_FAMILIES];
623 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
625 bool always_use_syncobj;
626 bool llvm_supports_spill;
627 bool has_distributed_tess;
630 uint32_t tess_offchip_block_dw_size;
631 uint32_t scratch_waves;
632 uint32_t dispatch_initiator;
634 uint32_t gs_table_depth;
636 /* MSAA sample locations.
637 * The first index is the sample index.
638 * The second index is the coordinate: X, Y. */
639 float sample_locations_1x[1][2];
640 float sample_locations_2x[2][2];
641 float sample_locations_4x[4][2];
642 float sample_locations_8x[8][2];
643 float sample_locations_16x[16][2];
646 uint32_t gfx_init_size_dw;
647 struct radeon_winsys_bo *gfx_init;
649 struct radeon_winsys_bo *trace_bo;
650 uint32_t *trace_id_ptr;
652 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
653 bool keep_shader_info;
655 struct radv_physical_device *physical_device;
657 /* Backup in-memory cache to be used if the app doesn't provide one */
658 struct radv_pipeline_cache * mem_cache;
661 * use different counters so MSAA MRTs get consecutive surface indices,
662 * even if MASK is allocated in between.
664 uint32_t image_mrt_offset_counter;
665 uint32_t fmask_mrt_offset_counter;
666 struct list_head shader_slabs;
667 mtx_t shader_slab_mutex;
669 /* For detecting VM faults reported by dmesg. */
670 uint64_t dmesg_timestamp;
672 struct radv_device_extension_table enabled_extensions;
674 /* Whether the driver uses a global BO list. */
675 bool use_global_bo_list;
677 struct radv_bo_list bo_list;
680 struct radv_device_memory {
681 struct radeon_winsys_bo *bo;
682 /* for dedicated allocations */
683 struct radv_image *image;
684 struct radv_buffer *buffer;
686 VkDeviceSize map_size;
692 struct radv_descriptor_range {
697 struct radv_descriptor_set {
698 const struct radv_descriptor_set_layout *layout;
701 struct radeon_winsys_bo *bo;
703 uint32_t *mapped_ptr;
704 struct radv_descriptor_range *dynamic_descriptors;
706 struct radeon_winsys_bo *descriptors[0];
709 struct radv_push_descriptor_set
711 struct radv_descriptor_set set;
715 struct radv_descriptor_pool_entry {
718 struct radv_descriptor_set *set;
721 struct radv_descriptor_pool {
722 struct radeon_winsys_bo *bo;
724 uint64_t current_offset;
727 uint8_t *host_memory_base;
728 uint8_t *host_memory_ptr;
729 uint8_t *host_memory_end;
731 uint32_t entry_count;
732 uint32_t max_entry_count;
733 struct radv_descriptor_pool_entry entries[0];
736 struct radv_descriptor_update_template_entry {
737 VkDescriptorType descriptor_type;
739 /* The number of descriptors to update */
740 uint32_t descriptor_count;
742 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
745 /* In dwords. Not valid/used for dynamic descriptors */
748 uint32_t buffer_offset;
750 /* Only valid for combined image samplers and samplers */
751 uint16_t has_sampler;
757 /* For push descriptors */
758 const uint32_t *immutable_samplers;
761 struct radv_descriptor_update_template {
762 uint32_t entry_count;
763 VkPipelineBindPoint bind_point;
764 struct radv_descriptor_update_template_entry entry[0];
770 VkBufferUsageFlags usage;
771 VkBufferCreateFlags flags;
774 struct radeon_winsys_bo * bo;
780 enum radv_dynamic_state_bits {
781 RADV_DYNAMIC_VIEWPORT = 1 << 0,
782 RADV_DYNAMIC_SCISSOR = 1 << 1,
783 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
784 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
785 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
786 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
787 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
788 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
789 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
790 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
791 RADV_DYNAMIC_ALL = (1 << 10) - 1,
794 enum radv_cmd_dirty_bits {
795 /* Keep the dynamic state dirty bits in sync with
796 * enum radv_dynamic_state_bits */
797 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
798 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
799 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
800 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
801 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
802 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
803 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
804 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
805 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
806 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
807 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
808 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
809 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
810 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
811 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
814 enum radv_cmd_flush_bits {
815 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
816 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
817 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
818 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
819 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
820 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
821 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
822 /* Same as above, but only writes back and doesn't invalidate */
823 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
824 /* Framebuffer caches */
825 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
826 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
827 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
828 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
829 /* Engine synchronization. */
830 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
831 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
832 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
833 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
835 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
836 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
837 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
838 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
841 struct radv_vertex_binding {
842 struct radv_buffer * buffer;
846 struct radv_viewport_state {
848 VkViewport viewports[MAX_VIEWPORTS];
851 struct radv_scissor_state {
853 VkRect2D scissors[MAX_SCISSORS];
856 struct radv_discard_rectangle_state {
858 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
861 struct radv_dynamic_state {
863 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
864 * Defines the set of saved dynamic state.
868 struct radv_viewport_state viewport;
870 struct radv_scissor_state scissor;
880 float blend_constants[4];
890 } stencil_compare_mask;
895 } stencil_write_mask;
902 struct radv_discard_rectangle_state discard_rectangle;
905 extern const struct radv_dynamic_state default_dynamic_state;
908 radv_get_debug_option_name(int id);
911 radv_get_perftest_option_name(int id);
914 * Attachment state when recording a renderpass instance.
916 * The clear value is valid only if there exists a pending clear.
918 struct radv_attachment_state {
919 VkImageAspectFlags pending_clear_aspects;
920 uint32_t cleared_views;
921 VkClearValue clear_value;
922 VkImageLayout current_layout;
925 struct radv_descriptor_state {
926 struct radv_descriptor_set *sets[MAX_SETS];
929 struct radv_push_descriptor_set push_set;
933 struct radv_cmd_state {
934 /* Vertex descriptors */
941 uint32_t prefetch_L2_mask;
943 struct radv_pipeline * pipeline;
944 struct radv_pipeline * emitted_pipeline;
945 struct radv_pipeline * compute_pipeline;
946 struct radv_pipeline * emitted_compute_pipeline;
947 struct radv_framebuffer * framebuffer;
948 struct radv_render_pass * pass;
949 const struct radv_subpass * subpass;
950 struct radv_dynamic_state dynamic;
951 struct radv_attachment_state * attachments;
952 VkRect2D render_area;
955 struct radv_buffer *index_buffer;
956 uint64_t index_offset;
958 uint32_t max_index_count;
960 int32_t last_index_type;
962 int32_t last_primitive_reset_en;
963 uint32_t last_primitive_reset_index;
964 enum radv_cmd_flush_bits flush_bits;
965 unsigned active_occlusion_queries;
966 bool perfect_occlusion_queries_enabled;
969 uint32_t last_ia_multi_vgt_param;
971 uint32_t last_num_instances;
972 uint32_t last_first_instance;
973 uint32_t last_vertex_offset;
976 struct radv_cmd_pool {
977 VkAllocationCallbacks alloc;
978 struct list_head cmd_buffers;
979 struct list_head free_cmd_buffers;
980 uint32_t queue_family_index;
983 struct radv_cmd_buffer_upload {
987 struct radeon_winsys_bo *upload_bo;
988 struct list_head list;
991 enum radv_cmd_buffer_status {
992 RADV_CMD_BUFFER_STATUS_INVALID,
993 RADV_CMD_BUFFER_STATUS_INITIAL,
994 RADV_CMD_BUFFER_STATUS_RECORDING,
995 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
996 RADV_CMD_BUFFER_STATUS_PENDING,
999 struct radv_cmd_buffer {
1000 VK_LOADER_DATA _loader_data;
1002 struct radv_device * device;
1004 struct radv_cmd_pool * pool;
1005 struct list_head pool_link;
1007 VkCommandBufferUsageFlags usage_flags;
1008 VkCommandBufferLevel level;
1009 enum radv_cmd_buffer_status status;
1010 struct radeon_winsys_cs *cs;
1011 struct radv_cmd_state state;
1012 struct radv_vertex_binding vertex_bindings[MAX_VBS];
1013 uint32_t queue_family_index;
1015 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
1016 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
1017 VkShaderStageFlags push_constant_stages;
1018 struct radv_descriptor_set meta_push_descriptors;
1020 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
1022 struct radv_cmd_buffer_upload upload;
1024 uint32_t scratch_size_needed;
1025 uint32_t compute_scratch_size_needed;
1026 uint32_t esgs_ring_size_needed;
1027 uint32_t gsvs_ring_size_needed;
1028 bool tess_rings_needed;
1029 bool sample_positions_needed;
1031 VkResult record_result;
1033 int ring_offsets_idx; /* just used for verification */
1034 uint32_t gfx9_fence_offset;
1035 struct radeon_winsys_bo *gfx9_fence_bo;
1036 uint32_t gfx9_fence_idx;
1039 * Whether a query pool has been resetted and we have to flush caches.
1041 bool pending_reset_query;
1046 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1048 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1049 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1051 void cik_create_gfx_config(struct radv_device *device);
1053 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
1054 int count, const VkViewport *viewports);
1055 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
1056 int count, const VkRect2D *scissors,
1057 const VkViewport *viewports, bool can_use_guardband);
1058 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1059 bool instanced_draw, bool indirect_draw,
1060 uint32_t draw_vertex_count);
1061 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
1063 enum chip_class chip_class,
1065 unsigned event, unsigned event_flags,
1069 uint32_t new_fence);
1071 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1073 uint64_t va, uint32_t ref,
1075 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1076 enum chip_class chip_class,
1077 uint32_t *fence_ptr, uint64_t va,
1079 enum radv_cmd_flush_bits flush_bits);
1080 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1081 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1082 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1083 uint64_t src_va, uint64_t dest_va,
1085 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1087 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1088 uint64_t size, unsigned value);
1089 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1091 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1094 unsigned *out_offset,
1097 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1098 const struct radv_subpass *subpass,
1101 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1102 unsigned size, unsigned alignmnet,
1103 const void *data, unsigned *out_offset);
1105 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1106 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1107 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1108 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1109 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1110 unsigned radv_cayman_get_maxdist(int log_samples);
1111 void radv_device_init_msaa(struct radv_device *device);
1112 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1113 struct radv_image *image,
1114 VkClearDepthStencilValue ds_clear_value,
1115 VkImageAspectFlags aspects);
1116 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1117 struct radv_image *image,
1119 uint32_t color_values[2]);
1120 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1121 struct radv_image *image,
1123 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1124 struct radeon_winsys_bo *bo,
1125 uint64_t offset, uint64_t size, uint32_t value);
1126 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1127 bool radv_get_memory_fd(struct radv_device *device,
1128 struct radv_device_memory *memory,
1131 static inline struct radv_descriptor_state *
1132 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1133 VkPipelineBindPoint bind_point)
1135 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1136 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1137 return &cmd_buffer->descriptors[bind_point];
1141 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1143 * Limitations: Can't call normal dispatch functions without binding or rebinding
1144 * the compute pipeline.
1146 void radv_unaligned_dispatch(
1147 struct radv_cmd_buffer *cmd_buffer,
1153 struct radeon_winsys_bo *bo;
1157 struct radv_shader_module;
1159 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1160 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1161 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1163 radv_hash_shaders(unsigned char *hash,
1164 const VkPipelineShaderStageCreateInfo **stages,
1165 const struct radv_pipeline_layout *layout,
1166 const struct radv_pipeline_key *key,
1169 static inline gl_shader_stage
1170 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1172 assert(__builtin_popcount(vk_stage) == 1);
1173 return ffs(vk_stage) - 1;
1176 static inline VkShaderStageFlagBits
1177 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1179 return (1 << mesa_stage);
1182 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1184 #define radv_foreach_stage(stage, stage_bits) \
1185 for (gl_shader_stage stage, \
1186 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1187 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1188 __tmp &= ~(1 << (stage)))
1190 unsigned radv_format_meta_fs_key(VkFormat format);
1192 struct radv_multisample_state {
1194 uint32_t pa_sc_line_cntl;
1195 uint32_t pa_sc_mode_cntl_0;
1196 uint32_t pa_sc_mode_cntl_1;
1197 uint32_t pa_sc_aa_config;
1198 uint32_t pa_sc_aa_mask[2];
1199 unsigned num_samples;
1202 struct radv_prim_vertex_count {
1207 struct radv_vertex_elements_info {
1208 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1209 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1210 uint32_t binding[MAX_VERTEX_ATTRIBS];
1211 uint32_t offset[MAX_VERTEX_ATTRIBS];
1215 struct radv_ia_multi_vgt_param_helpers {
1217 bool partial_es_wave;
1218 uint8_t primgroup_size;
1219 bool wd_switch_on_eop;
1220 bool ia_switch_on_eoi;
1221 bool partial_vs_wave;
1224 #define SI_GS_PER_ES 128
1226 struct radv_pipeline {
1227 struct radv_device * device;
1228 struct radv_dynamic_state dynamic_state;
1230 struct radv_pipeline_layout * layout;
1232 bool need_indirect_descriptor_sets;
1233 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1234 struct radv_shader_variant *gs_copy_shader;
1235 VkShaderStageFlags active_stages;
1237 struct radeon_winsys_cs cs;
1239 struct radv_vertex_elements_info vertex_elements;
1241 uint32_t binding_stride[MAX_VBS];
1243 uint32_t user_data_0[MESA_SHADER_STAGES];
1246 struct radv_multisample_state ms;
1247 uint32_t spi_baryc_cntl;
1248 bool prim_restart_enable;
1249 unsigned esgs_ring_size;
1250 unsigned gsvs_ring_size;
1251 uint32_t vtx_base_sgpr;
1252 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1253 uint8_t vtx_emit_num;
1254 struct radv_prim_vertex_count prim_vertex_count;
1255 bool can_use_guardband;
1256 uint32_t needed_dynamic_state;
1257 bool disable_out_of_order_rast_for_occlusion;
1259 /* Used for rbplus */
1260 uint32_t col_format;
1261 uint32_t cb_target_mask;
1266 unsigned scratch_bytes_per_wave;
1269 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1271 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1274 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1276 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1279 struct radv_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1280 gl_shader_stage stage,
1283 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1285 struct radv_graphics_pipeline_create_info {
1287 bool db_depth_clear;
1288 bool db_stencil_clear;
1289 bool db_depth_disable_expclear;
1290 bool db_stencil_disable_expclear;
1291 bool db_flush_depth_inplace;
1292 bool db_flush_stencil_inplace;
1293 bool db_resummarize;
1294 uint32_t custom_blend_mode;
1298 radv_graphics_pipeline_create(VkDevice device,
1299 VkPipelineCache cache,
1300 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1301 const struct radv_graphics_pipeline_create_info *extra,
1302 const VkAllocationCallbacks *alloc,
1303 VkPipeline *pPipeline);
1305 struct vk_format_description;
1306 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1307 int first_non_void);
1308 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1309 int first_non_void);
1310 uint32_t radv_translate_colorformat(VkFormat format);
1311 uint32_t radv_translate_color_numformat(VkFormat format,
1312 const struct vk_format_description *desc,
1313 int first_non_void);
1314 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1315 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1316 uint32_t radv_translate_dbformat(VkFormat format);
1317 uint32_t radv_translate_tex_dataformat(VkFormat format,
1318 const struct vk_format_description *desc,
1319 int first_non_void);
1320 uint32_t radv_translate_tex_numformat(VkFormat format,
1321 const struct vk_format_description *desc,
1322 int first_non_void);
1323 bool radv_format_pack_clear_color(VkFormat format,
1324 uint32_t clear_vals[2],
1325 VkClearColorValue *value);
1326 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1327 bool radv_dcc_formats_compatible(VkFormat format1,
1330 struct radv_fmask_info {
1334 unsigned pitch_in_pixels;
1335 unsigned bank_height;
1336 unsigned slice_tile_max;
1337 unsigned tile_mode_index;
1338 unsigned tile_swizzle;
1341 struct radv_cmask_info {
1345 unsigned slice_tile_max;
1350 /* The original VkFormat provided by the client. This may not match any
1351 * of the actual surface formats.
1354 VkImageAspectFlags aspects;
1355 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1356 struct ac_surf_info info;
1357 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1358 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1363 unsigned queue_family_mask;
1367 /* Set when bound */
1368 struct radeon_winsys_bo *bo;
1369 VkDeviceSize offset;
1370 uint64_t dcc_offset;
1371 uint64_t htile_offset;
1372 bool tc_compatible_htile;
1373 struct radeon_surf surface;
1375 struct radv_fmask_info fmask;
1376 struct radv_cmask_info cmask;
1377 uint64_t clear_value_offset;
1378 uint64_t dcc_pred_offset;
1380 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1381 VkDeviceMemory owned_memory;
1384 /* Whether the image has a htile that is known consistent with the contents of
1386 bool radv_layout_has_htile(const struct radv_image *image,
1387 VkImageLayout layout,
1388 unsigned queue_mask);
1390 /* Whether the image has a htile that is known consistent with the contents of
1391 * the image and is allowed to be in compressed form.
1393 * If this is false reads that don't use the htile should be able to return
1396 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1397 VkImageLayout layout,
1398 unsigned queue_mask);
1400 bool radv_layout_can_fast_clear(const struct radv_image *image,
1401 VkImageLayout layout,
1402 unsigned queue_mask);
1404 bool radv_layout_dcc_compressed(const struct radv_image *image,
1405 VkImageLayout layout,
1406 unsigned queue_mask);
1409 * Return whether the image has CMASK metadata for color surfaces.
1412 radv_image_has_cmask(const struct radv_image *image)
1414 return image->cmask.size;
1418 * Return whether the image has FMASK metadata for color surfaces.
1421 radv_image_has_fmask(const struct radv_image *image)
1423 return image->fmask.size;
1427 * Return whether the image has DCC metadata for color surfaces.
1430 radv_image_has_dcc(const struct radv_image *image)
1432 return image->surface.dcc_size;
1436 * Return whether DCC metadata is enabled for a level.
1439 radv_dcc_enabled(const struct radv_image *image, unsigned level)
1441 return radv_image_has_dcc(image) &&
1442 level < image->surface.num_dcc_levels;
1446 * Return whether the image has HTILE metadata for depth surfaces.
1449 radv_image_has_htile(const struct radv_image *image)
1451 return image->surface.htile_size;
1455 * Return whether HTILE metadata is enabled for a level.
1458 radv_htile_enabled(const struct radv_image *image, unsigned level)
1460 return radv_image_has_htile(image) && level == 0;
1464 * Return whether the image is TC-compatible HTILE.
1467 radv_image_is_tc_compat_htile(const struct radv_image *image)
1469 return radv_image_has_htile(image) && image->tc_compatible_htile;
1472 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1474 static inline uint32_t
1475 radv_get_layerCount(const struct radv_image *image,
1476 const VkImageSubresourceRange *range)
1478 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1479 image->info.array_size - range->baseArrayLayer : range->layerCount;
1482 static inline uint32_t
1483 radv_get_levelCount(const struct radv_image *image,
1484 const VkImageSubresourceRange *range)
1486 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1487 image->info.levels - range->baseMipLevel : range->levelCount;
1490 struct radeon_bo_metadata;
1492 radv_init_metadata(struct radv_device *device,
1493 struct radv_image *image,
1494 struct radeon_bo_metadata *metadata);
1496 struct radv_image_view {
1497 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1498 struct radeon_winsys_bo *bo;
1500 VkImageViewType type;
1501 VkImageAspectFlags aspect_mask;
1503 uint32_t base_layer;
1504 uint32_t layer_count;
1506 uint32_t level_count;
1507 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1509 uint32_t descriptor[16];
1511 /* Descriptor for use as a storage image as opposed to a sampled image.
1512 * This has a few differences for cube maps (e.g. type).
1514 uint32_t storage_descriptor[16];
1517 struct radv_image_create_info {
1518 const VkImageCreateInfo *vk_info;
1520 bool no_metadata_planes;
1523 VkResult radv_image_create(VkDevice _device,
1524 const struct radv_image_create_info *info,
1525 const VkAllocationCallbacks* alloc,
1529 radv_image_from_gralloc(VkDevice device_h,
1530 const VkImageCreateInfo *base_info,
1531 const VkNativeBufferANDROID *gralloc_info,
1532 const VkAllocationCallbacks *alloc,
1533 VkImage *out_image_h);
1535 void radv_image_view_init(struct radv_image_view *view,
1536 struct radv_device *device,
1537 const VkImageViewCreateInfo* pCreateInfo);
1539 struct radv_buffer_view {
1540 struct radeon_winsys_bo *bo;
1542 uint64_t range; /**< VkBufferViewCreateInfo::range */
1545 void radv_buffer_view_init(struct radv_buffer_view *view,
1546 struct radv_device *device,
1547 const VkBufferViewCreateInfo* pCreateInfo);
1549 static inline struct VkExtent3D
1550 radv_sanitize_image_extent(const VkImageType imageType,
1551 const struct VkExtent3D imageExtent)
1553 switch (imageType) {
1554 case VK_IMAGE_TYPE_1D:
1555 return (VkExtent3D) { imageExtent.width, 1, 1 };
1556 case VK_IMAGE_TYPE_2D:
1557 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1558 case VK_IMAGE_TYPE_3D:
1561 unreachable("invalid image type");
1565 static inline struct VkOffset3D
1566 radv_sanitize_image_offset(const VkImageType imageType,
1567 const struct VkOffset3D imageOffset)
1569 switch (imageType) {
1570 case VK_IMAGE_TYPE_1D:
1571 return (VkOffset3D) { imageOffset.x, 0, 0 };
1572 case VK_IMAGE_TYPE_2D:
1573 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1574 case VK_IMAGE_TYPE_3D:
1577 unreachable("invalid image type");
1582 radv_image_extent_compare(const struct radv_image *image,
1583 const VkExtent3D *extent)
1585 if (extent->width != image->info.width ||
1586 extent->height != image->info.height ||
1587 extent->depth != image->info.depth)
1592 struct radv_sampler {
1596 struct radv_color_buffer_info {
1597 uint64_t cb_color_base;
1598 uint64_t cb_color_cmask;
1599 uint64_t cb_color_fmask;
1600 uint64_t cb_dcc_base;
1601 uint32_t cb_color_pitch;
1602 uint32_t cb_color_slice;
1603 uint32_t cb_color_view;
1604 uint32_t cb_color_info;
1605 uint32_t cb_color_attrib;
1606 uint32_t cb_color_attrib2;
1607 uint32_t cb_dcc_control;
1608 uint32_t cb_color_cmask_slice;
1609 uint32_t cb_color_fmask_slice;
1612 struct radv_ds_buffer_info {
1613 uint64_t db_z_read_base;
1614 uint64_t db_stencil_read_base;
1615 uint64_t db_z_write_base;
1616 uint64_t db_stencil_write_base;
1617 uint64_t db_htile_data_base;
1618 uint32_t db_depth_info;
1620 uint32_t db_stencil_info;
1621 uint32_t db_depth_view;
1622 uint32_t db_depth_size;
1623 uint32_t db_depth_slice;
1624 uint32_t db_htile_surface;
1625 uint32_t pa_su_poly_offset_db_fmt_cntl;
1626 uint32_t db_z_info2;
1627 uint32_t db_stencil_info2;
1631 struct radv_attachment_info {
1633 struct radv_color_buffer_info cb;
1634 struct radv_ds_buffer_info ds;
1636 struct radv_image_view *attachment;
1639 struct radv_framebuffer {
1644 uint32_t attachment_count;
1645 struct radv_attachment_info attachments[0];
1648 struct radv_subpass_barrier {
1649 VkPipelineStageFlags src_stage_mask;
1650 VkAccessFlags src_access_mask;
1651 VkAccessFlags dst_access_mask;
1654 struct radv_subpass {
1655 uint32_t input_count;
1656 uint32_t color_count;
1657 VkAttachmentReference * input_attachments;
1658 VkAttachmentReference * color_attachments;
1659 VkAttachmentReference * resolve_attachments;
1660 VkAttachmentReference depth_stencil_attachment;
1662 /** Subpass has at least one resolve attachment */
1665 struct radv_subpass_barrier start_barrier;
1668 VkSampleCountFlagBits max_sample_count;
1671 struct radv_render_pass_attachment {
1674 VkAttachmentLoadOp load_op;
1675 VkAttachmentLoadOp stencil_load_op;
1676 VkImageLayout initial_layout;
1677 VkImageLayout final_layout;
1681 struct radv_render_pass {
1682 uint32_t attachment_count;
1683 uint32_t subpass_count;
1684 VkAttachmentReference * subpass_attachments;
1685 struct radv_render_pass_attachment * attachments;
1686 struct radv_subpass_barrier end_barrier;
1687 struct radv_subpass subpasses[0];
1690 VkResult radv_device_init_meta(struct radv_device *device);
1691 void radv_device_finish_meta(struct radv_device *device);
1693 struct radv_query_pool {
1694 struct radeon_winsys_bo *bo;
1696 uint32_t availability_offset;
1700 uint32_t pipeline_stats_mask;
1703 struct radv_semaphore {
1704 /* use a winsys sem for non-exportable */
1705 struct radeon_winsys_sem *sem;
1707 uint32_t temp_syncobj;
1710 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1712 const VkSemaphore *wait_sems,
1713 int num_signal_sems,
1714 const VkSemaphore *signal_sems,
1716 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1718 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1719 VkPipelineBindPoint bind_point,
1720 struct radv_descriptor_set *set,
1724 radv_update_descriptor_sets(struct radv_device *device,
1725 struct radv_cmd_buffer *cmd_buffer,
1726 VkDescriptorSet overrideSet,
1727 uint32_t descriptorWriteCount,
1728 const VkWriteDescriptorSet *pDescriptorWrites,
1729 uint32_t descriptorCopyCount,
1730 const VkCopyDescriptorSet *pDescriptorCopies);
1733 radv_update_descriptor_set_with_template(struct radv_device *device,
1734 struct radv_cmd_buffer *cmd_buffer,
1735 struct radv_descriptor_set *set,
1736 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1739 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1740 VkPipelineBindPoint pipelineBindPoint,
1741 VkPipelineLayout _layout,
1743 uint32_t descriptorWriteCount,
1744 const VkWriteDescriptorSet *pDescriptorWrites);
1746 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1747 struct radv_image *image, uint32_t value);
1750 struct radeon_winsys_fence *fence;
1755 uint32_t temp_syncobj;
1758 /* radv_nir_to_llvm.c */
1759 struct radv_shader_variant_info;
1760 struct radv_nir_compiler_options;
1762 void radv_compile_gs_copy_shader(LLVMTargetMachineRef tm,
1763 struct nir_shader *geom_shader,
1764 struct ac_shader_binary *binary,
1765 struct ac_shader_config *config,
1766 struct radv_shader_variant_info *shader_info,
1767 const struct radv_nir_compiler_options *option);
1769 void radv_compile_nir_shader(LLVMTargetMachineRef tm,
1770 struct ac_shader_binary *binary,
1771 struct ac_shader_config *config,
1772 struct radv_shader_variant_info *shader_info,
1773 struct nir_shader *const *nir,
1775 const struct radv_nir_compiler_options *options);
1777 /* radv_shader_info.h */
1778 struct radv_shader_info;
1780 void radv_nir_shader_info_pass(const struct nir_shader *nir,
1781 const struct radv_nir_compiler_options *options,
1782 struct radv_shader_info *info);
1784 struct radeon_winsys_sem;
1786 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1788 static inline struct __radv_type * \
1789 __radv_type ## _from_handle(__VkType _handle) \
1791 return (struct __radv_type *) _handle; \
1794 static inline __VkType \
1795 __radv_type ## _to_handle(struct __radv_type *_obj) \
1797 return (__VkType) _obj; \
1800 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1802 static inline struct __radv_type * \
1803 __radv_type ## _from_handle(__VkType _handle) \
1805 return (struct __radv_type *)(uintptr_t) _handle; \
1808 static inline __VkType \
1809 __radv_type ## _to_handle(struct __radv_type *_obj) \
1811 return (__VkType)(uintptr_t) _obj; \
1814 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1815 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1817 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1818 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1819 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1820 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1821 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1823 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1824 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1825 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1826 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1827 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1828 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1829 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1830 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1831 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1832 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1833 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1834 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1835 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1836 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1837 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1838 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1839 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1840 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1841 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1842 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1843 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1845 #endif /* RADV_PRIVATE_H */