2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #ifndef RADV_PRIVATE_H
29 #define RADV_PRIVATE_H
47 #include "compiler/shader_enums.h"
48 #include "util/macros.h"
49 #include "util/list.h"
50 #include "main/macros.h"
52 #include "vk_debug_report.h"
54 #include "radv_radeon_winsys.h"
55 #include "ac_binary.h"
56 #include "ac_nir_to_llvm.h"
57 #include "ac_gpu_info.h"
58 #include "ac_surface.h"
59 #include "radv_descriptor_set.h"
60 #include "radv_extensions.h"
62 #include <llvm-c/TargetMachine.h>
64 /* Pre-declarations needed for WSI entrypoints */
67 typedef struct xcb_connection_t xcb_connection_t;
68 typedef uint32_t xcb_visualid_t;
69 typedef uint32_t xcb_window_t;
71 #include <vulkan/vulkan.h>
72 #include <vulkan/vulkan_intel.h>
73 #include <vulkan/vk_icd.h>
74 #include <vulkan/vk_android_native_buffer.h>
76 #include "radv_entrypoints.h"
78 #include "wsi_common.h"
80 #define ATI_VENDOR_ID 0x1002
83 #define MAX_VERTEX_ATTRIBS 32
85 #define MAX_VIEWPORTS 16
86 #define MAX_SCISSORS 16
87 #define MAX_DISCARD_RECTANGLES 4
88 #define MAX_PUSH_CONSTANTS_SIZE 128
89 #define MAX_PUSH_DESCRIPTORS 32
90 #define MAX_DYNAMIC_BUFFERS 16
91 #define MAX_SAMPLES_LOG2 4
92 #define NUM_META_FS_KEYS 13
93 #define RADV_MAX_DRM_DEVICES 8
96 #define NUM_DEPTH_CLEAR_PIPELINES 3
100 RADV_MEM_HEAP_VRAM_CPU_ACCESS,
107 RADV_MEM_TYPE_GTT_WRITE_COMBINE,
108 RADV_MEM_TYPE_VRAM_CPU_ACCESS,
109 RADV_MEM_TYPE_GTT_CACHED,
113 #define radv_printflike(a, b) __attribute__((__format__(__printf__, a, b)))
115 static inline uint32_t
116 align_u32(uint32_t v, uint32_t a)
118 assert(a != 0 && a == (a & -a));
119 return (v + a - 1) & ~(a - 1);
122 static inline uint32_t
123 align_u32_npot(uint32_t v, uint32_t a)
125 return (v + a - 1) / a * a;
128 static inline uint64_t
129 align_u64(uint64_t v, uint64_t a)
131 assert(a != 0 && a == (a & -a));
132 return (v + a - 1) & ~(a - 1);
135 static inline int32_t
136 align_i32(int32_t v, int32_t a)
138 assert(a != 0 && a == (a & -a));
139 return (v + a - 1) & ~(a - 1);
142 /** Alignment must be a power of 2. */
144 radv_is_aligned(uintmax_t n, uintmax_t a)
146 assert(a == (a & -a));
147 return (n & (a - 1)) == 0;
150 static inline uint32_t
151 round_up_u32(uint32_t v, uint32_t a)
153 return (v + a - 1) / a;
156 static inline uint64_t
157 round_up_u64(uint64_t v, uint64_t a)
159 return (v + a - 1) / a;
162 static inline uint32_t
163 radv_minify(uint32_t n, uint32_t levels)
165 if (unlikely(n == 0))
168 return MAX2(n >> levels, 1);
171 radv_clamp_f(float f, float min, float max)
184 radv_clear_mask(uint32_t *inout_mask, uint32_t clear_mask)
186 if (*inout_mask & clear_mask) {
187 *inout_mask &= ~clear_mask;
194 #define for_each_bit(b, dword) \
195 for (uint32_t __dword = (dword); \
196 (b) = __builtin_ffs(__dword) - 1, __dword; \
197 __dword &= ~(1 << (b)))
199 #define typed_memcpy(dest, src, count) ({ \
200 STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
201 memcpy((dest), (src), (count) * sizeof(*(src))); \
204 /* Whenever we generate an error, pass it through this function. Useful for
205 * debugging, where we can break on it. Only call at error site, not when
206 * propagating errors. Might be useful to plug in a stack trace here.
209 VkResult __vk_errorf(VkResult error, const char *file, int line, const char *format, ...);
212 #define vk_error(error) __vk_errorf(error, __FILE__, __LINE__, NULL);
213 #define vk_errorf(error, format, ...) __vk_errorf(error, __FILE__, __LINE__, format, ## __VA_ARGS__);
215 #define vk_error(error) error
216 #define vk_errorf(error, format, ...) error
219 void __radv_finishme(const char *file, int line, const char *format, ...)
220 radv_printflike(3, 4);
221 void radv_loge(const char *format, ...) radv_printflike(1, 2);
222 void radv_loge_v(const char *format, va_list va);
225 * Print a FINISHME message, including its source location.
227 #define radv_finishme(format, ...) \
229 static bool reported = false; \
231 __radv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
236 /* A non-fatal assert. Useful for debugging. */
238 #define radv_assert(x) ({ \
239 if (unlikely(!(x))) \
240 fprintf(stderr, "%s:%d ASSERT: %s\n", __FILE__, __LINE__, #x); \
243 #define radv_assert(x)
246 #define stub_return(v) \
248 radv_finishme("stub %s", __func__); \
254 radv_finishme("stub %s", __func__); \
258 void *radv_lookup_entrypoint_unchecked(const char *name);
259 void *radv_lookup_entrypoint_checked(const char *name,
260 uint32_t core_version,
261 const struct radv_instance_extension_table *instance,
262 const struct radv_device_extension_table *device);
264 struct radv_physical_device {
265 VK_LOADER_DATA _loader_data;
267 struct radv_instance * instance;
269 struct radeon_winsys *ws;
270 struct radeon_info rad_info;
272 char name[VK_MAX_PHYSICAL_DEVICE_NAME_SIZE];
273 uint8_t driver_uuid[VK_UUID_SIZE];
274 uint8_t device_uuid[VK_UUID_SIZE];
275 uint8_t cache_uuid[VK_UUID_SIZE];
278 struct wsi_device wsi_device;
280 bool has_rbplus; /* if RB+ register exist */
281 bool rbplus_allowed; /* if RB+ is allowed */
282 bool has_clear_state;
283 bool cpdma_prefetch_writes_memory;
284 bool has_scissor_bug;
286 /* This is the drivers on-disk cache used as a fallback as opposed to
287 * the pipeline cache defined by apps.
289 struct disk_cache * disk_cache;
291 VkPhysicalDeviceMemoryProperties memory_properties;
292 enum radv_mem_type mem_type_indices[RADV_MEM_TYPE_COUNT];
294 struct radv_device_extension_table supported_extensions;
297 struct radv_instance {
298 VK_LOADER_DATA _loader_data;
300 VkAllocationCallbacks alloc;
303 int physicalDeviceCount;
304 struct radv_physical_device physicalDevices[RADV_MAX_DRM_DEVICES];
306 uint64_t debug_flags;
307 uint64_t perftest_flags;
309 struct vk_debug_report_instance debug_report_callbacks;
311 struct radv_instance_extension_table enabled_extensions;
314 VkResult radv_init_wsi(struct radv_physical_device *physical_device);
315 void radv_finish_wsi(struct radv_physical_device *physical_device);
317 bool radv_instance_extension_supported(const char *name);
318 uint32_t radv_physical_device_api_version(struct radv_physical_device *dev);
319 bool radv_physical_device_extension_supported(struct radv_physical_device *dev,
324 struct radv_pipeline_cache {
325 struct radv_device * device;
326 pthread_mutex_t mutex;
330 uint32_t kernel_count;
331 struct cache_entry ** hash_table;
334 VkAllocationCallbacks alloc;
337 struct radv_pipeline_key {
338 uint32_t instance_rate_inputs;
339 unsigned tess_input_vertices;
343 uint8_t log2_ps_iter_samples;
344 uint8_t log2_num_samples;
345 uint32_t multisample : 1;
346 uint32_t has_multiview_view_index : 1;
350 radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
351 struct radv_device *device);
353 radv_pipeline_cache_finish(struct radv_pipeline_cache *cache);
355 radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
356 const void *data, size_t size);
358 struct radv_shader_variant;
361 radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
362 struct radv_pipeline_cache *cache,
363 const unsigned char *sha1,
364 struct radv_shader_variant **variants);
367 radv_pipeline_cache_insert_shaders(struct radv_device *device,
368 struct radv_pipeline_cache *cache,
369 const unsigned char *sha1,
370 struct radv_shader_variant **variants,
371 const void *const *codes,
372 const unsigned *code_sizes);
374 enum radv_blit_ds_layout {
375 RADV_BLIT_DS_LAYOUT_TILE_ENABLE,
376 RADV_BLIT_DS_LAYOUT_TILE_DISABLE,
377 RADV_BLIT_DS_LAYOUT_COUNT,
380 static inline enum radv_blit_ds_layout radv_meta_blit_ds_to_type(VkImageLayout layout)
382 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_BLIT_DS_LAYOUT_TILE_DISABLE : RADV_BLIT_DS_LAYOUT_TILE_ENABLE;
385 static inline VkImageLayout radv_meta_blit_ds_to_layout(enum radv_blit_ds_layout ds_layout)
387 return ds_layout == RADV_BLIT_DS_LAYOUT_TILE_ENABLE ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
390 enum radv_meta_dst_layout {
391 RADV_META_DST_LAYOUT_GENERAL,
392 RADV_META_DST_LAYOUT_OPTIMAL,
393 RADV_META_DST_LAYOUT_COUNT,
396 static inline enum radv_meta_dst_layout radv_meta_dst_layout_from_layout(VkImageLayout layout)
398 return (layout == VK_IMAGE_LAYOUT_GENERAL) ? RADV_META_DST_LAYOUT_GENERAL : RADV_META_DST_LAYOUT_OPTIMAL;
401 static inline VkImageLayout radv_meta_dst_layout_to_layout(enum radv_meta_dst_layout layout)
403 return layout == RADV_META_DST_LAYOUT_OPTIMAL ? VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL : VK_IMAGE_LAYOUT_GENERAL;
406 struct radv_meta_state {
407 VkAllocationCallbacks alloc;
409 struct radv_pipeline_cache cache;
412 * Use array element `i` for images with `2^i` samples.
415 VkRenderPass render_pass[NUM_META_FS_KEYS];
416 VkPipeline color_pipelines[NUM_META_FS_KEYS];
418 VkRenderPass depthstencil_rp;
419 VkPipeline depth_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
420 VkPipeline stencil_only_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
421 VkPipeline depthstencil_pipeline[NUM_DEPTH_CLEAR_PIPELINES];
422 } clear[1 + MAX_SAMPLES_LOG2];
424 VkPipelineLayout clear_color_p_layout;
425 VkPipelineLayout clear_depth_p_layout;
427 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
429 /** Pipeline that blits from a 1D image. */
430 VkPipeline pipeline_1d_src[NUM_META_FS_KEYS];
432 /** Pipeline that blits from a 2D image. */
433 VkPipeline pipeline_2d_src[NUM_META_FS_KEYS];
435 /** Pipeline that blits from a 3D image. */
436 VkPipeline pipeline_3d_src[NUM_META_FS_KEYS];
438 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
439 VkPipeline depth_only_1d_pipeline;
440 VkPipeline depth_only_2d_pipeline;
441 VkPipeline depth_only_3d_pipeline;
443 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
444 VkPipeline stencil_only_1d_pipeline;
445 VkPipeline stencil_only_2d_pipeline;
446 VkPipeline stencil_only_3d_pipeline;
447 VkPipelineLayout pipeline_layout;
448 VkDescriptorSetLayout ds_layout;
452 VkRenderPass render_passes[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
454 VkPipelineLayout p_layouts[3];
455 VkDescriptorSetLayout ds_layouts[3];
456 VkPipeline pipelines[3][NUM_META_FS_KEYS];
458 VkRenderPass depth_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
459 VkPipeline depth_only_pipeline[3];
461 VkRenderPass stencil_only_rp[RADV_BLIT_DS_LAYOUT_COUNT];
462 VkPipeline stencil_only_pipeline[3];
466 VkPipelineLayout img_p_layout;
467 VkDescriptorSetLayout img_ds_layout;
469 VkPipeline pipeline_3d;
472 VkPipelineLayout img_p_layout;
473 VkDescriptorSetLayout img_ds_layout;
475 VkPipeline pipeline_3d;
478 VkPipelineLayout img_p_layout;
479 VkDescriptorSetLayout img_ds_layout;
481 VkPipeline pipeline_3d;
484 VkPipelineLayout img_p_layout;
485 VkDescriptorSetLayout img_ds_layout;
487 VkPipeline pipeline_3d;
491 VkPipelineLayout p_layout;
492 VkPipeline pipeline[NUM_META_FS_KEYS];
493 VkRenderPass pass[NUM_META_FS_KEYS];
497 VkDescriptorSetLayout ds_layout;
498 VkPipelineLayout p_layout;
501 VkPipeline i_pipeline;
502 VkPipeline srgb_pipeline;
503 } rc[MAX_SAMPLES_LOG2];
507 VkDescriptorSetLayout ds_layout;
508 VkPipelineLayout p_layout;
511 VkRenderPass render_pass[NUM_META_FS_KEYS][RADV_META_DST_LAYOUT_COUNT];
512 VkPipeline pipeline[NUM_META_FS_KEYS];
513 } rc[MAX_SAMPLES_LOG2];
517 VkPipelineLayout p_layout;
518 VkPipeline decompress_pipeline;
519 VkPipeline resummarize_pipeline;
521 } depth_decomp[1 + MAX_SAMPLES_LOG2];
524 VkPipelineLayout p_layout;
525 VkPipeline cmask_eliminate_pipeline;
526 VkPipeline fmask_decompress_pipeline;
527 VkPipeline dcc_decompress_pipeline;
530 VkDescriptorSetLayout dcc_decompress_compute_ds_layout;
531 VkPipelineLayout dcc_decompress_compute_p_layout;
532 VkPipeline dcc_decompress_compute_pipeline;
536 VkPipelineLayout fill_p_layout;
537 VkPipelineLayout copy_p_layout;
538 VkDescriptorSetLayout fill_ds_layout;
539 VkDescriptorSetLayout copy_ds_layout;
540 VkPipeline fill_pipeline;
541 VkPipeline copy_pipeline;
545 VkDescriptorSetLayout ds_layout;
546 VkPipelineLayout p_layout;
547 VkPipeline occlusion_query_pipeline;
548 VkPipeline pipeline_statistics_query_pipeline;
553 #define RADV_QUEUE_GENERAL 0
554 #define RADV_QUEUE_COMPUTE 1
555 #define RADV_QUEUE_TRANSFER 2
557 #define RADV_MAX_QUEUE_FAMILIES 3
559 enum ring_type radv_queue_family_to_ring(int f);
562 VK_LOADER_DATA _loader_data;
563 struct radv_device * device;
564 struct radeon_winsys_ctx *hw_ctx;
565 enum radeon_ctx_priority priority;
566 uint32_t queue_family_index;
569 uint32_t scratch_size;
570 uint32_t compute_scratch_size;
571 uint32_t esgs_ring_size;
572 uint32_t gsvs_ring_size;
574 bool has_sample_positions;
576 struct radeon_winsys_bo *scratch_bo;
577 struct radeon_winsys_bo *descriptor_bo;
578 struct radeon_winsys_bo *compute_scratch_bo;
579 struct radeon_winsys_bo *esgs_ring_bo;
580 struct radeon_winsys_bo *gsvs_ring_bo;
581 struct radeon_winsys_bo *tess_factor_ring_bo;
582 struct radeon_winsys_bo *tess_offchip_ring_bo;
583 struct radeon_winsys_cs *initial_preamble_cs;
584 struct radeon_winsys_cs *initial_full_flush_preamble_cs;
585 struct radeon_winsys_cs *continue_preamble_cs;
589 VK_LOADER_DATA _loader_data;
591 VkAllocationCallbacks alloc;
593 struct radv_instance * instance;
594 struct radeon_winsys *ws;
596 struct radv_meta_state meta_state;
598 struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
599 int queue_count[RADV_MAX_QUEUE_FAMILIES];
600 struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
602 bool always_use_syncobj;
603 bool llvm_supports_spill;
604 bool has_distributed_tess;
607 uint32_t tess_offchip_block_dw_size;
608 uint32_t scratch_waves;
609 uint32_t dispatch_initiator;
611 uint32_t gs_table_depth;
613 /* MSAA sample locations.
614 * The first index is the sample index.
615 * The second index is the coordinate: X, Y. */
616 float sample_locations_1x[1][2];
617 float sample_locations_2x[2][2];
618 float sample_locations_4x[4][2];
619 float sample_locations_8x[8][2];
620 float sample_locations_16x[16][2];
623 uint32_t gfx_init_size_dw;
624 struct radeon_winsys_bo *gfx_init;
626 struct radeon_winsys_bo *trace_bo;
627 uint32_t *trace_id_ptr;
629 /* Whether to keep shader debug info, for tracing or VK_AMD_shader_info */
630 bool keep_shader_info;
632 struct radv_physical_device *physical_device;
634 /* Backup in-memory cache to be used if the app doesn't provide one */
635 struct radv_pipeline_cache * mem_cache;
638 * use different counters so MSAA MRTs get consecutive surface indices,
639 * even if MASK is allocated in between.
641 uint32_t image_mrt_offset_counter;
642 uint32_t fmask_mrt_offset_counter;
643 struct list_head shader_slabs;
644 mtx_t shader_slab_mutex;
646 /* For detecting VM faults reported by dmesg. */
647 uint64_t dmesg_timestamp;
649 struct radv_device_extension_table enabled_extensions;
652 struct radv_device_memory {
653 struct radeon_winsys_bo *bo;
654 /* for dedicated allocations */
655 struct radv_image *image;
656 struct radv_buffer *buffer;
658 VkDeviceSize map_size;
664 struct radv_descriptor_range {
669 struct radv_descriptor_set {
670 const struct radv_descriptor_set_layout *layout;
673 struct radeon_winsys_bo *bo;
675 uint32_t *mapped_ptr;
676 struct radv_descriptor_range *dynamic_descriptors;
678 struct radeon_winsys_bo *descriptors[0];
681 struct radv_push_descriptor_set
683 struct radv_descriptor_set set;
687 struct radv_descriptor_pool_entry {
690 struct radv_descriptor_set *set;
693 struct radv_descriptor_pool {
694 struct radeon_winsys_bo *bo;
696 uint64_t current_offset;
699 uint8_t *host_memory_base;
700 uint8_t *host_memory_ptr;
701 uint8_t *host_memory_end;
703 uint32_t entry_count;
704 uint32_t max_entry_count;
705 struct radv_descriptor_pool_entry entries[0];
708 struct radv_descriptor_update_template_entry {
709 VkDescriptorType descriptor_type;
711 /* The number of descriptors to update */
712 uint32_t descriptor_count;
714 /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */
717 /* In dwords. Not valid/used for dynamic descriptors */
720 uint32_t buffer_offset;
722 /* Only valid for combined image samplers and samplers */
723 uint16_t has_sampler;
729 /* For push descriptors */
730 const uint32_t *immutable_samplers;
733 struct radv_descriptor_update_template {
734 uint32_t entry_count;
735 VkPipelineBindPoint bind_point;
736 struct radv_descriptor_update_template_entry entry[0];
740 struct radv_device * device;
743 VkBufferUsageFlags usage;
744 VkBufferCreateFlags flags;
747 struct radeon_winsys_bo * bo;
753 enum radv_dynamic_state_bits {
754 RADV_DYNAMIC_VIEWPORT = 1 << 0,
755 RADV_DYNAMIC_SCISSOR = 1 << 1,
756 RADV_DYNAMIC_LINE_WIDTH = 1 << 2,
757 RADV_DYNAMIC_DEPTH_BIAS = 1 << 3,
758 RADV_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
759 RADV_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
760 RADV_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
761 RADV_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
762 RADV_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
763 RADV_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
764 RADV_DYNAMIC_ALL = (1 << 10) - 1,
767 enum radv_cmd_dirty_bits {
768 /* Keep the dynamic state dirty bits in sync with
769 * enum radv_dynamic_state_bits */
770 RADV_CMD_DIRTY_DYNAMIC_VIEWPORT = 1 << 0,
771 RADV_CMD_DIRTY_DYNAMIC_SCISSOR = 1 << 1,
772 RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH = 1 << 2,
773 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS = 1 << 3,
774 RADV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS = 1 << 4,
775 RADV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS = 1 << 5,
776 RADV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK = 1 << 6,
777 RADV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK = 1 << 7,
778 RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE = 1 << 8,
779 RADV_CMD_DIRTY_DYNAMIC_DISCARD_RECTANGLE = 1 << 9,
780 RADV_CMD_DIRTY_DYNAMIC_ALL = (1 << 10) - 1,
781 RADV_CMD_DIRTY_PIPELINE = 1 << 10,
782 RADV_CMD_DIRTY_INDEX_BUFFER = 1 << 11,
783 RADV_CMD_DIRTY_FRAMEBUFFER = 1 << 12,
784 RADV_CMD_DIRTY_VERTEX_BUFFER = 1 << 13,
787 enum radv_cmd_flush_bits {
788 RADV_CMD_FLAG_INV_ICACHE = 1 << 0,
789 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
790 RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1,
791 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
792 RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2,
793 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
794 RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3,
795 /* Same as above, but only writes back and doesn't invalidate */
796 RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4,
797 /* Framebuffer caches */
798 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5,
799 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6,
800 RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7,
801 RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8,
802 /* Engine synchronization. */
803 RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9,
804 RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10,
805 RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11,
806 RADV_CMD_FLAG_VGT_FLUSH = 1 << 12,
808 RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB |
809 RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
810 RADV_CMD_FLAG_FLUSH_AND_INV_DB |
811 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META)
814 struct radv_vertex_binding {
815 struct radv_buffer * buffer;
819 struct radv_viewport_state {
821 VkViewport viewports[MAX_VIEWPORTS];
824 struct radv_scissor_state {
826 VkRect2D scissors[MAX_SCISSORS];
829 struct radv_discard_rectangle_state {
831 VkRect2D rectangles[MAX_DISCARD_RECTANGLES];
834 struct radv_dynamic_state {
836 * Bitmask of (1 << VK_DYNAMIC_STATE_*).
837 * Defines the set of saved dynamic state.
841 struct radv_viewport_state viewport;
843 struct radv_scissor_state scissor;
853 float blend_constants[4];
863 } stencil_compare_mask;
868 } stencil_write_mask;
875 struct radv_discard_rectangle_state discard_rectangle;
878 extern const struct radv_dynamic_state default_dynamic_state;
881 radv_get_debug_option_name(int id);
884 radv_get_perftest_option_name(int id);
887 * Attachment state when recording a renderpass instance.
889 * The clear value is valid only if there exists a pending clear.
891 struct radv_attachment_state {
892 VkImageAspectFlags pending_clear_aspects;
893 uint32_t cleared_views;
894 VkClearValue clear_value;
895 VkImageLayout current_layout;
898 struct radv_descriptor_state {
899 struct radv_descriptor_set *sets[MAX_SETS];
902 struct radv_push_descriptor_set push_set;
906 struct radv_cmd_state {
907 /* Vertex descriptors */
908 bool vb_prefetch_dirty;
915 struct radv_pipeline * pipeline;
916 struct radv_pipeline * emitted_pipeline;
917 struct radv_pipeline * compute_pipeline;
918 struct radv_pipeline * emitted_compute_pipeline;
919 struct radv_framebuffer * framebuffer;
920 struct radv_render_pass * pass;
921 const struct radv_subpass * subpass;
922 struct radv_dynamic_state dynamic;
923 struct radv_attachment_state * attachments;
924 VkRect2D render_area;
927 struct radv_buffer *index_buffer;
928 uint64_t index_offset;
930 uint32_t max_index_count;
932 int32_t last_index_type;
934 int32_t last_primitive_reset_en;
935 uint32_t last_primitive_reset_index;
936 enum radv_cmd_flush_bits flush_bits;
937 unsigned active_occlusion_queries;
940 uint32_t last_ia_multi_vgt_param;
942 uint32_t last_num_instances;
943 uint32_t last_first_instance;
944 uint32_t last_vertex_offset;
947 struct radv_cmd_pool {
948 VkAllocationCallbacks alloc;
949 struct list_head cmd_buffers;
950 struct list_head free_cmd_buffers;
951 uint32_t queue_family_index;
954 struct radv_cmd_buffer_upload {
958 struct radeon_winsys_bo *upload_bo;
959 struct list_head list;
962 enum radv_cmd_buffer_status {
963 RADV_CMD_BUFFER_STATUS_INVALID,
964 RADV_CMD_BUFFER_STATUS_INITIAL,
965 RADV_CMD_BUFFER_STATUS_RECORDING,
966 RADV_CMD_BUFFER_STATUS_EXECUTABLE,
967 RADV_CMD_BUFFER_STATUS_PENDING,
970 struct radv_cmd_buffer {
971 VK_LOADER_DATA _loader_data;
973 struct radv_device * device;
975 struct radv_cmd_pool * pool;
976 struct list_head pool_link;
978 VkCommandBufferUsageFlags usage_flags;
979 VkCommandBufferLevel level;
980 enum radv_cmd_buffer_status status;
981 struct radeon_winsys_cs *cs;
982 struct radv_cmd_state state;
983 struct radv_vertex_binding vertex_bindings[MAX_VBS];
984 uint32_t queue_family_index;
986 uint8_t push_constants[MAX_PUSH_CONSTANTS_SIZE];
987 uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS];
988 VkShaderStageFlags push_constant_stages;
989 struct radv_descriptor_set meta_push_descriptors;
991 struct radv_descriptor_state descriptors[VK_PIPELINE_BIND_POINT_RANGE_SIZE];
993 struct radv_cmd_buffer_upload upload;
995 uint32_t scratch_size_needed;
996 uint32_t compute_scratch_size_needed;
997 uint32_t esgs_ring_size_needed;
998 uint32_t gsvs_ring_size_needed;
999 bool tess_rings_needed;
1000 bool sample_positions_needed;
1002 VkResult record_result;
1004 int ring_offsets_idx; /* just used for verification */
1005 uint32_t gfx9_fence_offset;
1006 struct radeon_winsys_bo *gfx9_fence_bo;
1007 uint32_t gfx9_fence_idx;
1012 bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer);
1014 void si_init_compute(struct radv_cmd_buffer *cmd_buffer);
1015 void si_init_config(struct radv_cmd_buffer *cmd_buffer);
1017 void cik_create_gfx_config(struct radv_device *device);
1019 void si_write_viewport(struct radeon_winsys_cs *cs, int first_vp,
1020 int count, const VkViewport *viewports);
1021 void si_write_scissors(struct radeon_winsys_cs *cs, int first,
1022 int count, const VkRect2D *scissors,
1023 const VkViewport *viewports, bool can_use_guardband);
1024 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
1025 bool instanced_draw, bool indirect_draw,
1026 uint32_t draw_vertex_count);
1027 void si_cs_emit_write_event_eop(struct radeon_winsys_cs *cs,
1029 enum chip_class chip_class,
1031 unsigned event, unsigned event_flags,
1035 uint32_t new_fence);
1037 void si_emit_wait_fence(struct radeon_winsys_cs *cs,
1039 uint64_t va, uint32_t ref,
1041 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
1042 enum chip_class chip_class,
1043 uint32_t *fence_ptr, uint64_t va,
1045 enum radv_cmd_flush_bits flush_bits);
1046 void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer);
1047 void si_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, uint64_t va);
1048 void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer,
1049 uint64_t src_va, uint64_t dest_va,
1051 void si_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1053 void si_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va,
1054 uint64_t size, unsigned value);
1055 void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer);
1057 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer,
1060 unsigned *out_offset,
1063 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer,
1064 const struct radv_subpass *subpass,
1067 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer,
1068 unsigned size, unsigned alignmnet,
1069 const void *data, unsigned *out_offset);
1071 void radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer *cmd_buffer);
1072 void radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer);
1073 void radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer);
1074 void radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer);
1075 void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
1076 unsigned radv_cayman_get_maxdist(int log_samples);
1077 void radv_device_init_msaa(struct radv_device *device);
1078 void radv_set_depth_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1079 struct radv_image *image,
1080 VkClearDepthStencilValue ds_clear_value,
1081 VkImageAspectFlags aspects);
1082 void radv_set_color_clear_regs(struct radv_cmd_buffer *cmd_buffer,
1083 struct radv_image *image,
1085 uint32_t color_values[2]);
1086 void radv_set_dcc_need_cmask_elim_pred(struct radv_cmd_buffer *cmd_buffer,
1087 struct radv_image *image,
1089 uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer,
1090 struct radeon_winsys_bo *bo,
1091 uint64_t offset, uint64_t size, uint32_t value);
1092 void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer);
1093 bool radv_get_memory_fd(struct radv_device *device,
1094 struct radv_device_memory *memory,
1097 static inline struct radv_descriptor_state *
1098 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
1099 VkPipelineBindPoint bind_point)
1101 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ||
1102 bind_point == VK_PIPELINE_BIND_POINT_COMPUTE);
1103 return &cmd_buffer->descriptors[bind_point];
1107 * Takes x,y,z as exact numbers of invocations, instead of blocks.
1109 * Limitations: Can't call normal dispatch functions without binding or rebinding
1110 * the compute pipeline.
1112 void radv_unaligned_dispatch(
1113 struct radv_cmd_buffer *cmd_buffer,
1119 struct radeon_winsys_bo *bo;
1123 struct radv_shader_module;
1125 #define RADV_HASH_SHADER_IS_GEOM_COPY_SHADER (1 << 0)
1126 #define RADV_HASH_SHADER_SISCHED (1 << 1)
1127 #define RADV_HASH_SHADER_UNSAFE_MATH (1 << 2)
1129 radv_hash_shaders(unsigned char *hash,
1130 const VkPipelineShaderStageCreateInfo **stages,
1131 const struct radv_pipeline_layout *layout,
1132 const struct radv_pipeline_key *key,
1135 static inline gl_shader_stage
1136 vk_to_mesa_shader_stage(VkShaderStageFlagBits vk_stage)
1138 assert(__builtin_popcount(vk_stage) == 1);
1139 return ffs(vk_stage) - 1;
1142 static inline VkShaderStageFlagBits
1143 mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
1145 return (1 << mesa_stage);
1148 #define RADV_STAGE_MASK ((1 << MESA_SHADER_STAGES) - 1)
1150 #define radv_foreach_stage(stage, stage_bits) \
1151 for (gl_shader_stage stage, \
1152 __tmp = (gl_shader_stage)((stage_bits) & RADV_STAGE_MASK); \
1153 stage = __builtin_ffs(__tmp) - 1, __tmp; \
1154 __tmp &= ~(1 << (stage)))
1156 unsigned radv_format_meta_fs_key(VkFormat format);
1158 struct radv_multisample_state {
1160 uint32_t pa_sc_line_cntl;
1161 uint32_t pa_sc_mode_cntl_0;
1162 uint32_t pa_sc_mode_cntl_1;
1163 uint32_t pa_sc_aa_config;
1164 uint32_t pa_sc_aa_mask[2];
1165 unsigned num_samples;
1168 struct radv_prim_vertex_count {
1173 struct radv_vertex_elements_info {
1174 uint32_t rsrc_word3[MAX_VERTEX_ATTRIBS];
1175 uint32_t format_size[MAX_VERTEX_ATTRIBS];
1176 uint32_t binding[MAX_VERTEX_ATTRIBS];
1177 uint32_t offset[MAX_VERTEX_ATTRIBS];
1181 struct radv_ia_multi_vgt_param_helpers {
1183 bool partial_es_wave;
1184 uint8_t primgroup_size;
1185 bool wd_switch_on_eop;
1186 bool ia_switch_on_eoi;
1187 bool partial_vs_wave;
1190 #define SI_GS_PER_ES 128
1192 struct radv_pipeline {
1193 struct radv_device * device;
1194 struct radv_dynamic_state dynamic_state;
1196 struct radv_pipeline_layout * layout;
1198 bool needs_data_cache;
1199 bool need_indirect_descriptor_sets;
1200 struct radv_shader_variant * shaders[MESA_SHADER_STAGES];
1201 struct radv_shader_variant *gs_copy_shader;
1202 VkShaderStageFlags active_stages;
1204 struct radeon_winsys_cs cs;
1206 struct radv_vertex_elements_info vertex_elements;
1208 uint32_t binding_stride[MAX_VBS];
1210 uint32_t user_data_0[MESA_SHADER_STAGES];
1213 struct radv_multisample_state ms;
1214 uint32_t spi_baryc_cntl;
1215 bool prim_restart_enable;
1216 unsigned esgs_ring_size;
1217 unsigned gsvs_ring_size;
1218 uint32_t vtx_base_sgpr;
1219 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param;
1220 uint8_t vtx_emit_num;
1221 struct radv_prim_vertex_count prim_vertex_count;
1222 bool can_use_guardband;
1223 uint32_t needed_dynamic_state;
1228 unsigned scratch_bytes_per_wave;
1231 static inline bool radv_pipeline_has_gs(const struct radv_pipeline *pipeline)
1233 return pipeline->shaders[MESA_SHADER_GEOMETRY] ? true : false;
1236 static inline bool radv_pipeline_has_tess(const struct radv_pipeline *pipeline)
1238 return pipeline->shaders[MESA_SHADER_TESS_CTRL] ? true : false;
1241 struct ac_userdata_info *radv_lookup_user_sgpr(struct radv_pipeline *pipeline,
1242 gl_shader_stage stage,
1245 struct radv_shader_variant *radv_get_vertex_shader(struct radv_pipeline *pipeline);
1247 struct radv_graphics_pipeline_create_info {
1249 bool db_depth_clear;
1250 bool db_stencil_clear;
1251 bool db_depth_disable_expclear;
1252 bool db_stencil_disable_expclear;
1253 bool db_flush_depth_inplace;
1254 bool db_flush_stencil_inplace;
1255 bool db_resummarize;
1256 uint32_t custom_blend_mode;
1260 radv_graphics_pipeline_create(VkDevice device,
1261 VkPipelineCache cache,
1262 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1263 const struct radv_graphics_pipeline_create_info *extra,
1264 const VkAllocationCallbacks *alloc,
1265 VkPipeline *pPipeline);
1267 struct vk_format_description;
1268 uint32_t radv_translate_buffer_dataformat(const struct vk_format_description *desc,
1269 int first_non_void);
1270 uint32_t radv_translate_buffer_numformat(const struct vk_format_description *desc,
1271 int first_non_void);
1272 uint32_t radv_translate_colorformat(VkFormat format);
1273 uint32_t radv_translate_color_numformat(VkFormat format,
1274 const struct vk_format_description *desc,
1275 int first_non_void);
1276 uint32_t radv_colorformat_endian_swap(uint32_t colorformat);
1277 unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap);
1278 uint32_t radv_translate_dbformat(VkFormat format);
1279 uint32_t radv_translate_tex_dataformat(VkFormat format,
1280 const struct vk_format_description *desc,
1281 int first_non_void);
1282 uint32_t radv_translate_tex_numformat(VkFormat format,
1283 const struct vk_format_description *desc,
1284 int first_non_void);
1285 bool radv_format_pack_clear_color(VkFormat format,
1286 uint32_t clear_vals[2],
1287 VkClearColorValue *value);
1288 bool radv_is_colorbuffer_format_supported(VkFormat format, bool *blendable);
1289 bool radv_dcc_formats_compatible(VkFormat format1,
1292 struct radv_fmask_info {
1296 unsigned pitch_in_pixels;
1297 unsigned bank_height;
1298 unsigned slice_tile_max;
1299 unsigned tile_mode_index;
1300 unsigned tile_swizzle;
1303 struct radv_cmask_info {
1307 unsigned slice_tile_max;
1312 /* The original VkFormat provided by the client. This may not match any
1313 * of the actual surface formats.
1316 VkImageAspectFlags aspects;
1317 VkImageUsageFlags usage; /**< Superset of VkImageCreateInfo::usage. */
1318 struct ac_surf_info info;
1319 VkImageTiling tiling; /** VkImageCreateInfo::tiling */
1320 VkImageCreateFlags flags; /** VkImageCreateInfo::flags */
1325 unsigned queue_family_mask;
1329 /* Set when bound */
1330 struct radeon_winsys_bo *bo;
1331 VkDeviceSize offset;
1332 uint64_t dcc_offset;
1333 uint64_t htile_offset;
1334 bool tc_compatible_htile;
1335 struct radeon_surf surface;
1337 struct radv_fmask_info fmask;
1338 struct radv_cmask_info cmask;
1339 uint64_t clear_value_offset;
1340 uint64_t dcc_pred_offset;
1342 /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
1343 VkDeviceMemory owned_memory;
1346 /* Whether the image has a htile that is known consistent with the contents of
1348 bool radv_layout_has_htile(const struct radv_image *image,
1349 VkImageLayout layout,
1350 unsigned queue_mask);
1352 /* Whether the image has a htile that is known consistent with the contents of
1353 * the image and is allowed to be in compressed form.
1355 * If this is false reads that don't use the htile should be able to return
1358 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1359 VkImageLayout layout,
1360 unsigned queue_mask);
1362 bool radv_layout_can_fast_clear(const struct radv_image *image,
1363 VkImageLayout layout,
1364 unsigned queue_mask);
1366 bool radv_layout_dcc_compressed(const struct radv_image *image,
1367 VkImageLayout layout,
1368 unsigned queue_mask);
1371 radv_vi_dcc_enabled(const struct radv_image *image, unsigned level)
1373 return image->surface.dcc_size && level < image->surface.num_dcc_levels;
1377 radv_htile_enabled(const struct radv_image *image, unsigned level)
1379 return image->surface.htile_size && level == 0;
1382 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family);
1384 static inline uint32_t
1385 radv_get_layerCount(const struct radv_image *image,
1386 const VkImageSubresourceRange *range)
1388 return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
1389 image->info.array_size - range->baseArrayLayer : range->layerCount;
1392 static inline uint32_t
1393 radv_get_levelCount(const struct radv_image *image,
1394 const VkImageSubresourceRange *range)
1396 return range->levelCount == VK_REMAINING_MIP_LEVELS ?
1397 image->info.levels - range->baseMipLevel : range->levelCount;
1400 struct radeon_bo_metadata;
1402 radv_init_metadata(struct radv_device *device,
1403 struct radv_image *image,
1404 struct radeon_bo_metadata *metadata);
1406 struct radv_image_view {
1407 struct radv_image *image; /**< VkImageViewCreateInfo::image */
1408 struct radeon_winsys_bo *bo;
1410 VkImageViewType type;
1411 VkImageAspectFlags aspect_mask;
1413 uint32_t base_layer;
1414 uint32_t layer_count;
1416 uint32_t level_count;
1417 VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
1419 uint32_t descriptor[16];
1421 /* Descriptor for use as a storage image as opposed to a sampled image.
1422 * This has a few differences for cube maps (e.g. type).
1424 uint32_t storage_descriptor[16];
1427 struct radv_image_create_info {
1428 const VkImageCreateInfo *vk_info;
1430 bool no_metadata_planes;
1433 VkResult radv_image_create(VkDevice _device,
1434 const struct radv_image_create_info *info,
1435 const VkAllocationCallbacks* alloc,
1439 radv_image_from_gralloc(VkDevice device_h,
1440 const VkImageCreateInfo *base_info,
1441 const VkNativeBufferANDROID *gralloc_info,
1442 const VkAllocationCallbacks *alloc,
1443 VkImage *out_image_h);
1445 void radv_image_view_init(struct radv_image_view *view,
1446 struct radv_device *device,
1447 const VkImageViewCreateInfo* pCreateInfo);
1449 struct radv_buffer_view {
1450 struct radeon_winsys_bo *bo;
1452 uint64_t range; /**< VkBufferViewCreateInfo::range */
1455 void radv_buffer_view_init(struct radv_buffer_view *view,
1456 struct radv_device *device,
1457 const VkBufferViewCreateInfo* pCreateInfo);
1459 static inline struct VkExtent3D
1460 radv_sanitize_image_extent(const VkImageType imageType,
1461 const struct VkExtent3D imageExtent)
1463 switch (imageType) {
1464 case VK_IMAGE_TYPE_1D:
1465 return (VkExtent3D) { imageExtent.width, 1, 1 };
1466 case VK_IMAGE_TYPE_2D:
1467 return (VkExtent3D) { imageExtent.width, imageExtent.height, 1 };
1468 case VK_IMAGE_TYPE_3D:
1471 unreachable("invalid image type");
1475 static inline struct VkOffset3D
1476 radv_sanitize_image_offset(const VkImageType imageType,
1477 const struct VkOffset3D imageOffset)
1479 switch (imageType) {
1480 case VK_IMAGE_TYPE_1D:
1481 return (VkOffset3D) { imageOffset.x, 0, 0 };
1482 case VK_IMAGE_TYPE_2D:
1483 return (VkOffset3D) { imageOffset.x, imageOffset.y, 0 };
1484 case VK_IMAGE_TYPE_3D:
1487 unreachable("invalid image type");
1492 radv_image_extent_compare(const struct radv_image *image,
1493 const VkExtent3D *extent)
1495 if (extent->width != image->info.width ||
1496 extent->height != image->info.height ||
1497 extent->depth != image->info.depth)
1502 struct radv_sampler {
1506 struct radv_color_buffer_info {
1507 uint64_t cb_color_base;
1508 uint64_t cb_color_cmask;
1509 uint64_t cb_color_fmask;
1510 uint64_t cb_dcc_base;
1511 uint32_t cb_color_pitch;
1512 uint32_t cb_color_slice;
1513 uint32_t cb_color_view;
1514 uint32_t cb_color_info;
1515 uint32_t cb_color_attrib;
1516 uint32_t cb_color_attrib2;
1517 uint32_t cb_dcc_control;
1518 uint32_t cb_color_cmask_slice;
1519 uint32_t cb_color_fmask_slice;
1522 struct radv_ds_buffer_info {
1523 uint64_t db_z_read_base;
1524 uint64_t db_stencil_read_base;
1525 uint64_t db_z_write_base;
1526 uint64_t db_stencil_write_base;
1527 uint64_t db_htile_data_base;
1528 uint32_t db_depth_info;
1530 uint32_t db_stencil_info;
1531 uint32_t db_depth_view;
1532 uint32_t db_depth_size;
1533 uint32_t db_depth_slice;
1534 uint32_t db_htile_surface;
1535 uint32_t pa_su_poly_offset_db_fmt_cntl;
1536 uint32_t db_z_info2;
1537 uint32_t db_stencil_info2;
1541 struct radv_attachment_info {
1543 struct radv_color_buffer_info cb;
1544 struct radv_ds_buffer_info ds;
1546 struct radv_image_view *attachment;
1549 struct radv_framebuffer {
1554 uint32_t attachment_count;
1555 struct radv_attachment_info attachments[0];
1558 struct radv_subpass_barrier {
1559 VkPipelineStageFlags src_stage_mask;
1560 VkAccessFlags src_access_mask;
1561 VkAccessFlags dst_access_mask;
1564 struct radv_subpass {
1565 uint32_t input_count;
1566 uint32_t color_count;
1567 VkAttachmentReference * input_attachments;
1568 VkAttachmentReference * color_attachments;
1569 VkAttachmentReference * resolve_attachments;
1570 VkAttachmentReference depth_stencil_attachment;
1572 /** Subpass has at least one resolve attachment */
1575 struct radv_subpass_barrier start_barrier;
1580 struct radv_render_pass_attachment {
1583 VkAttachmentLoadOp load_op;
1584 VkAttachmentLoadOp stencil_load_op;
1585 VkImageLayout initial_layout;
1586 VkImageLayout final_layout;
1590 struct radv_render_pass {
1591 uint32_t attachment_count;
1592 uint32_t subpass_count;
1593 VkAttachmentReference * subpass_attachments;
1594 struct radv_render_pass_attachment * attachments;
1595 struct radv_subpass_barrier end_barrier;
1596 struct radv_subpass subpasses[0];
1599 VkResult radv_device_init_meta(struct radv_device *device);
1600 void radv_device_finish_meta(struct radv_device *device);
1602 struct radv_query_pool {
1603 struct radeon_winsys_bo *bo;
1605 uint32_t availability_offset;
1608 uint32_t pipeline_stats_mask;
1611 struct radv_semaphore {
1612 /* use a winsys sem for non-exportable */
1613 struct radeon_winsys_sem *sem;
1615 uint32_t temp_syncobj;
1618 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1620 const VkSemaphore *wait_sems,
1621 int num_signal_sems,
1622 const VkSemaphore *signal_sems,
1624 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info);
1626 void radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1627 VkPipelineBindPoint bind_point,
1628 struct radv_descriptor_set *set,
1632 radv_update_descriptor_sets(struct radv_device *device,
1633 struct radv_cmd_buffer *cmd_buffer,
1634 VkDescriptorSet overrideSet,
1635 uint32_t descriptorWriteCount,
1636 const VkWriteDescriptorSet *pDescriptorWrites,
1637 uint32_t descriptorCopyCount,
1638 const VkCopyDescriptorSet *pDescriptorCopies);
1641 radv_update_descriptor_set_with_template(struct radv_device *device,
1642 struct radv_cmd_buffer *cmd_buffer,
1643 struct radv_descriptor_set *set,
1644 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
1647 void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
1648 VkPipelineBindPoint pipelineBindPoint,
1649 VkPipelineLayout _layout,
1651 uint32_t descriptorWriteCount,
1652 const VkWriteDescriptorSet *pDescriptorWrites);
1654 void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
1655 struct radv_image *image, uint32_t value);
1656 void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
1657 struct radv_image *image, uint32_t value);
1660 struct radeon_winsys_fence *fence;
1665 uint32_t temp_syncobj;
1668 struct radeon_winsys_sem;
1670 #define RADV_DEFINE_HANDLE_CASTS(__radv_type, __VkType) \
1672 static inline struct __radv_type * \
1673 __radv_type ## _from_handle(__VkType _handle) \
1675 return (struct __radv_type *) _handle; \
1678 static inline __VkType \
1679 __radv_type ## _to_handle(struct __radv_type *_obj) \
1681 return (__VkType) _obj; \
1684 #define RADV_DEFINE_NONDISP_HANDLE_CASTS(__radv_type, __VkType) \
1686 static inline struct __radv_type * \
1687 __radv_type ## _from_handle(__VkType _handle) \
1689 return (struct __radv_type *)(uintptr_t) _handle; \
1692 static inline __VkType \
1693 __radv_type ## _to_handle(struct __radv_type *_obj) \
1695 return (__VkType)(uintptr_t) _obj; \
1698 #define RADV_FROM_HANDLE(__radv_type, __name, __handle) \
1699 struct __radv_type *__name = __radv_type ## _from_handle(__handle)
1701 RADV_DEFINE_HANDLE_CASTS(radv_cmd_buffer, VkCommandBuffer)
1702 RADV_DEFINE_HANDLE_CASTS(radv_device, VkDevice)
1703 RADV_DEFINE_HANDLE_CASTS(radv_instance, VkInstance)
1704 RADV_DEFINE_HANDLE_CASTS(radv_physical_device, VkPhysicalDevice)
1705 RADV_DEFINE_HANDLE_CASTS(radv_queue, VkQueue)
1707 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_cmd_pool, VkCommandPool)
1708 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer, VkBuffer)
1709 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_buffer_view, VkBufferView)
1710 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_pool, VkDescriptorPool)
1711 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set, VkDescriptorSet)
1712 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_set_layout, VkDescriptorSetLayout)
1713 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_descriptor_update_template, VkDescriptorUpdateTemplateKHR)
1714 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_device_memory, VkDeviceMemory)
1715 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_fence, VkFence)
1716 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_event, VkEvent)
1717 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_framebuffer, VkFramebuffer)
1718 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image, VkImage)
1719 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_image_view, VkImageView);
1720 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_cache, VkPipelineCache)
1721 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline, VkPipeline)
1722 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_pipeline_layout, VkPipelineLayout)
1723 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_query_pool, VkQueryPool)
1724 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_render_pass, VkRenderPass)
1725 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_sampler, VkSampler)
1726 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_shader_module, VkShaderModule)
1727 RADV_DEFINE_NONDISP_HANDLE_CASTS(radv_semaphore, VkSemaphore)
1729 #endif /* RADV_PRIVATE_H */