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26 * \file common_interface.c
27 * Platform independent interface glue.
29 * \author Ian Romanick <idr@us.ibm.com>
35 #include "pciaccess.h"
36 #include "pciaccess_private.h"
41 #if __BYTE_ORDER == __BIG_ENDIAN
42 # define LETOH_16(x) bswap_16(x)
43 # define HTOLE_16(x) bswap_16(x)
44 # define LETOH_32(x) bswap_32(x)
45 # define HTOLE_32(x) bswap_32(x)
47 # define LETOH_16(x) (x)
48 # define HTOLE_16(x) (x)
49 # define LETOH_32(x) (x)
50 # define HTOLE_32(x) (x)
55 #include <sys/endian.h>
57 #define LETOH_16(x) le16toh(x)
58 #define HTOLE_16(x) htole16(x)
59 #define LETOH_32(x) le32toh(x)
60 #define HTOLE_32(x) htole32(x)
65 * Read a device's expansion ROM.
67 * Reads the device's expansion ROM and stores the data in the memory pointed
68 * to by \c buffer. The buffer must be at least \c pci_device::rom_size
71 * \param dev Device whose expansion ROM is to be read.
72 * \param buffer Memory in which to store the ROM.
75 * Zero on success or an \c errno value on failure.
78 pci_device_read_rom( struct pci_device * dev, void * buffer )
80 if ( (dev == NULL) || (buffer == NULL) ) {
85 return (pci_sys->methods->read_rom)( dev, buffer );
90 * Probe a PCI device to learn information about the device.
92 * Probes a PCI device to learn various information about the device. Before
93 * calling this function, the only public fields in the \c pci_device
94 * structure that have valid values are \c pci_device::domain,
95 * \c pci_device::bus, \c pci_device::dev, and \c pci_device::func.
97 * \param dev Device to be probed.
100 * Zero on succes or an \c errno value on failure.
103 pci_device_probe( struct pci_device * dev )
110 return (pci_sys->methods->probe)( dev );
115 * Map the specified BAR so that it can be accessed by the CPU.
117 * Maps the specified BAR for acces by the processor. The pointer to the
118 * mapped region is stored in the \c pci_mem_region::memory pointer for the
121 * \param dev Device whose memory region is to be mapped.
122 * \param region Region, on the range [0, 5], that is to be mapped.
123 * \param write_enable Map for writing (non-zero).
126 * Zero on success or an \c errno value on failure.
128 * \sa pci_device_unmap_region
131 pci_device_map_region( struct pci_device * dev, unsigned region,
138 if ( (region > 5) || (dev->regions[ region ].size == 0) ) {
142 if ( dev->regions[ region ].memory != NULL ) {
146 return (pci_sys->methods->map)( dev, region, write_enable );
151 * Unmap the specified BAR so that it can no longer be accessed by the CPU.
153 * Unmaps the specified BAR that was previously mapped via
154 * \c pci_device_map_region.
156 * \param dev Device whose memory region is to be mapped.
157 * \param region Region, on the range [0, 5], that is to be mapped.
160 * Zero on success or an \c errno value on failure.
162 * \sa pci_device_map_region
165 pci_device_unmap_region( struct pci_device * dev, unsigned region )
171 if ( (region > 5) || (dev->regions[ region ].size == 0) ) {
175 if ( dev->regions[ region ].memory == NULL ) {
179 return (pci_sys->methods->unmap)( dev, region );
184 * Read arbitrary bytes from device's PCI config space
186 * Reads data from the device's PCI configuration space. As with the system
187 * read command, less data may be returned, without an error, than was
188 * requested. This is particuarly the case if a non-root user tries to read
189 * beyond the first 64-bytes of configuration space.
191 * \param dev Device whose PCI configuration data is to be read.
192 * \param data Location to store the data
193 * \param offset Initial byte offset to read
194 * \param size Total number of bytes to read
195 * \param bytes_read Location to store the actual number of bytes read. This
196 * pointer may be \c NULL.
199 * Zero on success or an errno value on failure.
202 * Data read from PCI configuartion space using this routine is \b not
203 * byte-swapped to the host's byte order. PCI configuration data is always
204 * stored in little-endian order, and that is what this routine returns.
207 pci_device_cfg_read( struct pci_device * dev, void * data,
208 pciaddr_t offset, pciaddr_t size,
209 pciaddr_t * bytes_read )
213 if ( (dev == NULL) || (data == NULL) ) {
217 return pci_sys->methods->read( dev, data, offset, size,
219 ? & scratch : bytes_read );
224 pci_device_cfg_read_u8( struct pci_device * dev, uint8_t * data,
228 int err = pci_device_cfg_read( dev, data, offset, 1, & bytes );
230 if ( (err == 0) && (bytes != 1) ) {
239 pci_device_cfg_read_u16( struct pci_device * dev, uint16_t * data,
243 int err = pci_device_cfg_read( dev, data, offset, 2, & bytes );
245 if ( (err == 0) && (bytes != 2) ) {
249 *data = LETOH_16( *data );
255 pci_device_cfg_read_u32( struct pci_device * dev, uint32_t * data,
259 int err = pci_device_cfg_read( dev, data, offset, 4, & bytes );
261 if ( (err == 0) && (bytes != 4) ) {
265 *data = LETOH_32( *data );
271 * Write arbitrary bytes to device's PCI config space
273 * Writess data to the device's PCI configuration space. As with the system
274 * write command, less data may be written, without an error, than was
277 * \param dev Device whose PCI configuration data is to be written.
278 * \param data Location of the source data
279 * \param offset Initial byte offset to write
280 * \param size Total number of bytes to write
281 * \param bytes_read Location to store the actual number of bytes written.
282 * This pointer may be \c NULL.
285 * Zero on success or an errno value on failure.
288 * Data written to PCI configuartion space using this routine is \b not
289 * byte-swapped from the host's byte order. PCI configuration data is always
290 * stored in little-endian order, so data written with this routine should be
291 * put in that order in advance.
294 pci_device_cfg_write( struct pci_device * dev, const void * data,
295 pciaddr_t offset, pciaddr_t size,
296 pciaddr_t * bytes_written )
300 if ( (dev == NULL) || (data == NULL) ) {
304 return pci_sys->methods->write( dev, data, offset, size,
305 (bytes_written == NULL)
306 ? & scratch : bytes_written );
311 pci_device_cfg_write_u8( struct pci_device * dev, const uint8_t * data,
315 int err = pci_device_cfg_write( dev, data, offset, 1, & bytes );
317 if ( (err == 0) && (bytes != 1) ) {
327 pci_device_cfg_write_u16( struct pci_device * dev, const uint16_t * data,
331 const uint16_t temp = HTOLE_16( *data );
332 int err = pci_device_cfg_write( dev, & temp, offset, 2, & bytes );
334 if ( (err == 0) && (bytes != 2) ) {
344 pci_device_cfg_write_u32( struct pci_device * dev, const uint32_t * data,
348 const uint32_t temp = HTOLE_32( *data );
349 int err = pci_device_cfg_write( dev, & temp, offset, 4, & bytes );
351 if ( (err == 0) && (bytes != 4) ) {
361 pci_device_cfg_write_bits( struct pci_device * dev, uint32_t mask,
362 uint32_t data, pciaddr_t offset )
367 err = pci_device_cfg_read_u32( dev, & temp, offset );
372 err = pci_device_cfg_write_u32( dev, & temp, offset );