2 * (C) Copyright Eric Anholt 2006
3 * (C) Copyright IBM Corporation 2006
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
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11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
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17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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23 * DEALINGS IN THE SOFTWARE.
29 * Access the kernel PCI support using /dev/pci's ioctl and mmap interface.
31 * \author Eric Anholt <eric@anholt.net>
40 #include <sys/types.h>
41 #include <sys/param.h>
42 #include <sys/pciio.h>
44 #include <sys/memrange.h>
47 #include "pciaccess.h"
48 #include "pciaccess_private.h"
50 #define PCIC_DISPLAY 0x03
51 #define PCIS_DISPLAY_VGA 0x00
52 #define PCIS_DISPLAY_XGA 0x01
53 #define PCIS_DISPLAY_3D 0x02
54 #define PCIS_DISPLAY_OTHER 0x80
56 /* Registers taken from pcireg.h */
57 #define PCIR_COMMAND 0x04
58 #define PCIM_CMD_PORTEN 0x0001
59 #define PCIM_CMD_MEMEN 0x0002
60 #define PCIR_BIOS 0x30
61 #define PCIM_BIOS_ENABLE 0x01
62 #define PCIM_BIOS_ADDR_MASK 0xfffff800
64 #define PCIR_BARS 0x10
65 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4)
66 #define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE)
67 #define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE)
68 #define PCIM_BAR_MEM_TYPE 0x00000006
69 #define PCIM_BAR_MEM_64 4
70 #define PCIM_BAR_MEM_PREFETCH 0x00000008
71 #define PCIM_BAR_SPACE 0x00000001
72 #define PCIM_BAR_MEM_SPACE 0
73 #define PCIM_BAR_IO_SPACE 1
76 * FreeBSD private pci_system structure that extends the base pci_system
79 * It is initialized once and used as a global, just as pci_system is used.
82 struct freebsd_pci_system {
83 /* This must be the first entry in the structure, as pci_system_cleanup()
86 struct pci_system pci_sys;
88 int pcidev; /**< fd for /dev/pci */
92 * Map a memory region for a device using /dev/mem.
94 * \param dev Device whose memory region is to be mapped.
95 * \param map Parameters of the mapping that is to be created.
98 * Zero on success or an \c errno value on failure.
101 pci_device_freebsd_map_range(struct pci_device *dev,
102 struct pci_device_mapping *map)
104 const int prot = ((map->flags & PCI_DEV_MAP_FLAG_WRITABLE) != 0)
105 ? (PROT_READ | PROT_WRITE) : PROT_READ;
106 struct mem_range_desc mrd;
107 struct mem_range_op mro;
111 fd = open("/dev/mem", O_RDWR);
115 map->memory = mmap(NULL, map->size, prot, MAP_SHARED, fd, map->base);
117 if (map->memory == MAP_FAILED) {
121 mrd.mr_base = map->base;
122 mrd.mr_len = map->size;
123 strncpy(mrd.mr_owner, "pciaccess", sizeof(mrd.mr_owner));
124 if (map->flags & PCI_DEV_MAP_FLAG_CACHABLE)
125 mrd.mr_flags = MDF_WRITEBACK;
126 else if (map->flags & PCI_DEV_MAP_FLAG_WRITE_COMBINE)
127 mrd.mr_flags = MDF_WRITECOMBINE;
129 mrd.mr_flags = MDF_UNCACHEABLE;
131 mro.mo_arg[0] = MEMRANGE_SET_UPDATE;
133 /* No need to set an MTRR if it's the default mode. */
134 if (mrd.mr_flags != MDF_UNCACHEABLE) {
135 if (ioctl(fd, MEMRANGE_SET, &mro)) {
136 fprintf(stderr, "failed to set mtrr: %s\n", strerror(errno));
146 pci_device_freebsd_unmap_range( struct pci_device *dev,
147 struct pci_device_mapping *map )
149 struct mem_range_desc mrd;
150 struct mem_range_op mro;
153 if ((map->flags & PCI_DEV_MAP_FLAG_CACHABLE) ||
154 (map->flags & PCI_DEV_MAP_FLAG_WRITE_COMBINE))
156 fd = open("/dev/mem", O_RDWR);
158 mrd.mr_base = map->base;
159 mrd.mr_len = map->size;
160 strncpy(mrd.mr_owner, "pciaccess", sizeof(mrd.mr_owner));
161 mrd.mr_flags = MDF_UNCACHEABLE;
163 mro.mo_arg[0] = MEMRANGE_SET_REMOVE;
165 if (ioctl(fd, MEMRANGE_SET, &mro)) {
166 fprintf(stderr, "failed to unset mtrr: %s\n", strerror(errno));
171 fprintf(stderr, "Failed to open /dev/mem\n");
175 return pci_device_generic_unmap_range(dev, map);
179 pci_device_freebsd_read( struct pci_device * dev, void * data,
180 pciaddr_t offset, pciaddr_t size,
181 pciaddr_t * bytes_read )
185 #if HAVE_PCI_IO_PC_DOMAIN
186 io.pi_sel.pc_domain = dev->domain;
188 io.pi_sel.pc_bus = dev->bus;
189 io.pi_sel.pc_dev = dev->dev;
190 io.pi_sel.pc_func = dev->func;
194 int toread = (size < 4) ? size : 4;
196 /* Only power of two allowed. */
201 io.pi_width = toread;
203 if ( ioctl( freebsd_pci_sys->pcidev, PCIOCREAD, &io ) < 0 )
206 memcpy(data, &io.pi_data, toread );
209 data = (char *)data + toread;
211 *bytes_read += toread;
219 pci_device_freebsd_write( struct pci_device * dev, const void * data,
220 pciaddr_t offset, pciaddr_t size,
221 pciaddr_t * bytes_written )
225 #if HAVE_PCI_IO_PC_DOMAIN
226 io.pi_sel.pc_domain = dev->domain;
228 io.pi_sel.pc_bus = dev->bus;
229 io.pi_sel.pc_dev = dev->dev;
230 io.pi_sel.pc_func = dev->func;
234 int towrite = (size < 4 ? size : 4);
236 /* Only power of two allowed. */
241 io.pi_width = towrite;
242 memcpy( &io.pi_data, data, towrite );
244 if ( ioctl( freebsd_pci_sys->pcidev, PCIOCWRITE, &io ) < 0 )
248 data = (char *)data + towrite;
250 *bytes_written += towrite;
257 * Read a VGA rom using the 0xc0000 mapping.
259 * This function should be extended to handle access through PCI resources,
260 * which should be more reliable when available.
263 pci_device_freebsd_read_rom( struct pci_device * dev, void * buffer )
265 struct pci_device_private *priv = (struct pci_device_private *) dev;
272 if ( ( dev->device_class & 0x00ffff00 ) !=
273 ( ( PCIC_DISPLAY << 16 ) | ( PCIS_DISPLAY_VGA << 8 ) ) )
278 if (priv->rom_base == 0) {
279 #if defined(__amd64__) || defined(__i386__)
286 rom_base = priv->rom_base;
289 pci_device_cfg_read_u16( dev, ®, PCIR_COMMAND );
290 pci_device_cfg_write_u16( dev, reg | PCIM_CMD_MEMEN, PCIR_COMMAND );
291 pci_device_cfg_read_u32( dev, &rom, PCIR_BIOS );
292 pci_device_cfg_write_u32( dev, rom | PCIM_BIOS_ENABLE, PCIR_BIOS );
295 printf("Using rom_base = 0x%lx\n", (long)rom_base);
296 memfd = open( "/dev/mem", O_RDONLY );
300 bios = mmap( NULL, dev->rom_size, PROT_READ, 0, memfd, rom_base );
301 if ( bios == MAP_FAILED ) {
306 memcpy( buffer, bios, dev->rom_size );
308 munmap( bios, dev->rom_size );
312 pci_device_cfg_write_u32( dev, PCIR_BIOS, rom );
313 pci_device_cfg_write_u16( dev, PCIR_COMMAND, reg );
319 /** Returns the number of regions (base address registers) the device has */
322 pci_device_freebsd_get_num_regions( struct pci_device * dev )
324 struct pci_device_private *priv = (struct pci_device_private *) dev;
326 switch (priv->header_type) {
334 printf("unknown header type %02x\n", priv->header_type);
342 pci_device_freebsd_probe( struct pci_device * dev )
344 struct pci_device_private *priv = (struct pci_device_private *) dev;
345 struct pci_bar_io bar;
349 #if HAVE_PCI_IO_PC_DOMAIN
350 bar.pbi_sel.pc_domain = dev->domain;
352 bar.pbi_sel.pc_bus = dev->bus;
353 bar.pbi_sel.pc_dev = dev->dev;
354 bar.pbi_sel.pc_func = dev->func;
357 /* Many of the fields were filled in during initial device enumeration.
358 * At this point, we need to fill in regions, rom_size, and irq.
361 err = pci_device_cfg_read_u8( dev, &irq, 60 );
366 for (i = 0; i < pci_device_freebsd_get_num_regions( dev ); i++) {
367 bar.pbi_reg = PCIR_BAR(i);
368 if ( ioctl( freebsd_pci_sys->pcidev, PCIOCGETBAR, &bar ) < 0 )
371 if (PCI_BAR_IO(bar.pbi_base))
372 dev->regions[i].is_IO = 1;
374 if ((bar.pbi_base & PCIM_BAR_MEM_TYPE) == PCIM_BAR_MEM_64)
375 dev->regions[i].is_64 = 1;
377 if (bar.pbi_base & PCIM_BAR_MEM_PREFETCH)
378 dev->regions[i].is_prefetchable = 1;
380 dev->regions[i].base_addr = bar.pbi_base & ~((uint64_t)0xf);
381 dev->regions[i].size = bar.pbi_length;
384 /* If it's a VGA device, set up the rom size for read_rom using the
387 if ((dev->device_class & 0x00ffff00) ==
388 ((PCIC_DISPLAY << 16) | (PCIS_DISPLAY_VGA << 8))) {
389 dev->rom_size = 64 * 1024;
397 /** Masks out the flag bigs of the base address register value */
399 get_map_base( uint32_t val )
407 /** Returns the size of a region based on the all-ones test value */
409 get_test_val_size( uint32_t testval )
414 /* Mask out the flag bits */
415 testval = get_map_base( testval );
417 return 1 << (ffs(testval) - 1);
421 * Sets the address and size information for the region from config space
424 * This would be much better provided by a kernel interface.
426 * \return 0 on success, or an errno value.
429 pci_device_freebsd_get_region_info( struct pci_device * dev, int region,
432 uint32_t addr, testval;
436 /* Get the base address */
437 err = pci_device_cfg_read_u32( dev, &addr, bar );
442 * We are going to be doing evil things to the registers here
443 * so disable them via the command register first.
445 err = pci_device_cfg_read_u16( dev, &cmd, PCIR_COMMAND );
449 err = pci_device_cfg_write_u16( dev,
450 cmd & ~(PCI_BAR_MEM(addr) ? PCIM_CMD_MEMEN : PCIM_CMD_PORTEN),
455 /* Test write all ones to the register, then restore it. */
456 err = pci_device_cfg_write_u32( dev, 0xffffffff, bar );
459 err = pci_device_cfg_read_u32( dev, &testval, bar );
462 err = pci_device_cfg_write_u32( dev, addr, bar );
466 /* Restore the command register */
467 err = pci_device_cfg_write_u16( dev, cmd, PCIR_COMMAND );
472 dev->regions[region].is_IO = 1;
474 dev->regions[region].is_64 = 1;
476 dev->regions[region].is_prefetchable = 1;
479 dev->regions[region].size = get_test_val_size( testval );
480 printf("size = 0x%lx\n", (long)dev->regions[region].size);
482 /* Set the base address value */
483 if (dev->regions[region].is_64) {
486 err = pci_device_cfg_read_u32( dev, &top, bar + 4 );
490 dev->regions[region].base_addr = ((uint64_t)top << 32) |
493 dev->regions[region].base_addr = get_map_base(addr);
500 pci_device_freebsd_probe( struct pci_device * dev )
502 struct pci_device_private *priv = (struct pci_device_private *) dev;
507 /* Many of the fields were filled in during initial device enumeration.
508 * At this point, we need to fill in regions, rom_size, and irq.
511 err = pci_device_cfg_read_u8( dev, &irq, 60 );
517 for (i = 0; i < pci_device_freebsd_get_num_regions( dev ); i++) {
518 pci_device_freebsd_get_region_info( dev, i, bar );
519 if (dev->regions[i].is_64) {
526 /* If it's a VGA device, set up the rom size for read_rom */
527 if ((dev->device_class & 0x00ffff00) ==
528 ((PCIC_DISPLAY << 16) | (PCIS_DISPLAY_VGA << 8)))
530 err = pci_device_cfg_read_u32( dev, ®, PCIR_BIOS );
535 dev->rom_size = 0x10000;
539 err = pci_device_cfg_write_u32( dev, ~PCIM_BIOS_ENABLE, PCIR_BIOS );
542 pci_device_cfg_read_u32( dev, &size, PCIR_BIOS );
543 pci_device_cfg_write_u32( dev, reg, PCIR_BIOS );
545 if ((reg & PCIM_BIOS_ADDR_MASK) != 0) {
546 priv->rom_base = (reg & PCIM_BIOS_ADDR_MASK);
547 dev->rom_size = -(size & PCIM_BIOS_ADDR_MASK);
557 pci_system_freebsd_destroy(void)
559 close(freebsd_pci_sys->pcidev);
560 free(freebsd_pci_sys->pci_sys.devices);
561 freebsd_pci_sys = NULL;
564 static const struct pci_system_methods freebsd_pci_methods = {
565 .destroy = pci_system_freebsd_destroy,
566 .destroy_device = NULL, /* nothing to do for this */
567 .read_rom = pci_device_freebsd_read_rom,
568 .probe = pci_device_freebsd_probe,
569 .map_range = pci_device_freebsd_map_range,
570 .unmap_range = pci_device_freebsd_unmap_range,
571 .read = pci_device_freebsd_read,
572 .write = pci_device_freebsd_write,
573 .fill_capabilities = pci_fill_capabilities_generic,
577 * Attempt to access the FreeBSD PCI interface.
580 pci_system_freebsd_create( void )
582 struct pci_conf_io pciconfio;
583 struct pci_conf pciconf[255];
587 /* Try to open the PCI device */
588 pcidev = open( "/dev/pci", O_RDWR );
592 freebsd_pci_sys = calloc( 1, sizeof( struct freebsd_pci_system ) );
593 if ( freebsd_pci_sys == NULL ) {
597 pci_sys = &freebsd_pci_sys->pci_sys;
599 pci_sys->methods = & freebsd_pci_methods;
600 freebsd_pci_sys->pcidev = pcidev;
602 /* Probe the list of devices known by the system */
603 bzero( &pciconfio, sizeof( struct pci_conf_io ) );
604 pciconfio.match_buf_len = sizeof(pciconf);
605 pciconfio.matches = pciconf;
607 if ( ioctl( pcidev, PCIOCGETCONF, &pciconfio ) == -1) {
613 if (pciconfio.status == PCI_GETCONF_ERROR ) {
619 /* Translate the list of devices into pciaccess's format. */
620 pci_sys->num_devices = pciconfio.num_matches;
621 pci_sys->devices = calloc( pciconfio.num_matches,
622 sizeof( struct pci_device_private ) );
624 for ( i = 0; i < pciconfio.num_matches; i++ ) {
625 struct pci_conf *p = &pciconf[ i ];
627 #if HAVE_PCI_IO_PC_DOMAIN
628 pci_sys->devices[ i ].base.domain = p->pc_sel.pc_domain;
630 pci_sys->devices[ i ].base.domain = 0;
632 pci_sys->devices[ i ].base.bus = p->pc_sel.pc_bus;
633 pci_sys->devices[ i ].base.dev = p->pc_sel.pc_dev;
634 pci_sys->devices[ i ].base.func = p->pc_sel.pc_func;
635 pci_sys->devices[ i ].base.vendor_id = p->pc_vendor;
636 pci_sys->devices[ i ].base.device_id = p->pc_device;
637 pci_sys->devices[ i ].base.subvendor_id = p->pc_subvendor;
638 pci_sys->devices[ i ].base.subdevice_id = p->pc_subdevice;
639 pci_sys->devices[ i ].base.revision = p->pc_revid;
640 pci_sys->devices[ i ].base.device_class = (uint32_t)p->pc_class << 16 |
641 (uint32_t)p->pc_subclass << 8 | (uint32_t)p->pc_progif;
642 pci_sys->devices[ i ].header_type = p->pc_hdr & 0x7f;