1 /**************************************************************************
3 * Copyright 2007-2008 VMware, Inc.
5 * Copyright 2009-2010 VMware, Inc. All rights Reserved.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
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12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
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20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **************************************************************************/
30 * TGSI interpreter/executor.
32 * Flow control information:
34 * Since we operate on 'quads' (4 pixels or 4 vertices in parallel)
35 * flow control statements (IF/ELSE/ENDIF, LOOP/ENDLOOP) require special
36 * care since a condition may be true for some quad components but false
37 * for other components.
39 * We basically execute all statements (even if they're in the part of
40 * an IF/ELSE clause that's "not taken") and use a special mask to
41 * control writing to destination registers. This is the ExecMask.
44 * The ExecMask is computed from three other masks (CondMask, LoopMask and
45 * ContMask) which are controlled by the flow control instructions (namely:
46 * (IF/ELSE/ENDIF, LOOP/ENDLOOP and CONT).
54 #include "pipe/p_compiler.h"
55 #include "pipe/p_state.h"
56 #include "pipe/p_shader_tokens.h"
57 #include "tgsi/tgsi_dump.h"
58 #include "tgsi/tgsi_parse.h"
59 #include "tgsi/tgsi_util.h"
60 #include "tgsi_exec.h"
61 #include "util/u_memory.h"
62 #include "util/u_math.h"
65 #define DEBUG_EXECUTION 0
70 #define TILE_TOP_LEFT 0
71 #define TILE_TOP_RIGHT 1
72 #define TILE_BOTTOM_LEFT 2
73 #define TILE_BOTTOM_RIGHT 3
76 micro_abs(union tgsi_exec_channel *dst,
77 const union tgsi_exec_channel *src)
79 dst->f[0] = fabsf(src->f[0]);
80 dst->f[1] = fabsf(src->f[1]);
81 dst->f[2] = fabsf(src->f[2]);
82 dst->f[3] = fabsf(src->f[3]);
86 micro_arl(union tgsi_exec_channel *dst,
87 const union tgsi_exec_channel *src)
89 dst->i[0] = (int)floorf(src->f[0]);
90 dst->i[1] = (int)floorf(src->f[1]);
91 dst->i[2] = (int)floorf(src->f[2]);
92 dst->i[3] = (int)floorf(src->f[3]);
96 micro_arr(union tgsi_exec_channel *dst,
97 const union tgsi_exec_channel *src)
99 dst->i[0] = (int)floorf(src->f[0] + 0.5f);
100 dst->i[1] = (int)floorf(src->f[1] + 0.5f);
101 dst->i[2] = (int)floorf(src->f[2] + 0.5f);
102 dst->i[3] = (int)floorf(src->f[3] + 0.5f);
106 micro_ceil(union tgsi_exec_channel *dst,
107 const union tgsi_exec_channel *src)
109 dst->f[0] = ceilf(src->f[0]);
110 dst->f[1] = ceilf(src->f[1]);
111 dst->f[2] = ceilf(src->f[2]);
112 dst->f[3] = ceilf(src->f[3]);
116 micro_clamp(union tgsi_exec_channel *dst,
117 const union tgsi_exec_channel *src0,
118 const union tgsi_exec_channel *src1,
119 const union tgsi_exec_channel *src2)
121 dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[0];
122 dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[1];
123 dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[2];
124 dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[3];
128 micro_cmp(union tgsi_exec_channel *dst,
129 const union tgsi_exec_channel *src0,
130 const union tgsi_exec_channel *src1,
131 const union tgsi_exec_channel *src2)
133 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0];
134 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1];
135 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2];
136 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3];
140 micro_cnd(union tgsi_exec_channel *dst,
141 const union tgsi_exec_channel *src0,
142 const union tgsi_exec_channel *src1,
143 const union tgsi_exec_channel *src2)
145 dst->f[0] = src2->f[0] > 0.5f ? src0->f[0] : src1->f[0];
146 dst->f[1] = src2->f[1] > 0.5f ? src0->f[1] : src1->f[1];
147 dst->f[2] = src2->f[2] > 0.5f ? src0->f[2] : src1->f[2];
148 dst->f[3] = src2->f[3] > 0.5f ? src0->f[3] : src1->f[3];
152 micro_cos(union tgsi_exec_channel *dst,
153 const union tgsi_exec_channel *src)
155 dst->f[0] = cosf(src->f[0]);
156 dst->f[1] = cosf(src->f[1]);
157 dst->f[2] = cosf(src->f[2]);
158 dst->f[3] = cosf(src->f[3]);
162 micro_ddx(union tgsi_exec_channel *dst,
163 const union tgsi_exec_channel *src)
168 dst->f[3] = src->f[TILE_BOTTOM_RIGHT] - src->f[TILE_BOTTOM_LEFT];
172 micro_ddy(union tgsi_exec_channel *dst,
173 const union tgsi_exec_channel *src)
178 dst->f[3] = src->f[TILE_BOTTOM_LEFT] - src->f[TILE_TOP_LEFT];
182 micro_exp2(union tgsi_exec_channel *dst,
183 const union tgsi_exec_channel *src)
186 dst->f[0] = util_fast_exp2(src->f[0]);
187 dst->f[1] = util_fast_exp2(src->f[1]);
188 dst->f[2] = util_fast_exp2(src->f[2]);
189 dst->f[3] = util_fast_exp2(src->f[3]);
192 /* Inf is okay for this instruction, so clamp it to silence assertions. */
194 union tgsi_exec_channel clamped;
196 for (i = 0; i < 4; i++) {
197 if (src->f[i] > 127.99999f) {
198 clamped.f[i] = 127.99999f;
199 } else if (src->f[i] < -126.99999f) {
200 clamped.f[i] = -126.99999f;
202 clamped.f[i] = src->f[i];
208 dst->f[0] = powf(2.0f, src->f[0]);
209 dst->f[1] = powf(2.0f, src->f[1]);
210 dst->f[2] = powf(2.0f, src->f[2]);
211 dst->f[3] = powf(2.0f, src->f[3]);
212 #endif /* FAST_MATH */
216 micro_flr(union tgsi_exec_channel *dst,
217 const union tgsi_exec_channel *src)
219 dst->f[0] = floorf(src->f[0]);
220 dst->f[1] = floorf(src->f[1]);
221 dst->f[2] = floorf(src->f[2]);
222 dst->f[3] = floorf(src->f[3]);
226 micro_frc(union tgsi_exec_channel *dst,
227 const union tgsi_exec_channel *src)
229 dst->f[0] = src->f[0] - floorf(src->f[0]);
230 dst->f[1] = src->f[1] - floorf(src->f[1]);
231 dst->f[2] = src->f[2] - floorf(src->f[2]);
232 dst->f[3] = src->f[3] - floorf(src->f[3]);
236 micro_iabs(union tgsi_exec_channel *dst,
237 const union tgsi_exec_channel *src)
239 dst->i[0] = src->i[0] >= 0 ? src->i[0] : -src->i[0];
240 dst->i[1] = src->i[1] >= 0 ? src->i[1] : -src->i[1];
241 dst->i[2] = src->i[2] >= 0 ? src->i[2] : -src->i[2];
242 dst->i[3] = src->i[3] >= 0 ? src->i[3] : -src->i[3];
246 micro_ineg(union tgsi_exec_channel *dst,
247 const union tgsi_exec_channel *src)
249 dst->i[0] = -src->i[0];
250 dst->i[1] = -src->i[1];
251 dst->i[2] = -src->i[2];
252 dst->i[3] = -src->i[3];
256 micro_lg2(union tgsi_exec_channel *dst,
257 const union tgsi_exec_channel *src)
260 dst->f[0] = util_fast_log2(src->f[0]);
261 dst->f[1] = util_fast_log2(src->f[1]);
262 dst->f[2] = util_fast_log2(src->f[2]);
263 dst->f[3] = util_fast_log2(src->f[3]);
265 dst->f[0] = logf(src->f[0]) * 1.442695f;
266 dst->f[1] = logf(src->f[1]) * 1.442695f;
267 dst->f[2] = logf(src->f[2]) * 1.442695f;
268 dst->f[3] = logf(src->f[3]) * 1.442695f;
273 micro_lrp(union tgsi_exec_channel *dst,
274 const union tgsi_exec_channel *src0,
275 const union tgsi_exec_channel *src1,
276 const union tgsi_exec_channel *src2)
278 dst->f[0] = src0->f[0] * (src1->f[0] - src2->f[0]) + src2->f[0];
279 dst->f[1] = src0->f[1] * (src1->f[1] - src2->f[1]) + src2->f[1];
280 dst->f[2] = src0->f[2] * (src1->f[2] - src2->f[2]) + src2->f[2];
281 dst->f[3] = src0->f[3] * (src1->f[3] - src2->f[3]) + src2->f[3];
285 micro_mad(union tgsi_exec_channel *dst,
286 const union tgsi_exec_channel *src0,
287 const union tgsi_exec_channel *src1,
288 const union tgsi_exec_channel *src2)
290 dst->f[0] = src0->f[0] * src1->f[0] + src2->f[0];
291 dst->f[1] = src0->f[1] * src1->f[1] + src2->f[1];
292 dst->f[2] = src0->f[2] * src1->f[2] + src2->f[2];
293 dst->f[3] = src0->f[3] * src1->f[3] + src2->f[3];
297 micro_mov(union tgsi_exec_channel *dst,
298 const union tgsi_exec_channel *src)
300 dst->u[0] = src->u[0];
301 dst->u[1] = src->u[1];
302 dst->u[2] = src->u[2];
303 dst->u[3] = src->u[3];
307 micro_rcp(union tgsi_exec_channel *dst,
308 const union tgsi_exec_channel *src)
310 #if 0 /* for debugging */
311 assert(src->f[0] != 0.0f);
312 assert(src->f[1] != 0.0f);
313 assert(src->f[2] != 0.0f);
314 assert(src->f[3] != 0.0f);
316 dst->f[0] = 1.0f / src->f[0];
317 dst->f[1] = 1.0f / src->f[1];
318 dst->f[2] = 1.0f / src->f[2];
319 dst->f[3] = 1.0f / src->f[3];
323 micro_rnd(union tgsi_exec_channel *dst,
324 const union tgsi_exec_channel *src)
326 dst->f[0] = floorf(src->f[0] + 0.5f);
327 dst->f[1] = floorf(src->f[1] + 0.5f);
328 dst->f[2] = floorf(src->f[2] + 0.5f);
329 dst->f[3] = floorf(src->f[3] + 0.5f);
333 micro_rsq(union tgsi_exec_channel *dst,
334 const union tgsi_exec_channel *src)
336 #if 0 /* for debugging */
337 assert(src->f[0] != 0.0f);
338 assert(src->f[1] != 0.0f);
339 assert(src->f[2] != 0.0f);
340 assert(src->f[3] != 0.0f);
342 dst->f[0] = 1.0f / sqrtf(src->f[0]);
343 dst->f[1] = 1.0f / sqrtf(src->f[1]);
344 dst->f[2] = 1.0f / sqrtf(src->f[2]);
345 dst->f[3] = 1.0f / sqrtf(src->f[3]);
349 micro_sqrt(union tgsi_exec_channel *dst,
350 const union tgsi_exec_channel *src)
352 dst->f[0] = sqrtf(src->f[0]);
353 dst->f[1] = sqrtf(src->f[1]);
354 dst->f[2] = sqrtf(src->f[2]);
355 dst->f[3] = sqrtf(src->f[3]);
359 micro_seq(union tgsi_exec_channel *dst,
360 const union tgsi_exec_channel *src0,
361 const union tgsi_exec_channel *src1)
363 dst->f[0] = src0->f[0] == src1->f[0] ? 1.0f : 0.0f;
364 dst->f[1] = src0->f[1] == src1->f[1] ? 1.0f : 0.0f;
365 dst->f[2] = src0->f[2] == src1->f[2] ? 1.0f : 0.0f;
366 dst->f[3] = src0->f[3] == src1->f[3] ? 1.0f : 0.0f;
370 micro_sge(union tgsi_exec_channel *dst,
371 const union tgsi_exec_channel *src0,
372 const union tgsi_exec_channel *src1)
374 dst->f[0] = src0->f[0] >= src1->f[0] ? 1.0f : 0.0f;
375 dst->f[1] = src0->f[1] >= src1->f[1] ? 1.0f : 0.0f;
376 dst->f[2] = src0->f[2] >= src1->f[2] ? 1.0f : 0.0f;
377 dst->f[3] = src0->f[3] >= src1->f[3] ? 1.0f : 0.0f;
381 micro_sgn(union tgsi_exec_channel *dst,
382 const union tgsi_exec_channel *src)
384 dst->f[0] = src->f[0] < 0.0f ? -1.0f : src->f[0] > 0.0f ? 1.0f : 0.0f;
385 dst->f[1] = src->f[1] < 0.0f ? -1.0f : src->f[1] > 0.0f ? 1.0f : 0.0f;
386 dst->f[2] = src->f[2] < 0.0f ? -1.0f : src->f[2] > 0.0f ? 1.0f : 0.0f;
387 dst->f[3] = src->f[3] < 0.0f ? -1.0f : src->f[3] > 0.0f ? 1.0f : 0.0f;
391 micro_isgn(union tgsi_exec_channel *dst,
392 const union tgsi_exec_channel *src)
394 dst->i[0] = src->i[0] < 0 ? -1 : src->i[0] > 0 ? 1 : 0;
395 dst->i[1] = src->i[1] < 0 ? -1 : src->i[1] > 0 ? 1 : 0;
396 dst->i[2] = src->i[2] < 0 ? -1 : src->i[2] > 0 ? 1 : 0;
397 dst->i[3] = src->i[3] < 0 ? -1 : src->i[3] > 0 ? 1 : 0;
401 micro_sgt(union tgsi_exec_channel *dst,
402 const union tgsi_exec_channel *src0,
403 const union tgsi_exec_channel *src1)
405 dst->f[0] = src0->f[0] > src1->f[0] ? 1.0f : 0.0f;
406 dst->f[1] = src0->f[1] > src1->f[1] ? 1.0f : 0.0f;
407 dst->f[2] = src0->f[2] > src1->f[2] ? 1.0f : 0.0f;
408 dst->f[3] = src0->f[3] > src1->f[3] ? 1.0f : 0.0f;
412 micro_sin(union tgsi_exec_channel *dst,
413 const union tgsi_exec_channel *src)
415 dst->f[0] = sinf(src->f[0]);
416 dst->f[1] = sinf(src->f[1]);
417 dst->f[2] = sinf(src->f[2]);
418 dst->f[3] = sinf(src->f[3]);
422 micro_sle(union tgsi_exec_channel *dst,
423 const union tgsi_exec_channel *src0,
424 const union tgsi_exec_channel *src1)
426 dst->f[0] = src0->f[0] <= src1->f[0] ? 1.0f : 0.0f;
427 dst->f[1] = src0->f[1] <= src1->f[1] ? 1.0f : 0.0f;
428 dst->f[2] = src0->f[2] <= src1->f[2] ? 1.0f : 0.0f;
429 dst->f[3] = src0->f[3] <= src1->f[3] ? 1.0f : 0.0f;
433 micro_slt(union tgsi_exec_channel *dst,
434 const union tgsi_exec_channel *src0,
435 const union tgsi_exec_channel *src1)
437 dst->f[0] = src0->f[0] < src1->f[0] ? 1.0f : 0.0f;
438 dst->f[1] = src0->f[1] < src1->f[1] ? 1.0f : 0.0f;
439 dst->f[2] = src0->f[2] < src1->f[2] ? 1.0f : 0.0f;
440 dst->f[3] = src0->f[3] < src1->f[3] ? 1.0f : 0.0f;
444 micro_sne(union tgsi_exec_channel *dst,
445 const union tgsi_exec_channel *src0,
446 const union tgsi_exec_channel *src1)
448 dst->f[0] = src0->f[0] != src1->f[0] ? 1.0f : 0.0f;
449 dst->f[1] = src0->f[1] != src1->f[1] ? 1.0f : 0.0f;
450 dst->f[2] = src0->f[2] != src1->f[2] ? 1.0f : 0.0f;
451 dst->f[3] = src0->f[3] != src1->f[3] ? 1.0f : 0.0f;
455 micro_sfl(union tgsi_exec_channel *dst)
464 micro_str(union tgsi_exec_channel *dst)
473 micro_trunc(union tgsi_exec_channel *dst,
474 const union tgsi_exec_channel *src)
476 dst->f[0] = (float)(int)src->f[0];
477 dst->f[1] = (float)(int)src->f[1];
478 dst->f[2] = (float)(int)src->f[2];
479 dst->f[3] = (float)(int)src->f[3];
483 enum tgsi_exec_datatype {
484 TGSI_EXEC_DATA_FLOAT,
490 * Shorthand locations of various utility registers (_I = Index, _C = Channel)
492 #define TEMP_KILMASK_I TGSI_EXEC_TEMP_KILMASK_I
493 #define TEMP_KILMASK_C TGSI_EXEC_TEMP_KILMASK_C
494 #define TEMP_OUTPUT_I TGSI_EXEC_TEMP_OUTPUT_I
495 #define TEMP_OUTPUT_C TGSI_EXEC_TEMP_OUTPUT_C
496 #define TEMP_PRIMITIVE_I TGSI_EXEC_TEMP_PRIMITIVE_I
497 #define TEMP_PRIMITIVE_C TGSI_EXEC_TEMP_PRIMITIVE_C
500 /** The execution mask depends on the conditional mask and the loop mask */
501 #define UPDATE_EXEC_MASK(MACH) \
502 MACH->ExecMask = MACH->CondMask & MACH->LoopMask & MACH->ContMask & MACH->Switch.mask & MACH->FuncMask
505 static const union tgsi_exec_channel ZeroVec =
506 { { 0.0, 0.0, 0.0, 0.0 } };
508 static const union tgsi_exec_channel OneVec = {
509 {1.0f, 1.0f, 1.0f, 1.0f}
512 static const union tgsi_exec_channel P128Vec = {
513 {128.0f, 128.0f, 128.0f, 128.0f}
516 static const union tgsi_exec_channel M128Vec = {
517 {-128.0f, -128.0f, -128.0f, -128.0f}
522 * Assert that none of the float values in 'chan' are infinite or NaN.
523 * NaN and Inf may occur normally during program execution and should
524 * not lead to crashes, etc. But when debugging, it's helpful to catch
528 check_inf_or_nan(const union tgsi_exec_channel *chan)
530 assert(!util_is_inf_or_nan((chan)->f[0]));
531 assert(!util_is_inf_or_nan((chan)->f[1]));
532 assert(!util_is_inf_or_nan((chan)->f[2]));
533 assert(!util_is_inf_or_nan((chan)->f[3]));
539 print_chan(const char *msg, const union tgsi_exec_channel *chan)
541 debug_printf("%s = {%f, %f, %f, %f}\n",
542 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
549 print_temp(const struct tgsi_exec_machine *mach, uint index)
551 const struct tgsi_exec_vector *tmp = &mach->Temps[index];
553 debug_printf("Temp[%u] =\n", index);
554 for (i = 0; i < 4; i++) {
555 debug_printf(" %c: { %f, %f, %f, %f }\n",
567 tgsi_exec_set_constant_buffers(struct tgsi_exec_machine *mach,
570 const unsigned *buf_sizes)
574 for (i = 0; i < num_bufs; i++) {
575 mach->Consts[i] = bufs[i];
576 mach->ConstsSize[i] = buf_sizes[i];
582 * Check if there's a potential src/dst register data dependency when
583 * using SOA execution.
586 * This would expand into:
591 * The second instruction will have the wrong value for t0 if executed as-is.
594 tgsi_check_soa_dependencies(const struct tgsi_full_instruction *inst)
598 uint writemask = inst->Dst[0].Register.WriteMask;
599 if (writemask == TGSI_WRITEMASK_X ||
600 writemask == TGSI_WRITEMASK_Y ||
601 writemask == TGSI_WRITEMASK_Z ||
602 writemask == TGSI_WRITEMASK_W ||
603 writemask == TGSI_WRITEMASK_NONE) {
604 /* no chance of data dependency */
608 /* loop over src regs */
609 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
610 if ((inst->Src[i].Register.File ==
611 inst->Dst[0].Register.File) &&
612 ((inst->Src[i].Register.Index ==
613 inst->Dst[0].Register.Index) ||
614 inst->Src[i].Register.Indirect ||
615 inst->Dst[0].Register.Indirect)) {
616 /* loop over dest channels */
617 uint channelsWritten = 0x0;
618 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
619 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
620 /* check if we're reading a channel that's been written */
621 uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
622 if (channelsWritten & (1 << swizzle)) {
626 channelsWritten |= (1 << chan);
636 * Initialize machine state by expanding tokens to full instructions,
637 * allocating temporary storage, setting up constants, etc.
638 * After this, we can call tgsi_exec_machine_run() many times.
641 tgsi_exec_machine_bind_shader(
642 struct tgsi_exec_machine *mach,
643 const struct tgsi_token *tokens,
644 struct tgsi_sampler *sampler)
647 struct tgsi_parse_context parse;
648 struct tgsi_full_instruction *instructions;
649 struct tgsi_full_declaration *declarations;
650 uint maxInstructions = 10, numInstructions = 0;
651 uint maxDeclarations = 10, numDeclarations = 0;
654 tgsi_dump(tokens, 0);
660 mach->Tokens = tokens;
661 mach->Sampler = sampler;
664 /* unbind and free all */
665 FREE(mach->Declarations);
666 mach->Declarations = NULL;
667 mach->NumDeclarations = 0;
669 FREE(mach->Instructions);
670 mach->Instructions = NULL;
671 mach->NumInstructions = 0;
676 k = tgsi_parse_init (&parse, mach->Tokens);
677 if (k != TGSI_PARSE_OK) {
678 debug_printf( "Problem parsing!\n" );
682 mach->Processor = parse.FullHeader.Processor.Processor;
684 mach->NumOutputs = 0;
686 if (mach->Processor == TGSI_PROCESSOR_GEOMETRY &&
687 !mach->UsedGeometryShader) {
688 struct tgsi_exec_vector *inputs;
689 struct tgsi_exec_vector *outputs;
691 inputs = align_malloc(sizeof(struct tgsi_exec_vector) *
692 TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS,
698 outputs = align_malloc(sizeof(struct tgsi_exec_vector) *
699 TGSI_MAX_TOTAL_VERTICES, 16);
706 align_free(mach->Inputs);
707 align_free(mach->Outputs);
709 mach->Inputs = inputs;
710 mach->Outputs = outputs;
711 mach->UsedGeometryShader = TRUE;
714 declarations = (struct tgsi_full_declaration *)
715 MALLOC( maxDeclarations * sizeof(struct tgsi_full_declaration) );
721 instructions = (struct tgsi_full_instruction *)
722 MALLOC( maxInstructions * sizeof(struct tgsi_full_instruction) );
725 FREE( declarations );
729 while( !tgsi_parse_end_of_tokens( &parse ) ) {
732 tgsi_parse_token( &parse );
733 switch( parse.FullToken.Token.Type ) {
734 case TGSI_TOKEN_TYPE_DECLARATION:
735 /* save expanded declaration */
736 if (numDeclarations == maxDeclarations) {
737 declarations = REALLOC(declarations,
739 * sizeof(struct tgsi_full_declaration),
740 (maxDeclarations + 10)
741 * sizeof(struct tgsi_full_declaration));
742 maxDeclarations += 10;
744 if (parse.FullToken.FullDeclaration.Declaration.File == TGSI_FILE_OUTPUT) {
746 for (reg = parse.FullToken.FullDeclaration.Range.First;
747 reg <= parse.FullToken.FullDeclaration.Range.Last;
752 memcpy(declarations + numDeclarations,
753 &parse.FullToken.FullDeclaration,
754 sizeof(declarations[0]));
758 case TGSI_TOKEN_TYPE_IMMEDIATE:
760 uint size = parse.FullToken.FullImmediate.Immediate.NrTokens - 1;
762 assert( mach->ImmLimit + 1 <= TGSI_EXEC_NUM_IMMEDIATES );
764 for( i = 0; i < size; i++ ) {
765 mach->Imms[mach->ImmLimit][i] =
766 parse.FullToken.FullImmediate.u[i].Float;
772 case TGSI_TOKEN_TYPE_INSTRUCTION:
774 /* save expanded instruction */
775 if (numInstructions == maxInstructions) {
776 instructions = REALLOC(instructions,
778 * sizeof(struct tgsi_full_instruction),
779 (maxInstructions + 10)
780 * sizeof(struct tgsi_full_instruction));
781 maxInstructions += 10;
784 memcpy(instructions + numInstructions,
785 &parse.FullToken.FullInstruction,
786 sizeof(instructions[0]));
791 case TGSI_TOKEN_TYPE_PROPERTY:
798 tgsi_parse_free (&parse);
800 FREE(mach->Declarations);
801 mach->Declarations = declarations;
802 mach->NumDeclarations = numDeclarations;
804 FREE(mach->Instructions);
805 mach->Instructions = instructions;
806 mach->NumInstructions = numInstructions;
810 struct tgsi_exec_machine *
811 tgsi_exec_machine_create( void )
813 struct tgsi_exec_machine *mach;
816 mach = align_malloc( sizeof *mach, 16 );
820 memset(mach, 0, sizeof(*mach));
822 mach->Addrs = &mach->Temps[TGSI_EXEC_TEMP_ADDR];
823 mach->MaxGeometryShaderOutputs = TGSI_MAX_TOTAL_VERTICES;
824 mach->Predicates = &mach->Temps[TGSI_EXEC_TEMP_P0];
826 mach->Inputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
827 mach->Outputs = align_malloc(sizeof(struct tgsi_exec_vector) * PIPE_MAX_ATTRIBS, 16);
828 if (!mach->Inputs || !mach->Outputs)
831 /* Setup constants needed by the SSE2 executor. */
832 for( i = 0; i < 4; i++ ) {
833 mach->Temps[TGSI_EXEC_TEMP_00000000_I].xyzw[TGSI_EXEC_TEMP_00000000_C].u[i] = 0x00000000;
834 mach->Temps[TGSI_EXEC_TEMP_7FFFFFFF_I].xyzw[TGSI_EXEC_TEMP_7FFFFFFF_C].u[i] = 0x7FFFFFFF;
835 mach->Temps[TGSI_EXEC_TEMP_80000000_I].xyzw[TGSI_EXEC_TEMP_80000000_C].u[i] = 0x80000000;
836 mach->Temps[TGSI_EXEC_TEMP_FFFFFFFF_I].xyzw[TGSI_EXEC_TEMP_FFFFFFFF_C].u[i] = 0xFFFFFFFF; /* not used */
837 mach->Temps[TGSI_EXEC_TEMP_ONE_I].xyzw[TGSI_EXEC_TEMP_ONE_C].f[i] = 1.0f;
838 mach->Temps[TGSI_EXEC_TEMP_TWO_I].xyzw[TGSI_EXEC_TEMP_TWO_C].f[i] = 2.0f; /* not used */
839 mach->Temps[TGSI_EXEC_TEMP_128_I].xyzw[TGSI_EXEC_TEMP_128_C].f[i] = 128.0f;
840 mach->Temps[TGSI_EXEC_TEMP_MINUS_128_I].xyzw[TGSI_EXEC_TEMP_MINUS_128_C].f[i] = -128.0f;
841 mach->Temps[TGSI_EXEC_TEMP_THREE_I].xyzw[TGSI_EXEC_TEMP_THREE_C].f[i] = 3.0f;
842 mach->Temps[TGSI_EXEC_TEMP_HALF_I].xyzw[TGSI_EXEC_TEMP_HALF_C].f[i] = 0.5f;
846 /* silence warnings */
855 align_free(mach->Inputs);
856 align_free(mach->Outputs);
864 tgsi_exec_machine_destroy(struct tgsi_exec_machine *mach)
867 FREE(mach->Instructions);
868 FREE(mach->Declarations);
870 align_free(mach->Inputs);
871 align_free(mach->Outputs);
878 micro_add(union tgsi_exec_channel *dst,
879 const union tgsi_exec_channel *src0,
880 const union tgsi_exec_channel *src1)
882 dst->f[0] = src0->f[0] + src1->f[0];
883 dst->f[1] = src0->f[1] + src1->f[1];
884 dst->f[2] = src0->f[2] + src1->f[2];
885 dst->f[3] = src0->f[3] + src1->f[3];
890 union tgsi_exec_channel *dst,
891 const union tgsi_exec_channel *src0,
892 const union tgsi_exec_channel *src1 )
894 if (src1->f[0] != 0) {
895 dst->f[0] = src0->f[0] / src1->f[0];
897 if (src1->f[1] != 0) {
898 dst->f[1] = src0->f[1] / src1->f[1];
900 if (src1->f[2] != 0) {
901 dst->f[2] = src0->f[2] / src1->f[2];
903 if (src1->f[3] != 0) {
904 dst->f[3] = src0->f[3] / src1->f[3];
909 micro_rcc(union tgsi_exec_channel *dst,
910 const union tgsi_exec_channel *src)
914 for (i = 0; i < 4; i++) {
915 float recip = 1.0f / src->f[i];
918 dst->f[i] = CLAMP(recip, 5.42101e-020f, 1.84467e+019f);
920 dst->f[i] = CLAMP(recip, -1.84467e+019f, -5.42101e-020f);
926 union tgsi_exec_channel *dst,
927 const union tgsi_exec_channel *src0,
928 const union tgsi_exec_channel *src1,
929 const union tgsi_exec_channel *src2,
930 const union tgsi_exec_channel *src3 )
932 dst->f[0] = src0->f[0] < src1->f[0] ? src2->f[0] : src3->f[0];
933 dst->f[1] = src0->f[1] < src1->f[1] ? src2->f[1] : src3->f[1];
934 dst->f[2] = src0->f[2] < src1->f[2] ? src2->f[2] : src3->f[2];
935 dst->f[3] = src0->f[3] < src1->f[3] ? src2->f[3] : src3->f[3];
939 micro_max(union tgsi_exec_channel *dst,
940 const union tgsi_exec_channel *src0,
941 const union tgsi_exec_channel *src1)
943 dst->f[0] = src0->f[0] > src1->f[0] ? src0->f[0] : src1->f[0];
944 dst->f[1] = src0->f[1] > src1->f[1] ? src0->f[1] : src1->f[1];
945 dst->f[2] = src0->f[2] > src1->f[2] ? src0->f[2] : src1->f[2];
946 dst->f[3] = src0->f[3] > src1->f[3] ? src0->f[3] : src1->f[3];
950 micro_min(union tgsi_exec_channel *dst,
951 const union tgsi_exec_channel *src0,
952 const union tgsi_exec_channel *src1)
954 dst->f[0] = src0->f[0] < src1->f[0] ? src0->f[0] : src1->f[0];
955 dst->f[1] = src0->f[1] < src1->f[1] ? src0->f[1] : src1->f[1];
956 dst->f[2] = src0->f[2] < src1->f[2] ? src0->f[2] : src1->f[2];
957 dst->f[3] = src0->f[3] < src1->f[3] ? src0->f[3] : src1->f[3];
961 micro_mul(union tgsi_exec_channel *dst,
962 const union tgsi_exec_channel *src0,
963 const union tgsi_exec_channel *src1)
965 dst->f[0] = src0->f[0] * src1->f[0];
966 dst->f[1] = src0->f[1] * src1->f[1];
967 dst->f[2] = src0->f[2] * src1->f[2];
968 dst->f[3] = src0->f[3] * src1->f[3];
973 union tgsi_exec_channel *dst,
974 const union tgsi_exec_channel *src )
976 dst->f[0] = -src->f[0];
977 dst->f[1] = -src->f[1];
978 dst->f[2] = -src->f[2];
979 dst->f[3] = -src->f[3];
984 union tgsi_exec_channel *dst,
985 const union tgsi_exec_channel *src0,
986 const union tgsi_exec_channel *src1 )
989 dst->f[0] = util_fast_pow( src0->f[0], src1->f[0] );
990 dst->f[1] = util_fast_pow( src0->f[1], src1->f[1] );
991 dst->f[2] = util_fast_pow( src0->f[2], src1->f[2] );
992 dst->f[3] = util_fast_pow( src0->f[3], src1->f[3] );
994 dst->f[0] = powf( src0->f[0], src1->f[0] );
995 dst->f[1] = powf( src0->f[1], src1->f[1] );
996 dst->f[2] = powf( src0->f[2], src1->f[2] );
997 dst->f[3] = powf( src0->f[3], src1->f[3] );
1002 micro_sub(union tgsi_exec_channel *dst,
1003 const union tgsi_exec_channel *src0,
1004 const union tgsi_exec_channel *src1)
1006 dst->f[0] = src0->f[0] - src1->f[0];
1007 dst->f[1] = src0->f[1] - src1->f[1];
1008 dst->f[2] = src0->f[2] - src1->f[2];
1009 dst->f[3] = src0->f[3] - src1->f[3];
1013 fetch_src_file_channel(const struct tgsi_exec_machine *mach,
1014 const uint chan_index,
1017 const union tgsi_exec_channel *index,
1018 const union tgsi_exec_channel *index2D,
1019 union tgsi_exec_channel *chan)
1023 assert(swizzle < 4);
1026 case TGSI_FILE_CONSTANT:
1027 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1028 assert(index2D->i[i] >= 0 && index2D->i[i] < PIPE_MAX_CONSTANT_BUFFERS);
1029 assert(mach->Consts[index2D->i[i]]);
1031 if (index->i[i] < 0) {
1034 /* NOTE: copying the const value as a uint instead of float */
1035 const uint constbuf = index2D->i[i];
1036 const uint *buf = (const uint *)mach->Consts[constbuf];
1037 const int pos = index->i[i] * 4 + swizzle;
1038 /* const buffer bounds check */
1039 if (pos < 0 || pos >= (int) mach->ConstsSize[constbuf]) {
1041 /* Debug: print warning */
1042 static int count = 0;
1044 debug_printf("TGSI Exec: const buffer index %d"
1045 " out of bounds\n", pos);
1050 chan->u[i] = buf[pos];
1055 case TGSI_FILE_INPUT:
1056 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1058 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1059 debug_printf("Fetching Input[%d] (2d=%d, 1d=%d)\n",
1060 index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i],
1061 index2D->i[i], index->i[i]);
1063 int pos = index2D->i[i] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index->i[i];
1065 assert(pos < TGSI_MAX_PRIM_VERTICES * PIPE_MAX_ATTRIBS);
1066 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1070 case TGSI_FILE_SYSTEM_VALUE:
1071 /* XXX no swizzling at this point. Will be needed if we put
1072 * gl_FragCoord, for example, in a sys value register.
1074 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1075 chan->u[i] = mach->SystemValue[index->i[i]].u[i];
1079 case TGSI_FILE_TEMPORARY:
1080 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1081 assert(index->i[i] < TGSI_EXEC_NUM_TEMPS);
1082 assert(index2D->i[i] == 0);
1084 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1088 case TGSI_FILE_IMMEDIATE:
1089 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1090 assert(index->i[i] >= 0 && index->i[i] < (int)mach->ImmLimit);
1091 assert(index2D->i[i] == 0);
1093 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1097 case TGSI_FILE_ADDRESS:
1098 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1099 assert(index->i[i] >= 0);
1100 assert(index2D->i[i] == 0);
1102 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1106 case TGSI_FILE_PREDICATE:
1107 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1108 assert(index->i[i] >= 0 && index->i[i] < TGSI_EXEC_NUM_PREDS);
1109 assert(index2D->i[i] == 0);
1111 chan->u[i] = mach->Predicates[0].xyzw[swizzle].u[i];
1115 case TGSI_FILE_OUTPUT:
1116 /* vertex/fragment output vars can be read too */
1117 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1118 assert(index->i[i] >= 0);
1119 assert(index2D->i[i] == 0);
1121 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1127 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1134 fetch_source(const struct tgsi_exec_machine *mach,
1135 union tgsi_exec_channel *chan,
1136 const struct tgsi_full_src_register *reg,
1137 const uint chan_index,
1138 enum tgsi_exec_datatype src_datatype)
1140 union tgsi_exec_channel index;
1141 union tgsi_exec_channel index2D;
1144 /* We start with a direct index into a register file.
1148 * file = Register.File
1149 * [1] = Register.Index
1154 index.i[3] = reg->Register.Index;
1156 /* There is an extra source register that indirectly subscripts
1157 * a register file. The direct index now becomes an offset
1158 * that is being added to the indirect register.
1162 * ind = Indirect.File
1163 * [2] = Indirect.Index
1164 * .x = Indirect.SwizzleX
1166 if (reg->Register.Indirect) {
1167 union tgsi_exec_channel index2;
1168 union tgsi_exec_channel indir_index;
1169 const uint execmask = mach->ExecMask;
1172 /* which address register (always zero now) */
1176 index2.i[3] = reg->Indirect.Index;
1177 /* get current value of address register[swizzle] */
1178 swizzle = reg->Indirect.Swizzle;
1179 fetch_src_file_channel(mach,
1187 /* add value of address register to the offset */
1188 index.i[0] += indir_index.i[0];
1189 index.i[1] += indir_index.i[1];
1190 index.i[2] += indir_index.i[2];
1191 index.i[3] += indir_index.i[3];
1193 /* for disabled execution channels, zero-out the index to
1194 * avoid using a potential garbage value.
1196 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1197 if ((execmask & (1 << i)) == 0)
1202 /* There is an extra source register that is a second
1203 * subscript to a register file. Effectively it means that
1204 * the register file is actually a 2D array of registers.
1208 * [3] = Dimension.Index
1210 if (reg->Register.Dimension) {
1214 index2D.i[3] = reg->Dimension.Index;
1216 /* Again, the second subscript index can be addressed indirectly
1217 * identically to the first one.
1218 * Nothing stops us from indirectly addressing the indirect register,
1219 * but there is no need for that, so we won't exercise it.
1221 * file[ind[4].y+3][1],
1223 * ind = DimIndirect.File
1224 * [4] = DimIndirect.Index
1225 * .y = DimIndirect.SwizzleX
1227 if (reg->Dimension.Indirect) {
1228 union tgsi_exec_channel index2;
1229 union tgsi_exec_channel indir_index;
1230 const uint execmask = mach->ExecMask;
1236 index2.i[3] = reg->DimIndirect.Index;
1238 swizzle = reg->DimIndirect.Swizzle;
1239 fetch_src_file_channel(mach,
1241 reg->DimIndirect.File,
1247 index2D.i[0] += indir_index.i[0];
1248 index2D.i[1] += indir_index.i[1];
1249 index2D.i[2] += indir_index.i[2];
1250 index2D.i[3] += indir_index.i[3];
1252 /* for disabled execution channels, zero-out the index to
1253 * avoid using a potential garbage value.
1255 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1256 if ((execmask & (1 << i)) == 0) {
1262 /* If by any chance there was a need for a 3D array of register
1263 * files, we would have to check whether Dimension is followed
1264 * by a dimension register and continue the saga.
1273 swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
1274 fetch_src_file_channel(mach,
1282 if (reg->Register.Absolute) {
1283 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1284 micro_abs(chan, chan);
1286 micro_iabs(chan, chan);
1290 if (reg->Register.Negate) {
1291 if (src_datatype == TGSI_EXEC_DATA_FLOAT) {
1292 micro_neg(chan, chan);
1294 micro_ineg(chan, chan);
1300 store_dest(struct tgsi_exec_machine *mach,
1301 const union tgsi_exec_channel *chan,
1302 const struct tgsi_full_dst_register *reg,
1303 const struct tgsi_full_instruction *inst,
1305 enum tgsi_exec_datatype dst_datatype)
1308 union tgsi_exec_channel null;
1309 union tgsi_exec_channel *dst;
1310 union tgsi_exec_channel index2D;
1311 uint execmask = mach->ExecMask;
1312 int offset = 0; /* indirection offset */
1316 if (0 && dst_datatype == TGSI_EXEC_DATA_FLOAT) {
1317 check_inf_or_nan(chan);
1320 /* There is an extra source register that indirectly subscripts
1321 * a register file. The direct index now becomes an offset
1322 * that is being added to the indirect register.
1326 * ind = Indirect.File
1327 * [2] = Indirect.Index
1328 * .x = Indirect.SwizzleX
1330 if (reg->Register.Indirect) {
1331 union tgsi_exec_channel index;
1332 union tgsi_exec_channel indir_index;
1335 /* which address register (always zero for now) */
1339 index.i[3] = reg->Indirect.Index;
1341 /* get current value of address register[swizzle] */
1342 swizzle = reg->Indirect.Swizzle;
1344 /* fetch values from the address/indirection register */
1345 fetch_src_file_channel(mach,
1353 /* save indirection offset */
1354 offset = indir_index.i[0];
1357 /* There is an extra source register that is a second
1358 * subscript to a register file. Effectively it means that
1359 * the register file is actually a 2D array of registers.
1363 * [3] = Dimension.Index
1365 if (reg->Register.Dimension) {
1369 index2D.i[3] = reg->Dimension.Index;
1371 /* Again, the second subscript index can be addressed indirectly
1372 * identically to the first one.
1373 * Nothing stops us from indirectly addressing the indirect register,
1374 * but there is no need for that, so we won't exercise it.
1376 * file[ind[4].y+3][1],
1378 * ind = DimIndirect.File
1379 * [4] = DimIndirect.Index
1380 * .y = DimIndirect.SwizzleX
1382 if (reg->Dimension.Indirect) {
1383 union tgsi_exec_channel index2;
1384 union tgsi_exec_channel indir_index;
1385 const uint execmask = mach->ExecMask;
1392 index2.i[3] = reg->DimIndirect.Index;
1394 swizzle = reg->DimIndirect.Swizzle;
1395 fetch_src_file_channel(mach,
1397 reg->DimIndirect.File,
1403 index2D.i[0] += indir_index.i[0];
1404 index2D.i[1] += indir_index.i[1];
1405 index2D.i[2] += indir_index.i[2];
1406 index2D.i[3] += indir_index.i[3];
1408 /* for disabled execution channels, zero-out the index to
1409 * avoid using a potential garbage value.
1411 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1412 if ((execmask & (1 << i)) == 0) {
1418 /* If by any chance there was a need for a 3D array of register
1419 * files, we would have to check whether Dimension is followed
1420 * by a dimension register and continue the saga.
1429 switch (reg->Register.File) {
1430 case TGSI_FILE_NULL:
1434 case TGSI_FILE_OUTPUT:
1435 index = mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0]
1436 + reg->Register.Index;
1437 dst = &mach->Outputs[offset + index].xyzw[chan_index];
1439 debug_printf("NumOutputs = %d, TEMP_O_C/I = %d, redindex = %d\n",
1440 mach->NumOutputs, mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0],
1441 reg->Register.Index);
1442 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1443 debug_printf("STORING OUT[%d] mask(%d), = (", offset + index, execmask);
1444 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1445 if (execmask & (1 << i))
1446 debug_printf("%f, ", chan->f[i]);
1447 debug_printf(")\n");
1452 case TGSI_FILE_TEMPORARY:
1453 index = reg->Register.Index;
1454 assert( index < TGSI_EXEC_NUM_TEMPS );
1455 dst = &mach->Temps[offset + index].xyzw[chan_index];
1458 case TGSI_FILE_ADDRESS:
1459 index = reg->Register.Index;
1460 dst = &mach->Addrs[index].xyzw[chan_index];
1463 case TGSI_FILE_PREDICATE:
1464 index = reg->Register.Index;
1465 assert(index < TGSI_EXEC_NUM_PREDS);
1466 dst = &mach->Predicates[index].xyzw[chan_index];
1474 if (inst->Instruction.Predicate) {
1476 union tgsi_exec_channel *pred;
1478 switch (chan_index) {
1480 swizzle = inst->Predicate.SwizzleX;
1483 swizzle = inst->Predicate.SwizzleY;
1486 swizzle = inst->Predicate.SwizzleZ;
1489 swizzle = inst->Predicate.SwizzleW;
1496 assert(inst->Predicate.Index == 0);
1498 pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
1500 if (inst->Predicate.Negate) {
1501 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1503 execmask &= ~(1 << i);
1507 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
1509 execmask &= ~(1 << i);
1515 switch (inst->Instruction.Saturate) {
1517 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1518 if (execmask & (1 << i))
1519 dst->i[i] = chan->i[i];
1522 case TGSI_SAT_ZERO_ONE:
1523 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1524 if (execmask & (1 << i)) {
1525 if (chan->f[i] < 0.0f)
1527 else if (chan->f[i] > 1.0f)
1530 dst->i[i] = chan->i[i];
1534 case TGSI_SAT_MINUS_PLUS_ONE:
1535 for (i = 0; i < TGSI_QUAD_SIZE; i++)
1536 if (execmask & (1 << i)) {
1537 if (chan->f[i] < -1.0f)
1539 else if (chan->f[i] > 1.0f)
1542 dst->i[i] = chan->i[i];
1551 #define FETCH(VAL,INDEX,CHAN)\
1552 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_FLOAT)
1554 #define IFETCH(VAL,INDEX,CHAN)\
1555 fetch_source(mach, VAL, &inst->Src[INDEX], CHAN, TGSI_EXEC_DATA_INT)
1559 * Execute ARB-style KIL which is predicated by a src register.
1560 * Kill fragment if any of the four values is less than zero.
1563 exec_kill_if(struct tgsi_exec_machine *mach,
1564 const struct tgsi_full_instruction *inst)
1568 uint kilmask = 0; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1569 union tgsi_exec_channel r[1];
1571 /* This mask stores component bits that were already tested. */
1574 for (chan_index = 0; chan_index < 4; chan_index++)
1579 /* unswizzle channel */
1580 swizzle = tgsi_util_get_full_src_register_swizzle (
1584 /* check if the component has not been already tested */
1585 if (uniquemask & (1 << swizzle))
1587 uniquemask |= 1 << swizzle;
1589 FETCH(&r[0], 0, chan_index);
1590 for (i = 0; i < 4; i++)
1591 if (r[0].f[i] < 0.0f)
1595 /* restrict to fragments currently executing */
1596 kilmask &= mach->ExecMask;
1598 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1602 * Unconditional fragment kill/discard.
1605 exec_kill(struct tgsi_exec_machine *mach,
1606 const struct tgsi_full_instruction *inst)
1608 uint kilmask; /* bit 0 = pixel 0, bit 1 = pixel 1, etc */
1610 /* kill fragment for all fragments currently executing */
1611 kilmask = mach->ExecMask;
1612 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] |= kilmask;
1616 emit_vertex(struct tgsi_exec_machine *mach)
1618 /* FIXME: check for exec mask correctly
1620 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1621 if ((mach->ExecMask & (1 << i)))
1623 if (mach->ExecMask) {
1624 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] += mach->NumOutputs;
1625 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]]++;
1630 emit_primitive(struct tgsi_exec_machine *mach)
1632 unsigned *prim_count = &mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0];
1633 /* FIXME: check for exec mask correctly
1635 for (i = 0; i < TGSI_QUAD_SIZE; ++i) {
1636 if ((mach->ExecMask & (1 << i)))
1638 if (mach->ExecMask) {
1640 debug_assert((*prim_count * mach->NumOutputs) < mach->MaxGeometryShaderOutputs);
1641 mach->Primitives[*prim_count] = 0;
1646 conditional_emit_primitive(struct tgsi_exec_machine *mach)
1648 if (TGSI_PROCESSOR_GEOMETRY == mach->Processor) {
1650 mach->Primitives[mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0]];
1651 if (emitted_verts) {
1652 emit_primitive(mach);
1659 * Fetch four texture samples using STR texture coordinates.
1662 fetch_texel( struct tgsi_sampler *sampler,
1663 const unsigned sview_idx,
1664 const unsigned sampler_idx,
1665 const union tgsi_exec_channel *s,
1666 const union tgsi_exec_channel *t,
1667 const union tgsi_exec_channel *p,
1668 const union tgsi_exec_channel *c0,
1669 const union tgsi_exec_channel *c1,
1670 float derivs[3][2][TGSI_QUAD_SIZE],
1671 const int8_t offset[3],
1672 enum tgsi_sampler_control control,
1673 union tgsi_exec_channel *r,
1674 union tgsi_exec_channel *g,
1675 union tgsi_exec_channel *b,
1676 union tgsi_exec_channel *a )
1679 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1681 /* FIXME: handle explicit derivs, offsets */
1682 sampler->get_samples(sampler, sview_idx, sampler_idx,
1683 s->f, t->f, p->f, c0->f, c1->f, derivs, offset, control, rgba);
1685 for (j = 0; j < 4; j++) {
1686 r->f[j] = rgba[0][j];
1687 g->f[j] = rgba[1][j];
1688 b->f[j] = rgba[2][j];
1689 a->f[j] = rgba[3][j];
1694 #define TEX_MODIFIER_NONE 0
1695 #define TEX_MODIFIER_PROJECTED 1
1696 #define TEX_MODIFIER_LOD_BIAS 2
1697 #define TEX_MODIFIER_EXPLICIT_LOD 3
1698 #define TEX_MODIFIER_LEVEL_ZERO 4
1702 * Fetch all 3 (for s,t,r coords) texel offsets, put them into int array.
1705 fetch_texel_offsets(struct tgsi_exec_machine *mach,
1706 const struct tgsi_full_instruction *inst,
1709 if (inst->Texture.NumOffsets == 1) {
1710 union tgsi_exec_channel index;
1711 union tgsi_exec_channel offset[3];
1712 index.i[0] = index.i[1] = index.i[2] = index.i[3] = inst->TexOffsets[0].Index;
1713 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1714 inst->TexOffsets[0].SwizzleX, &index, &ZeroVec, &offset[0]);
1715 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1716 inst->TexOffsets[0].SwizzleY, &index, &ZeroVec, &offset[1]);
1717 fetch_src_file_channel(mach, 0, inst->TexOffsets[0].File,
1718 inst->TexOffsets[0].SwizzleZ, &index, &ZeroVec, &offset[2]);
1719 offsets[0] = offset[0].i[0];
1720 offsets[1] = offset[1].i[0];
1721 offsets[2] = offset[2].i[0];
1723 assert(inst->Texture.NumOffsets == 0);
1724 offsets[0] = offsets[1] = offsets[2] = 0;
1730 * Fetch dx and dy values for one channel (s, t or r).
1731 * Put dx values into one float array, dy values into another.
1734 fetch_assign_deriv_channel(struct tgsi_exec_machine *mach,
1735 const struct tgsi_full_instruction *inst,
1738 float derivs[2][TGSI_QUAD_SIZE])
1740 union tgsi_exec_channel d;
1741 FETCH(&d, regdsrcx, chan);
1742 derivs[0][0] = d.f[0];
1743 derivs[0][1] = d.f[1];
1744 derivs[0][2] = d.f[2];
1745 derivs[0][3] = d.f[3];
1746 FETCH(&d, regdsrcx + 1, chan);
1747 derivs[1][0] = d.f[0];
1748 derivs[1][1] = d.f[1];
1749 derivs[1][2] = d.f[2];
1750 derivs[1][3] = d.f[3];
1755 * execute a texture instruction.
1757 * modifier is used to control the channel routing for the\
1758 * instruction variants like proj, lod, and texture with lod bias.
1759 * sampler indicates which src register the sampler is contained in.
1762 exec_tex(struct tgsi_exec_machine *mach,
1763 const struct tgsi_full_instruction *inst,
1764 uint modifier, uint sampler)
1766 const uint unit = inst->Src[sampler].Register.Index;
1767 const union tgsi_exec_channel *args[5], *proj = NULL;
1768 union tgsi_exec_channel r[5];
1769 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
1772 int dim, shadow_ref, i;
1774 /* always fetch all 3 offsets, overkill but keeps code simple */
1775 fetch_texel_offsets(mach, inst, offsets);
1777 assert(modifier != TEX_MODIFIER_LEVEL_ZERO);
1778 assert(inst->Texture.Texture != TGSI_TEXTURE_BUFFER);
1780 dim = tgsi_util_get_texture_coord_dim(inst->Texture.Texture, &shadow_ref);
1783 if (shadow_ref >= 0)
1784 assert(shadow_ref >= dim && shadow_ref < Elements(args));
1786 /* fetch modifier to the last argument */
1787 if (modifier != TEX_MODIFIER_NONE) {
1788 const int last = Elements(args) - 1;
1790 /* fetch modifier from src0.w or src1.x */
1792 assert(dim <= TGSI_CHAN_W && shadow_ref != TGSI_CHAN_W);
1793 FETCH(&r[last], 0, TGSI_CHAN_W);
1796 assert(shadow_ref != 4);
1797 FETCH(&r[last], 1, TGSI_CHAN_X);
1800 if (modifier != TEX_MODIFIER_PROJECTED) {
1801 args[last] = &r[last];
1805 args[last] = &ZeroVec;
1808 /* point unused arguments to zero vector */
1809 for (i = dim; i < last; i++)
1812 if (modifier == TEX_MODIFIER_EXPLICIT_LOD)
1813 control = tgsi_sampler_lod_explicit;
1814 else if (modifier == TEX_MODIFIER_LOD_BIAS)
1815 control = tgsi_sampler_lod_bias;
1818 for (i = dim; i < Elements(args); i++)
1822 /* fetch coordinates */
1823 for (i = 0; i < dim; i++) {
1824 FETCH(&r[i], 0, TGSI_CHAN_X + i);
1827 micro_div(&r[i], &r[i], proj);
1832 /* fetch reference value */
1833 if (shadow_ref >= 0) {
1834 FETCH(&r[shadow_ref], shadow_ref / 4, TGSI_CHAN_X + (shadow_ref % 4));
1837 micro_div(&r[shadow_ref], &r[shadow_ref], proj);
1839 args[shadow_ref] = &r[shadow_ref];
1842 fetch_texel(mach->Sampler, unit, unit,
1843 args[0], args[1], args[2], args[3], args[4],
1844 NULL, offsets, control,
1845 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1848 debug_printf("fetch r: %g %g %g %g\n",
1849 r[0].f[0], r[0].f[1], r[0].f[2], r[0].f[3]);
1850 debug_printf("fetch g: %g %g %g %g\n",
1851 r[1].f[0], r[1].f[1], r[1].f[2], r[1].f[3]);
1852 debug_printf("fetch b: %g %g %g %g\n",
1853 r[2].f[0], r[2].f[1], r[2].f[2], r[2].f[3]);
1854 debug_printf("fetch a: %g %g %g %g\n",
1855 r[3].f[0], r[3].f[1], r[3].f[2], r[3].f[3]);
1858 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1859 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1860 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1867 exec_txd(struct tgsi_exec_machine *mach,
1868 const struct tgsi_full_instruction *inst)
1870 const uint unit = inst->Src[3].Register.Index;
1871 union tgsi_exec_channel r[4];
1872 float derivs[3][2][TGSI_QUAD_SIZE];
1876 /* always fetch all 3 offsets, overkill but keeps code simple */
1877 fetch_texel_offsets(mach, inst, offsets);
1879 switch (inst->Texture.Texture) {
1880 case TGSI_TEXTURE_1D:
1881 FETCH(&r[0], 0, TGSI_CHAN_X);
1883 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1885 fetch_texel(mach->Sampler, unit, unit,
1886 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1887 derivs, offsets, tgsi_sampler_derivs_explicit,
1888 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1891 case TGSI_TEXTURE_SHADOW1D:
1892 case TGSI_TEXTURE_1D_ARRAY:
1893 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1894 /* SHADOW1D/1D_ARRAY would not need Y/Z respectively, but don't bother */
1895 FETCH(&r[0], 0, TGSI_CHAN_X);
1896 FETCH(&r[1], 0, TGSI_CHAN_Y);
1897 FETCH(&r[2], 0, TGSI_CHAN_Z);
1899 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1901 fetch_texel(mach->Sampler, unit, unit,
1902 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1903 derivs, offsets, tgsi_sampler_derivs_explicit,
1904 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1907 case TGSI_TEXTURE_2D:
1908 case TGSI_TEXTURE_RECT:
1909 FETCH(&r[0], 0, TGSI_CHAN_X);
1910 FETCH(&r[1], 0, TGSI_CHAN_Y);
1912 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1913 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1915 fetch_texel(mach->Sampler, unit, unit,
1916 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
1917 derivs, offsets, tgsi_sampler_derivs_explicit,
1918 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
1922 case TGSI_TEXTURE_SHADOW2D:
1923 case TGSI_TEXTURE_SHADOWRECT:
1924 case TGSI_TEXTURE_2D_ARRAY:
1925 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1926 /* only SHADOW2D_ARRAY actually needs W */
1927 FETCH(&r[0], 0, TGSI_CHAN_X);
1928 FETCH(&r[1], 0, TGSI_CHAN_Y);
1929 FETCH(&r[2], 0, TGSI_CHAN_Z);
1930 FETCH(&r[3], 0, TGSI_CHAN_W);
1932 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1933 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1935 fetch_texel(mach->Sampler, unit, unit,
1936 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
1937 derivs, offsets, tgsi_sampler_derivs_explicit,
1938 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1941 case TGSI_TEXTURE_3D:
1942 case TGSI_TEXTURE_CUBE:
1943 case TGSI_TEXTURE_CUBE_ARRAY:
1944 /* only TEXTURE_CUBE_ARRAY actually needs W */
1945 FETCH(&r[0], 0, TGSI_CHAN_X);
1946 FETCH(&r[1], 0, TGSI_CHAN_Y);
1947 FETCH(&r[2], 0, TGSI_CHAN_Z);
1948 FETCH(&r[3], 0, TGSI_CHAN_W);
1950 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_X, derivs[0]);
1951 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Y, derivs[1]);
1952 fetch_assign_deriv_channel(mach, inst, 1, TGSI_CHAN_Z, derivs[2]);
1954 fetch_texel(mach->Sampler, unit, unit,
1955 &r[0], &r[1], &r[2], &r[3], &ZeroVec, /* inputs */
1956 derivs, offsets, tgsi_sampler_derivs_explicit,
1957 &r[0], &r[1], &r[2], &r[3]); /* outputs */
1964 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1965 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
1966 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
1973 exec_txf(struct tgsi_exec_machine *mach,
1974 const struct tgsi_full_instruction *inst)
1976 const uint unit = inst->Src[1].Register.Index;
1977 union tgsi_exec_channel r[4];
1979 float rgba[TGSI_NUM_CHANNELS][TGSI_QUAD_SIZE];
1984 /* always fetch all 3 offsets, overkill but keeps code simple */
1985 fetch_texel_offsets(mach, inst, offsets);
1987 IFETCH(&r[3], 0, TGSI_CHAN_W);
1989 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
1990 target = mach->SamplerViews[unit].Resource;
1993 target = inst->Texture.Texture;
1996 case TGSI_TEXTURE_3D:
1997 case TGSI_TEXTURE_2D_ARRAY:
1998 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1999 IFETCH(&r[2], 0, TGSI_CHAN_Z);
2001 case TGSI_TEXTURE_2D:
2002 case TGSI_TEXTURE_RECT:
2003 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2004 case TGSI_TEXTURE_SHADOW2D:
2005 case TGSI_TEXTURE_SHADOWRECT:
2006 case TGSI_TEXTURE_1D_ARRAY:
2007 IFETCH(&r[1], 0, TGSI_CHAN_Y);
2009 case TGSI_TEXTURE_BUFFER:
2010 case TGSI_TEXTURE_1D:
2011 case TGSI_TEXTURE_SHADOW1D:
2012 IFETCH(&r[0], 0, TGSI_CHAN_X);
2019 mach->Sampler->get_texel(mach->Sampler, unit, r[0].i, r[1].i, r[2].i, r[3].i,
2022 for (j = 0; j < TGSI_QUAD_SIZE; j++) {
2023 r[0].f[j] = rgba[0][j];
2024 r[1].f[j] = rgba[1][j];
2025 r[2].f[j] = rgba[2][j];
2026 r[3].f[j] = rgba[3][j];
2029 if (inst->Instruction.Opcode == TGSI_OPCODE_SAMPLE_I) {
2030 unsigned char swizzles[4];
2031 swizzles[0] = inst->Src[1].Register.SwizzleX;
2032 swizzles[1] = inst->Src[1].Register.SwizzleY;
2033 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2034 swizzles[3] = inst->Src[1].Register.SwizzleW;
2036 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2037 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2038 store_dest(mach, &r[swizzles[chan]],
2039 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2044 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2045 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2046 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2053 exec_txq(struct tgsi_exec_machine *mach,
2054 const struct tgsi_full_instruction *inst)
2056 const uint unit = inst->Src[1].Register.Index;
2058 union tgsi_exec_channel r[4], src;
2062 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_INT);
2064 /* XXX: This interface can't return per-pixel values */
2065 mach->Sampler->get_dims(mach->Sampler, unit, src.i[0], result);
2067 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2068 for (j = 0; j < 4; j++) {
2069 r[j].i[i] = result[j];
2073 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2074 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2075 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan,
2076 TGSI_EXEC_DATA_INT);
2082 exec_sample(struct tgsi_exec_machine *mach,
2083 const struct tgsi_full_instruction *inst,
2084 uint modifier, boolean compare)
2086 const uint resource_unit = inst->Src[1].Register.Index;
2087 const uint sampler_unit = inst->Src[2].Register.Index;
2088 union tgsi_exec_channel r[4], c1;
2089 const union tgsi_exec_channel *lod = &ZeroVec;
2090 enum tgsi_sampler_control control = tgsi_sampler_lod_none;
2092 unsigned char swizzles[4];
2095 /* always fetch all 3 offsets, overkill but keeps code simple */
2096 fetch_texel_offsets(mach, inst, offsets);
2098 assert(modifier != TEX_MODIFIER_PROJECTED);
2100 if (modifier != TEX_MODIFIER_NONE) {
2101 if (modifier == TEX_MODIFIER_LOD_BIAS) {
2102 FETCH(&c1, 3, TGSI_CHAN_X);
2104 control = tgsi_sampler_lod_bias;
2106 else if (modifier == TEX_MODIFIER_EXPLICIT_LOD) {
2107 FETCH(&c1, 3, TGSI_CHAN_X);
2109 control = tgsi_sampler_lod_explicit;
2112 assert(modifier == TEX_MODIFIER_LEVEL_ZERO);
2113 control = tgsi_sampler_lod_zero;
2117 FETCH(&r[0], 0, TGSI_CHAN_X);
2119 switch (mach->SamplerViews[resource_unit].Resource) {
2120 case TGSI_TEXTURE_1D:
2122 FETCH(&r[2], 3, TGSI_CHAN_X);
2123 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2124 &r[0], &ZeroVec, &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2125 NULL, offsets, control,
2126 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2129 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2130 &r[0], &ZeroVec, &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2131 NULL, offsets, control,
2132 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2136 case TGSI_TEXTURE_1D_ARRAY:
2137 case TGSI_TEXTURE_2D:
2138 case TGSI_TEXTURE_RECT:
2139 FETCH(&r[1], 0, TGSI_CHAN_Y);
2141 FETCH(&r[2], 3, TGSI_CHAN_X);
2142 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2143 &r[0], &r[1], &r[2], &ZeroVec, lod, /* S, T, P, C, LOD */
2144 NULL, offsets, control,
2145 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2148 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2149 &r[0], &r[1], &ZeroVec, &ZeroVec, lod, /* S, T, P, C, LOD */
2150 NULL, offsets, control,
2151 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2155 case TGSI_TEXTURE_2D_ARRAY:
2156 case TGSI_TEXTURE_3D:
2157 case TGSI_TEXTURE_CUBE:
2158 FETCH(&r[1], 0, TGSI_CHAN_Y);
2159 FETCH(&r[2], 0, TGSI_CHAN_Z);
2161 FETCH(&r[3], 3, TGSI_CHAN_X);
2162 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2163 &r[0], &r[1], &r[2], &r[3], lod,
2164 NULL, offsets, control,
2165 &r[0], &r[1], &r[2], &r[3]);
2168 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2169 &r[0], &r[1], &r[2], &ZeroVec, lod,
2170 NULL, offsets, control,
2171 &r[0], &r[1], &r[2], &r[3]);
2175 case TGSI_TEXTURE_CUBE_ARRAY:
2176 FETCH(&r[1], 0, TGSI_CHAN_Y);
2177 FETCH(&r[2], 0, TGSI_CHAN_Z);
2178 FETCH(&r[3], 0, TGSI_CHAN_W);
2180 FETCH(&r[4], 3, TGSI_CHAN_X);
2181 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2182 &r[0], &r[1], &r[2], &r[3], &r[4],
2183 NULL, offsets, control,
2184 &r[0], &r[1], &r[2], &r[3]);
2187 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2188 &r[0], &r[1], &r[2], &r[3], lod,
2189 NULL, offsets, control,
2190 &r[0], &r[1], &r[2], &r[3]);
2199 swizzles[0] = inst->Src[1].Register.SwizzleX;
2200 swizzles[1] = inst->Src[1].Register.SwizzleY;
2201 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2202 swizzles[3] = inst->Src[1].Register.SwizzleW;
2204 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2205 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2206 store_dest(mach, &r[swizzles[chan]],
2207 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2213 exec_sample_d(struct tgsi_exec_machine *mach,
2214 const struct tgsi_full_instruction *inst)
2216 const uint resource_unit = inst->Src[1].Register.Index;
2217 const uint sampler_unit = inst->Src[2].Register.Index;
2218 union tgsi_exec_channel r[4];
2219 float derivs[3][2][TGSI_QUAD_SIZE];
2221 unsigned char swizzles[4];
2224 /* always fetch all 3 offsets, overkill but keeps code simple */
2225 fetch_texel_offsets(mach, inst, offsets);
2227 FETCH(&r[0], 0, TGSI_CHAN_X);
2229 switch (mach->SamplerViews[resource_unit].Resource) {
2230 case TGSI_TEXTURE_1D:
2231 case TGSI_TEXTURE_1D_ARRAY:
2232 /* only 1D array actually needs Y */
2233 FETCH(&r[1], 0, TGSI_CHAN_Y);
2235 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2237 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2238 &r[0], &r[1], &ZeroVec, &ZeroVec, &ZeroVec, /* S, T, P, C, LOD */
2239 derivs, offsets, tgsi_sampler_derivs_explicit,
2240 &r[0], &r[1], &r[2], &r[3]); /* R, G, B, A */
2243 case TGSI_TEXTURE_2D:
2244 case TGSI_TEXTURE_RECT:
2245 case TGSI_TEXTURE_2D_ARRAY:
2246 /* only 2D array actually needs Z */
2247 FETCH(&r[1], 0, TGSI_CHAN_Y);
2248 FETCH(&r[2], 0, TGSI_CHAN_Z);
2250 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2251 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2253 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2254 &r[0], &r[1], &r[2], &ZeroVec, &ZeroVec, /* inputs */
2255 derivs, offsets, tgsi_sampler_derivs_explicit,
2256 &r[0], &r[1], &r[2], &r[3]); /* outputs */
2259 case TGSI_TEXTURE_3D:
2260 case TGSI_TEXTURE_CUBE:
2261 case TGSI_TEXTURE_CUBE_ARRAY:
2262 /* only cube array actually needs W */
2263 FETCH(&r[1], 0, TGSI_CHAN_Y);
2264 FETCH(&r[2], 0, TGSI_CHAN_Z);
2265 FETCH(&r[3], 0, TGSI_CHAN_W);
2267 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_X, derivs[0]);
2268 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Y, derivs[1]);
2269 fetch_assign_deriv_channel(mach, inst, 3, TGSI_CHAN_Z, derivs[2]);
2271 fetch_texel(mach->Sampler, resource_unit, sampler_unit,
2272 &r[0], &r[1], &r[2], &r[3], &ZeroVec,
2273 derivs, offsets, tgsi_sampler_derivs_explicit,
2274 &r[0], &r[1], &r[2], &r[3]);
2281 swizzles[0] = inst->Src[1].Register.SwizzleX;
2282 swizzles[1] = inst->Src[1].Register.SwizzleY;
2283 swizzles[2] = inst->Src[1].Register.SwizzleZ;
2284 swizzles[3] = inst->Src[1].Register.SwizzleW;
2286 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2287 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2288 store_dest(mach, &r[swizzles[chan]],
2289 &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2296 * Evaluate a constant-valued coefficient at the position of the
2301 struct tgsi_exec_machine *mach,
2307 for( i = 0; i < TGSI_QUAD_SIZE; i++ ) {
2308 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2313 * Evaluate a linear-valued coefficient at the position of the
2318 struct tgsi_exec_machine *mach,
2322 const float x = mach->QuadPos.xyzw[0].f[0];
2323 const float y = mach->QuadPos.xyzw[1].f[0];
2324 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2325 const float dady = mach->InterpCoefs[attrib].dady[chan];
2326 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2327 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2328 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2329 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2330 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2334 * Evaluate a perspective-valued coefficient at the position of the
2338 eval_perspective_coef(
2339 struct tgsi_exec_machine *mach,
2343 const float x = mach->QuadPos.xyzw[0].f[0];
2344 const float y = mach->QuadPos.xyzw[1].f[0];
2345 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2346 const float dady = mach->InterpCoefs[attrib].dady[chan];
2347 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2348 const float *w = mach->QuadPos.xyzw[3].f;
2349 /* divide by W here */
2350 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2351 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2352 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2353 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2357 typedef void (* eval_coef_func)(
2358 struct tgsi_exec_machine *mach,
2363 exec_declaration(struct tgsi_exec_machine *mach,
2364 const struct tgsi_full_declaration *decl)
2366 if (decl->Declaration.File == TGSI_FILE_SAMPLER_VIEW) {
2367 mach->SamplerViews[decl->Range.First] = decl->SamplerView;
2371 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
2372 if (decl->Declaration.File == TGSI_FILE_INPUT) {
2373 uint first, last, mask;
2375 first = decl->Range.First;
2376 last = decl->Range.Last;
2377 mask = decl->Declaration.UsageMask;
2379 /* XXX we could remove this special-case code since
2380 * mach->InterpCoefs[first].a0 should already have the
2381 * front/back-face value. But we should first update the
2382 * ureg code to emit the right UsageMask value (WRITEMASK_X).
2383 * Then, we could remove the tgsi_exec_machine::Face field.
2385 /* XXX make FACE a system value */
2386 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
2389 assert(decl->Semantic.Index == 0);
2390 assert(first == last);
2392 for (i = 0; i < TGSI_QUAD_SIZE; i++) {
2393 mach->Inputs[first].xyzw[0].f[i] = mach->Face;
2396 eval_coef_func eval;
2399 switch (decl->Interp.Interpolate) {
2400 case TGSI_INTERPOLATE_CONSTANT:
2401 eval = eval_constant_coef;
2404 case TGSI_INTERPOLATE_LINEAR:
2405 eval = eval_linear_coef;
2408 case TGSI_INTERPOLATE_PERSPECTIVE:
2409 eval = eval_perspective_coef;
2412 case TGSI_INTERPOLATE_COLOR:
2413 eval = mach->flatshade_color ? eval_constant_coef : eval_perspective_coef;
2421 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2422 if (mask & (1 << j)) {
2423 for (i = first; i <= last; i++) {
2430 if (DEBUG_EXECUTION) {
2432 for (i = first; i <= last; ++i) {
2433 debug_printf("IN[%2u] = ", i);
2434 for (j = 0; j < TGSI_NUM_CHANNELS; j++) {
2438 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
2439 mach->Inputs[i].xyzw[0].f[j], mach->Inputs[i].xyzw[0].u[j],
2440 mach->Inputs[i].xyzw[1].f[j], mach->Inputs[i].xyzw[1].u[j],
2441 mach->Inputs[i].xyzw[2].f[j], mach->Inputs[i].xyzw[2].u[j],
2442 mach->Inputs[i].xyzw[3].f[j], mach->Inputs[i].xyzw[3].u[j]);
2449 if (decl->Declaration.File == TGSI_FILE_SYSTEM_VALUE) {
2450 mach->SysSemanticToIndex[decl->Declaration.Semantic] = decl->Range.First;
2455 typedef void (* micro_op)(union tgsi_exec_channel *dst);
2458 exec_vector(struct tgsi_exec_machine *mach,
2459 const struct tgsi_full_instruction *inst,
2461 enum tgsi_exec_datatype dst_datatype)
2465 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2466 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2467 union tgsi_exec_channel dst;
2470 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2475 typedef void (* micro_unary_op)(union tgsi_exec_channel *dst,
2476 const union tgsi_exec_channel *src);
2479 exec_scalar_unary(struct tgsi_exec_machine *mach,
2480 const struct tgsi_full_instruction *inst,
2482 enum tgsi_exec_datatype dst_datatype,
2483 enum tgsi_exec_datatype src_datatype)
2486 union tgsi_exec_channel src;
2487 union tgsi_exec_channel dst;
2489 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, src_datatype);
2491 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2492 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2493 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2499 exec_vector_unary(struct tgsi_exec_machine *mach,
2500 const struct tgsi_full_instruction *inst,
2502 enum tgsi_exec_datatype dst_datatype,
2503 enum tgsi_exec_datatype src_datatype)
2506 struct tgsi_exec_vector dst;
2508 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2509 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2510 union tgsi_exec_channel src;
2512 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2513 op(&dst.xyzw[chan], &src);
2516 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2517 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2518 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2523 typedef void (* micro_binary_op)(union tgsi_exec_channel *dst,
2524 const union tgsi_exec_channel *src0,
2525 const union tgsi_exec_channel *src1);
2528 exec_scalar_binary(struct tgsi_exec_machine *mach,
2529 const struct tgsi_full_instruction *inst,
2531 enum tgsi_exec_datatype dst_datatype,
2532 enum tgsi_exec_datatype src_datatype)
2535 union tgsi_exec_channel src[2];
2536 union tgsi_exec_channel dst;
2538 fetch_source(mach, &src[0], &inst->Src[0], TGSI_CHAN_X, src_datatype);
2539 fetch_source(mach, &src[1], &inst->Src[1], TGSI_CHAN_X, src_datatype);
2540 op(&dst, &src[0], &src[1]);
2541 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2542 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2543 store_dest(mach, &dst, &inst->Dst[0], inst, chan, dst_datatype);
2549 exec_vector_binary(struct tgsi_exec_machine *mach,
2550 const struct tgsi_full_instruction *inst,
2552 enum tgsi_exec_datatype dst_datatype,
2553 enum tgsi_exec_datatype src_datatype)
2556 struct tgsi_exec_vector dst;
2558 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2559 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2560 union tgsi_exec_channel src[2];
2562 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2563 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2564 op(&dst.xyzw[chan], &src[0], &src[1]);
2567 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2568 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2569 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2574 typedef void (* micro_trinary_op)(union tgsi_exec_channel *dst,
2575 const union tgsi_exec_channel *src0,
2576 const union tgsi_exec_channel *src1,
2577 const union tgsi_exec_channel *src2);
2580 exec_vector_trinary(struct tgsi_exec_machine *mach,
2581 const struct tgsi_full_instruction *inst,
2582 micro_trinary_op op,
2583 enum tgsi_exec_datatype dst_datatype,
2584 enum tgsi_exec_datatype src_datatype)
2587 struct tgsi_exec_vector dst;
2589 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2590 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2591 union tgsi_exec_channel src[3];
2593 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2594 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2595 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2596 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2599 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2600 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2601 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan, dst_datatype);
2607 exec_dp3(struct tgsi_exec_machine *mach,
2608 const struct tgsi_full_instruction *inst)
2611 union tgsi_exec_channel arg[3];
2613 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2614 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2615 micro_mul(&arg[2], &arg[0], &arg[1]);
2617 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2618 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2619 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2620 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2623 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2624 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2625 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2631 exec_dp4(struct tgsi_exec_machine *mach,
2632 const struct tgsi_full_instruction *inst)
2635 union tgsi_exec_channel arg[3];
2637 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2638 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2639 micro_mul(&arg[2], &arg[0], &arg[1]);
2641 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2642 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2643 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
2644 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2647 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2648 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2649 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2655 exec_dp2a(struct tgsi_exec_machine *mach,
2656 const struct tgsi_full_instruction *inst)
2659 union tgsi_exec_channel arg[3];
2661 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2662 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2663 micro_mul(&arg[2], &arg[0], &arg[1]);
2665 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2666 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2667 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2669 fetch_source(mach, &arg[1], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2670 micro_add(&arg[0], &arg[0], &arg[1]);
2672 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2673 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2674 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2680 exec_dph(struct tgsi_exec_machine *mach,
2681 const struct tgsi_full_instruction *inst)
2684 union tgsi_exec_channel arg[3];
2686 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2687 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2688 micro_mul(&arg[2], &arg[0], &arg[1]);
2690 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2691 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2692 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2694 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2695 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2696 micro_mad(&arg[0], &arg[0], &arg[1], &arg[2]);
2698 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2699 micro_add(&arg[0], &arg[0], &arg[1]);
2701 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2702 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2703 store_dest(mach, &arg[0], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2709 exec_dp2(struct tgsi_exec_machine *mach,
2710 const struct tgsi_full_instruction *inst)
2713 union tgsi_exec_channel arg[3];
2715 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2716 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2717 micro_mul(&arg[2], &arg[0], &arg[1]);
2719 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2720 fetch_source(mach, &arg[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2721 micro_mad(&arg[2], &arg[0], &arg[1], &arg[2]);
2723 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2724 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2725 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2731 exec_nrm4(struct tgsi_exec_machine *mach,
2732 const struct tgsi_full_instruction *inst)
2735 union tgsi_exec_channel arg[4];
2736 union tgsi_exec_channel scale;
2738 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2739 micro_mul(&scale, &arg[0], &arg[0]);
2741 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
2742 union tgsi_exec_channel product;
2744 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2745 micro_mul(&product, &arg[chan], &arg[chan]);
2746 micro_add(&scale, &scale, &product);
2749 micro_rsq(&scale, &scale);
2751 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_W; chan++) {
2752 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2753 micro_mul(&arg[chan], &arg[chan], &scale);
2754 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2760 exec_nrm3(struct tgsi_exec_machine *mach,
2761 const struct tgsi_full_instruction *inst)
2763 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2765 union tgsi_exec_channel arg[3];
2766 union tgsi_exec_channel scale;
2768 fetch_source(mach, &arg[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2769 micro_mul(&scale, &arg[0], &arg[0]);
2771 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
2772 union tgsi_exec_channel product;
2774 fetch_source(mach, &arg[chan], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
2775 micro_mul(&product, &arg[chan], &arg[chan]);
2776 micro_add(&scale, &scale, &product);
2779 micro_rsq(&scale, &scale);
2781 for (chan = TGSI_CHAN_X; chan <= TGSI_CHAN_Z; chan++) {
2782 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2783 micro_mul(&arg[chan], &arg[chan], &scale);
2784 store_dest(mach, &arg[chan], &inst->Dst[0], inst, chan, TGSI_EXEC_DATA_FLOAT);
2789 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2790 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2795 exec_scs(struct tgsi_exec_machine *mach,
2796 const struct tgsi_full_instruction *inst)
2798 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XY) {
2799 union tgsi_exec_channel arg;
2800 union tgsi_exec_channel result;
2802 fetch_source(mach, &arg, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2804 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2805 micro_cos(&result, &arg);
2806 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2808 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2809 micro_sin(&result, &arg);
2810 store_dest(mach, &result, &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2813 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2814 store_dest(mach, &ZeroVec, &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2816 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2817 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2822 exec_x2d(struct tgsi_exec_machine *mach,
2823 const struct tgsi_full_instruction *inst)
2825 union tgsi_exec_channel r[4];
2826 union tgsi_exec_channel d[2];
2828 fetch_source(mach, &r[0], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2829 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2830 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XZ) {
2831 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2832 micro_mul(&r[2], &r[2], &r[0]);
2833 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2834 micro_mul(&r[3], &r[3], &r[1]);
2835 micro_add(&r[2], &r[2], &r[3]);
2836 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2837 micro_add(&d[0], &r[2], &r[3]);
2839 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YW) {
2840 fetch_source(mach, &r[2], &inst->Src[2], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2841 micro_mul(&r[2], &r[2], &r[0]);
2842 fetch_source(mach, &r[3], &inst->Src[2], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2843 micro_mul(&r[3], &r[3], &r[1]);
2844 micro_add(&r[2], &r[2], &r[3]);
2845 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2846 micro_add(&d[1], &r[2], &r[3]);
2848 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2849 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2851 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2852 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2854 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2855 store_dest(mach, &d[0], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2857 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2858 store_dest(mach, &d[1], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2863 exec_rfl(struct tgsi_exec_machine *mach,
2864 const struct tgsi_full_instruction *inst)
2866 union tgsi_exec_channel r[9];
2868 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_XYZ) {
2869 /* r0 = dp3(src0, src0) */
2870 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2871 micro_mul(&r[0], &r[2], &r[2]);
2872 fetch_source(mach, &r[4], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2873 micro_mul(&r[8], &r[4], &r[4]);
2874 micro_add(&r[0], &r[0], &r[8]);
2875 fetch_source(mach, &r[6], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2876 micro_mul(&r[8], &r[6], &r[6]);
2877 micro_add(&r[0], &r[0], &r[8]);
2879 /* r1 = dp3(src0, src1) */
2880 fetch_source(mach, &r[3], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2881 micro_mul(&r[1], &r[2], &r[3]);
2882 fetch_source(mach, &r[5], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2883 micro_mul(&r[8], &r[4], &r[5]);
2884 micro_add(&r[1], &r[1], &r[8]);
2885 fetch_source(mach, &r[7], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2886 micro_mul(&r[8], &r[6], &r[7]);
2887 micro_add(&r[1], &r[1], &r[8]);
2889 /* r1 = 2 * r1 / r0 */
2890 micro_add(&r[1], &r[1], &r[1]);
2891 micro_div(&r[1], &r[1], &r[0]);
2893 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2894 micro_mul(&r[2], &r[2], &r[1]);
2895 micro_sub(&r[2], &r[2], &r[3]);
2896 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2898 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2899 micro_mul(&r[4], &r[4], &r[1]);
2900 micro_sub(&r[4], &r[4], &r[5]);
2901 store_dest(mach, &r[4], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2903 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2904 micro_mul(&r[6], &r[6], &r[1]);
2905 micro_sub(&r[6], &r[6], &r[7]);
2906 store_dest(mach, &r[6], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2909 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2910 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2915 exec_xpd(struct tgsi_exec_machine *mach,
2916 const struct tgsi_full_instruction *inst)
2918 union tgsi_exec_channel r[6];
2919 union tgsi_exec_channel d[3];
2921 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2922 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2924 micro_mul(&r[2], &r[0], &r[1]);
2926 fetch_source(mach, &r[3], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2927 fetch_source(mach, &r[4], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2929 micro_mul(&r[5], &r[3], &r[4] );
2930 micro_sub(&d[TGSI_CHAN_X], &r[2], &r[5]);
2932 fetch_source(mach, &r[2], &inst->Src[1], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2934 micro_mul(&r[3], &r[3], &r[2]);
2936 fetch_source(mach, &r[5], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2938 micro_mul(&r[1], &r[1], &r[5]);
2939 micro_sub(&d[TGSI_CHAN_Y], &r[3], &r[1]);
2941 micro_mul(&r[5], &r[5], &r[4]);
2942 micro_mul(&r[0], &r[0], &r[2]);
2943 micro_sub(&d[TGSI_CHAN_Z], &r[5], &r[0]);
2945 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2946 store_dest(mach, &d[TGSI_CHAN_X], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2948 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2949 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2951 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2952 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2954 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2955 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2960 exec_dst(struct tgsi_exec_machine *mach,
2961 const struct tgsi_full_instruction *inst)
2963 union tgsi_exec_channel r[2];
2964 union tgsi_exec_channel d[4];
2966 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2967 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2968 fetch_source(mach, &r[1], &inst->Src[1], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2969 micro_mul(&d[TGSI_CHAN_Y], &r[0], &r[1]);
2971 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2972 fetch_source(mach, &d[TGSI_CHAN_Z], &inst->Src[0], TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2974 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2975 fetch_source(mach, &d[TGSI_CHAN_W], &inst->Src[1], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2978 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
2979 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2981 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
2982 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
2984 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
2985 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
2987 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
2988 store_dest(mach, &d[TGSI_CHAN_W], &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
2993 exec_log(struct tgsi_exec_machine *mach,
2994 const struct tgsi_full_instruction *inst)
2996 union tgsi_exec_channel r[3];
2998 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
2999 micro_abs(&r[2], &r[0]); /* r2 = abs(r0) */
3000 micro_lg2(&r[1], &r[2]); /* r1 = lg2(r2) */
3001 micro_flr(&r[0], &r[1]); /* r0 = floor(r1) */
3002 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3003 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3005 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3006 micro_exp2(&r[0], &r[0]); /* r0 = 2 ^ r0 */
3007 micro_div(&r[0], &r[2], &r[0]); /* r0 = r2 / r0 */
3008 store_dest(mach, &r[0], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3010 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3011 store_dest(mach, &r[1], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3013 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3014 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3019 exec_exp(struct tgsi_exec_machine *mach,
3020 const struct tgsi_full_instruction *inst)
3022 union tgsi_exec_channel r[3];
3024 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3025 micro_flr(&r[1], &r[0]); /* r1 = floor(r0) */
3026 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3027 micro_exp2(&r[2], &r[1]); /* r2 = 2 ^ r1 */
3028 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3030 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3031 micro_sub(&r[2], &r[0], &r[1]); /* r2 = r0 - r1 */
3032 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3034 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3035 micro_exp2(&r[2], &r[0]); /* r2 = 2 ^ r0 */
3036 store_dest(mach, &r[2], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3038 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3039 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3044 exec_lit(struct tgsi_exec_machine *mach,
3045 const struct tgsi_full_instruction *inst)
3047 union tgsi_exec_channel r[3];
3048 union tgsi_exec_channel d[3];
3050 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_YZ) {
3051 fetch_source(mach, &r[0], &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3052 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Z) {
3053 fetch_source(mach, &r[1], &inst->Src[0], TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3054 micro_max(&r[1], &r[1], &ZeroVec);
3056 fetch_source(mach, &r[2], &inst->Src[0], TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3057 micro_min(&r[2], &r[2], &P128Vec);
3058 micro_max(&r[2], &r[2], &M128Vec);
3059 micro_pow(&r[1], &r[1], &r[2]);
3060 micro_lt(&d[TGSI_CHAN_Z], &ZeroVec, &r[0], &r[1], &ZeroVec);
3061 store_dest(mach, &d[TGSI_CHAN_Z], &inst->Dst[0], inst, TGSI_CHAN_Z, TGSI_EXEC_DATA_FLOAT);
3063 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_Y) {
3064 micro_max(&d[TGSI_CHAN_Y], &r[0], &ZeroVec);
3065 store_dest(mach, &d[TGSI_CHAN_Y], &inst->Dst[0], inst, TGSI_CHAN_Y, TGSI_EXEC_DATA_FLOAT);
3068 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_X) {
3069 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_X, TGSI_EXEC_DATA_FLOAT);
3072 if (inst->Dst[0].Register.WriteMask & TGSI_WRITEMASK_W) {
3073 store_dest(mach, &OneVec, &inst->Dst[0], inst, TGSI_CHAN_W, TGSI_EXEC_DATA_FLOAT);
3078 exec_break(struct tgsi_exec_machine *mach)
3080 if (mach->BreakType == TGSI_EXEC_BREAK_INSIDE_LOOP) {
3081 /* turn off loop channels for each enabled exec channel */
3082 mach->LoopMask &= ~mach->ExecMask;
3083 /* Todo: if mach->LoopMask == 0, jump to end of loop */
3084 UPDATE_EXEC_MASK(mach);
3086 assert(mach->BreakType == TGSI_EXEC_BREAK_INSIDE_SWITCH);
3088 mach->Switch.mask = 0x0;
3090 UPDATE_EXEC_MASK(mach);
3095 exec_switch(struct tgsi_exec_machine *mach,
3096 const struct tgsi_full_instruction *inst)
3098 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3099 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3101 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3102 fetch_source(mach, &mach->Switch.selector, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3103 mach->Switch.mask = 0x0;
3104 mach->Switch.defaultMask = 0x0;
3106 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3107 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_SWITCH;
3109 UPDATE_EXEC_MASK(mach);
3113 exec_case(struct tgsi_exec_machine *mach,
3114 const struct tgsi_full_instruction *inst)
3116 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3117 union tgsi_exec_channel src;
3120 fetch_source(mach, &src, &inst->Src[0], TGSI_CHAN_X, TGSI_EXEC_DATA_UINT);
3122 if (mach->Switch.selector.u[0] == src.u[0]) {
3125 if (mach->Switch.selector.u[1] == src.u[1]) {
3128 if (mach->Switch.selector.u[2] == src.u[2]) {
3131 if (mach->Switch.selector.u[3] == src.u[3]) {
3135 mach->Switch.defaultMask |= mask;
3137 mach->Switch.mask |= mask & prevMask;
3139 UPDATE_EXEC_MASK(mach);
3142 /* FIXME: this will only work if default is last */
3144 exec_default(struct tgsi_exec_machine *mach)
3146 uint prevMask = mach->SwitchStack[mach->SwitchStackTop - 1].mask;
3148 mach->Switch.mask |= ~mach->Switch.defaultMask & prevMask;
3150 UPDATE_EXEC_MASK(mach);
3154 exec_endswitch(struct tgsi_exec_machine *mach)
3156 mach->Switch = mach->SwitchStack[--mach->SwitchStackTop];
3157 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
3159 UPDATE_EXEC_MASK(mach);
3163 micro_i2f(union tgsi_exec_channel *dst,
3164 const union tgsi_exec_channel *src)
3166 dst->f[0] = (float)src->i[0];
3167 dst->f[1] = (float)src->i[1];
3168 dst->f[2] = (float)src->i[2];
3169 dst->f[3] = (float)src->i[3];
3173 micro_not(union tgsi_exec_channel *dst,
3174 const union tgsi_exec_channel *src)
3176 dst->u[0] = ~src->u[0];
3177 dst->u[1] = ~src->u[1];
3178 dst->u[2] = ~src->u[2];
3179 dst->u[3] = ~src->u[3];
3183 micro_shl(union tgsi_exec_channel *dst,
3184 const union tgsi_exec_channel *src0,
3185 const union tgsi_exec_channel *src1)
3187 unsigned masked_count;
3188 masked_count = src1->u[0] & 0x1f;
3189 dst->u[0] = src0->u[0] << masked_count;
3190 masked_count = src1->u[1] & 0x1f;
3191 dst->u[1] = src0->u[1] << masked_count;
3192 masked_count = src1->u[2] & 0x1f;
3193 dst->u[2] = src0->u[2] << masked_count;
3194 masked_count = src1->u[3] & 0x1f;
3195 dst->u[3] = src0->u[3] << masked_count;
3199 micro_and(union tgsi_exec_channel *dst,
3200 const union tgsi_exec_channel *src0,
3201 const union tgsi_exec_channel *src1)
3203 dst->u[0] = src0->u[0] & src1->u[0];
3204 dst->u[1] = src0->u[1] & src1->u[1];
3205 dst->u[2] = src0->u[2] & src1->u[2];
3206 dst->u[3] = src0->u[3] & src1->u[3];
3210 micro_or(union tgsi_exec_channel *dst,
3211 const union tgsi_exec_channel *src0,
3212 const union tgsi_exec_channel *src1)
3214 dst->u[0] = src0->u[0] | src1->u[0];
3215 dst->u[1] = src0->u[1] | src1->u[1];
3216 dst->u[2] = src0->u[2] | src1->u[2];
3217 dst->u[3] = src0->u[3] | src1->u[3];
3221 micro_xor(union tgsi_exec_channel *dst,
3222 const union tgsi_exec_channel *src0,
3223 const union tgsi_exec_channel *src1)
3225 dst->u[0] = src0->u[0] ^ src1->u[0];
3226 dst->u[1] = src0->u[1] ^ src1->u[1];
3227 dst->u[2] = src0->u[2] ^ src1->u[2];
3228 dst->u[3] = src0->u[3] ^ src1->u[3];
3232 micro_mod(union tgsi_exec_channel *dst,
3233 const union tgsi_exec_channel *src0,
3234 const union tgsi_exec_channel *src1)
3236 dst->i[0] = src0->i[0] % src1->i[0];
3237 dst->i[1] = src0->i[1] % src1->i[1];
3238 dst->i[2] = src0->i[2] % src1->i[2];
3239 dst->i[3] = src0->i[3] % src1->i[3];
3243 micro_f2i(union tgsi_exec_channel *dst,
3244 const union tgsi_exec_channel *src)
3246 dst->i[0] = (int)src->f[0];
3247 dst->i[1] = (int)src->f[1];
3248 dst->i[2] = (int)src->f[2];
3249 dst->i[3] = (int)src->f[3];
3253 micro_fseq(union tgsi_exec_channel *dst,
3254 const union tgsi_exec_channel *src0,
3255 const union tgsi_exec_channel *src1)
3257 dst->u[0] = src0->f[0] == src1->f[0] ? ~0 : 0;
3258 dst->u[1] = src0->f[1] == src1->f[1] ? ~0 : 0;
3259 dst->u[2] = src0->f[2] == src1->f[2] ? ~0 : 0;
3260 dst->u[3] = src0->f[3] == src1->f[3] ? ~0 : 0;
3264 micro_fsge(union tgsi_exec_channel *dst,
3265 const union tgsi_exec_channel *src0,
3266 const union tgsi_exec_channel *src1)
3268 dst->u[0] = src0->f[0] >= src1->f[0] ? ~0 : 0;
3269 dst->u[1] = src0->f[1] >= src1->f[1] ? ~0 : 0;
3270 dst->u[2] = src0->f[2] >= src1->f[2] ? ~0 : 0;
3271 dst->u[3] = src0->f[3] >= src1->f[3] ? ~0 : 0;
3275 micro_fslt(union tgsi_exec_channel *dst,
3276 const union tgsi_exec_channel *src0,
3277 const union tgsi_exec_channel *src1)
3279 dst->u[0] = src0->f[0] < src1->f[0] ? ~0 : 0;
3280 dst->u[1] = src0->f[1] < src1->f[1] ? ~0 : 0;
3281 dst->u[2] = src0->f[2] < src1->f[2] ? ~0 : 0;
3282 dst->u[3] = src0->f[3] < src1->f[3] ? ~0 : 0;
3286 micro_fsne(union tgsi_exec_channel *dst,
3287 const union tgsi_exec_channel *src0,
3288 const union tgsi_exec_channel *src1)
3290 dst->u[0] = src0->f[0] != src1->f[0] ? ~0 : 0;
3291 dst->u[1] = src0->f[1] != src1->f[1] ? ~0 : 0;
3292 dst->u[2] = src0->f[2] != src1->f[2] ? ~0 : 0;
3293 dst->u[3] = src0->f[3] != src1->f[3] ? ~0 : 0;
3297 micro_idiv(union tgsi_exec_channel *dst,
3298 const union tgsi_exec_channel *src0,
3299 const union tgsi_exec_channel *src1)
3301 dst->i[0] = src0->i[0] / src1->i[0];
3302 dst->i[1] = src0->i[1] / src1->i[1];
3303 dst->i[2] = src0->i[2] / src1->i[2];
3304 dst->i[3] = src0->i[3] / src1->i[3];
3308 micro_imax(union tgsi_exec_channel *dst,
3309 const union tgsi_exec_channel *src0,
3310 const union tgsi_exec_channel *src1)
3312 dst->i[0] = src0->i[0] > src1->i[0] ? src0->i[0] : src1->i[0];
3313 dst->i[1] = src0->i[1] > src1->i[1] ? src0->i[1] : src1->i[1];
3314 dst->i[2] = src0->i[2] > src1->i[2] ? src0->i[2] : src1->i[2];
3315 dst->i[3] = src0->i[3] > src1->i[3] ? src0->i[3] : src1->i[3];
3319 micro_imin(union tgsi_exec_channel *dst,
3320 const union tgsi_exec_channel *src0,
3321 const union tgsi_exec_channel *src1)
3323 dst->i[0] = src0->i[0] < src1->i[0] ? src0->i[0] : src1->i[0];
3324 dst->i[1] = src0->i[1] < src1->i[1] ? src0->i[1] : src1->i[1];
3325 dst->i[2] = src0->i[2] < src1->i[2] ? src0->i[2] : src1->i[2];
3326 dst->i[3] = src0->i[3] < src1->i[3] ? src0->i[3] : src1->i[3];
3330 micro_isge(union tgsi_exec_channel *dst,
3331 const union tgsi_exec_channel *src0,
3332 const union tgsi_exec_channel *src1)
3334 dst->i[0] = src0->i[0] >= src1->i[0] ? -1 : 0;
3335 dst->i[1] = src0->i[1] >= src1->i[1] ? -1 : 0;
3336 dst->i[2] = src0->i[2] >= src1->i[2] ? -1 : 0;
3337 dst->i[3] = src0->i[3] >= src1->i[3] ? -1 : 0;
3341 micro_ishr(union tgsi_exec_channel *dst,
3342 const union tgsi_exec_channel *src0,
3343 const union tgsi_exec_channel *src1)
3345 unsigned masked_count;
3346 masked_count = src1->i[0] & 0x1f;
3347 dst->i[0] = src0->i[0] >> masked_count;
3348 masked_count = src1->i[1] & 0x1f;
3349 dst->i[1] = src0->i[1] >> masked_count;
3350 masked_count = src1->i[2] & 0x1f;
3351 dst->i[2] = src0->i[2] >> masked_count;
3352 masked_count = src1->i[3] & 0x1f;
3353 dst->i[3] = src0->i[3] >> masked_count;
3357 micro_islt(union tgsi_exec_channel *dst,
3358 const union tgsi_exec_channel *src0,
3359 const union tgsi_exec_channel *src1)
3361 dst->i[0] = src0->i[0] < src1->i[0] ? -1 : 0;
3362 dst->i[1] = src0->i[1] < src1->i[1] ? -1 : 0;
3363 dst->i[2] = src0->i[2] < src1->i[2] ? -1 : 0;
3364 dst->i[3] = src0->i[3] < src1->i[3] ? -1 : 0;
3368 micro_f2u(union tgsi_exec_channel *dst,
3369 const union tgsi_exec_channel *src)
3371 dst->u[0] = (uint)src->f[0];
3372 dst->u[1] = (uint)src->f[1];
3373 dst->u[2] = (uint)src->f[2];
3374 dst->u[3] = (uint)src->f[3];
3378 micro_u2f(union tgsi_exec_channel *dst,
3379 const union tgsi_exec_channel *src)
3381 dst->f[0] = (float)src->u[0];
3382 dst->f[1] = (float)src->u[1];
3383 dst->f[2] = (float)src->u[2];
3384 dst->f[3] = (float)src->u[3];
3388 micro_uadd(union tgsi_exec_channel *dst,
3389 const union tgsi_exec_channel *src0,
3390 const union tgsi_exec_channel *src1)
3392 dst->u[0] = src0->u[0] + src1->u[0];
3393 dst->u[1] = src0->u[1] + src1->u[1];
3394 dst->u[2] = src0->u[2] + src1->u[2];
3395 dst->u[3] = src0->u[3] + src1->u[3];
3399 micro_udiv(union tgsi_exec_channel *dst,
3400 const union tgsi_exec_channel *src0,
3401 const union tgsi_exec_channel *src1)
3403 dst->u[0] = src1->u[0] ? src0->u[0] / src1->u[0] : ~0u;
3404 dst->u[1] = src1->u[1] ? src0->u[1] / src1->u[1] : ~0u;
3405 dst->u[2] = src1->u[2] ? src0->u[2] / src1->u[2] : ~0u;
3406 dst->u[3] = src1->u[3] ? src0->u[3] / src1->u[3] : ~0u;
3410 micro_umad(union tgsi_exec_channel *dst,
3411 const union tgsi_exec_channel *src0,
3412 const union tgsi_exec_channel *src1,
3413 const union tgsi_exec_channel *src2)
3415 dst->u[0] = src0->u[0] * src1->u[0] + src2->u[0];
3416 dst->u[1] = src0->u[1] * src1->u[1] + src2->u[1];
3417 dst->u[2] = src0->u[2] * src1->u[2] + src2->u[2];
3418 dst->u[3] = src0->u[3] * src1->u[3] + src2->u[3];
3422 micro_umax(union tgsi_exec_channel *dst,
3423 const union tgsi_exec_channel *src0,
3424 const union tgsi_exec_channel *src1)
3426 dst->u[0] = src0->u[0] > src1->u[0] ? src0->u[0] : src1->u[0];
3427 dst->u[1] = src0->u[1] > src1->u[1] ? src0->u[1] : src1->u[1];
3428 dst->u[2] = src0->u[2] > src1->u[2] ? src0->u[2] : src1->u[2];
3429 dst->u[3] = src0->u[3] > src1->u[3] ? src0->u[3] : src1->u[3];
3433 micro_umin(union tgsi_exec_channel *dst,
3434 const union tgsi_exec_channel *src0,
3435 const union tgsi_exec_channel *src1)
3437 dst->u[0] = src0->u[0] < src1->u[0] ? src0->u[0] : src1->u[0];
3438 dst->u[1] = src0->u[1] < src1->u[1] ? src0->u[1] : src1->u[1];
3439 dst->u[2] = src0->u[2] < src1->u[2] ? src0->u[2] : src1->u[2];
3440 dst->u[3] = src0->u[3] < src1->u[3] ? src0->u[3] : src1->u[3];
3444 micro_umod(union tgsi_exec_channel *dst,
3445 const union tgsi_exec_channel *src0,
3446 const union tgsi_exec_channel *src1)
3448 dst->u[0] = src1->u[0] ? src0->u[0] % src1->u[0] : ~0u;
3449 dst->u[1] = src1->u[1] ? src0->u[1] % src1->u[1] : ~0u;
3450 dst->u[2] = src1->u[2] ? src0->u[2] % src1->u[2] : ~0u;
3451 dst->u[3] = src1->u[3] ? src0->u[3] % src1->u[3] : ~0u;
3455 micro_umul(union tgsi_exec_channel *dst,
3456 const union tgsi_exec_channel *src0,
3457 const union tgsi_exec_channel *src1)
3459 dst->u[0] = src0->u[0] * src1->u[0];
3460 dst->u[1] = src0->u[1] * src1->u[1];
3461 dst->u[2] = src0->u[2] * src1->u[2];
3462 dst->u[3] = src0->u[3] * src1->u[3];
3466 micro_imul_hi(union tgsi_exec_channel *dst,
3467 const union tgsi_exec_channel *src0,
3468 const union tgsi_exec_channel *src1)
3470 #define I64M(x, y) ((((int64_t)x) * ((int64_t)y)) >> 32)
3471 dst->i[0] = I64M(src0->i[0], src1->i[0]);
3472 dst->i[1] = I64M(src0->i[1], src1->i[1]);
3473 dst->i[2] = I64M(src0->i[2], src1->i[2]);
3474 dst->i[3] = I64M(src0->i[3], src1->i[3]);
3479 micro_umul_hi(union tgsi_exec_channel *dst,
3480 const union tgsi_exec_channel *src0,
3481 const union tgsi_exec_channel *src1)
3483 #define U64M(x, y) ((((uint64_t)x) * ((uint64_t)y)) >> 32)
3484 dst->u[0] = U64M(src0->u[0], src1->u[0]);
3485 dst->u[1] = U64M(src0->u[1], src1->u[1]);
3486 dst->u[2] = U64M(src0->u[2], src1->u[2]);
3487 dst->u[3] = U64M(src0->u[3], src1->u[3]);
3492 micro_useq(union tgsi_exec_channel *dst,
3493 const union tgsi_exec_channel *src0,
3494 const union tgsi_exec_channel *src1)
3496 dst->u[0] = src0->u[0] == src1->u[0] ? ~0 : 0;
3497 dst->u[1] = src0->u[1] == src1->u[1] ? ~0 : 0;
3498 dst->u[2] = src0->u[2] == src1->u[2] ? ~0 : 0;
3499 dst->u[3] = src0->u[3] == src1->u[3] ? ~0 : 0;
3503 micro_usge(union tgsi_exec_channel *dst,
3504 const union tgsi_exec_channel *src0,
3505 const union tgsi_exec_channel *src1)
3507 dst->u[0] = src0->u[0] >= src1->u[0] ? ~0 : 0;
3508 dst->u[1] = src0->u[1] >= src1->u[1] ? ~0 : 0;
3509 dst->u[2] = src0->u[2] >= src1->u[2] ? ~0 : 0;
3510 dst->u[3] = src0->u[3] >= src1->u[3] ? ~0 : 0;
3514 micro_ushr(union tgsi_exec_channel *dst,
3515 const union tgsi_exec_channel *src0,
3516 const union tgsi_exec_channel *src1)
3518 unsigned masked_count;
3519 masked_count = src1->u[0] & 0x1f;
3520 dst->u[0] = src0->u[0] >> masked_count;
3521 masked_count = src1->u[1] & 0x1f;
3522 dst->u[1] = src0->u[1] >> masked_count;
3523 masked_count = src1->u[2] & 0x1f;
3524 dst->u[2] = src0->u[2] >> masked_count;
3525 masked_count = src1->u[3] & 0x1f;
3526 dst->u[3] = src0->u[3] >> masked_count;
3530 micro_uslt(union tgsi_exec_channel *dst,
3531 const union tgsi_exec_channel *src0,
3532 const union tgsi_exec_channel *src1)
3534 dst->u[0] = src0->u[0] < src1->u[0] ? ~0 : 0;
3535 dst->u[1] = src0->u[1] < src1->u[1] ? ~0 : 0;
3536 dst->u[2] = src0->u[2] < src1->u[2] ? ~0 : 0;
3537 dst->u[3] = src0->u[3] < src1->u[3] ? ~0 : 0;
3541 micro_usne(union tgsi_exec_channel *dst,
3542 const union tgsi_exec_channel *src0,
3543 const union tgsi_exec_channel *src1)
3545 dst->u[0] = src0->u[0] != src1->u[0] ? ~0 : 0;
3546 dst->u[1] = src0->u[1] != src1->u[1] ? ~0 : 0;
3547 dst->u[2] = src0->u[2] != src1->u[2] ? ~0 : 0;
3548 dst->u[3] = src0->u[3] != src1->u[3] ? ~0 : 0;
3552 micro_uarl(union tgsi_exec_channel *dst,
3553 const union tgsi_exec_channel *src)
3555 dst->i[0] = src->u[0];
3556 dst->i[1] = src->u[1];
3557 dst->i[2] = src->u[2];
3558 dst->i[3] = src->u[3];
3562 micro_ucmp(union tgsi_exec_channel *dst,
3563 const union tgsi_exec_channel *src0,
3564 const union tgsi_exec_channel *src1,
3565 const union tgsi_exec_channel *src2)
3567 dst->u[0] = src0->u[0] ? src1->u[0] : src2->u[0];
3568 dst->u[1] = src0->u[1] ? src1->u[1] : src2->u[1];
3569 dst->u[2] = src0->u[2] ? src1->u[2] : src2->u[2];
3570 dst->u[3] = src0->u[3] ? src1->u[3] : src2->u[3];
3575 struct tgsi_exec_machine *mach,
3576 const struct tgsi_full_instruction *inst,
3579 union tgsi_exec_channel r[10];
3583 switch (inst->Instruction.Opcode) {
3584 case TGSI_OPCODE_ARL:
3585 exec_vector_unary(mach, inst, micro_arl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3588 case TGSI_OPCODE_MOV:
3589 exec_vector_unary(mach, inst, micro_mov, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
3592 case TGSI_OPCODE_LIT:
3593 exec_lit(mach, inst);
3596 case TGSI_OPCODE_RCP:
3597 exec_scalar_unary(mach, inst, micro_rcp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3600 case TGSI_OPCODE_RSQ:
3601 exec_scalar_unary(mach, inst, micro_rsq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3604 case TGSI_OPCODE_EXP:
3605 exec_exp(mach, inst);
3608 case TGSI_OPCODE_LOG:
3609 exec_log(mach, inst);
3612 case TGSI_OPCODE_MUL:
3613 exec_vector_binary(mach, inst, micro_mul, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3616 case TGSI_OPCODE_ADD:
3617 exec_vector_binary(mach, inst, micro_add, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3620 case TGSI_OPCODE_DP3:
3621 exec_dp3(mach, inst);
3624 case TGSI_OPCODE_DP4:
3625 exec_dp4(mach, inst);
3628 case TGSI_OPCODE_DST:
3629 exec_dst(mach, inst);
3632 case TGSI_OPCODE_MIN:
3633 exec_vector_binary(mach, inst, micro_min, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3636 case TGSI_OPCODE_MAX:
3637 exec_vector_binary(mach, inst, micro_max, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3640 case TGSI_OPCODE_SLT:
3641 exec_vector_binary(mach, inst, micro_slt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3644 case TGSI_OPCODE_SGE:
3645 exec_vector_binary(mach, inst, micro_sge, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3648 case TGSI_OPCODE_MAD:
3649 exec_vector_trinary(mach, inst, micro_mad, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3652 case TGSI_OPCODE_SUB:
3653 exec_vector_binary(mach, inst, micro_sub, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3656 case TGSI_OPCODE_LRP:
3657 exec_vector_trinary(mach, inst, micro_lrp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3660 case TGSI_OPCODE_CND:
3661 exec_vector_trinary(mach, inst, micro_cnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3664 case TGSI_OPCODE_SQRT:
3665 exec_scalar_unary(mach, inst, micro_sqrt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3668 case TGSI_OPCODE_DP2A:
3669 exec_dp2a(mach, inst);
3672 case TGSI_OPCODE_FRC:
3673 exec_vector_unary(mach, inst, micro_frc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3676 case TGSI_OPCODE_CLAMP:
3677 exec_vector_trinary(mach, inst, micro_clamp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3680 case TGSI_OPCODE_FLR:
3681 exec_vector_unary(mach, inst, micro_flr, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3684 case TGSI_OPCODE_ROUND:
3685 exec_vector_unary(mach, inst, micro_rnd, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3688 case TGSI_OPCODE_EX2:
3689 exec_scalar_unary(mach, inst, micro_exp2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3692 case TGSI_OPCODE_LG2:
3693 exec_scalar_unary(mach, inst, micro_lg2, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3696 case TGSI_OPCODE_POW:
3697 exec_scalar_binary(mach, inst, micro_pow, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3700 case TGSI_OPCODE_XPD:
3701 exec_xpd(mach, inst);
3704 case TGSI_OPCODE_ABS:
3705 exec_vector_unary(mach, inst, micro_abs, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3708 case TGSI_OPCODE_RCC:
3709 exec_scalar_unary(mach, inst, micro_rcc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3712 case TGSI_OPCODE_DPH:
3713 exec_dph(mach, inst);
3716 case TGSI_OPCODE_COS:
3717 exec_scalar_unary(mach, inst, micro_cos, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3720 case TGSI_OPCODE_DDX:
3721 exec_vector_unary(mach, inst, micro_ddx, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3724 case TGSI_OPCODE_DDY:
3725 exec_vector_unary(mach, inst, micro_ddy, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3728 case TGSI_OPCODE_KILL:
3729 exec_kill (mach, inst);
3732 case TGSI_OPCODE_KILL_IF:
3733 exec_kill_if (mach, inst);
3736 case TGSI_OPCODE_PK2H:
3740 case TGSI_OPCODE_PK2US:
3744 case TGSI_OPCODE_PK4B:
3748 case TGSI_OPCODE_PK4UB:
3752 case TGSI_OPCODE_RFL:
3753 exec_rfl(mach, inst);
3756 case TGSI_OPCODE_SEQ:
3757 exec_vector_binary(mach, inst, micro_seq, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3760 case TGSI_OPCODE_SFL:
3761 exec_vector(mach, inst, micro_sfl, TGSI_EXEC_DATA_FLOAT);
3764 case TGSI_OPCODE_SGT:
3765 exec_vector_binary(mach, inst, micro_sgt, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3768 case TGSI_OPCODE_SIN:
3769 exec_scalar_unary(mach, inst, micro_sin, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3772 case TGSI_OPCODE_SLE:
3773 exec_vector_binary(mach, inst, micro_sle, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3776 case TGSI_OPCODE_SNE:
3777 exec_vector_binary(mach, inst, micro_sne, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3780 case TGSI_OPCODE_STR:
3781 exec_vector(mach, inst, micro_str, TGSI_EXEC_DATA_FLOAT);
3784 case TGSI_OPCODE_TEX:
3785 /* simple texture lookup */
3786 /* src[0] = texcoord */
3787 /* src[1] = sampler unit */
3788 exec_tex(mach, inst, TEX_MODIFIER_NONE, 1);
3791 case TGSI_OPCODE_TXB:
3792 /* Texture lookup with lod bias */
3793 /* src[0] = texcoord (src[0].w = LOD bias) */
3794 /* src[1] = sampler unit */
3795 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 1);
3798 case TGSI_OPCODE_TXD:
3799 /* Texture lookup with explict partial derivatives */
3800 /* src[0] = texcoord */
3801 /* src[1] = d[strq]/dx */
3802 /* src[2] = d[strq]/dy */
3803 /* src[3] = sampler unit */
3804 exec_txd(mach, inst);
3807 case TGSI_OPCODE_TXL:
3808 /* Texture lookup with explit LOD */
3809 /* src[0] = texcoord (src[0].w = LOD) */
3810 /* src[1] = sampler unit */
3811 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 1);
3814 case TGSI_OPCODE_TXP:
3815 /* Texture lookup with projection */
3816 /* src[0] = texcoord (src[0].w = projection) */
3817 /* src[1] = sampler unit */
3818 exec_tex(mach, inst, TEX_MODIFIER_PROJECTED, 1);
3821 case TGSI_OPCODE_UP2H:
3825 case TGSI_OPCODE_UP2US:
3829 case TGSI_OPCODE_UP4B:
3833 case TGSI_OPCODE_UP4UB:
3837 case TGSI_OPCODE_X2D:
3838 exec_x2d(mach, inst);
3841 case TGSI_OPCODE_ARA:
3845 case TGSI_OPCODE_ARR:
3846 exec_vector_unary(mach, inst, micro_arr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
3849 case TGSI_OPCODE_BRA:
3853 case TGSI_OPCODE_CAL:
3854 /* skip the call if no execution channels are enabled */
3855 if (mach->ExecMask) {
3858 /* First, record the depths of the execution stacks.
3859 * This is important for deeply nested/looped return statements.
3860 * We have to unwind the stacks by the correct amount. For a
3861 * real code generator, we could determine the number of entries
3862 * to pop off each stack with simple static analysis and avoid
3863 * implementing this data structure at run time.
3865 mach->CallStack[mach->CallStackTop].CondStackTop = mach->CondStackTop;
3866 mach->CallStack[mach->CallStackTop].LoopStackTop = mach->LoopStackTop;
3867 mach->CallStack[mach->CallStackTop].ContStackTop = mach->ContStackTop;
3868 mach->CallStack[mach->CallStackTop].SwitchStackTop = mach->SwitchStackTop;
3869 mach->CallStack[mach->CallStackTop].BreakStackTop = mach->BreakStackTop;
3870 /* note that PC was already incremented above */
3871 mach->CallStack[mach->CallStackTop].ReturnAddr = *pc;
3873 mach->CallStackTop++;
3875 /* Second, push the Cond, Loop, Cont, Func stacks */
3876 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3877 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3878 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
3879 assert(mach->SwitchStackTop < TGSI_EXEC_MAX_SWITCH_NESTING);
3880 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
3881 assert(mach->FuncStackTop < TGSI_EXEC_MAX_CALL_NESTING);
3883 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3884 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
3885 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
3886 mach->SwitchStack[mach->SwitchStackTop++] = mach->Switch;
3887 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
3888 mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
3890 /* Finally, jump to the subroutine */
3891 *pc = inst->Label.Label;
3895 case TGSI_OPCODE_RET:
3896 mach->FuncMask &= ~mach->ExecMask;
3897 UPDATE_EXEC_MASK(mach);
3899 if (mach->FuncMask == 0x0) {
3900 /* really return now (otherwise, keep executing */
3902 if (mach->CallStackTop == 0) {
3903 /* returning from main() */
3904 mach->CondStackTop = 0;
3905 mach->LoopStackTop = 0;
3910 assert(mach->CallStackTop > 0);
3911 mach->CallStackTop--;
3913 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
3914 mach->CondMask = mach->CondStack[mach->CondStackTop];
3916 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
3917 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
3919 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
3920 mach->ContMask = mach->ContStack[mach->ContStackTop];
3922 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
3923 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
3925 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
3926 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
3928 assert(mach->FuncStackTop > 0);
3929 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
3931 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
3933 UPDATE_EXEC_MASK(mach);
3937 case TGSI_OPCODE_SSG:
3938 exec_vector_unary(mach, inst, micro_sgn, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3941 case TGSI_OPCODE_CMP:
3942 exec_vector_trinary(mach, inst, micro_cmp, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3945 case TGSI_OPCODE_SCS:
3946 exec_scs(mach, inst);
3949 case TGSI_OPCODE_NRM:
3950 exec_nrm3(mach, inst);
3953 case TGSI_OPCODE_NRM4:
3954 exec_nrm4(mach, inst);
3957 case TGSI_OPCODE_DIV:
3958 exec_vector_binary(mach, inst, micro_div, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
3961 case TGSI_OPCODE_DP2:
3962 exec_dp2(mach, inst);
3965 case TGSI_OPCODE_IF:
3967 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3968 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3969 FETCH( &r[0], 0, TGSI_CHAN_X );
3970 /* update CondMask */
3972 mach->CondMask &= ~0x1;
3975 mach->CondMask &= ~0x2;
3978 mach->CondMask &= ~0x4;
3981 mach->CondMask &= ~0x8;
3983 UPDATE_EXEC_MASK(mach);
3984 /* Todo: If CondMask==0, jump to ELSE */
3987 case TGSI_OPCODE_UIF:
3989 assert(mach->CondStackTop < TGSI_EXEC_MAX_COND_NESTING);
3990 mach->CondStack[mach->CondStackTop++] = mach->CondMask;
3991 IFETCH( &r[0], 0, TGSI_CHAN_X );
3992 /* update CondMask */
3994 mach->CondMask &= ~0x1;
3997 mach->CondMask &= ~0x2;
4000 mach->CondMask &= ~0x4;
4003 mach->CondMask &= ~0x8;
4005 UPDATE_EXEC_MASK(mach);
4006 /* Todo: If CondMask==0, jump to ELSE */
4009 case TGSI_OPCODE_ELSE:
4010 /* invert CondMask wrt previous mask */
4013 assert(mach->CondStackTop > 0);
4014 prevMask = mach->CondStack[mach->CondStackTop - 1];
4015 mach->CondMask = ~mach->CondMask & prevMask;
4016 UPDATE_EXEC_MASK(mach);
4017 /* Todo: If CondMask==0, jump to ENDIF */
4021 case TGSI_OPCODE_ENDIF:
4023 assert(mach->CondStackTop > 0);
4024 mach->CondMask = mach->CondStack[--mach->CondStackTop];
4025 UPDATE_EXEC_MASK(mach);
4028 case TGSI_OPCODE_END:
4029 /* make sure we end primitives which haven't
4030 * been explicitly emitted */
4031 conditional_emit_primitive(mach);
4032 /* halt execution */
4036 case TGSI_OPCODE_PUSHA:
4040 case TGSI_OPCODE_POPA:
4044 case TGSI_OPCODE_CEIL:
4045 exec_vector_unary(mach, inst, micro_ceil, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4048 case TGSI_OPCODE_I2F:
4049 exec_vector_unary(mach, inst, micro_i2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_INT);
4052 case TGSI_OPCODE_NOT:
4053 exec_vector_unary(mach, inst, micro_not, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4056 case TGSI_OPCODE_TRUNC:
4057 exec_vector_unary(mach, inst, micro_trunc, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_FLOAT);
4060 case TGSI_OPCODE_SHL:
4061 exec_vector_binary(mach, inst, micro_shl, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4064 case TGSI_OPCODE_AND:
4065 exec_vector_binary(mach, inst, micro_and, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4068 case TGSI_OPCODE_OR:
4069 exec_vector_binary(mach, inst, micro_or, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4072 case TGSI_OPCODE_MOD:
4073 exec_vector_binary(mach, inst, micro_mod, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4076 case TGSI_OPCODE_XOR:
4077 exec_vector_binary(mach, inst, micro_xor, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4080 case TGSI_OPCODE_SAD:
4084 case TGSI_OPCODE_TXF:
4085 exec_txf(mach, inst);
4088 case TGSI_OPCODE_TXQ:
4089 exec_txq(mach, inst);
4092 case TGSI_OPCODE_EMIT:
4096 case TGSI_OPCODE_ENDPRIM:
4097 emit_primitive(mach);
4100 case TGSI_OPCODE_BGNLOOP:
4101 /* push LoopMask and ContMasks */
4102 assert(mach->LoopStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4103 assert(mach->ContStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4104 assert(mach->LoopLabelStackTop < TGSI_EXEC_MAX_LOOP_NESTING);
4105 assert(mach->BreakStackTop < TGSI_EXEC_MAX_BREAK_STACK);
4107 mach->LoopStack[mach->LoopStackTop++] = mach->LoopMask;
4108 mach->ContStack[mach->ContStackTop++] = mach->ContMask;
4109 mach->LoopLabelStack[mach->LoopLabelStackTop++] = *pc - 1;
4110 mach->BreakStack[mach->BreakStackTop++] = mach->BreakType;
4111 mach->BreakType = TGSI_EXEC_BREAK_INSIDE_LOOP;
4114 case TGSI_OPCODE_ENDLOOP:
4115 /* Restore ContMask, but don't pop */
4116 assert(mach->ContStackTop > 0);
4117 mach->ContMask = mach->ContStack[mach->ContStackTop - 1];
4118 UPDATE_EXEC_MASK(mach);
4119 if (mach->ExecMask) {
4120 /* repeat loop: jump to instruction just past BGNLOOP */
4121 assert(mach->LoopLabelStackTop > 0);
4122 *pc = mach->LoopLabelStack[mach->LoopLabelStackTop - 1] + 1;
4125 /* exit loop: pop LoopMask */
4126 assert(mach->LoopStackTop > 0);
4127 mach->LoopMask = mach->LoopStack[--mach->LoopStackTop];
4129 assert(mach->ContStackTop > 0);
4130 mach->ContMask = mach->ContStack[--mach->ContStackTop];
4131 assert(mach->LoopLabelStackTop > 0);
4132 --mach->LoopLabelStackTop;
4134 mach->BreakType = mach->BreakStack[--mach->BreakStackTop];
4136 UPDATE_EXEC_MASK(mach);
4139 case TGSI_OPCODE_BRK:
4143 case TGSI_OPCODE_CONT:
4144 /* turn off cont channels for each enabled exec channel */
4145 mach->ContMask &= ~mach->ExecMask;
4146 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4147 UPDATE_EXEC_MASK(mach);
4150 case TGSI_OPCODE_BGNSUB:
4154 case TGSI_OPCODE_ENDSUB:
4156 * XXX: This really should be a no-op. We should never reach this opcode.
4159 assert(mach->CallStackTop > 0);
4160 mach->CallStackTop--;
4162 mach->CondStackTop = mach->CallStack[mach->CallStackTop].CondStackTop;
4163 mach->CondMask = mach->CondStack[mach->CondStackTop];
4165 mach->LoopStackTop = mach->CallStack[mach->CallStackTop].LoopStackTop;
4166 mach->LoopMask = mach->LoopStack[mach->LoopStackTop];
4168 mach->ContStackTop = mach->CallStack[mach->CallStackTop].ContStackTop;
4169 mach->ContMask = mach->ContStack[mach->ContStackTop];
4171 mach->SwitchStackTop = mach->CallStack[mach->CallStackTop].SwitchStackTop;
4172 mach->Switch = mach->SwitchStack[mach->SwitchStackTop];
4174 mach->BreakStackTop = mach->CallStack[mach->CallStackTop].BreakStackTop;
4175 mach->BreakType = mach->BreakStack[mach->BreakStackTop];
4177 assert(mach->FuncStackTop > 0);
4178 mach->FuncMask = mach->FuncStack[--mach->FuncStackTop];
4180 *pc = mach->CallStack[mach->CallStackTop].ReturnAddr;
4182 UPDATE_EXEC_MASK(mach);
4185 case TGSI_OPCODE_NOP:
4188 case TGSI_OPCODE_BREAKC:
4189 IFETCH(&r[0], 0, TGSI_CHAN_X);
4190 /* update CondMask */
4191 if (r[0].u[0] && (mach->ExecMask & 0x1)) {
4192 mach->LoopMask &= ~0x1;
4194 if (r[0].u[1] && (mach->ExecMask & 0x2)) {
4195 mach->LoopMask &= ~0x2;
4197 if (r[0].u[2] && (mach->ExecMask & 0x4)) {
4198 mach->LoopMask &= ~0x4;
4200 if (r[0].u[3] && (mach->ExecMask & 0x8)) {
4201 mach->LoopMask &= ~0x8;
4203 /* Todo: if mach->LoopMask == 0, jump to end of loop */
4204 UPDATE_EXEC_MASK(mach);
4207 case TGSI_OPCODE_F2I:
4208 exec_vector_unary(mach, inst, micro_f2i, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_FLOAT);
4211 case TGSI_OPCODE_FSEQ:
4212 exec_vector_binary(mach, inst, micro_fseq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4215 case TGSI_OPCODE_FSGE:
4216 exec_vector_binary(mach, inst, micro_fsge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4219 case TGSI_OPCODE_FSLT:
4220 exec_vector_binary(mach, inst, micro_fslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4223 case TGSI_OPCODE_FSNE:
4224 exec_vector_binary(mach, inst, micro_fsne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4227 case TGSI_OPCODE_IDIV:
4228 exec_vector_binary(mach, inst, micro_idiv, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4231 case TGSI_OPCODE_IMAX:
4232 exec_vector_binary(mach, inst, micro_imax, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4235 case TGSI_OPCODE_IMIN:
4236 exec_vector_binary(mach, inst, micro_imin, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4239 case TGSI_OPCODE_INEG:
4240 exec_vector_unary(mach, inst, micro_ineg, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4243 case TGSI_OPCODE_ISGE:
4244 exec_vector_binary(mach, inst, micro_isge, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4247 case TGSI_OPCODE_ISHR:
4248 exec_vector_binary(mach, inst, micro_ishr, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4251 case TGSI_OPCODE_ISLT:
4252 exec_vector_binary(mach, inst, micro_islt, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4255 case TGSI_OPCODE_F2U:
4256 exec_vector_unary(mach, inst, micro_f2u, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_FLOAT);
4259 case TGSI_OPCODE_U2F:
4260 exec_vector_unary(mach, inst, micro_u2f, TGSI_EXEC_DATA_FLOAT, TGSI_EXEC_DATA_UINT);
4263 case TGSI_OPCODE_UADD:
4264 exec_vector_binary(mach, inst, micro_uadd, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4267 case TGSI_OPCODE_UDIV:
4268 exec_vector_binary(mach, inst, micro_udiv, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4271 case TGSI_OPCODE_UMAD:
4272 exec_vector_trinary(mach, inst, micro_umad, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4275 case TGSI_OPCODE_UMAX:
4276 exec_vector_binary(mach, inst, micro_umax, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4279 case TGSI_OPCODE_UMIN:
4280 exec_vector_binary(mach, inst, micro_umin, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4283 case TGSI_OPCODE_UMOD:
4284 exec_vector_binary(mach, inst, micro_umod, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4287 case TGSI_OPCODE_UMUL:
4288 exec_vector_binary(mach, inst, micro_umul, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4291 case TGSI_OPCODE_IMUL_HI:
4292 exec_vector_binary(mach, inst, micro_imul_hi, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4295 case TGSI_OPCODE_UMUL_HI:
4296 exec_vector_binary(mach, inst, micro_umul_hi, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4299 case TGSI_OPCODE_USEQ:
4300 exec_vector_binary(mach, inst, micro_useq, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4303 case TGSI_OPCODE_USGE:
4304 exec_vector_binary(mach, inst, micro_usge, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4307 case TGSI_OPCODE_USHR:
4308 exec_vector_binary(mach, inst, micro_ushr, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4311 case TGSI_OPCODE_USLT:
4312 exec_vector_binary(mach, inst, micro_uslt, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4315 case TGSI_OPCODE_USNE:
4316 exec_vector_binary(mach, inst, micro_usne, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4319 case TGSI_OPCODE_SWITCH:
4320 exec_switch(mach, inst);
4323 case TGSI_OPCODE_CASE:
4324 exec_case(mach, inst);
4327 case TGSI_OPCODE_DEFAULT:
4331 case TGSI_OPCODE_ENDSWITCH:
4332 exec_endswitch(mach);
4335 case TGSI_OPCODE_SAMPLE_I:
4336 exec_txf(mach, inst);
4339 case TGSI_OPCODE_SAMPLE_I_MS:
4343 case TGSI_OPCODE_SAMPLE:
4344 exec_sample(mach, inst, TEX_MODIFIER_NONE, FALSE);
4347 case TGSI_OPCODE_SAMPLE_B:
4348 exec_sample(mach, inst, TEX_MODIFIER_LOD_BIAS, FALSE);
4351 case TGSI_OPCODE_SAMPLE_C:
4352 exec_sample(mach, inst, TEX_MODIFIER_NONE, TRUE);
4355 case TGSI_OPCODE_SAMPLE_C_LZ:
4356 exec_sample(mach, inst, TEX_MODIFIER_LEVEL_ZERO, TRUE);
4359 case TGSI_OPCODE_SAMPLE_D:
4360 exec_sample_d(mach, inst);
4363 case TGSI_OPCODE_SAMPLE_L:
4364 exec_sample(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, FALSE);
4367 case TGSI_OPCODE_GATHER4:
4371 case TGSI_OPCODE_SVIEWINFO:
4372 exec_txq(mach, inst);
4375 case TGSI_OPCODE_SAMPLE_POS:
4379 case TGSI_OPCODE_SAMPLE_INFO:
4383 case TGSI_OPCODE_UARL:
4384 exec_vector_unary(mach, inst, micro_uarl, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_UINT);
4387 case TGSI_OPCODE_UCMP:
4388 exec_vector_trinary(mach, inst, micro_ucmp, TGSI_EXEC_DATA_UINT, TGSI_EXEC_DATA_UINT);
4391 case TGSI_OPCODE_IABS:
4392 exec_vector_unary(mach, inst, micro_iabs, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4395 case TGSI_OPCODE_ISSG:
4396 exec_vector_unary(mach, inst, micro_isgn, TGSI_EXEC_DATA_INT, TGSI_EXEC_DATA_INT);
4399 case TGSI_OPCODE_TEX2:
4400 /* simple texture lookup */
4401 /* src[0] = texcoord */
4402 /* src[1] = compare */
4403 /* src[2] = sampler unit */
4404 exec_tex(mach, inst, TEX_MODIFIER_NONE, 2);
4406 case TGSI_OPCODE_TXB2:
4407 /* simple texture lookup */
4408 /* src[0] = texcoord */
4410 /* src[2] = sampler unit */
4411 exec_tex(mach, inst, TEX_MODIFIER_LOD_BIAS, 2);
4413 case TGSI_OPCODE_TXL2:
4414 /* simple texture lookup */
4415 /* src[0] = texcoord */
4417 /* src[2] = sampler unit */
4418 exec_tex(mach, inst, TEX_MODIFIER_EXPLICIT_LOD, 2);
4427 * Run TGSI interpreter.
4428 * \return bitmask of "alive" quad components
4431 tgsi_exec_machine_run( struct tgsi_exec_machine *mach )
4435 uint default_mask = 0xf;
4437 mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0] = 0;
4438 mach->Temps[TEMP_OUTPUT_I].xyzw[TEMP_OUTPUT_C].u[0] = 0;
4440 if( mach->Processor == TGSI_PROCESSOR_GEOMETRY ) {
4441 mach->Temps[TEMP_PRIMITIVE_I].xyzw[TEMP_PRIMITIVE_C].u[0] = 0;
4442 mach->Primitives[0] = 0;
4443 /* GS runs on a single primitive for now */
4447 mach->CondMask = default_mask;
4448 mach->LoopMask = default_mask;
4449 mach->ContMask = default_mask;
4450 mach->FuncMask = default_mask;
4451 mach->ExecMask = default_mask;
4453 mach->Switch.mask = default_mask;
4455 assert(mach->CondStackTop == 0);
4456 assert(mach->LoopStackTop == 0);
4457 assert(mach->ContStackTop == 0);
4458 assert(mach->SwitchStackTop == 0);
4459 assert(mach->BreakStackTop == 0);
4460 assert(mach->CallStackTop == 0);
4463 /* execute declarations (interpolants) */
4464 for (i = 0; i < mach->NumDeclarations; i++) {
4465 exec_declaration( mach, mach->Declarations+i );
4470 struct tgsi_exec_vector temps[TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS];
4471 struct tgsi_exec_vector outputs[PIPE_MAX_ATTRIBS];
4474 memset(mach->Temps, 0, sizeof(temps));
4475 memset(mach->Outputs, 0, sizeof(outputs));
4476 memset(temps, 0, sizeof(temps));
4477 memset(outputs, 0, sizeof(outputs));
4480 /* execute instructions, until pc is set to -1 */
4486 tgsi_dump_instruction(&mach->Instructions[pc], inst++);
4489 assert(pc < (int) mach->NumInstructions);
4490 exec_instruction(mach, mach->Instructions + pc, &pc);
4493 for (i = 0; i < TGSI_EXEC_NUM_TEMPS + TGSI_EXEC_NUM_TEMP_EXTRAS; i++) {
4494 if (memcmp(&temps[i], &mach->Temps[i], sizeof(temps[i]))) {
4497 memcpy(&temps[i], &mach->Temps[i], sizeof(temps[i]));
4498 debug_printf("TEMP[%2u] = ", i);
4499 for (j = 0; j < 4; j++) {
4503 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4504 temps[i].xyzw[0].f[j], temps[i].xyzw[0].u[j],
4505 temps[i].xyzw[1].f[j], temps[i].xyzw[1].u[j],
4506 temps[i].xyzw[2].f[j], temps[i].xyzw[2].u[j],
4507 temps[i].xyzw[3].f[j], temps[i].xyzw[3].u[j]);
4511 for (i = 0; i < PIPE_MAX_ATTRIBS; i++) {
4512 if (memcmp(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]))) {
4515 memcpy(&outputs[i], &mach->Outputs[i], sizeof(outputs[i]));
4516 debug_printf("OUT[%2u] = ", i);
4517 for (j = 0; j < 4; j++) {
4521 debug_printf("(%6f %u, %6f %u, %6f %u, %6f %u)\n",
4522 outputs[i].xyzw[0].f[j], outputs[i].xyzw[0].u[j],
4523 outputs[i].xyzw[1].f[j], outputs[i].xyzw[1].u[j],
4524 outputs[i].xyzw[2].f[j], outputs[i].xyzw[2].u[j],
4525 outputs[i].xyzw[3].f[j], outputs[i].xyzw[3].u[j]);
4534 /* we scale from floats in [0,1] to Zbuffer ints in sp_quad_depth_test.c */
4535 if (mach->Processor == TGSI_PROCESSOR_FRAGMENT) {
4537 * Scale back depth component.
4539 for (i = 0; i < 4; i++)
4540 mach->Outputs[0].xyzw[2].f[i] *= ctx->DrawBuffer->_DepthMaxF;
4544 /* Strictly speaking, these assertions aren't really needed but they
4545 * can potentially catch some bugs in the control flow code.
4547 assert(mach->CondStackTop == 0);
4548 assert(mach->LoopStackTop == 0);
4549 assert(mach->ContStackTop == 0);
4550 assert(mach->SwitchStackTop == 0);
4551 assert(mach->BreakStackTop == 0);
4552 assert(mach->CallStackTop == 0);
4554 return ~mach->Temps[TEMP_KILMASK_I].xyzw[TEMP_KILMASK_C].u[0];