2 * Copyright (c) 2012-2015 Etnaviv Project
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 * Christian Gmeiner <christian.gmeiner@gmail.com>
28 #include "etnaviv_screen.h"
30 #include "hw/common.xml.h"
32 #include "etnaviv_compiler.h"
33 #include "etnaviv_context.h"
34 #include "etnaviv_debug.h"
35 #include "etnaviv_fence.h"
36 #include "etnaviv_format.h"
37 #include "etnaviv_query.h"
38 #include "etnaviv_resource.h"
39 #include "etnaviv_translate.h"
41 #include "util/os_time.h"
42 #include "util/u_math.h"
43 #include "util/u_memory.h"
44 #include "util/u_string.h"
46 #include "state_tracker/drm_driver.h"
48 #include <drm_fourcc.h>
50 #define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor))
51 #define ETNA_DRM_VERSION_FENCE_FD ETNA_DRM_VERSION(1, 1)
52 #define ETNA_DRM_VERSION_PERFMON ETNA_DRM_VERSION(1, 2)
54 static const struct debug_named_value debug_options[] = {
55 {"dbg_msgs", ETNA_DBG_MSGS, "Print debug messages"},
56 {"frame_msgs", ETNA_DBG_FRAME_MSGS, "Print frame messages"},
57 {"resource_msgs", ETNA_DBG_RESOURCE_MSGS, "Print resource messages"},
58 {"compiler_msgs", ETNA_DBG_COMPILER_MSGS, "Print compiler messages"},
59 {"linker_msgs", ETNA_DBG_LINKER_MSGS, "Print linker messages"},
60 {"dump_shaders", ETNA_DBG_DUMP_SHADERS, "Dump shaders"},
61 {"no_ts", ETNA_DBG_NO_TS, "Disable TS"},
62 {"no_autodisable", ETNA_DBG_NO_AUTODISABLE, "Disable autodisable"},
63 {"no_supertile", ETNA_DBG_NO_SUPERTILE, "Disable supertiles"},
64 {"no_early_z", ETNA_DBG_NO_EARLY_Z, "Disable early z"},
65 {"cflush_all", ETNA_DBG_CFLUSH_ALL, "Flush every cash before state update"},
66 {"msaa2x", ETNA_DBG_MSAA_2X, "Force 2x msaa"},
67 {"msaa4x", ETNA_DBG_MSAA_4X, "Force 4x msaa"},
68 {"flush_all", ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"},
69 {"zero", ETNA_DBG_ZERO, "Zero all resources after allocation"},
70 {"draw_stall", ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"},
71 {"shaderdb", ETNA_DBG_SHADERDB, "Enable shaderdb output"},
72 {"no_singlebuffer",ETNA_DBG_NO_SINGLEBUF, "Disable single buffer feature"},
76 DEBUG_GET_ONCE_FLAGS_OPTION(etna_mesa_debug, "ETNA_MESA_DEBUG", debug_options, 0)
77 int etna_mesa_debug = 0;
80 etna_screen_destroy(struct pipe_screen *pscreen)
82 struct etna_screen *screen = etna_screen(pscreen);
85 etna_perfmon_del(screen->perfmon);
88 etna_pipe_del(screen->pipe);
91 etna_gpu_del(screen->gpu);
97 etna_device_del(screen->dev);
103 etna_screen_get_name(struct pipe_screen *pscreen)
105 struct etna_screen *priv = etna_screen(pscreen);
106 static char buffer[128];
108 util_snprintf(buffer, sizeof(buffer), "Vivante GC%x rev %04x", priv->model,
115 etna_screen_get_vendor(struct pipe_screen *pscreen)
121 etna_screen_get_device_vendor(struct pipe_screen *pscreen)
127 etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
129 struct etna_screen *screen = etna_screen(pscreen);
132 /* Supported features (boolean caps). */
133 case PIPE_CAP_ANISOTROPIC_FILTER:
134 case PIPE_CAP_POINT_SPRITE:
135 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
136 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
137 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
139 case PIPE_CAP_TEXTURE_BARRIER:
140 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
141 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
142 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
143 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
144 case PIPE_CAP_TGSI_TEXCOORD:
145 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
146 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
148 case PIPE_CAP_NATIVE_FENCE_FD:
149 return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
152 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
154 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
155 return 4; /* XXX could easily be supported */
156 case PIPE_CAP_GLSL_FEATURE_LEVEL:
157 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
160 case PIPE_CAP_NPOT_TEXTURES:
161 return true; /* VIV_FEATURE(priv->dev, chipMinorFeatures1,
162 NON_POWER_OF_TWO); */
164 case PIPE_CAP_TEXTURE_SWIZZLE:
165 case PIPE_CAP_PRIMITIVE_RESTART:
166 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
168 case PIPE_CAP_ENDIANNESS:
169 return PIPE_ENDIAN_LITTLE; /* on most Viv hw this is configurable (feature
170 ENDIANNESS_CONFIG) */
172 /* Unsupported features. */
173 case PIPE_CAP_SEAMLESS_CUBE_MAP:
174 case PIPE_CAP_COMPUTE: /* XXX supported on gc2000 */
175 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: /* only one colorbuffer supported, so mixing makes no sense */
176 case PIPE_CAP_CONDITIONAL_RENDER: /* no occlusion queries */
177 case PIPE_CAP_TGSI_INSTANCEID: /* no idea, really */
178 case PIPE_CAP_START_INSTANCE: /* instancing not supported AFAIK */
179 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* instancing not supported AFAIK */
180 case PIPE_CAP_SHADER_STENCIL_EXPORT: /* Fragment shader cannot export stencil value */
181 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: /* no dual-source supported */
182 case PIPE_CAP_TEXTURE_MULTISAMPLE: /* no texture multisample */
183 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: /* only mirrored repeat */
184 case PIPE_CAP_INDEP_BLEND_ENABLE:
185 case PIPE_CAP_INDEP_BLEND_FUNC:
186 case PIPE_CAP_DEPTH_CLIP_DISABLE:
187 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
188 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
189 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
190 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: /* Don't skip strict max uniform limit check */
191 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
192 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
193 case PIPE_CAP_USER_VERTEX_BUFFERS:
194 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
195 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
196 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
197 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: /* TODO: test me out with piglit */
198 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
199 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
200 case PIPE_CAP_TEXTURE_GATHER_SM5:
201 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
202 case PIPE_CAP_FAKE_SW_MSAA:
203 case PIPE_CAP_TEXTURE_QUERY_LOD:
204 case PIPE_CAP_SAMPLE_SHADING:
205 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
206 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
207 case PIPE_CAP_DRAW_INDIRECT:
208 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
209 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
210 case PIPE_CAP_SAMPLER_VIEW_TARGET:
211 case PIPE_CAP_CLIP_HALFZ:
212 case PIPE_CAP_VERTEXID_NOBASE:
213 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
214 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
215 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
216 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
217 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
218 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
219 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
220 case PIPE_CAP_DEPTH_BOUNDS_TEST:
221 case PIPE_CAP_TGSI_TXQS:
222 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
223 case PIPE_CAP_SHAREABLE_SHADERS:
224 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
225 case PIPE_CAP_CLEAR_TEXTURE:
226 case PIPE_CAP_DRAW_PARAMETERS:
227 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
228 case PIPE_CAP_MULTI_DRAW_INDIRECT:
229 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
230 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
231 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
232 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
233 case PIPE_CAP_INVALIDATE_BUFFER:
234 case PIPE_CAP_GENERATE_MIPMAP:
235 case PIPE_CAP_STRING_MARKER:
236 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
237 case PIPE_CAP_QUERY_BUFFER_OBJECT:
238 case PIPE_CAP_QUERY_MEMORY_INFO:
239 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
240 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
241 case PIPE_CAP_CULL_DISTANCE:
242 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
243 case PIPE_CAP_TGSI_VOTE:
244 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
245 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
246 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
247 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
248 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
249 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
250 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
251 case PIPE_CAP_TGSI_FS_FBFETCH:
252 case PIPE_CAP_TGSI_MUL_ZERO_WINS:
253 case PIPE_CAP_DOUBLES:
255 case PIPE_CAP_INT64_DIVMOD:
256 case PIPE_CAP_TGSI_TEX_TXF_LZ:
257 case PIPE_CAP_TGSI_CLOCK:
258 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
259 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
260 case PIPE_CAP_TGSI_BALLOT:
261 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
262 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
263 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
264 case PIPE_CAP_POST_DEPTH_COVERAGE:
265 case PIPE_CAP_BINDLESS_TEXTURE:
266 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
267 case PIPE_CAP_QUERY_SO_OVERFLOW:
268 case PIPE_CAP_MEMOBJ:
269 case PIPE_CAP_LOAD_CONSTBUF:
270 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
271 case PIPE_CAP_TILE_RASTER_ORDER:
272 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
273 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
274 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
275 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
276 case PIPE_CAP_FENCE_SIGNAL:
277 case PIPE_CAP_CONSTBUF0_FLAGS:
278 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
279 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
280 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
281 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
282 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
283 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
284 case PIPE_CAP_PACKED_UNIFORMS:
285 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
288 case PIPE_CAP_MAX_GS_INVOCATIONS:
292 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
293 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
294 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
295 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
298 /* Geometry shader output, unsupported. */
299 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
300 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
301 case PIPE_CAP_MAX_VERTEX_STREAMS:
304 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
308 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
309 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
311 int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
312 assert(log2_max_tex_size > 0);
313 return log2_max_tex_size;
315 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: /* 3D textures not supported - fake it */
317 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
319 case PIPE_CAP_CUBE_MAP_ARRAY:
321 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
322 case PIPE_CAP_MIN_TEXEL_OFFSET:
324 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
325 case PIPE_CAP_MAX_TEXEL_OFFSET:
327 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
329 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
332 /* Render targets. */
333 case PIPE_CAP_MAX_RENDER_TARGETS:
336 /* Viewports and scissors. */
337 case PIPE_CAP_MAX_VIEWPORTS:
341 case PIPE_CAP_QUERY_TIME_ELAPSED:
343 case PIPE_CAP_OCCLUSION_QUERY:
344 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
345 case PIPE_CAP_QUERY_TIMESTAMP:
347 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
351 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
354 case PIPE_CAP_PCI_GROUP:
355 case PIPE_CAP_PCI_BUS:
356 case PIPE_CAP_PCI_DEVICE:
357 case PIPE_CAP_PCI_FUNCTION:
359 case PIPE_CAP_VENDOR_ID:
360 case PIPE_CAP_DEVICE_ID:
362 case PIPE_CAP_ACCELERATED:
364 case PIPE_CAP_VIDEO_MEMORY:
370 debug_printf("unknown param %d", param);
375 etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
377 struct etna_screen *screen = etna_screen(pscreen);
380 case PIPE_CAPF_MAX_LINE_WIDTH:
381 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
382 case PIPE_CAPF_MAX_POINT_WIDTH:
383 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
385 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
387 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
388 return util_last_bit(screen->specs.max_texture_size);
389 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
390 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
391 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
395 debug_printf("unknown paramf %d", param);
400 etna_screen_get_shader_param(struct pipe_screen *pscreen,
401 enum pipe_shader_type shader,
402 enum pipe_shader_cap param)
404 struct etna_screen *screen = etna_screen(pscreen);
407 case PIPE_SHADER_FRAGMENT:
408 case PIPE_SHADER_VERTEX:
410 case PIPE_SHADER_COMPUTE:
411 case PIPE_SHADER_GEOMETRY:
412 case PIPE_SHADER_TESS_CTRL:
413 case PIPE_SHADER_TESS_EVAL:
416 DBG("unknown shader type %d", shader);
421 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
422 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
423 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
424 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
425 return ETNA_MAX_TOKENS;
426 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
427 return ETNA_MAX_DEPTH; /* XXX */
428 case PIPE_SHADER_CAP_MAX_INPUTS:
429 /* Maximum number of inputs for the vertex shader is the number
430 * of vertex elements - each element defines one vertex shader
431 * input register. For the fragment shader, this is the number
433 return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
434 : screen->specs.vertex_max_elements;
435 case PIPE_SHADER_CAP_MAX_OUTPUTS:
436 return 16; /* see VIVS_VS_OUTPUT */
437 case PIPE_SHADER_CAP_MAX_TEMPS:
438 return 64; /* Max native temporaries. */
439 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
441 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
443 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
444 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
445 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
446 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
448 case PIPE_SHADER_CAP_SUBROUTINES:
450 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
451 return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
452 case PIPE_SHADER_CAP_INTEGERS:
453 case PIPE_SHADER_CAP_INT64_ATOMICS:
454 case PIPE_SHADER_CAP_FP16:
456 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
457 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
458 return shader == PIPE_SHADER_FRAGMENT
459 ? screen->specs.fragment_sampler_count
460 : screen->specs.vertex_sampler_count;
461 case PIPE_SHADER_CAP_PREFERRED_IR:
462 return PIPE_SHADER_IR_TGSI;
463 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
465 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
466 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
467 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
468 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
469 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
471 case PIPE_SHADER_CAP_SUPPORTED_IRS:
473 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
475 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
476 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
477 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
478 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
479 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
480 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
481 case PIPE_SHADER_CAP_SCALAR_ISA:
485 debug_printf("unknown shader param %d", param);
490 etna_screen_get_timestamp(struct pipe_screen *pscreen)
492 return os_time_get_nano();
496 gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt,
497 enum pipe_format format)
499 bool supported = true;
501 if (fmt == TEXTURE_FORMAT_ETC1)
502 supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
504 if (fmt >= TEXTURE_FORMAT_DXT1 && fmt <= TEXTURE_FORMAT_DXT4_DXT5)
505 supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
507 if (util_format_is_srgb(format))
508 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
510 if (fmt & EXT_FORMAT) {
511 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
513 /* ETC1 is checked above, as it has its own feature bit. ETC2 is
514 * supported with HALTI0, however that implementation is buggy in hardware.
515 * The blob driver does per-block patching to work around this. As this
516 * is currently not implemented by etnaviv, enable it for HALTI1 (GC3000)
519 if (util_format_is_etc(format))
520 supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1);
523 if (fmt & ASTC_FORMAT) {
524 supported = screen->specs.tex_astc;
530 if (texture_format_needs_swiz(format))
531 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
537 etna_screen_is_format_supported(struct pipe_screen *pscreen,
538 enum pipe_format format,
539 enum pipe_texture_target target,
540 unsigned sample_count,
541 unsigned storage_sample_count,
544 struct etna_screen *screen = etna_screen(pscreen);
545 unsigned allowed = 0;
547 if (target != PIPE_BUFFER &&
548 target != PIPE_TEXTURE_1D &&
549 target != PIPE_TEXTURE_2D &&
550 target != PIPE_TEXTURE_3D &&
551 target != PIPE_TEXTURE_CUBE &&
552 target != PIPE_TEXTURE_RECT)
555 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
558 if (usage & PIPE_BIND_RENDER_TARGET) {
559 /* if render target, must be RS-supported format */
560 if (translate_rs_format(format) != ETNA_NO_MATCH) {
561 /* Validate MSAA; number of samples must be allowed, and render target
562 * must have MSAA'able format. */
563 if (sample_count > 1) {
564 if (translate_samples_to_xyscale(sample_count, NULL, NULL, NULL) &&
565 translate_msaa_format(format) != ETNA_NO_MATCH) {
566 allowed |= PIPE_BIND_RENDER_TARGET;
569 allowed |= PIPE_BIND_RENDER_TARGET;
574 if (usage & PIPE_BIND_DEPTH_STENCIL) {
575 if (translate_depth_format(format) != ETNA_NO_MATCH)
576 allowed |= PIPE_BIND_DEPTH_STENCIL;
579 if (usage & PIPE_BIND_SAMPLER_VIEW) {
580 uint32_t fmt = translate_texture_format(format);
582 if (!gpu_supports_texure_format(screen, fmt, format))
585 if (sample_count < 2 && fmt != ETNA_NO_MATCH)
586 allowed |= PIPE_BIND_SAMPLER_VIEW;
589 if (usage & PIPE_BIND_VERTEX_BUFFER) {
590 if (translate_vertex_format_type(format) != ETNA_NO_MATCH)
591 allowed |= PIPE_BIND_VERTEX_BUFFER;
594 if (usage & PIPE_BIND_INDEX_BUFFER) {
595 /* must be supported index format */
596 if (format == PIPE_FORMAT_I8_UINT || format == PIPE_FORMAT_I16_UINT ||
597 (format == PIPE_FORMAT_I32_UINT &&
598 VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
599 allowed |= PIPE_BIND_INDEX_BUFFER;
605 usage & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED);
607 if (usage != allowed) {
608 DBG("not supported: format=%s, target=%d, sample_count=%d, "
609 "usage=%x, allowed=%x",
610 util_format_name(format), target, sample_count, usage, allowed);
613 return usage == allowed;
616 const uint64_t supported_modifiers[] = {
617 DRM_FORMAT_MOD_LINEAR,
618 DRM_FORMAT_MOD_VIVANTE_TILED,
619 DRM_FORMAT_MOD_VIVANTE_SUPER_TILED,
620 DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED,
621 DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED,
625 etna_screen_query_dmabuf_modifiers(struct pipe_screen *pscreen,
626 enum pipe_format format, int max,
628 unsigned int *external_only, int *count)
630 struct etna_screen *screen = etna_screen(pscreen);
631 int i, num_modifiers = 0;
633 if (max > ARRAY_SIZE(supported_modifiers))
634 max = ARRAY_SIZE(supported_modifiers);
638 max = ARRAY_SIZE(supported_modifiers);
641 for (i = 0; num_modifiers < max; i++) {
642 /* don't advertise split tiled formats on single pipe/buffer GPUs */
643 if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) &&
648 modifiers[num_modifiers] = supported_modifiers[i];
650 external_only[num_modifiers] = util_format_is_yuv(format) ? 1 : 0;
654 *count = num_modifiers;
658 etna_get_specs(struct etna_screen *screen)
661 uint32_t instruction_count;
663 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
664 DBG("could not get ETNA_GPU_INSTRUCTION_COUNT");
667 instruction_count = val;
669 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
671 DBG("could not get ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE");
674 screen->specs.vertex_output_buffer_size = val;
676 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
677 DBG("could not get ETNA_GPU_VERTEX_CACHE_SIZE");
680 screen->specs.vertex_cache_size = val;
682 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
683 DBG("could not get ETNA_GPU_SHADER_CORE_COUNT");
686 screen->specs.shader_core_count = val;
688 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
689 DBG("could not get ETNA_GPU_STREAM_COUNT");
692 screen->specs.stream_count = val;
694 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
695 DBG("could not get ETNA_GPU_REGISTER_MAX");
698 screen->specs.max_registers = val;
700 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
701 DBG("could not get ETNA_GPU_PIXEL_PIPES");
704 screen->specs.pixel_pipes = val;
706 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
707 DBG("could not get %s", "ETNA_GPU_NUM_CONSTANTS");
711 fprintf(stderr, "Warning: zero num constants (update kernel?)\n");
714 screen->specs.num_constants = val;
716 /* Figure out gross GPU architecture. See rnndb/common.xml for a specific
717 * description of the differences. */
718 if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5))
719 screen->specs.halti = 5; /* New GC7000/GC8x00 */
720 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4))
721 screen->specs.halti = 4; /* Old GC7000/GC7400 */
722 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3))
723 screen->specs.halti = 3; /* None? */
724 else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2))
725 screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */
726 else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1))
727 screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */
728 else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0))
729 screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */
731 screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */
732 if (screen->specs.halti >= 0)
733 DBG("etnaviv: GPU arch: HALTI%d", screen->specs.halti);
735 DBG("etnaviv: GPU arch: pre-HALTI");
737 screen->specs.can_supertile =
738 VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
739 screen->specs.bits_per_tile =
740 VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 2 : 4;
741 screen->specs.ts_clear_value =
742 VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ? 0x55555555
745 /* vertex and fragment samplers live in one address space */
746 screen->specs.vertex_sampler_offset = 8;
747 screen->specs.fragment_sampler_count = 8;
748 screen->specs.vertex_sampler_count = 4;
749 screen->specs.vs_need_z_div =
750 screen->model < 0x1000 && screen->model != 0x880;
751 screen->specs.has_sin_cos_sqrt =
752 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
753 screen->specs.has_sign_floor_ceil =
754 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
755 screen->specs.has_shader_range_registers =
756 screen->model >= 0x1000 || screen->model == 0x880;
757 screen->specs.npot_tex_any_wrap =
758 VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
759 screen->specs.has_new_transcendentals =
760 VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
761 screen->specs.has_halti2_instructions =
762 VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
764 if (screen->specs.halti >= 5) {
765 /* GC7000 - this core must load shaders from memory. */
766 screen->specs.vs_offset = 0;
767 screen->specs.ps_offset = 0;
768 screen->specs.max_instructions = 0; /* Do not program shaders manually */
769 screen->specs.has_icache = true;
770 } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
771 /* GC3000 - this core is capable of loading shaders from
772 * memory. It can also run shaders from registers, as a fallback, but
773 * "max_instructions" does not have the correct value. It has place for
774 * 2*256 instructions just like GC2000, but the offsets are slightly
777 screen->specs.vs_offset = 0xC000;
778 /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses
779 * this mirror for writing PS instructions, probably safest to do the
782 screen->specs.ps_offset = 0x8000 + 0x1000;
783 screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */
784 screen->specs.has_icache = true;
786 if (instruction_count > 256) { /* unified instruction memory? */
787 screen->specs.vs_offset = 0xC000;
788 screen->specs.ps_offset = 0xD000; /* like vivante driver */
789 screen->specs.max_instructions = 256;
791 screen->specs.vs_offset = 0x4000;
792 screen->specs.ps_offset = 0x6000;
793 screen->specs.max_instructions = instruction_count / 2;
795 screen->specs.has_icache = false;
798 if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
799 screen->specs.max_varyings = 12;
800 screen->specs.vertex_max_elements = 16;
802 screen->specs.max_varyings = 8;
803 /* Etna_viv documentation seems confused over the correct value
804 * here so choose the lower to be safe: HALTI0 says 16 i.s.o.
805 * 10, but VERTEX_ELEMENT_CONFIG register says 16 i.s.o. 12. */
806 screen->specs.vertex_max_elements = 10;
809 /* Etna_viv documentation does not indicate where varyings above 8 are
810 * stored. Moreover, if we are passed more than 8 varyings, we will
811 * walk off the end of some arrays. Limit the maximum number of varyings. */
812 if (screen->specs.max_varyings > ETNA_NUM_VARYINGS)
813 screen->specs.max_varyings = ETNA_NUM_VARYINGS;
815 /* from QueryShaderCaps in kernel driver */
816 if (screen->model < chipModel_GC4000) {
817 screen->specs.max_vs_uniforms = 168;
818 screen->specs.max_ps_uniforms = 64;
820 screen->specs.max_vs_uniforms = 256;
821 screen->specs.max_ps_uniforms = 256;
824 if (screen->specs.halti >= 5) {
825 screen->specs.has_unified_uniforms = true;
826 screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
827 screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4);
828 } else if (screen->specs.halti >= 1) {
829 /* unified uniform memory on GC3000 - HALTI1 feature bit is just a guess
831 screen->specs.has_unified_uniforms = true;
832 screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0);
833 /* hardcode PS uniforms to start after end of VS uniforms -
834 * for more flexibility this offset could be variable based on the
837 screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4);
839 screen->specs.has_unified_uniforms = false;
840 screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0);
841 screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0);
844 screen->specs.max_texture_size =
845 VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
846 screen->specs.max_rendertarget_size =
847 VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
849 screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
850 if (screen->specs.single_buffer)
851 DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes);
853 screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC);
855 screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE);
864 etna_screen_bo_from_handle(struct pipe_screen *pscreen,
865 struct winsys_handle *whandle, unsigned *out_stride)
867 struct etna_screen *screen = etna_screen(pscreen);
870 if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
871 bo = etna_bo_from_name(screen->dev, whandle->handle);
872 } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
873 bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
875 DBG("Attempt to import unsupported handle type %d", whandle->type);
880 DBG("ref name 0x%08x failed", whandle->handle);
884 *out_stride = whandle->stride;
890 etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu,
891 struct renderonly *ro)
893 struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
894 struct pipe_screen *pscreen;
895 drmVersionPtr version;
901 pscreen = &screen->base;
904 screen->ro = renderonly_dup(ro);
908 DBG("could not create renderonly object");
912 version = drmGetVersion(screen->ro->gpu_fd);
913 screen->drm_version = ETNA_DRM_VERSION(version->version_major,
914 version->version_minor);
915 drmFreeVersion(version);
917 etna_mesa_debug = debug_get_option_etna_mesa_debug();
919 /* Disable autodisable for correct rendering with TS */
920 etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE;
922 screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
924 DBG("could not create 3d pipe");
928 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
929 DBG("could not get ETNA_GPU_MODEL");
934 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
935 DBG("could not get ETNA_GPU_REVISION");
938 screen->revision = val;
940 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
941 DBG("could not get ETNA_GPU_FEATURES_0");
944 screen->features[0] = val;
946 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
947 DBG("could not get ETNA_GPU_FEATURES_1");
950 screen->features[1] = val;
952 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
953 DBG("could not get ETNA_GPU_FEATURES_2");
956 screen->features[2] = val;
958 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
959 DBG("could not get ETNA_GPU_FEATURES_3");
962 screen->features[3] = val;
964 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
965 DBG("could not get ETNA_GPU_FEATURES_4");
968 screen->features[4] = val;
970 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) {
971 DBG("could not get ETNA_GPU_FEATURES_5");
974 screen->features[5] = val;
976 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) {
977 DBG("could not get ETNA_GPU_FEATURES_6");
980 screen->features[6] = val;
982 if (!etna_get_specs(screen))
985 /* apply debug options that disable individual features */
986 if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z))
987 screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z;
988 if (DBG_ENABLED(ETNA_DBG_NO_TS))
989 screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
990 if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE))
991 screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE;
992 if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE))
993 screen->specs.can_supertile = 0;
994 if (DBG_ENABLED(ETNA_DBG_NO_SINGLEBUF))
995 screen->specs.single_buffer = 0;
997 pscreen->destroy = etna_screen_destroy;
998 pscreen->get_param = etna_screen_get_param;
999 pscreen->get_paramf = etna_screen_get_paramf;
1000 pscreen->get_shader_param = etna_screen_get_shader_param;
1002 pscreen->get_name = etna_screen_get_name;
1003 pscreen->get_vendor = etna_screen_get_vendor;
1004 pscreen->get_device_vendor = etna_screen_get_device_vendor;
1006 pscreen->get_timestamp = etna_screen_get_timestamp;
1007 pscreen->context_create = etna_context_create;
1008 pscreen->is_format_supported = etna_screen_is_format_supported;
1009 pscreen->query_dmabuf_modifiers = etna_screen_query_dmabuf_modifiers;
1011 etna_fence_screen_init(pscreen);
1012 etna_query_screen_init(pscreen);
1013 etna_resource_screen_init(pscreen);
1015 util_dynarray_init(&screen->supported_pm_queries, NULL);
1016 slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
1018 if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON)
1019 etna_pm_query_setup(screen);
1024 etna_screen_destroy(pscreen);