src/gallium/drivers/freedreno/freedreno_screen.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29
  30 #include "pipe/p_defines.h"
  31 #include "pipe/p_screen.h"
  32 #include "pipe/p_state.h"
  33
  34 #include "util/u_memory.h"
  35 #include "util/u_inlines.h"
  36 #include "util/u_format.h"
  37 #include "util/u_format_s3tc.h"
  38 #include "util/u_string.h"
  39 #include "util/u_debug.h"
  40
  41 #include "util/os_time.h"
  42
  43 #include <errno.h>
  44 #include <stdio.h>
  45 #include <stdlib.h>
  46 #include <sys/sysinfo.h>
  47
  48 #include "freedreno_screen.h"
  49 #include "freedreno_resource.h"
  50 #include "freedreno_fence.h"
  51 #include "freedreno_query.h"
  52 #include "freedreno_util.h"
  53
  54 #include "a2xx/fd2_screen.h"
  55 #include "a3xx/fd3_screen.h"
  56 #include "a4xx/fd4_screen.h"
  57 #include "a5xx/fd5_screen.h"
  58 #include "a6xx/fd6_screen.h"
  59
  60
  61 #include "ir3/ir3_nir.h"
  62
  63 /* XXX this should go away */
  64 #include "state_tracker/drm_driver.h"
  65
  66 static const struct debug_named_value debug_options[] = {
  67                 {"msgs",      FD_DBG_MSGS,   "Print debug messages"},
  68                 {"disasm",    FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"},
  69                 {"dclear",    FD_DBG_DCLEAR, "Mark all state dirty after clear"},
  70                 {"ddraw",     FD_DBG_DDRAW,  "Mark all state dirty after draw"},
  71                 {"noscis",    FD_DBG_NOSCIS, "Disable scissor optimization"},
  72                 {"direct",    FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"},
  73                 {"nobypass",  FD_DBG_NOBYPASS, "Disable GMEM bypass"},
  74                 {"fraghalf",  FD_DBG_FRAGHALF, "Use half-precision in fragment shader"},
  75                 {"nobin",     FD_DBG_NOBIN,  "Disable hw binning"},
  76                 {"optmsgs",   FD_DBG_OPTMSGS,"Enable optimizer debug messages"},
  77                 {"glsl120",   FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"},
  78                 {"shaderdb",  FD_DBG_SHADERDB, "Enable shaderdb output"},
  79                 {"flush",     FD_DBG_FLUSH,  "Force flush after every draw"},
  80                 {"deqp",      FD_DBG_DEQP,   "Enable dEQP hacks"},
  81                 {"inorder",   FD_DBG_INORDER,"Disable reordering for draws/blits"},
  82                 {"bstat",     FD_DBG_BSTAT,  "Print batch stats at context destroy"},
  83                 {"nogrow",    FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"},
  84                 {"lrz",       FD_DBG_LRZ,    "Enable experimental LRZ support (a5xx+)"},
  85                 {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"},
  86                 {"noblit",    FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"},
  87                 {"hiprio",    FD_DBG_HIPRIO, "Force high-priority context"},
  88                 {"ttile",     FD_DBG_TTILE,  "Enable texture tiling (a5xx)"},
  89                 {"perfcntrs", FD_DBG_PERFC,  "Expose performance counters"},
  90                 DEBUG_NAMED_VALUE_END
  91 };
  92
  93 DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0)
  94
  95 int fd_mesa_debug = 0;
  96 bool fd_binning_enabled = true;
  97 static bool glsl120 = false;
  98
  99 static const struct debug_named_value shader_debug_options[] = {
 100                 {"vs", FD_DBG_SHADER_VS, "Print shader disasm for vertex shaders"},
 101                 {"fs", FD_DBG_SHADER_FS, "Print shader disasm for fragment shaders"},
 102                 {"cs", FD_DBG_SHADER_CS, "Print shader disasm for compute shaders"},
 103                 DEBUG_NAMED_VALUE_END
 104 };
 105
 106 DEBUG_GET_ONCE_FLAGS_OPTION(fd_shader_debug, "FD_SHADER_DEBUG", shader_debug_options, 0)
 107
 108 enum fd_shader_debug fd_shader_debug = 0;
 109
 110 static const char *
 111 fd_screen_get_name(struct pipe_screen *pscreen)
 112 {
 113         static char buffer[128];
 114         util_snprintf(buffer, sizeof(buffer), "FD%03d",
 115                         fd_screen(pscreen)->device_id);
 116         return buffer;
 117 }
 118
 119 static const char *
 120 fd_screen_get_vendor(struct pipe_screen *pscreen)
 121 {
 122         return "freedreno";
 123 }
 124
 125 static const char *
 126 fd_screen_get_device_vendor(struct pipe_screen *pscreen)
 127 {
 128         return "Qualcomm";
 129 }
 130
 131
 132 static uint64_t
 133 fd_screen_get_timestamp(struct pipe_screen *pscreen)
 134 {
 135         struct fd_screen *screen = fd_screen(pscreen);
 136
 137         if (screen->has_timestamp) {
 138                 uint64_t n;
 139                 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
 140                 debug_assert(screen->max_freq > 0);
 141                 return n * 1000000000 / screen->max_freq;
 142         } else {
 143                 int64_t cpu_time = os_time_get() * 1000;
 144                 return cpu_time + screen->cpu_gpu_time_delta;
 145         }
 146
 147 }
 148
 149 static void
 150 fd_screen_destroy(struct pipe_screen *pscreen)
 151 {
 152         struct fd_screen *screen = fd_screen(pscreen);
 153
 154         if (screen->pipe)
 155                 fd_pipe_del(screen->pipe);
 156
 157         if (screen->dev)
 158                 fd_device_del(screen->dev);
 159
 160         fd_bc_fini(&screen->batch_cache);
 161
 162         slab_destroy_parent(&screen->transfer_pool);
 163
 164         mtx_destroy(&screen->lock);
 165
 166         ralloc_free(screen->compiler);
 167
 168         free(screen->perfcntr_queries);
 169         free(screen);
 170 }
 171
 172 /*
 173 TODO either move caps to a2xx/a3xx specific code, or maybe have some
 174 tables for things that differ if the delta is not too much..
 175  */
 176 static int
 177 fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 178 {
 179         struct fd_screen *screen = fd_screen(pscreen);
 180
 181         /* this is probably not totally correct.. but it's a start: */
 182         switch (param) {
 183         /* Supported features (boolean caps). */
 184         case PIPE_CAP_NPOT_TEXTURES:
 185         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 186         case PIPE_CAP_ANISOTROPIC_FILTER:
 187         case PIPE_CAP_POINT_SPRITE:
 188         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 189         case PIPE_CAP_TEXTURE_SWIZZLE:
 190         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 191         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 192         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 193         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 194         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 195         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 196         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 197         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 198         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 199         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 200         case PIPE_CAP_STRING_MARKER:
 201         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 202         case PIPE_CAP_TEXTURE_BARRIER:
 203         case PIPE_CAP_INVALIDATE_BUFFER:
 204                 return 1;
 205
 206         case PIPE_CAP_VERTEXID_NOBASE:
 207                 return is_a3xx(screen) || is_a4xx(screen);
 208
 209         case PIPE_CAP_COMPUTE:
 210                 return has_compute(screen);
 211
 212         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 213         case PIPE_CAP_TGSI_TEXCOORD:
 214         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 215         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 216         case PIPE_CAP_QUERY_MEMORY_INFO:
 217         case PIPE_CAP_PCI_GROUP:
 218         case PIPE_CAP_PCI_BUS:
 219         case PIPE_CAP_PCI_DEVICE:
 220         case PIPE_CAP_PCI_FUNCTION:
 221                 return 0;
 222
 223         case PIPE_CAP_SM3:
 224         case PIPE_CAP_PRIMITIVE_RESTART:
 225         case PIPE_CAP_TGSI_INSTANCEID:
 226         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 227         case PIPE_CAP_INDEP_BLEND_ENABLE:
 228         case PIPE_CAP_INDEP_BLEND_FUNC:
 229         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 230         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 231         case PIPE_CAP_CONDITIONAL_RENDER:
 232         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 233         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 234         case PIPE_CAP_CLIP_HALFZ:
 235                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 236
 237         case PIPE_CAP_FAKE_SW_MSAA:
 238                 return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE);
 239
 240         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 241                 return is_a5xx(screen) || is_a6xx(screen);
 242
 243         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 244                 return is_a3xx(screen) || is_a4xx(screen);
 245
 246         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 247                 return is_a5xx(screen) || is_a6xx(screen);
 248
 249         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 250                 return 0;
 251         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 252                 if (is_a3xx(screen)) return 16;
 253                 if (is_a4xx(screen)) return 32;
 254                 if (is_a5xx(screen)) return 32;
 255                 if (is_a6xx(screen)) return 32;
 256                 return 0;
 257         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 258                 /* We could possibly emulate more by pretending 2d/rect textures and
 259                  * splitting high bits of index into 2nd dimension..
 260                  */
 261                 if (is_a3xx(screen)) return 8192;
 262                 if (is_a4xx(screen)) return 16384;
 263                 if (is_a5xx(screen)) return 16384;
 264                 if (is_a6xx(screen)) return 16384;
 265                 return 0;
 266
 267         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 268         case PIPE_CAP_CUBE_MAP_ARRAY:
 269         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 270         case PIPE_CAP_TEXTURE_QUERY_LOD:
 271                 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 272
 273         case PIPE_CAP_START_INSTANCE:
 274                 /* Note that a5xx can do this, it just can't (at least with
 275                  * current firmware) do draw_indirect with base_instance.
 276                  * Since draw_indirect is needed sooner (gles31 and gl40 vs
 277                  * gl42), hide base_instance on a5xx.  :-/
 278                  */
 279                 return is_a4xx(screen);
 280
 281         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 282                 return 64;
 283
 284         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 285         case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
 286                 if (glsl120)
 287                         return 120;
 288                 return is_ir3(screen) ? 140 : 120;
 289
 290         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 291                 if (is_a5xx(screen) || is_a6xx(screen))
 292                         return 4;
 293                 return 0;
 294
 295         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 296                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 297                         return 4;
 298                 return 0;
 299
 300         /* Unsupported features. */
 301         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 302         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 303         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 304         case PIPE_CAP_USER_VERTEX_BUFFERS:
 305         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 306         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 307         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 308         case PIPE_CAP_TEXTURE_GATHER_SM5:
 309         case PIPE_CAP_SAMPLE_SHADING:
 310         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 311         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 312         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 313         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 314         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 315         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 316         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 317         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 318         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 319         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 320         case PIPE_CAP_TGSI_TXQS:
 321         /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */
 322         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 323         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 324         case PIPE_CAP_CLEAR_TEXTURE:
 325         case PIPE_CAP_DRAW_PARAMETERS:
 326         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 327         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 328         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 329         case PIPE_CAP_GENERATE_MIPMAP:
 330         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 331         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 332         case PIPE_CAP_CULL_DISTANCE:
 333         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 334         case PIPE_CAP_TGSI_VOTE:
 335         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 336         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 337         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 338         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 339         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 340         case PIPE_CAP_TGSI_FS_FBFETCH:
 341         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 342         case PIPE_CAP_DOUBLES:
 343         case PIPE_CAP_INT64:
 344         case PIPE_CAP_INT64_DIVMOD:
 345         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 346         case PIPE_CAP_TGSI_CLOCK:
 347         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 348         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 349         case PIPE_CAP_TGSI_BALLOT:
 350         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 351         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 352         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 353         case PIPE_CAP_POST_DEPTH_COVERAGE:
 354         case PIPE_CAP_BINDLESS_TEXTURE:
 355         case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
 356         case PIPE_CAP_QUERY_SO_OVERFLOW:
 357         case PIPE_CAP_MEMOBJ:
 358         case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
 359         case PIPE_CAP_TILE_RASTER_ORDER:
 360         case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
 361         case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
 362         case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
 363         case PIPE_CAP_FENCE_SIGNAL:
 364         case PIPE_CAP_CONSTBUF0_FLAGS:
 365         case PIPE_CAP_PACKED_UNIFORMS:
 366         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
 367         case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
 368         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
 369         case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
 370         case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
 371         case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
 372         case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
 373                 return 0;
 374
 375         case PIPE_CAP_CONTEXT_PRIORITY_MASK:
 376                 return screen->priority_mask;
 377
 378         case PIPE_CAP_DRAW_INDIRECT:
 379                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 380                         return 1;
 381                 return 0;
 382
 383         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 384                 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
 385                         return 1;
 386                 return 0;
 387
 388         case PIPE_CAP_LOAD_CONSTBUF:
 389                 /* name is confusing, but this turns on std430 packing */
 390                 if (is_ir3(screen))
 391                         return 1;
 392                 return 0;
 393
 394         case PIPE_CAP_MAX_VIEWPORTS:
 395                 return 1;
 396
 397         case PIPE_CAP_SHAREABLE_SHADERS:
 398         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 399         /* manage the variants for these ourself, to avoid breaking precompile: */
 400         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 401         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 402                 if (is_ir3(screen))
 403                         return 1;
 404                 return 0;
 405
 406         /* Stream output. */
 407         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 408                 if (is_ir3(screen))
 409                         return PIPE_MAX_SO_BUFFERS;
 410                 return 0;
 411         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 412         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 413                 if (is_ir3(screen))
 414                         return 1;
 415                 return 0;
 416         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 417         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 418                 if (is_ir3(screen))
 419                         return 16 * 4;   /* should only be shader out limit? */
 420                 return 0;
 421
 422         /* Geometry shader output, unsupported. */
 423         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 424         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 425         case PIPE_CAP_MAX_VERTEX_STREAMS:
 426                 return 0;
 427
 428         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 429                 return 2048;
 430
 431         /* Texturing. */
 432         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 433         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 434                 return MAX_MIP_LEVELS;
 435         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 436                 return 11;
 437
 438         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 439                 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 256 : 0;
 440
 441         /* Render targets. */
 442         case PIPE_CAP_MAX_RENDER_TARGETS:
 443                 return screen->max_rts;
 444         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 445                 return is_a3xx(screen) ? 1 : 0;
 446
 447         /* Queries. */
 448         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 449                 return 0;
 450         case PIPE_CAP_OCCLUSION_QUERY:
 451                 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
 452         case PIPE_CAP_QUERY_TIMESTAMP:
 453         case PIPE_CAP_QUERY_TIME_ELAPSED:
 454                 /* only a4xx, requires new enough kernel so we know max_freq: */
 455                 return (screen->max_freq > 0) && (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen));
 456
 457         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 458         case PIPE_CAP_MIN_TEXEL_OFFSET:
 459                 return -8;
 460
 461         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 462         case PIPE_CAP_MAX_TEXEL_OFFSET:
 463                 return 7;
 464
 465         case PIPE_CAP_ENDIANNESS:
 466                 return PIPE_ENDIAN_LITTLE;
 467
 468         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 469                 return 64;
 470
 471         case PIPE_CAP_VENDOR_ID:
 472                 return 0x5143;
 473         case PIPE_CAP_DEVICE_ID:
 474                 return 0xFFFFFFFF;
 475         case PIPE_CAP_ACCELERATED:
 476                 return 1;
 477         case PIPE_CAP_VIDEO_MEMORY:
 478                 DBG("FINISHME: The value returned is incorrect\n");
 479                 return 10;
 480         case PIPE_CAP_UMA:
 481                 return 1;
 482         case PIPE_CAP_NATIVE_FENCE_FD:
 483                 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
 484         }
 485         debug_printf("unknown param %d\n", param);
 486         return 0;
 487 }
 488
 489 static float
 490 fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 491 {
 492         switch (param) {
 493         case PIPE_CAPF_MAX_LINE_WIDTH:
 494         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 495                 /* NOTE: actual value is 127.0f, but this is working around a deqp
 496                  * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide
 497                  * uses too small of a render target size, and gets confused when
 498                  * the lines start going offscreen.
 499                  *
 500                  * See: https://code.google.com/p/android/issues/detail?id=206513
 501                  */
 502                 if (fd_mesa_debug & FD_DBG_DEQP)
 503                         return 48.0f;
 504                 return 127.0f;
 505         case PIPE_CAPF_MAX_POINT_WIDTH:
 506         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 507                 return 4092.0f;
 508         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 509                 return 16.0f;
 510         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 511                 return 15.0f;
 512         case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
 513         case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
 514         case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
 515                 return 0.0f;
 516         }
 517         debug_printf("unknown paramf %d\n", param);
 518         return 0;
 519 }
 520
 521 static int
 522 fd_screen_get_shader_param(struct pipe_screen *pscreen,
 523                 enum pipe_shader_type shader,
 524                 enum pipe_shader_cap param)
 525 {
 526         struct fd_screen *screen = fd_screen(pscreen);
 527
 528         switch(shader)
 529         {
 530         case PIPE_SHADER_FRAGMENT:
 531         case PIPE_SHADER_VERTEX:
 532                 break;
 533         case PIPE_SHADER_COMPUTE:
 534                 if (has_compute(screen))
 535                         break;
 536                 return 0;
 537         case PIPE_SHADER_GEOMETRY:
 538                 /* maye we could emulate.. */
 539                 return 0;
 540         default:
 541                 DBG("unknown shader type %d", shader);
 542                 return 0;
 543         }
 544
 545         /* this is probably not totally correct.. but it's a start: */
 546         switch (param) {
 547         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 548         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 549         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 550         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 551                 return 16384;
 552         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 553                 return 8; /* XXX */
 554         case PIPE_SHADER_CAP_MAX_INPUTS:
 555         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 556                 return 16;
 557         case PIPE_SHADER_CAP_MAX_TEMPS:
 558                 return 64; /* Max native temporaries. */
 559         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 560                 /* NOTE: seems to be limit for a3xx is actually 512 but
 561                  * split between VS and FS.  Use lower limit of 256 to
 562                  * avoid getting into impossible situations:
 563                  */
 564                 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) ? 4096 : 64) * sizeof(float[4]);
 565         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 566                 return is_ir3(screen) ? 16 : 1;
 567         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 568                 return 1;
 569         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 570         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 571                 /* Technically this should be the same as for TEMP/CONST, since
 572                  * everything is just normal registers.  This is just temporary
 573                  * hack until load_input/store_output handle arrays in a similar
 574                  * way as load_var/store_var..
 575                  */
 576                 return 0;
 577         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 578         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 579                 /* a2xx compiler doesn't handle indirect: */
 580                 return is_ir3(screen) ? 1 : 0;
 581         case PIPE_SHADER_CAP_SUBROUTINES:
 582         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 583         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 584         case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
 585         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 586         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 587         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
 588         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 589         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 590         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
 591                 return 0;
 592         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 593                 return 1;
 594         case PIPE_SHADER_CAP_INTEGERS:
 595                 if (glsl120)
 596                         return 0;
 597                 return is_ir3(screen) ? 1 : 0;
 598         case PIPE_SHADER_CAP_INT64_ATOMICS:
 599                 return 0;
 600         case PIPE_SHADER_CAP_FP16:
 601                 return 0;
 602         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 603         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 604                 return 16;
 605         case PIPE_SHADER_CAP_PREFERRED_IR:
 606                 if (is_ir3(screen))
 607                         return PIPE_SHADER_IR_NIR;
 608                 return PIPE_SHADER_IR_TGSI;
 609         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 610                 if (is_ir3(screen)) {
 611                         return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
 612                 } else {
 613                         return (1 << PIPE_SHADER_IR_TGSI);
 614                 }
 615                 return 0;
 616         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 617                 return 32;
 618         case PIPE_SHADER_CAP_SCALAR_ISA:
 619                 return is_ir3(screen) ? 1 : 0;
 620         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 621         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 622                 if (is_a5xx(screen) || is_a6xx(screen)) {
 623                         /* a5xx (and a4xx for that matter) has one state-block
 624                          * for compute-shader SSBO's and another that is shared
 625                          * by VS/HS/DS/GS/FS..  so to simplify things for now
 626                          * just advertise SSBOs for FS and CS.  We could possibly
 627                          * do what blob does, and partition the space for
 628                          * VS/HS/DS/GS/FS.  The blob advertises:
 629                          *
 630                          *   GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4
 631                          *   GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4
 632                          *   GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4
 633                          *   GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4
 634                          *   GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4
 635                          *   GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24
 636                          *   GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24
 637                          *
 638                          * I think that way we could avoid having to patch shaders
 639                          * for actual SSBO indexes by using a static partitioning.
 640                          *
 641                          * Note same state block is used for images and buffers,
 642                          * but images also need texture state for read access
 643                          * (isam/isam.3d)
 644                          */
 645                         switch(shader)
 646                         {
 647                         case PIPE_SHADER_FRAGMENT:
 648                         case PIPE_SHADER_COMPUTE:
 649                                 return 24;
 650                         default:
 651                                 return 0;
 652                         }
 653                 }
 654                 return 0;
 655         }
 656         debug_printf("unknown shader param %d\n", param);
 657         return 0;
 658 }
 659
 660 /* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this
 661  * into per-generation backend?
 662  */
 663 static int
 664 fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
 665                 enum pipe_compute_cap param, void *ret)
 666 {
 667         struct fd_screen *screen = fd_screen(pscreen);
 668         const char * const ir = "ir3";
 669
 670         if (!has_compute(screen))
 671                 return 0;
 672
 673 #define RET(x) do {                  \
 674    if (ret)                          \
 675       memcpy(ret, x, sizeof(x));     \
 676    return sizeof(x);                 \
 677 } while (0)
 678
 679         switch (param) {
 680         case PIPE_COMPUTE_CAP_ADDRESS_BITS:
 681 // don't expose 64b pointer support yet, until ir3 supports 64b
 682 // math, otherwise spir64 target is used and we get 64b pointer
 683 // calculations that we can't do yet
 684 //              if (is_a5xx(screen))
 685 //                      RET((uint32_t []){ 64 });
 686                 RET((uint32_t []){ 32 });
 687
 688         case PIPE_COMPUTE_CAP_IR_TARGET:
 689                 if (ret)
 690                         sprintf(ret, ir);
 691                 return strlen(ir) * sizeof(char);
 692
 693         case PIPE_COMPUTE_CAP_GRID_DIMENSION:
 694                 RET((uint64_t []) { 3 });
 695
 696         case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
 697                 RET(((uint64_t []) { 65535, 65535, 65535 }));
 698
 699         case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
 700                 RET(((uint64_t []) { 1024, 1024, 64 }));
 701
 702         case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
 703                 RET((uint64_t []) { 1024 });
 704
 705         case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
 706                 RET((uint64_t []) { screen->ram_size });
 707
 708         case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
 709                 RET((uint64_t []) { 32768 });
 710
 711         case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
 712         case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
 713                 RET((uint64_t []) { 4096 });
 714
 715         case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
 716                 RET((uint64_t []) { screen->ram_size });
 717
 718         case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
 719                 RET((uint32_t []) { screen->max_freq / 1000000 });
 720
 721         case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
 722                 RET((uint32_t []) { 9999 });  // TODO
 723
 724         case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
 725                 RET((uint32_t []) { 1 });
 726
 727         case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
 728                 RET((uint32_t []) { 32 });  // TODO
 729
 730         case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
 731                 RET((uint64_t []) { 1024 }); // TODO
 732         }
 733
 734         return 0;
 735 }
 736
 737 static const void *
 738 fd_get_compiler_options(struct pipe_screen *pscreen,
 739                 enum pipe_shader_ir ir, unsigned shader)
 740 {
 741         struct fd_screen *screen = fd_screen(pscreen);
 742
 743         if (is_ir3(screen))
 744                 return ir3_get_compiler_options(screen->compiler);
 745
 746         return NULL;
 747 }
 748
 749 boolean
 750 fd_screen_bo_get_handle(struct pipe_screen *pscreen,
 751                 struct fd_bo *bo,
 752                 unsigned stride,
 753                 struct winsys_handle *whandle)
 754 {
 755         whandle->stride = stride;
 756
 757         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 758                 return fd_bo_get_name(bo, &whandle->handle) == 0;
 759         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 760                 whandle->handle = fd_bo_handle(bo);
 761                 return TRUE;
 762         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 763                 whandle->handle = fd_bo_dmabuf(bo);
 764                 return TRUE;
 765         } else {
 766                 return FALSE;
 767         }
 768 }
 769
 770 struct fd_bo *
 771 fd_screen_bo_from_handle(struct pipe_screen *pscreen,
 772                 struct winsys_handle *whandle)
 773 {
 774         struct fd_screen *screen = fd_screen(pscreen);
 775         struct fd_bo *bo;
 776
 777         if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) {
 778                 bo = fd_bo_from_name(screen->dev, whandle->handle);
 779         } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) {
 780                 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
 781         } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) {
 782                 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
 783         } else {
 784                 DBG("Attempt to import unsupported handle type %d", whandle->type);
 785                 return NULL;
 786         }
 787
 788         if (!bo) {
 789                 DBG("ref name 0x%08x failed", whandle->handle);
 790                 return NULL;
 791         }
 792
 793         return bo;
 794 }
 795
 796 struct pipe_screen *
 797 fd_screen_create(struct fd_device *dev)
 798 {
 799         struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
 800         struct pipe_screen *pscreen;
 801         uint64_t val;
 802
 803         fd_mesa_debug = debug_get_option_fd_mesa_debug();
 804         fd_shader_debug = debug_get_option_fd_shader_debug();
 805
 806         if (fd_mesa_debug & FD_DBG_NOBIN)
 807                 fd_binning_enabled = false;
 808
 809         glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120);
 810
 811         if (!screen)
 812                 return NULL;
 813
 814         pscreen = &screen->base;
 815
 816         screen->dev = dev;
 817         screen->refcnt = 1;
 818
 819         // maybe this should be in context?
 820         screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
 821         if (!screen->pipe) {
 822                 DBG("could not create 3d pipe");
 823                 goto fail;
 824         }
 825
 826         if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
 827                 DBG("could not get GMEM size");
 828                 goto fail;
 829         }
 830         screen->gmemsize_bytes = val;
 831
 832         if (fd_pipe_get_param(screen->pipe, FD_DEVICE_ID, &val)) {
 833                 DBG("could not get device-id");
 834                 goto fail;
 835         }
 836         screen->device_id = val;
 837
 838         if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
 839                 DBG("could not get gpu freq");
 840                 /* this limits what performance related queries are
 841                  * supported but is not fatal
 842                  */
 843                 screen->max_freq = 0;
 844         } else {
 845                 screen->max_freq = val;
 846                 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
 847                         screen->has_timestamp = true;
 848         }
 849
 850         if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
 851                 DBG("could not get gpu-id");
 852                 goto fail;
 853         }
 854         screen->gpu_id = val;
 855
 856         if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
 857                 DBG("could not get chip-id");
 858                 /* older kernels may not have this property: */
 859                 unsigned core  = screen->gpu_id / 100;
 860                 unsigned major = (screen->gpu_id % 100) / 10;
 861                 unsigned minor = screen->gpu_id % 10;
 862                 unsigned patch = 0;  /* assume the worst */
 863                 val = (patch & 0xff) | ((minor & 0xff) << 8) |
 864                         ((major & 0xff) << 16) | ((core & 0xff) << 24);
 865         }
 866         screen->chip_id = val;
 867
 868         if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
 869                 DBG("could not get # of rings");
 870                 screen->priority_mask = 0;
 871         } else {
 872                 /* # of rings equates to number of unique priority values: */
 873                 screen->priority_mask = (1 << val) - 1;
 874         }
 875
 876         struct sysinfo si;
 877         sysinfo(&si);
 878         screen->ram_size = si.totalram;
 879
 880         DBG("Pipe Info:");
 881         DBG(" GPU-id:          %d", screen->gpu_id);
 882         DBG(" Chip-id:         0x%08x", screen->chip_id);
 883         DBG(" GMEM size:       0x%08x", screen->gmemsize_bytes);
 884
 885         /* explicitly checking for GPU revisions that are known to work.  This
 886          * may be overly conservative for a3xx, where spoofing the gpu_id with
 887          * the blob driver seems to generate identical cmdstream dumps.  But
 888          * on a2xx, there seem to be small differences between the GPU revs
 889          * so it is probably better to actually test first on real hardware
 890          * before enabling:
 891          *
 892          * If you have a different adreno version, feel free to add it to one
 893          * of the cases below and see what happens.  And if it works, please
 894          * send a patch ;-)
 895          */
 896         switch (screen->gpu_id) {
 897         case 205:
 898         case 220:
 899                 fd2_screen_init(pscreen);
 900                 break;
 901         case 305:
 902         case 307:
 903         case 320:
 904         case 330:
 905                 fd3_screen_init(pscreen);
 906                 break;
 907         case 420:
 908         case 430:
 909                 fd4_screen_init(pscreen);
 910                 break;
 911         case 530:
 912                 fd5_screen_init(pscreen);
 913                 break;
 914         case 630:
 915                 fd6_screen_init(pscreen);
 916                 break;
 917         default:
 918                 debug_printf("unsupported GPU: a%03d\n", screen->gpu_id);
 919                 goto fail;
 920         }
 921
 922         if (screen->gpu_id >= 500) {
 923                 screen->gmem_alignw = 64;
 924                 screen->gmem_alignh = 32;
 925                 screen->num_vsc_pipes = 16;
 926         } else {
 927                 screen->gmem_alignw = 32;
 928                 screen->gmem_alignh = 32;
 929                 screen->num_vsc_pipes = 8;
 930         }
 931
 932         /* NOTE: don't enable reordering on a2xx, since completely untested.
 933          * Also, don't enable if we have too old of a kernel to support
 934          * growable cmdstream buffers, since memory requirement for cmdstream
 935          * buffers would be too much otherwise.
 936          */
 937         if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS))
 938                 screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER);
 939
 940         fd_bc_init(&screen->batch_cache);
 941
 942         (void) mtx_init(&screen->lock, mtx_plain);
 943
 944         pscreen->destroy = fd_screen_destroy;
 945         pscreen->get_param = fd_screen_get_param;
 946         pscreen->get_paramf = fd_screen_get_paramf;
 947         pscreen->get_shader_param = fd_screen_get_shader_param;
 948         pscreen->get_compute_param = fd_get_compute_param;
 949         pscreen->get_compiler_options = fd_get_compiler_options;
 950
 951         fd_resource_screen_init(pscreen);
 952         fd_query_screen_init(pscreen);
 953
 954         pscreen->get_name = fd_screen_get_name;
 955         pscreen->get_vendor = fd_screen_get_vendor;
 956         pscreen->get_device_vendor = fd_screen_get_device_vendor;
 957
 958         pscreen->get_timestamp = fd_screen_get_timestamp;
 959
 960         pscreen->fence_reference = fd_fence_ref;
 961         pscreen->fence_finish = fd_fence_finish;
 962         pscreen->fence_get_fd = fd_fence_get_fd;
 963
 964         slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);
 965
 966         return pscreen;
 967
 968 fail:
 969         fd_screen_destroy(pscreen);
 970         return NULL;
 971 }