2 * Mesa 3-D graphics library
4 * Copyright (C) 2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "genhw/genhw.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_prim.h"
32 #include "ilo_blitter.h"
33 #include "ilo_builder_3d.h"
34 #include "ilo_builder_mi.h"
35 #include "ilo_builder_render.h"
36 #include "ilo_query.h"
37 #include "ilo_shader.h"
38 #include "ilo_state.h"
39 #include "ilo_3d_pipeline.h"
40 #include "ilo_3d_pipeline_gen6.h"
43 * This should be called before any depth stall flush (including those
44 * produced by non-pipelined state commands) or cache flush on GEN6.
46 * \see intel_emit_post_sync_nonzero_flush()
49 gen6_wa_pipe_control_post_sync(struct ilo_3d_pipeline *p,
50 bool caller_post_sync)
52 assert(ilo_dev_gen(p->dev) == ILO_GEN(6));
55 if (p->state.has_gen6_wa_pipe_control)
58 p->state.has_gen6_wa_pipe_control = true;
61 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
63 * "Pipe-control with CS-stall bit set must be sent BEFORE the
64 * pipe-control with a post-sync op and no write-cache flushes."
66 * The workaround below necessitates this workaround.
68 gen6_PIPE_CONTROL(p->builder,
69 GEN6_PIPE_CONTROL_CS_STALL |
70 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL,
73 /* the caller will emit the post-sync op */
78 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
80 * "Before any depth stall flush (including those produced by
81 * non-pipelined state commands), software needs to first send a
82 * PIPE_CONTROL with no bits set except Post-Sync Operation != 0."
84 * "Before a PIPE_CONTROL with Write Cache Flush Enable =1, a
85 * PIPE_CONTROL with any non-zero post-sync-op is required."
87 gen6_PIPE_CONTROL(p->builder,
88 GEN6_PIPE_CONTROL_WRITE_IMM,
89 p->workaround_bo, 0, false);
93 gen6_wa_pipe_control_wm_multisample_flush(struct ilo_3d_pipeline *p)
95 assert(ilo_dev_gen(p->dev) == ILO_GEN(6));
97 gen6_wa_pipe_control_post_sync(p, false);
100 * From the Sandy Bridge PRM, volume 2 part 1, page 305:
102 * "Driver must guarentee that all the caches in the depth pipe are
103 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
104 * requires driver to send a PIPE_CONTROL with a CS stall along with a
105 * Depth Flush prior to this command."
107 gen6_PIPE_CONTROL(p->builder,
108 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
109 GEN6_PIPE_CONTROL_CS_STALL,
114 gen6_wa_pipe_control_wm_depth_flush(struct ilo_3d_pipeline *p)
116 assert(ilo_dev_gen(p->dev) == ILO_GEN(6));
118 gen6_wa_pipe_control_post_sync(p, false);
121 * According to intel_emit_depth_stall_flushes() of classic i965, we need
122 * to emit a sequence of PIPE_CONTROLs prior to emitting depth related
125 gen6_PIPE_CONTROL(p->builder,
126 GEN6_PIPE_CONTROL_DEPTH_STALL,
129 gen6_PIPE_CONTROL(p->builder,
130 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH,
133 gen6_PIPE_CONTROL(p->builder,
134 GEN6_PIPE_CONTROL_DEPTH_STALL,
139 gen6_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline *p)
141 assert(ilo_dev_gen(p->dev) == ILO_GEN(6));
143 /* the post-sync workaround should cover this already */
144 if (p->state.has_gen6_wa_pipe_control)
148 * From the Sandy Bridge PRM, volume 2 part 1, page 274:
150 * "A PIPE_CONTROL command, with only the Stall At Pixel Scoreboard
151 * field set (DW1 Bit 1), must be issued prior to any change to the
152 * value in this field (Maximum Number of Threads in 3DSTATE_WM)"
154 gen6_PIPE_CONTROL(p->builder,
155 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL,
161 gen6_wa_pipe_control_vs_const_flush(struct ilo_3d_pipeline *p)
163 assert(ilo_dev_gen(p->dev) == ILO_GEN(6));
165 gen6_wa_pipe_control_post_sync(p, false);
168 * According to upload_vs_state() of classic i965, we need to emit
169 * PIPE_CONTROL after 3DSTATE_CONSTANT_VS so that the command is kept being
170 * buffered by VS FF, to the point that the FF dies.
172 gen6_PIPE_CONTROL(p->builder,
173 GEN6_PIPE_CONTROL_DEPTH_STALL |
174 GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE |
175 GEN6_PIPE_CONTROL_STATE_CACHE_INVALIDATE,
179 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
182 gen6_pipeline_common_select(struct ilo_3d_pipeline *p,
183 const struct ilo_state_vector *vec,
184 struct gen6_pipeline_session *session)
186 /* PIPELINE_SELECT */
187 if (session->hw_ctx_changed) {
188 if (ilo_dev_gen(p->dev) == ILO_GEN(6))
189 gen6_wa_pipe_control_post_sync(p, false);
191 gen6_PIPELINE_SELECT(p->builder, 0x0);
196 gen6_pipeline_common_sip(struct ilo_3d_pipeline *p,
197 const struct ilo_state_vector *vec,
198 struct gen6_pipeline_session *session)
201 if (session->hw_ctx_changed) {
202 if (ilo_dev_gen(p->dev) == ILO_GEN(6))
203 gen6_wa_pipe_control_post_sync(p, false);
205 gen6_STATE_SIP(p->builder, 0);
210 gen6_pipeline_common_base_address(struct ilo_3d_pipeline *p,
211 const struct ilo_state_vector *vec,
212 struct gen6_pipeline_session *session)
214 /* STATE_BASE_ADDRESS */
215 if (session->state_bo_changed || session->kernel_bo_changed ||
216 session->batch_bo_changed) {
217 if (ilo_dev_gen(p->dev) == ILO_GEN(6))
218 gen6_wa_pipe_control_post_sync(p, false);
220 gen6_state_base_address(p->builder, session->hw_ctx_changed);
223 * From the Sandy Bridge PRM, volume 1 part 1, page 28:
225 * "The following commands must be reissued following any change to
226 * the base addresses:
228 * * 3DSTATE_BINDING_TABLE_POINTERS
229 * * 3DSTATE_SAMPLER_STATE_POINTERS
230 * * 3DSTATE_VIEWPORT_STATE_POINTERS
231 * * 3DSTATE_CC_POINTERS
232 * * MEDIA_STATE_POINTERS"
234 * 3DSTATE_SCISSOR_STATE_POINTERS is not on the list, but it is
235 * reasonable to also reissue the command. Same to PCB.
237 session->viewport_state_changed = true;
239 session->cc_state_blend_changed = true;
240 session->cc_state_dsa_changed = true;
241 session->cc_state_cc_changed = true;
243 session->scissor_state_changed = true;
245 session->binding_table_vs_changed = true;
246 session->binding_table_gs_changed = true;
247 session->binding_table_fs_changed = true;
249 session->sampler_state_vs_changed = true;
250 session->sampler_state_gs_changed = true;
251 session->sampler_state_fs_changed = true;
253 session->pcb_state_vs_changed = true;
254 session->pcb_state_gs_changed = true;
255 session->pcb_state_fs_changed = true;
260 gen6_pipeline_common_urb(struct ilo_3d_pipeline *p,
261 const struct ilo_state_vector *vec,
262 struct gen6_pipeline_session *session)
265 if (DIRTY(VE) || DIRTY(VS) || DIRTY(GS)) {
266 const bool gs_active = (vec->gs || (vec->vs &&
267 ilo_shader_get_kernel_param(vec->vs, ILO_KERNEL_VS_GEN6_SO)));
268 int vs_entry_size, gs_entry_size;
269 int vs_total_size, gs_total_size;
271 vs_entry_size = (vec->vs) ?
272 ilo_shader_get_kernel_param(vec->vs, ILO_KERNEL_OUTPUT_COUNT) : 0;
275 * As indicated by 2e712e41db0c0676e9f30fc73172c0e8de8d84d4, VF and VS
276 * share VUE handles. The VUE allocation size must be large enough to
277 * store either VF outputs (number of VERTEX_ELEMENTs) and VS outputs.
279 * I am not sure if the PRM explicitly states that VF and VS share VUE
280 * handles. But here is a citation that implies so:
282 * From the Sandy Bridge PRM, volume 2 part 1, page 44:
284 * "Once a FF stage that spawn threads has sufficient input to
285 * initiate a thread, it must guarantee that it is safe to request
286 * the thread initiation. For all these FF stages, this check is
289 * - The availability of output URB entries:
290 * - VS: As the input URB entries are overwritten with the
291 * VS-generated output data, output URB availability isn't a
294 if (vs_entry_size < vec->ve->count)
295 vs_entry_size = vec->ve->count;
297 gs_entry_size = (vec->gs) ?
298 ilo_shader_get_kernel_param(vec->gs, ILO_KERNEL_OUTPUT_COUNT) :
299 (gs_active) ? vs_entry_size : 0;
302 vs_entry_size *= sizeof(float) * 4;
303 gs_entry_size *= sizeof(float) * 4;
304 vs_total_size = p->dev->urb_size;
308 gs_total_size = vs_total_size;
314 gen6_3DSTATE_URB(p->builder, vs_total_size, gs_total_size,
315 vs_entry_size, gs_entry_size);
318 * From the Sandy Bridge PRM, volume 2 part 1, page 27:
320 * "Because of a urb corruption caused by allocating a previous
321 * gsunit's urb entry to vsunit software is required to send a
322 * "GS NULL Fence" (Send URB fence with VS URB size == 1 and GS URB
323 * size == 0) plus a dummy DRAW call before any case where VS will
324 * be taking over GS URB space."
326 if (p->state.gs.active && !gs_active)
327 ilo_3d_pipeline_emit_flush_gen6(p);
329 p->state.gs.active = gs_active;
334 gen6_pipeline_common_pointers_1(struct ilo_3d_pipeline *p,
335 const struct ilo_state_vector *vec,
336 struct gen6_pipeline_session *session)
338 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
339 if (session->viewport_state_changed) {
340 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(p->builder,
341 p->state.CLIP_VIEWPORT,
342 p->state.SF_VIEWPORT,
343 p->state.CC_VIEWPORT);
348 gen6_pipeline_common_pointers_2(struct ilo_3d_pipeline *p,
349 const struct ilo_state_vector *vec,
350 struct gen6_pipeline_session *session)
352 /* 3DSTATE_CC_STATE_POINTERS */
353 if (session->cc_state_blend_changed ||
354 session->cc_state_dsa_changed ||
355 session->cc_state_cc_changed) {
356 gen6_3DSTATE_CC_STATE_POINTERS(p->builder,
357 p->state.BLEND_STATE,
358 p->state.DEPTH_STENCIL_STATE,
359 p->state.COLOR_CALC_STATE);
362 /* 3DSTATE_SAMPLER_STATE_POINTERS */
363 if (session->sampler_state_vs_changed ||
364 session->sampler_state_gs_changed ||
365 session->sampler_state_fs_changed) {
366 gen6_3DSTATE_SAMPLER_STATE_POINTERS(p->builder,
367 p->state.vs.SAMPLER_STATE,
369 p->state.wm.SAMPLER_STATE);
374 gen6_pipeline_common_pointers_3(struct ilo_3d_pipeline *p,
375 const struct ilo_state_vector *vec,
376 struct gen6_pipeline_session *session)
378 /* 3DSTATE_SCISSOR_STATE_POINTERS */
379 if (session->scissor_state_changed) {
380 gen6_3DSTATE_SCISSOR_STATE_POINTERS(p->builder,
381 p->state.SCISSOR_RECT);
384 /* 3DSTATE_BINDING_TABLE_POINTERS */
385 if (session->binding_table_vs_changed ||
386 session->binding_table_gs_changed ||
387 session->binding_table_fs_changed) {
388 gen6_3DSTATE_BINDING_TABLE_POINTERS(p->builder,
389 p->state.vs.BINDING_TABLE_STATE,
390 p->state.gs.BINDING_TABLE_STATE,
391 p->state.wm.BINDING_TABLE_STATE);
396 gen6_pipeline_vf(struct ilo_3d_pipeline *p,
397 const struct ilo_state_vector *vec,
398 struct gen6_pipeline_session *session)
400 if (ilo_dev_gen(p->dev) >= ILO_GEN(7.5)) {
401 /* 3DSTATE_INDEX_BUFFER */
402 if (DIRTY(IB) || session->batch_bo_changed) {
403 gen6_3DSTATE_INDEX_BUFFER(p->builder,
408 if (session->primitive_restart_changed) {
409 gen7_3DSTATE_VF(p->builder, vec->draw->primitive_restart,
410 vec->draw->restart_index);
414 /* 3DSTATE_INDEX_BUFFER */
415 if (DIRTY(IB) || session->primitive_restart_changed ||
416 session->batch_bo_changed) {
417 gen6_3DSTATE_INDEX_BUFFER(p->builder,
418 &vec->ib, vec->draw->primitive_restart);
422 /* 3DSTATE_VERTEX_BUFFERS */
423 if (DIRTY(VB) || DIRTY(VE) || session->batch_bo_changed)
424 gen6_3DSTATE_VERTEX_BUFFERS(p->builder, vec->ve, &vec->vb);
426 /* 3DSTATE_VERTEX_ELEMENTS */
427 if (DIRTY(VE) || DIRTY(VS)) {
428 const struct ilo_ve_state *ve = vec->ve;
429 bool last_velement_edgeflag = false;
430 bool prepend_generate_ids = false;
433 if (ilo_shader_get_kernel_param(vec->vs,
434 ILO_KERNEL_VS_INPUT_EDGEFLAG)) {
435 /* we rely on the state tracker here */
436 assert(ilo_shader_get_kernel_param(vec->vs,
437 ILO_KERNEL_INPUT_COUNT) == ve->count);
439 last_velement_edgeflag = true;
442 if (ilo_shader_get_kernel_param(vec->vs,
443 ILO_KERNEL_VS_INPUT_INSTANCEID) ||
444 ilo_shader_get_kernel_param(vec->vs,
445 ILO_KERNEL_VS_INPUT_VERTEXID))
446 prepend_generate_ids = true;
449 gen6_3DSTATE_VERTEX_ELEMENTS(p->builder, ve,
450 last_velement_edgeflag, prepend_generate_ids);
455 gen6_pipeline_vf_statistics(struct ilo_3d_pipeline *p,
456 const struct ilo_state_vector *vec,
457 struct gen6_pipeline_session *session)
459 /* 3DSTATE_VF_STATISTICS */
460 if (session->hw_ctx_changed)
461 gen6_3DSTATE_VF_STATISTICS(p->builder, false);
465 gen6_pipeline_vf_draw(struct ilo_3d_pipeline *p,
466 const struct ilo_state_vector *vec,
467 struct gen6_pipeline_session *session)
470 gen6_3DPRIMITIVE(p->builder, vec->draw, &vec->ib);
471 p->state.has_gen6_wa_pipe_control = false;
475 gen6_pipeline_vs(struct ilo_3d_pipeline *p,
476 const struct ilo_state_vector *vec,
477 struct gen6_pipeline_session *session)
479 const bool emit_3dstate_vs = (DIRTY(VS) || DIRTY(SAMPLER_VS) ||
480 session->kernel_bo_changed);
481 const bool emit_3dstate_constant_vs = session->pcb_state_vs_changed;
484 * the classic i965 does this in upload_vs_state(), citing a spec that I
487 if (emit_3dstate_vs && ilo_dev_gen(p->dev) == ILO_GEN(6))
488 gen6_wa_pipe_control_post_sync(p, false);
490 /* 3DSTATE_CONSTANT_VS */
491 if (emit_3dstate_constant_vs) {
492 gen6_3DSTATE_CONSTANT_VS(p->builder,
493 &p->state.vs.PUSH_CONSTANT_BUFFER,
494 &p->state.vs.PUSH_CONSTANT_BUFFER_size,
499 if (emit_3dstate_vs) {
500 const int num_samplers = vec->sampler[PIPE_SHADER_VERTEX].count;
502 gen6_3DSTATE_VS(p->builder, vec->vs, num_samplers);
505 if (emit_3dstate_constant_vs && ilo_dev_gen(p->dev) == ILO_GEN(6))
506 gen6_wa_pipe_control_vs_const_flush(p);
510 gen6_pipeline_gs(struct ilo_3d_pipeline *p,
511 const struct ilo_state_vector *vec,
512 struct gen6_pipeline_session *session)
514 /* 3DSTATE_CONSTANT_GS */
515 if (session->pcb_state_gs_changed)
516 gen6_3DSTATE_CONSTANT_GS(p->builder, NULL, NULL, 0);
519 if (DIRTY(GS) || DIRTY(VS) ||
520 session->prim_changed || session->kernel_bo_changed) {
521 const int verts_per_prim = u_vertices_per_prim(session->reduced_prim);
523 gen6_3DSTATE_GS(p->builder, vec->gs, vec->vs, verts_per_prim);
528 gen6_pipeline_update_max_svbi(struct ilo_3d_pipeline *p,
529 const struct ilo_state_vector *vec,
530 struct gen6_pipeline_session *session)
532 if (DIRTY(VS) || DIRTY(GS) || DIRTY(SO)) {
533 const struct pipe_stream_output_info *so_info =
534 (vec->gs) ? ilo_shader_get_kernel_so_info(vec->gs) :
535 (vec->vs) ? ilo_shader_get_kernel_so_info(vec->vs) : NULL;
536 unsigned max_svbi = 0xffffffff;
539 for (i = 0; i < so_info->num_outputs; i++) {
540 const int output_buffer = so_info->output[i].output_buffer;
541 const struct pipe_stream_output_target *so =
542 vec->so.states[output_buffer];
543 const int struct_size = so_info->stride[output_buffer] * 4;
544 const int elem_size = so_info->output[i].num_components * 4;
552 buf_size = so->buffer_size - so_info->output[i].dst_offset * 4;
554 count = buf_size / struct_size;
555 if (buf_size % struct_size >= elem_size)
558 if (count < max_svbi)
562 if (p->state.so_max_vertices != max_svbi) {
563 p->state.so_max_vertices = max_svbi;
572 gen6_pipeline_gs_svbi(struct ilo_3d_pipeline *p,
573 const struct ilo_state_vector *vec,
574 struct gen6_pipeline_session *session)
576 const bool emit = gen6_pipeline_update_max_svbi(p, vec, session);
578 /* 3DSTATE_GS_SVB_INDEX */
580 if (ilo_dev_gen(p->dev) == ILO_GEN(6))
581 gen6_wa_pipe_control_post_sync(p, false);
583 gen6_3DSTATE_GS_SVB_INDEX(p->builder,
584 0, 0, p->state.so_max_vertices,
587 if (session->hw_ctx_changed) {
591 * From the Sandy Bridge PRM, volume 2 part 1, page 148:
593 * "If a buffer is not enabled then the SVBI must be set to 0x0
594 * in order to not cause overflow in that SVBI."
596 * "If a buffer is not enabled then the MaxSVBI must be set to
597 * 0xFFFFFFFF in order to not cause overflow in that SVBI."
599 for (i = 1; i < 4; i++) {
600 gen6_3DSTATE_GS_SVB_INDEX(p->builder,
601 i, 0, 0xffffffff, false);
608 gen6_pipeline_clip(struct ilo_3d_pipeline *p,
609 const struct ilo_state_vector *vec,
610 struct gen6_pipeline_session *session)
613 if (DIRTY(RASTERIZER) || DIRTY(FS) || DIRTY(VIEWPORT) || DIRTY(FB)) {
614 bool enable_guardband = true;
618 * We do not do 2D clipping yet. Guard band test should only be enabled
619 * when the viewport is larger than the framebuffer.
621 for (i = 0; i < vec->viewport.count; i++) {
622 const struct ilo_viewport_cso *vp = &vec->viewport.cso[i];
624 if (vp->min_x > 0.0f || vp->max_x < vec->fb.state.width ||
625 vp->min_y > 0.0f || vp->max_y < vec->fb.state.height) {
626 enable_guardband = false;
631 gen6_3DSTATE_CLIP(p->builder, vec->rasterizer,
632 vec->fs, enable_guardband, 1);
637 gen6_pipeline_sf(struct ilo_3d_pipeline *p,
638 const struct ilo_state_vector *vec,
639 struct gen6_pipeline_session *session)
642 if (DIRTY(RASTERIZER) || DIRTY(FS))
643 gen6_3DSTATE_SF(p->builder, vec->rasterizer, vec->fs);
647 gen6_pipeline_sf_rect(struct ilo_3d_pipeline *p,
648 const struct ilo_state_vector *vec,
649 struct gen6_pipeline_session *session)
651 /* 3DSTATE_DRAWING_RECTANGLE */
653 if (ilo_dev_gen(p->dev) == ILO_GEN(6))
654 gen6_wa_pipe_control_post_sync(p, false);
656 gen6_3DSTATE_DRAWING_RECTANGLE(p->builder, 0, 0,
657 vec->fb.state.width, vec->fb.state.height);
662 gen6_pipeline_wm(struct ilo_3d_pipeline *p,
663 const struct ilo_state_vector *vec,
664 struct gen6_pipeline_session *session)
666 /* 3DSTATE_CONSTANT_PS */
667 if (session->pcb_state_fs_changed) {
668 gen6_3DSTATE_CONSTANT_PS(p->builder,
669 &p->state.wm.PUSH_CONSTANT_BUFFER,
670 &p->state.wm.PUSH_CONSTANT_BUFFER_size,
675 if (DIRTY(FS) || DIRTY(SAMPLER_FS) || DIRTY(BLEND) || DIRTY(DSA) ||
676 DIRTY(RASTERIZER) || session->kernel_bo_changed) {
677 const int num_samplers = vec->sampler[PIPE_SHADER_FRAGMENT].count;
678 const bool dual_blend = vec->blend->dual_blend;
679 const bool cc_may_kill = (vec->dsa->dw_alpha ||
680 vec->blend->alpha_to_coverage);
682 if (ilo_dev_gen(p->dev) == ILO_GEN(6) && session->hw_ctx_changed)
683 gen6_wa_pipe_control_wm_max_threads_stall(p);
685 gen6_3DSTATE_WM(p->builder, vec->fs, num_samplers,
686 vec->rasterizer, dual_blend, cc_may_kill, 0);
691 gen6_pipeline_wm_multisample(struct ilo_3d_pipeline *p,
692 const struct ilo_state_vector *vec,
693 struct gen6_pipeline_session *session)
695 /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
696 if (DIRTY(SAMPLE_MASK) || DIRTY(FB)) {
697 const uint32_t *packed_sample_pos;
699 packed_sample_pos = (vec->fb.num_samples > 1) ?
700 &p->packed_sample_position_4x : &p->packed_sample_position_1x;
702 if (ilo_dev_gen(p->dev) == ILO_GEN(6)) {
703 gen6_wa_pipe_control_post_sync(p, false);
704 gen6_wa_pipe_control_wm_multisample_flush(p);
707 gen6_3DSTATE_MULTISAMPLE(p->builder,
708 vec->fb.num_samples, packed_sample_pos,
709 vec->rasterizer->state.half_pixel_center);
711 gen6_3DSTATE_SAMPLE_MASK(p->builder,
712 (vec->fb.num_samples > 1) ? vec->sample_mask : 0x1);
717 gen6_pipeline_wm_depth(struct ilo_3d_pipeline *p,
718 const struct ilo_state_vector *vec,
719 struct gen6_pipeline_session *session)
721 /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
722 if (DIRTY(FB) || session->batch_bo_changed) {
723 const struct ilo_zs_surface *zs;
724 uint32_t clear_params;
726 if (vec->fb.state.zsbuf) {
727 const struct ilo_surface_cso *surface =
728 (const struct ilo_surface_cso *) vec->fb.state.zsbuf;
729 const struct ilo_texture_slice *slice =
730 ilo_texture_get_slice(ilo_texture(surface->base.texture),
731 surface->base.u.tex.level, surface->base.u.tex.first_layer);
733 assert(!surface->is_rt);
736 clear_params = slice->clear_value;
739 zs = &vec->fb.null_zs;
743 if (ilo_dev_gen(p->dev) == ILO_GEN(6)) {
744 gen6_wa_pipe_control_post_sync(p, false);
745 gen6_wa_pipe_control_wm_depth_flush(p);
748 gen6_3DSTATE_DEPTH_BUFFER(p->builder, zs);
749 gen6_3DSTATE_HIER_DEPTH_BUFFER(p->builder, zs);
750 gen6_3DSTATE_STENCIL_BUFFER(p->builder, zs);
751 gen6_3DSTATE_CLEAR_PARAMS(p->builder, clear_params);
756 gen6_pipeline_wm_raster(struct ilo_3d_pipeline *p,
757 const struct ilo_state_vector *vec,
758 struct gen6_pipeline_session *session)
760 /* 3DSTATE_POLY_STIPPLE_PATTERN and 3DSTATE_POLY_STIPPLE_OFFSET */
761 if ((DIRTY(RASTERIZER) || DIRTY(POLY_STIPPLE)) &&
762 vec->rasterizer->state.poly_stipple_enable) {
763 if (ilo_dev_gen(p->dev) == ILO_GEN(6))
764 gen6_wa_pipe_control_post_sync(p, false);
766 gen6_3DSTATE_POLY_STIPPLE_PATTERN(p->builder,
769 gen6_3DSTATE_POLY_STIPPLE_OFFSET(p->builder, 0, 0);
772 /* 3DSTATE_LINE_STIPPLE */
773 if (DIRTY(RASTERIZER) && vec->rasterizer->state.line_stipple_enable) {
774 if (ilo_dev_gen(p->dev) == ILO_GEN(6))
775 gen6_wa_pipe_control_post_sync(p, false);
777 gen6_3DSTATE_LINE_STIPPLE(p->builder,
778 vec->rasterizer->state.line_stipple_pattern,
779 vec->rasterizer->state.line_stipple_factor + 1);
782 /* 3DSTATE_AA_LINE_PARAMETERS */
783 if (DIRTY(RASTERIZER) && vec->rasterizer->state.line_smooth) {
784 if (ilo_dev_gen(p->dev) == ILO_GEN(6))
785 gen6_wa_pipe_control_post_sync(p, false);
787 gen6_3DSTATE_AA_LINE_PARAMETERS(p->builder);
792 gen6_pipeline_state_viewports(struct ilo_3d_pipeline *p,
793 const struct ilo_state_vector *vec,
794 struct gen6_pipeline_session *session)
796 /* SF_CLIP_VIEWPORT and CC_VIEWPORT */
797 if (ilo_dev_gen(p->dev) >= ILO_GEN(7) && DIRTY(VIEWPORT)) {
798 p->state.SF_CLIP_VIEWPORT = gen7_SF_CLIP_VIEWPORT(p->builder,
799 vec->viewport.cso, vec->viewport.count);
801 p->state.CC_VIEWPORT = gen6_CC_VIEWPORT(p->builder,
802 vec->viewport.cso, vec->viewport.count);
804 session->viewport_state_changed = true;
806 /* SF_VIEWPORT, CLIP_VIEWPORT, and CC_VIEWPORT */
807 else if (DIRTY(VIEWPORT)) {
808 p->state.CLIP_VIEWPORT = gen6_CLIP_VIEWPORT(p->builder,
809 vec->viewport.cso, vec->viewport.count);
811 p->state.SF_VIEWPORT = gen6_SF_VIEWPORT(p->builder,
812 vec->viewport.cso, vec->viewport.count);
814 p->state.CC_VIEWPORT = gen6_CC_VIEWPORT(p->builder,
815 vec->viewport.cso, vec->viewport.count);
817 session->viewport_state_changed = true;
822 gen6_pipeline_state_cc(struct ilo_3d_pipeline *p,
823 const struct ilo_state_vector *vec,
824 struct gen6_pipeline_session *session)
827 if (DIRTY(BLEND) || DIRTY(FB) || DIRTY(DSA)) {
828 p->state.BLEND_STATE = gen6_BLEND_STATE(p->builder,
829 vec->blend, &vec->fb, vec->dsa);
831 session->cc_state_blend_changed = true;
834 /* COLOR_CALC_STATE */
835 if (DIRTY(DSA) || DIRTY(STENCIL_REF) || DIRTY(BLEND_COLOR)) {
836 p->state.COLOR_CALC_STATE =
837 gen6_COLOR_CALC_STATE(p->builder, &vec->stencil_ref,
838 vec->dsa->alpha_ref, &vec->blend_color);
840 session->cc_state_cc_changed = true;
843 /* DEPTH_STENCIL_STATE */
845 p->state.DEPTH_STENCIL_STATE =
846 gen6_DEPTH_STENCIL_STATE(p->builder, vec->dsa);
848 session->cc_state_dsa_changed = true;
853 gen6_pipeline_state_scissors(struct ilo_3d_pipeline *p,
854 const struct ilo_state_vector *vec,
855 struct gen6_pipeline_session *session)
858 if (DIRTY(SCISSOR) || DIRTY(VIEWPORT)) {
859 /* there should be as many scissors as there are viewports */
860 p->state.SCISSOR_RECT = gen6_SCISSOR_RECT(p->builder,
861 &vec->scissor, vec->viewport.count);
863 session->scissor_state_changed = true;
868 gen6_pipeline_state_surfaces_rt(struct ilo_3d_pipeline *p,
869 const struct ilo_state_vector *vec,
870 struct gen6_pipeline_session *session)
872 /* SURFACE_STATEs for render targets */
874 const struct ilo_fb_state *fb = &vec->fb;
875 const int offset = ILO_WM_DRAW_SURFACE(0);
876 uint32_t *surface_state = &p->state.wm.SURFACE_STATE[offset];
879 for (i = 0; i < fb->state.nr_cbufs; i++) {
880 const struct ilo_surface_cso *surface =
881 (const struct ilo_surface_cso *) fb->state.cbufs[i];
885 gen6_SURFACE_STATE(p->builder, &fb->null_rt, true);
888 assert(surface && surface->is_rt);
890 gen6_SURFACE_STATE(p->builder, &surface->u.rt, true);
895 * Upload at least one render target, as
896 * brw_update_renderbuffer_surfaces() does. I don't know why.
900 gen6_SURFACE_STATE(p->builder, &fb->null_rt, true);
905 memset(&surface_state[i], 0, (ILO_MAX_DRAW_BUFFERS - i) * 4);
907 if (i && session->num_surfaces[PIPE_SHADER_FRAGMENT] < offset + i)
908 session->num_surfaces[PIPE_SHADER_FRAGMENT] = offset + i;
910 session->binding_table_fs_changed = true;
915 gen6_pipeline_state_surfaces_so(struct ilo_3d_pipeline *p,
916 const struct ilo_state_vector *vec,
917 struct gen6_pipeline_session *session)
919 const struct ilo_so_state *so = &vec->so;
921 if (ilo_dev_gen(p->dev) != ILO_GEN(6))
924 /* SURFACE_STATEs for stream output targets */
925 if (DIRTY(VS) || DIRTY(GS) || DIRTY(SO)) {
926 const struct pipe_stream_output_info *so_info =
927 (vec->gs) ? ilo_shader_get_kernel_so_info(vec->gs) :
928 (vec->vs) ? ilo_shader_get_kernel_so_info(vec->vs) : NULL;
929 const int offset = ILO_GS_SO_SURFACE(0);
930 uint32_t *surface_state = &p->state.gs.SURFACE_STATE[offset];
933 for (i = 0; so_info && i < so_info->num_outputs; i++) {
934 const int target = so_info->output[i].output_buffer;
935 const struct pipe_stream_output_target *so_target =
936 (target < so->count) ? so->states[target] : NULL;
939 surface_state[i] = gen6_so_SURFACE_STATE(p->builder,
940 so_target, so_info, i);
943 surface_state[i] = 0;
947 memset(&surface_state[i], 0, (ILO_MAX_SO_BINDINGS - i) * 4);
949 if (i && session->num_surfaces[PIPE_SHADER_GEOMETRY] < offset + i)
950 session->num_surfaces[PIPE_SHADER_GEOMETRY] = offset + i;
952 session->binding_table_gs_changed = true;
957 gen6_pipeline_state_surfaces_view(struct ilo_3d_pipeline *p,
958 const struct ilo_state_vector *vec,
960 struct gen6_pipeline_session *session)
962 const struct ilo_view_state *view = &vec->view[shader_type];
963 uint32_t *surface_state;
967 /* SURFACE_STATEs for sampler views */
968 switch (shader_type) {
969 case PIPE_SHADER_VERTEX:
970 if (DIRTY(VIEW_VS)) {
971 offset = ILO_VS_TEXTURE_SURFACE(0);
972 surface_state = &p->state.vs.SURFACE_STATE[offset];
974 session->binding_table_vs_changed = true;
980 case PIPE_SHADER_FRAGMENT:
981 if (DIRTY(VIEW_FS)) {
982 offset = ILO_WM_TEXTURE_SURFACE(0);
983 surface_state = &p->state.wm.SURFACE_STATE[offset];
985 session->binding_table_fs_changed = true;
999 for (i = 0; i < view->count; i++) {
1000 if (view->states[i]) {
1001 const struct ilo_view_cso *cso =
1002 (const struct ilo_view_cso *) view->states[i];
1005 gen6_SURFACE_STATE(p->builder, &cso->surface, false);
1008 surface_state[i] = 0;
1012 memset(&surface_state[i], 0, (ILO_MAX_SAMPLER_VIEWS - i) * 4);
1014 if (i && session->num_surfaces[shader_type] < offset + i)
1015 session->num_surfaces[shader_type] = offset + i;
1019 gen6_pipeline_state_surfaces_const(struct ilo_3d_pipeline *p,
1020 const struct ilo_state_vector *vec,
1022 struct gen6_pipeline_session *session)
1024 const struct ilo_cbuf_state *cbuf = &vec->cbuf[shader_type];
1025 uint32_t *surface_state;
1026 bool *binding_table_changed;
1027 int offset, count, i;
1032 /* SURFACE_STATEs for constant buffers */
1033 switch (shader_type) {
1034 case PIPE_SHADER_VERTEX:
1035 offset = ILO_VS_CONST_SURFACE(0);
1036 surface_state = &p->state.vs.SURFACE_STATE[offset];
1037 binding_table_changed = &session->binding_table_vs_changed;
1039 case PIPE_SHADER_FRAGMENT:
1040 offset = ILO_WM_CONST_SURFACE(0);
1041 surface_state = &p->state.wm.SURFACE_STATE[offset];
1042 binding_table_changed = &session->binding_table_fs_changed;
1049 /* constants are pushed via PCB */
1050 if (cbuf->enabled_mask == 0x1 && !cbuf->cso[0].resource) {
1051 memset(surface_state, 0, ILO_MAX_CONST_BUFFERS * 4);
1055 count = util_last_bit(cbuf->enabled_mask);
1056 for (i = 0; i < count; i++) {
1057 if (cbuf->cso[i].resource) {
1058 surface_state[i] = gen6_SURFACE_STATE(p->builder,
1059 &cbuf->cso[i].surface, false);
1062 surface_state[i] = 0;
1066 memset(&surface_state[count], 0, (ILO_MAX_CONST_BUFFERS - count) * 4);
1068 if (count && session->num_surfaces[shader_type] < offset + count)
1069 session->num_surfaces[shader_type] = offset + count;
1071 *binding_table_changed = true;
1075 gen6_pipeline_state_binding_tables(struct ilo_3d_pipeline *p,
1076 const struct ilo_state_vector *vec,
1078 struct gen6_pipeline_session *session)
1080 uint32_t *binding_table_state, *surface_state;
1081 int *binding_table_state_size, size;
1084 /* BINDING_TABLE_STATE */
1085 switch (shader_type) {
1086 case PIPE_SHADER_VERTEX:
1087 surface_state = p->state.vs.SURFACE_STATE;
1088 binding_table_state = &p->state.vs.BINDING_TABLE_STATE;
1089 binding_table_state_size = &p->state.vs.BINDING_TABLE_STATE_size;
1091 skip = !session->binding_table_vs_changed;
1093 case PIPE_SHADER_GEOMETRY:
1094 surface_state = p->state.gs.SURFACE_STATE;
1095 binding_table_state = &p->state.gs.BINDING_TABLE_STATE;
1096 binding_table_state_size = &p->state.gs.BINDING_TABLE_STATE_size;
1098 skip = !session->binding_table_gs_changed;
1100 case PIPE_SHADER_FRAGMENT:
1101 surface_state = p->state.wm.SURFACE_STATE;
1102 binding_table_state = &p->state.wm.BINDING_TABLE_STATE;
1103 binding_table_state_size = &p->state.wm.BINDING_TABLE_STATE_size;
1105 skip = !session->binding_table_fs_changed;
1116 * If we have seemingly less SURFACE_STATEs than before, it could be that
1117 * we did not touch those reside at the tail in this upload. Loop over
1118 * them to figure out the real number of SURFACE_STATEs.
1120 for (size = *binding_table_state_size;
1121 size > session->num_surfaces[shader_type]; size--) {
1122 if (surface_state[size - 1])
1125 if (size < session->num_surfaces[shader_type])
1126 size = session->num_surfaces[shader_type];
1128 *binding_table_state = gen6_BINDING_TABLE_STATE(p->builder,
1129 surface_state, size);
1130 *binding_table_state_size = size;
1134 gen6_pipeline_state_samplers(struct ilo_3d_pipeline *p,
1135 const struct ilo_state_vector *vec,
1137 struct gen6_pipeline_session *session)
1139 const struct ilo_sampler_cso * const *samplers =
1140 vec->sampler[shader_type].cso;
1141 const struct pipe_sampler_view * const *views =
1142 (const struct pipe_sampler_view **) vec->view[shader_type].states;
1143 const int num_samplers = vec->sampler[shader_type].count;
1144 const int num_views = vec->view[shader_type].count;
1145 uint32_t *sampler_state, *border_color_state;
1146 bool emit_border_color = false;
1149 /* SAMPLER_BORDER_COLOR_STATE and SAMPLER_STATE */
1150 switch (shader_type) {
1151 case PIPE_SHADER_VERTEX:
1152 if (DIRTY(SAMPLER_VS) || DIRTY(VIEW_VS)) {
1153 sampler_state = &p->state.vs.SAMPLER_STATE;
1154 border_color_state = p->state.vs.SAMPLER_BORDER_COLOR_STATE;
1156 if (DIRTY(SAMPLER_VS))
1157 emit_border_color = true;
1159 session->sampler_state_vs_changed = true;
1165 case PIPE_SHADER_FRAGMENT:
1166 if (DIRTY(SAMPLER_FS) || DIRTY(VIEW_FS)) {
1167 sampler_state = &p->state.wm.SAMPLER_STATE;
1168 border_color_state = p->state.wm.SAMPLER_BORDER_COLOR_STATE;
1170 if (DIRTY(SAMPLER_FS))
1171 emit_border_color = true;
1173 session->sampler_state_fs_changed = true;
1187 if (emit_border_color) {
1190 for (i = 0; i < num_samplers; i++) {
1191 border_color_state[i] = (samplers[i]) ?
1192 gen6_SAMPLER_BORDER_COLOR_STATE(p->builder, samplers[i]) : 0;
1196 /* should we take the minimum of num_samplers and num_views? */
1197 *sampler_state = gen6_SAMPLER_STATE(p->builder,
1200 MIN2(num_samplers, num_views));
1204 gen6_pipeline_state_pcb(struct ilo_3d_pipeline *p,
1205 const struct ilo_state_vector *vec,
1206 struct gen6_pipeline_session *session)
1208 /* push constant buffer for VS */
1209 if (DIRTY(VS) || DIRTY(CBUF) || DIRTY(CLIP)) {
1210 const int cbuf0_size = (vec->vs) ?
1211 ilo_shader_get_kernel_param(vec->vs,
1212 ILO_KERNEL_PCB_CBUF0_SIZE) : 0;
1213 const int clip_state_size = (vec->vs) ?
1214 ilo_shader_get_kernel_param(vec->vs,
1215 ILO_KERNEL_VS_PCB_UCP_SIZE) : 0;
1216 const int total_size = cbuf0_size + clip_state_size;
1221 p->state.vs.PUSH_CONSTANT_BUFFER =
1222 gen6_push_constant_buffer(p->builder, total_size, &pcb);
1223 p->state.vs.PUSH_CONSTANT_BUFFER_size = total_size;
1226 const struct ilo_cbuf_state *cbuf =
1227 &vec->cbuf[PIPE_SHADER_VERTEX];
1229 if (cbuf0_size <= cbuf->cso[0].user_buffer_size) {
1230 memcpy(pcb, cbuf->cso[0].user_buffer, cbuf0_size);
1233 memcpy(pcb, cbuf->cso[0].user_buffer,
1234 cbuf->cso[0].user_buffer_size);
1235 memset(pcb + cbuf->cso[0].user_buffer_size, 0,
1236 cbuf0_size - cbuf->cso[0].user_buffer_size);
1242 if (clip_state_size)
1243 memcpy(pcb, &vec->clip, clip_state_size);
1245 session->pcb_state_vs_changed = true;
1247 else if (p->state.vs.PUSH_CONSTANT_BUFFER_size) {
1248 p->state.vs.PUSH_CONSTANT_BUFFER = 0;
1249 p->state.vs.PUSH_CONSTANT_BUFFER_size = 0;
1251 session->pcb_state_vs_changed = true;
1255 /* push constant buffer for FS */
1256 if (DIRTY(FS) || DIRTY(CBUF)) {
1257 const int cbuf0_size = (vec->fs) ?
1258 ilo_shader_get_kernel_param(vec->fs, ILO_KERNEL_PCB_CBUF0_SIZE) : 0;
1261 const struct ilo_cbuf_state *cbuf = &vec->cbuf[PIPE_SHADER_FRAGMENT];
1264 p->state.wm.PUSH_CONSTANT_BUFFER =
1265 gen6_push_constant_buffer(p->builder, cbuf0_size, &pcb);
1266 p->state.wm.PUSH_CONSTANT_BUFFER_size = cbuf0_size;
1268 if (cbuf0_size <= cbuf->cso[0].user_buffer_size) {
1269 memcpy(pcb, cbuf->cso[0].user_buffer, cbuf0_size);
1272 memcpy(pcb, cbuf->cso[0].user_buffer,
1273 cbuf->cso[0].user_buffer_size);
1274 memset(pcb + cbuf->cso[0].user_buffer_size, 0,
1275 cbuf0_size - cbuf->cso[0].user_buffer_size);
1278 session->pcb_state_fs_changed = true;
1280 else if (p->state.wm.PUSH_CONSTANT_BUFFER_size) {
1281 p->state.wm.PUSH_CONSTANT_BUFFER = 0;
1282 p->state.wm.PUSH_CONSTANT_BUFFER_size = 0;
1284 session->pcb_state_fs_changed = true;
1292 gen6_pipeline_commands(struct ilo_3d_pipeline *p,
1293 const struct ilo_state_vector *vec,
1294 struct gen6_pipeline_session *session)
1297 * We try to keep the order of the commands match, as closely as possible,
1298 * that of the classic i965 driver. It allows us to compare the command
1301 gen6_pipeline_common_select(p, vec, session);
1302 gen6_pipeline_gs_svbi(p, vec, session);
1303 gen6_pipeline_common_sip(p, vec, session);
1304 gen6_pipeline_vf_statistics(p, vec, session);
1305 gen6_pipeline_common_base_address(p, vec, session);
1306 gen6_pipeline_common_pointers_1(p, vec, session);
1307 gen6_pipeline_common_urb(p, vec, session);
1308 gen6_pipeline_common_pointers_2(p, vec, session);
1309 gen6_pipeline_wm_multisample(p, vec, session);
1310 gen6_pipeline_vs(p, vec, session);
1311 gen6_pipeline_gs(p, vec, session);
1312 gen6_pipeline_clip(p, vec, session);
1313 gen6_pipeline_sf(p, vec, session);
1314 gen6_pipeline_wm(p, vec, session);
1315 gen6_pipeline_common_pointers_3(p, vec, session);
1316 gen6_pipeline_wm_depth(p, vec, session);
1317 gen6_pipeline_wm_raster(p, vec, session);
1318 gen6_pipeline_sf_rect(p, vec, session);
1319 gen6_pipeline_vf(p, vec, session);
1320 gen6_pipeline_vf_draw(p, vec, session);
1324 gen6_pipeline_states(struct ilo_3d_pipeline *p,
1325 const struct ilo_state_vector *vec,
1326 struct gen6_pipeline_session *session)
1330 gen6_pipeline_state_viewports(p, vec, session);
1331 gen6_pipeline_state_cc(p, vec, session);
1332 gen6_pipeline_state_scissors(p, vec, session);
1333 gen6_pipeline_state_pcb(p, vec, session);
1336 * upload all SURAFCE_STATEs together so that we know there are minimal
1339 gen6_pipeline_state_surfaces_rt(p, vec, session);
1340 gen6_pipeline_state_surfaces_so(p, vec, session);
1341 for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
1342 gen6_pipeline_state_surfaces_view(p, vec, shader_type, session);
1343 gen6_pipeline_state_surfaces_const(p, vec, shader_type, session);
1346 for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
1347 gen6_pipeline_state_samplers(p, vec, shader_type, session);
1348 /* this must be called after all SURFACE_STATEs are uploaded */
1349 gen6_pipeline_state_binding_tables(p, vec, shader_type, session);
1354 gen6_pipeline_prepare(const struct ilo_3d_pipeline *p,
1355 const struct ilo_state_vector *vec,
1356 struct gen6_pipeline_session *session)
1358 memset(session, 0, sizeof(*session));
1359 session->pipe_dirty = vec->dirty;
1360 session->reduced_prim = u_reduced_prim(vec->draw->mode);
1362 session->hw_ctx_changed =
1363 (p->invalidate_flags & ILO_3D_PIPELINE_INVALIDATE_HW);
1365 if (session->hw_ctx_changed) {
1366 /* these should be enough to make everything uploaded */
1367 session->batch_bo_changed = true;
1368 session->state_bo_changed = true;
1369 session->kernel_bo_changed = true;
1370 session->prim_changed = true;
1371 session->primitive_restart_changed = true;
1374 * Any state that involves resources needs to be re-emitted when the
1375 * batch bo changed. This is because we do not pin the resources and
1376 * their offsets (or existence) may change between batch buffers.
1378 session->batch_bo_changed =
1379 (p->invalidate_flags & ILO_3D_PIPELINE_INVALIDATE_BATCH_BO);
1381 session->state_bo_changed =
1382 (p->invalidate_flags & ILO_3D_PIPELINE_INVALIDATE_STATE_BO);
1383 session->kernel_bo_changed =
1384 (p->invalidate_flags & ILO_3D_PIPELINE_INVALIDATE_KERNEL_BO);
1385 session->prim_changed = (p->state.reduced_prim != session->reduced_prim);
1386 session->primitive_restart_changed =
1387 (p->state.primitive_restart != vec->draw->primitive_restart);
1392 gen6_pipeline_draw(struct ilo_3d_pipeline *p,
1393 const struct ilo_state_vector *vec,
1394 struct gen6_pipeline_session *session)
1396 /* force all states to be uploaded if the state bo changed */
1397 if (session->state_bo_changed)
1398 session->pipe_dirty = ILO_DIRTY_ALL;
1400 session->pipe_dirty = vec->dirty;
1402 session->emit_draw_states(p, vec, session);
1404 /* force all commands to be uploaded if the HW context changed */
1405 if (session->hw_ctx_changed)
1406 session->pipe_dirty = ILO_DIRTY_ALL;
1408 session->pipe_dirty = vec->dirty;
1410 session->emit_draw_commands(p, vec, session);
1414 gen6_pipeline_end(struct ilo_3d_pipeline *p,
1415 const struct ilo_state_vector *vec,
1416 struct gen6_pipeline_session *session)
1418 p->state.reduced_prim = session->reduced_prim;
1419 p->state.primitive_restart = vec->draw->primitive_restart;
1423 ilo_3d_pipeline_emit_draw_gen6(struct ilo_3d_pipeline *p,
1424 const struct ilo_state_vector *vec)
1426 struct gen6_pipeline_session session;
1428 gen6_pipeline_prepare(p, vec, &session);
1430 session.emit_draw_states = gen6_pipeline_states;
1431 session.emit_draw_commands = gen6_pipeline_commands;
1433 gen6_pipeline_draw(p, vec, &session);
1434 gen6_pipeline_end(p, vec, &session);
1438 ilo_3d_pipeline_emit_flush_gen6(struct ilo_3d_pipeline *p)
1440 if (ilo_dev_gen(p->dev) == ILO_GEN(6))
1441 gen6_wa_pipe_control_post_sync(p, false);
1443 gen6_PIPE_CONTROL(p->builder,
1444 GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE |
1445 GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH |
1446 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
1447 GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE |
1448 GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1449 GEN6_PIPE_CONTROL_WRITE_NONE |
1450 GEN6_PIPE_CONTROL_CS_STALL,
1455 ilo_3d_pipeline_emit_query_gen6(struct ilo_3d_pipeline *p,
1456 struct ilo_query *q, uint32_t offset)
1458 const uint32_t pipeline_statistics_regs[] = {
1459 GEN6_REG_IA_VERTICES_COUNT,
1460 GEN6_REG_IA_PRIMITIVES_COUNT,
1461 GEN6_REG_VS_INVOCATION_COUNT,
1462 GEN6_REG_GS_INVOCATION_COUNT,
1463 GEN6_REG_GS_PRIMITIVES_COUNT,
1464 GEN6_REG_CL_INVOCATION_COUNT,
1465 GEN6_REG_CL_PRIMITIVES_COUNT,
1466 GEN6_REG_PS_INVOCATION_COUNT,
1467 (ilo_dev_gen(p->dev) >= ILO_GEN(7)) ? GEN7_REG_HS_INVOCATION_COUNT : 0,
1468 (ilo_dev_gen(p->dev) >= ILO_GEN(7)) ? GEN7_REG_DS_INVOCATION_COUNT : 0,
1471 const uint32_t primitives_generated_reg =
1472 (ilo_dev_gen(p->dev) >= ILO_GEN(7) && q->index > 0) ?
1473 GEN7_REG_SO_PRIM_STORAGE_NEEDED(q->index) :
1474 GEN6_REG_CL_INVOCATION_COUNT;
1475 const uint32_t primitives_emitted_reg =
1476 (ilo_dev_gen(p->dev) >= ILO_GEN(7)) ?
1477 GEN7_REG_SO_NUM_PRIMS_WRITTEN(q->index) :
1478 GEN6_REG_SO_NUM_PRIMS_WRITTEN;
1479 const uint32_t *regs;
1480 int reg_count = 0, i;
1482 ILO_DEV_ASSERT(p->dev, 6, 7.5);
1485 case PIPE_QUERY_OCCLUSION_COUNTER:
1486 if (ilo_dev_gen(p->dev) == ILO_GEN(6))
1487 gen6_wa_pipe_control_post_sync(p, false);
1489 gen6_PIPE_CONTROL(p->builder,
1490 GEN6_PIPE_CONTROL_DEPTH_STALL |
1491 GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT,
1492 q->bo, offset, true);
1494 case PIPE_QUERY_TIMESTAMP:
1495 case PIPE_QUERY_TIME_ELAPSED:
1496 if (ilo_dev_gen(p->dev) == ILO_GEN(6))
1497 gen6_wa_pipe_control_post_sync(p, true);
1499 gen6_PIPE_CONTROL(p->builder,
1500 GEN6_PIPE_CONTROL_WRITE_TIMESTAMP,
1501 q->bo, offset, true);
1503 case PIPE_QUERY_PRIMITIVES_GENERATED:
1504 regs = &primitives_generated_reg;
1507 case PIPE_QUERY_PRIMITIVES_EMITTED:
1508 regs = &primitives_emitted_reg;
1511 case PIPE_QUERY_PIPELINE_STATISTICS:
1512 regs = pipeline_statistics_regs;
1513 reg_count = Elements(pipeline_statistics_regs);
1524 for (i = 0; i < reg_count; i++) {
1526 /* store lower 32 bits */
1527 gen6_MI_STORE_REGISTER_MEM(p->builder, q->bo, offset, regs[i]);
1528 /* store higher 32 bits */
1529 gen6_MI_STORE_REGISTER_MEM(p->builder, q->bo,
1530 offset + 4, regs[i] + 4);
1532 gen6_MI_STORE_DATA_IMM(p->builder, q->bo, offset, 0, true);
1540 gen6_rectlist_vs_to_sf(struct ilo_3d_pipeline *p,
1541 const struct ilo_blitter *blitter,
1542 struct gen6_rectlist_session *session)
1544 gen6_3DSTATE_CONSTANT_VS(p->builder, NULL, NULL, 0);
1545 gen6_3DSTATE_VS(p->builder, NULL, 0);
1547 gen6_wa_pipe_control_vs_const_flush(p);
1549 gen6_3DSTATE_CONSTANT_GS(p->builder, NULL, NULL, 0);
1550 gen6_3DSTATE_GS(p->builder, NULL, NULL, 0);
1552 gen6_3DSTATE_CLIP(p->builder, NULL, NULL, false, 0);
1553 gen6_3DSTATE_SF(p->builder, NULL, NULL);
1557 gen6_rectlist_wm(struct ilo_3d_pipeline *p,
1558 const struct ilo_blitter *blitter,
1559 struct gen6_rectlist_session *session)
1563 switch (blitter->op) {
1564 case ILO_BLITTER_RECTLIST_CLEAR_ZS:
1565 hiz_op = GEN6_WM_DW4_DEPTH_CLEAR;
1567 case ILO_BLITTER_RECTLIST_RESOLVE_Z:
1568 hiz_op = GEN6_WM_DW4_DEPTH_RESOLVE;
1570 case ILO_BLITTER_RECTLIST_RESOLVE_HIZ:
1571 hiz_op = GEN6_WM_DW4_HIZ_RESOLVE;
1578 gen6_3DSTATE_CONSTANT_PS(p->builder, NULL, NULL, 0);
1580 gen6_wa_pipe_control_wm_max_threads_stall(p);
1581 gen6_3DSTATE_WM(p->builder, NULL, 0, NULL, false, false, hiz_op);
1585 gen6_rectlist_wm_depth(struct ilo_3d_pipeline *p,
1586 const struct ilo_blitter *blitter,
1587 struct gen6_rectlist_session *session)
1589 gen6_wa_pipe_control_wm_depth_flush(p);
1591 if (blitter->uses & (ILO_BLITTER_USE_FB_DEPTH |
1592 ILO_BLITTER_USE_FB_STENCIL)) {
1593 gen6_3DSTATE_DEPTH_BUFFER(p->builder,
1594 &blitter->fb.dst.u.zs);
1597 if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH) {
1598 gen6_3DSTATE_HIER_DEPTH_BUFFER(p->builder,
1599 &blitter->fb.dst.u.zs);
1602 if (blitter->uses & ILO_BLITTER_USE_FB_STENCIL) {
1603 gen6_3DSTATE_STENCIL_BUFFER(p->builder,
1604 &blitter->fb.dst.u.zs);
1607 gen6_3DSTATE_CLEAR_PARAMS(p->builder,
1608 blitter->depth_clear_value);
1612 gen6_rectlist_wm_multisample(struct ilo_3d_pipeline *p,
1613 const struct ilo_blitter *blitter,
1614 struct gen6_rectlist_session *session)
1616 const uint32_t *packed_sample_pos = (blitter->fb.num_samples > 1) ?
1617 &p->packed_sample_position_4x : &p->packed_sample_position_1x;
1619 gen6_wa_pipe_control_wm_multisample_flush(p);
1621 gen6_3DSTATE_MULTISAMPLE(p->builder, blitter->fb.num_samples,
1622 packed_sample_pos, true);
1624 gen6_3DSTATE_SAMPLE_MASK(p->builder,
1625 (1 << blitter->fb.num_samples) - 1);
1629 gen6_rectlist_commands(struct ilo_3d_pipeline *p,
1630 const struct ilo_blitter *blitter,
1631 struct gen6_rectlist_session *session)
1633 gen6_wa_pipe_control_post_sync(p, false);
1635 gen6_rectlist_wm_multisample(p, blitter, session);
1637 gen6_state_base_address(p->builder, true);
1639 gen6_3DSTATE_VERTEX_BUFFERS(p->builder,
1640 &blitter->ve, &blitter->vb);
1642 gen6_3DSTATE_VERTEX_ELEMENTS(p->builder,
1643 &blitter->ve, false, false);
1645 gen6_3DSTATE_URB(p->builder,
1646 p->dev->urb_size, 0, blitter->ve.count * 4 * sizeof(float), 0);
1647 /* 3DSTATE_URB workaround */
1648 if (p->state.gs.active) {
1649 ilo_3d_pipeline_emit_flush_gen6(p);
1650 p->state.gs.active = false;
1654 (ILO_BLITTER_USE_DSA | ILO_BLITTER_USE_CC)) {
1655 gen6_3DSTATE_CC_STATE_POINTERS(p->builder, 0,
1656 session->DEPTH_STENCIL_STATE, session->COLOR_CALC_STATE);
1659 gen6_rectlist_vs_to_sf(p, blitter, session);
1660 gen6_rectlist_wm(p, blitter, session);
1662 if (blitter->uses & ILO_BLITTER_USE_VIEWPORT) {
1663 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(p->builder,
1664 0, 0, session->CC_VIEWPORT);
1667 gen6_rectlist_wm_depth(p, blitter, session);
1669 gen6_3DSTATE_DRAWING_RECTANGLE(p->builder, 0, 0,
1670 blitter->fb.width, blitter->fb.height);
1672 gen6_3DPRIMITIVE(p->builder, &blitter->draw, NULL);
1676 gen6_rectlist_states(struct ilo_3d_pipeline *p,
1677 const struct ilo_blitter *blitter,
1678 struct gen6_rectlist_session *session)
1680 if (blitter->uses & ILO_BLITTER_USE_DSA) {
1681 session->DEPTH_STENCIL_STATE =
1682 gen6_DEPTH_STENCIL_STATE(p->builder, &blitter->dsa);
1685 if (blitter->uses & ILO_BLITTER_USE_CC) {
1686 session->COLOR_CALC_STATE =
1687 gen6_COLOR_CALC_STATE(p->builder, &blitter->cc.stencil_ref,
1688 blitter->cc.alpha_ref, &blitter->cc.blend_color);
1691 if (blitter->uses & ILO_BLITTER_USE_VIEWPORT) {
1692 session->CC_VIEWPORT =
1693 gen6_CC_VIEWPORT(p->builder, &blitter->viewport, 1);
1698 ilo_3d_pipeline_emit_rectlist_gen6(struct ilo_3d_pipeline *p,
1699 const struct ilo_blitter *blitter)
1701 struct gen6_rectlist_session session;
1703 memset(&session, 0, sizeof(session));
1704 gen6_rectlist_states(p, blitter, &session);
1705 gen6_rectlist_commands(p, blitter, &session);
1709 gen6_pipeline_max_command_size(const struct ilo_3d_pipeline *p)
1714 size += GEN6_3DSTATE_CONSTANT_ANY__SIZE * 3;
1715 size += GEN6_3DSTATE_GS_SVB_INDEX__SIZE * 4;
1716 size += GEN6_PIPE_CONTROL__SIZE * 5;
1719 GEN6_STATE_BASE_ADDRESS__SIZE +
1720 GEN6_STATE_SIP__SIZE +
1721 GEN6_3DSTATE_VF_STATISTICS__SIZE +
1722 GEN6_PIPELINE_SELECT__SIZE +
1723 GEN6_3DSTATE_BINDING_TABLE_POINTERS__SIZE +
1724 GEN6_3DSTATE_SAMPLER_STATE_POINTERS__SIZE +
1725 GEN6_3DSTATE_URB__SIZE +
1726 GEN6_3DSTATE_VERTEX_BUFFERS__SIZE +
1727 GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE +
1728 GEN6_3DSTATE_INDEX_BUFFER__SIZE +
1729 GEN6_3DSTATE_VIEWPORT_STATE_POINTERS__SIZE +
1730 GEN6_3DSTATE_CC_STATE_POINTERS__SIZE +
1731 GEN6_3DSTATE_SCISSOR_STATE_POINTERS__SIZE +
1732 GEN6_3DSTATE_VS__SIZE +
1733 GEN6_3DSTATE_GS__SIZE +
1734 GEN6_3DSTATE_CLIP__SIZE +
1735 GEN6_3DSTATE_SF__SIZE +
1736 GEN6_3DSTATE_WM__SIZE +
1737 GEN6_3DSTATE_SAMPLE_MASK__SIZE +
1738 GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE +
1739 GEN6_3DSTATE_DEPTH_BUFFER__SIZE +
1740 GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE +
1741 GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE +
1742 GEN6_3DSTATE_LINE_STIPPLE__SIZE +
1743 GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE +
1744 GEN6_3DSTATE_MULTISAMPLE__SIZE +
1745 GEN6_3DSTATE_STENCIL_BUFFER__SIZE +
1746 GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE +
1747 GEN6_3DSTATE_CLEAR_PARAMS__SIZE +
1748 GEN6_3DPRIMITIVE__SIZE;
1755 gen6_pipeline_estimate_state_size(const struct ilo_3d_pipeline *p,
1756 const struct ilo_state_vector *vec)
1758 static int static_size;
1762 /* 64 bytes, or 16 dwords */
1763 const int alignment = 64 / 4;
1766 size = alignment - 1;
1769 size += align(GEN6_BLEND_STATE__SIZE * ILO_MAX_DRAW_BUFFERS, alignment);
1770 size += align(GEN6_DEPTH_STENCIL_STATE__SIZE, alignment);
1771 size += align(GEN6_COLOR_CALC_STATE__SIZE, alignment);
1773 /* viewport arrays */
1774 if (ilo_dev_gen(p->dev) >= ILO_GEN(7)) {
1776 align(GEN7_SF_CLIP_VIEWPORT__SIZE * ILO_MAX_VIEWPORTS, 16) +
1777 align(GEN6_CC_VIEWPORT__SIZE * ILO_MAX_VIEWPORTS, 8) +
1778 align(GEN6_SCISSOR_RECT__SIZE * ILO_MAX_VIEWPORTS, 8);
1782 align(GEN6_SF_VIEWPORT__SIZE * ILO_MAX_VIEWPORTS, 8) +
1783 align(GEN6_CLIP_VIEWPORT__SIZE * ILO_MAX_VIEWPORTS, 8) +
1784 align(GEN6_CC_VIEWPORT__SIZE * ILO_MAX_VIEWPORTS, 8) +
1785 align(GEN6_SCISSOR_RECT__SIZE * ILO_MAX_VIEWPORTS, 8);
1793 for (sh_type = 0; sh_type < PIPE_SHADER_TYPES; sh_type++) {
1794 const int alignment = 32 / 4;
1795 int num_samplers, num_surfaces, pcb_size;
1798 num_samplers = vec->sampler[sh_type].count;
1800 /* sampler views and constant buffers */
1801 num_surfaces = vec->view[sh_type].count +
1802 util_bitcount(vec->cbuf[sh_type].enabled_mask);
1807 case PIPE_SHADER_VERTEX:
1809 if (ilo_dev_gen(p->dev) == ILO_GEN(6)) {
1810 const struct pipe_stream_output_info *so_info =
1811 ilo_shader_get_kernel_so_info(vec->vs);
1813 /* stream outputs */
1814 num_surfaces += so_info->num_outputs;
1817 pcb_size = ilo_shader_get_kernel_param(vec->vs,
1818 ILO_KERNEL_PCB_CBUF0_SIZE);
1819 pcb_size += ilo_shader_get_kernel_param(vec->vs,
1820 ILO_KERNEL_VS_PCB_UCP_SIZE);
1823 case PIPE_SHADER_GEOMETRY:
1824 if (vec->gs && ilo_dev_gen(p->dev) == ILO_GEN(6)) {
1825 const struct pipe_stream_output_info *so_info =
1826 ilo_shader_get_kernel_so_info(vec->gs);
1828 /* stream outputs */
1829 num_surfaces += so_info->num_outputs;
1832 case PIPE_SHADER_FRAGMENT:
1833 /* render targets */
1834 num_surfaces += vec->fb.state.nr_cbufs;
1837 pcb_size = ilo_shader_get_kernel_param(vec->fs,
1838 ILO_KERNEL_PCB_CBUF0_SIZE);
1845 /* SAMPLER_STATE array and SAMPLER_BORDER_COLORs */
1847 size += align(GEN6_SAMPLER_STATE__SIZE * num_samplers, alignment) +
1848 align(GEN6_SAMPLER_BORDER_COLOR__SIZE, alignment) * num_samplers;
1851 /* BINDING_TABLE_STATE and SURFACE_STATEs */
1853 size += align(num_surfaces, alignment) +
1854 align(GEN6_SURFACE_STATE__SIZE, alignment) * num_surfaces;
1859 size += align(pcb_size, alignment);
1866 gen6_pipeline_estimate_query_size(const struct ilo_3d_pipeline *p,
1867 const struct ilo_query *q)
1871 ILO_DEV_ASSERT(p->dev, 6, 7.5);
1874 case PIPE_QUERY_OCCLUSION_COUNTER:
1875 size = GEN6_PIPE_CONTROL__SIZE;
1876 if (ilo_dev_gen(p->dev) == ILO_GEN(6))
1879 case PIPE_QUERY_TIMESTAMP:
1880 case PIPE_QUERY_TIME_ELAPSED:
1881 size = GEN6_PIPE_CONTROL__SIZE;
1882 if (ilo_dev_gen(p->dev) == ILO_GEN(6))
1885 case PIPE_QUERY_PRIMITIVES_GENERATED:
1886 case PIPE_QUERY_PRIMITIVES_EMITTED:
1887 size = GEN6_PIPE_CONTROL__SIZE;
1888 if (ilo_dev_gen(p->dev) == ILO_GEN(6))
1891 size += GEN6_MI_STORE_REGISTER_MEM__SIZE * 2;
1893 case PIPE_QUERY_PIPELINE_STATISTICS:
1894 if (ilo_dev_gen(p->dev) >= ILO_GEN(7)) {
1895 const int num_regs = 10;
1896 const int num_pads = 1;
1898 size = GEN6_PIPE_CONTROL__SIZE +
1899 GEN6_MI_STORE_REGISTER_MEM__SIZE * 2 * num_regs +
1900 GEN6_MI_STORE_DATA_IMM__SIZE * num_pads;
1902 const int num_regs = 8;
1903 const int num_pads = 3;
1905 size = GEN6_PIPE_CONTROL__SIZE * 3 +
1906 GEN6_MI_STORE_REGISTER_MEM__SIZE * 2 * num_regs +
1907 GEN6_MI_STORE_DATA_IMM__SIZE * num_pads;
1919 ilo_3d_pipeline_estimate_size_gen6(struct ilo_3d_pipeline *p,
1920 enum ilo_3d_pipeline_action action,
1926 case ILO_3D_PIPELINE_DRAW:
1928 const struct ilo_state_vector *ilo = arg;
1930 size = gen6_pipeline_max_command_size(p) +
1931 gen6_pipeline_estimate_state_size(p, ilo);
1934 case ILO_3D_PIPELINE_FLUSH:
1935 size = GEN6_PIPE_CONTROL__SIZE * 3;
1937 case ILO_3D_PIPELINE_QUERY:
1938 size = gen6_pipeline_estimate_query_size(p,
1939 (const struct ilo_query *) arg);
1941 case ILO_3D_PIPELINE_RECTLIST:
1942 size = 64 + 256; /* states + commands */
1945 assert(!"unknown 3D pipeline action");
1954 ilo_3d_pipeline_init_gen6(struct ilo_3d_pipeline *p)
1956 p->estimate_size = ilo_3d_pipeline_estimate_size_gen6;
1957 p->emit_draw = ilo_3d_pipeline_emit_draw_gen6;
1958 p->emit_flush = ilo_3d_pipeline_emit_flush_gen6;
1959 p->emit_query = ilo_3d_pipeline_emit_query_gen6;
1960 p->emit_rectlist = ilo_3d_pipeline_emit_rectlist_gen6;