src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "util/u_dual_blend.h"
  29 #include "util/u_prim.h"
  30 #include "intel_reg.h"
  31
  32 #include "ilo_context.h"
  33 #include "ilo_cp.h"
  34 #include "ilo_gpe_gen6.h"
  35 #include "ilo_shader.h"
  36 #include "ilo_state.h"
  37 #include "ilo_3d_pipeline.h"
  38 #include "ilo_3d_pipeline_gen6.h"
  39
  40 /**
  41  * This should be called before any depth stall flush (including those
  42  * produced by non-pipelined state commands) or cache flush on GEN6.
  43  *
  44  * \see intel_emit_post_sync_nonzero_flush()
  45  */
  46 static void
  47 gen6_wa_pipe_control_post_sync(struct ilo_3d_pipeline *p,
  48                                bool caller_post_sync)
  49 {
  50    assert(p->dev->gen == ILO_GEN(6));
  51
  52    /* emit once */
  53    if (p->state.has_gen6_wa_pipe_control)
  54       return;
  55
  56    p->state.has_gen6_wa_pipe_control = true;
  57
  58    /*
  59     * From the Sandy Bridge PRM, volume 2 part 1, page 60:
  60     *
  61     *     "Pipe-control with CS-stall bit set must be sent BEFORE the
  62     *      pipe-control with a post-sync op and no write-cache flushes."
  63     *
  64     * The workaround below necessitates this workaround.
  65     */
  66    p->gen6_PIPE_CONTROL(p->dev,
  67          PIPE_CONTROL_CS_STALL |
  68          PIPE_CONTROL_STALL_AT_SCOREBOARD,
  69          NULL, 0, false, p->cp);
  70
  71    /* the caller will emit the post-sync op */
  72    if (caller_post_sync)
  73       return;
  74
  75    /*
  76     * From the Sandy Bridge PRM, volume 2 part 1, page 60:
  77     *
  78     *     "Before any depth stall flush (including those produced by
  79     *      non-pipelined state commands), software needs to first send a
  80     *      PIPE_CONTROL with no bits set except Post-Sync Operation != 0."
  81     *
  82     *     "Before a PIPE_CONTROL with Write Cache Flush Enable =1, a
  83     *      PIPE_CONTROL with any non-zero post-sync-op is required."
  84     */
  85    p->gen6_PIPE_CONTROL(p->dev,
  86          PIPE_CONTROL_WRITE_IMMEDIATE,
  87          p->workaround_bo, 0, false, p->cp);
  88 }
  89
  90 static void
  91 gen6_wa_pipe_control_wm_multisample_flush(struct ilo_3d_pipeline *p)
  92 {
  93    assert(p->dev->gen == ILO_GEN(6));
  94
  95    gen6_wa_pipe_control_post_sync(p, false);
  96
  97    /*
  98     * From the Sandy Bridge PRM, volume 2 part 1, page 305:
  99     *
 100     *     "Driver must guarentee that all the caches in the depth pipe are
 101     *      flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
 102     *      requires driver to send a PIPE_CONTROL with a CS stall along with a
 103     *      Depth Flush prior to this command."
 104     */
 105    p->gen6_PIPE_CONTROL(p->dev,
 106          PIPE_CONTROL_DEPTH_CACHE_FLUSH |
 107          PIPE_CONTROL_CS_STALL,
 108          0, 0, false, p->cp);
 109 }
 110
 111 static void
 112 gen6_wa_pipe_control_wm_depth_flush(struct ilo_3d_pipeline *p)
 113 {
 114    assert(p->dev->gen == ILO_GEN(6));
 115
 116    gen6_wa_pipe_control_post_sync(p, false);
 117
 118    /*
 119     * According to intel_emit_depth_stall_flushes() of classic i965, we need
 120     * to emit a sequence of PIPE_CONTROLs prior to emitting depth related
 121     * commands.
 122     */
 123    p->gen6_PIPE_CONTROL(p->dev,
 124          PIPE_CONTROL_DEPTH_STALL,
 125          NULL, 0, false, p->cp);
 126
 127    p->gen6_PIPE_CONTROL(p->dev,
 128          PIPE_CONTROL_DEPTH_CACHE_FLUSH,
 129          NULL, 0, false, p->cp);
 130
 131    p->gen6_PIPE_CONTROL(p->dev,
 132          PIPE_CONTROL_DEPTH_STALL,
 133          NULL, 0, false, p->cp);
 134 }
 135
 136 static void
 137 gen6_wa_pipe_control_wm_max_threads_stall(struct ilo_3d_pipeline *p)
 138 {
 139    assert(p->dev->gen == ILO_GEN(6));
 140
 141    /* the post-sync workaround should cover this already */
 142    if (p->state.has_gen6_wa_pipe_control)
 143       return;
 144
 145    /*
 146     * From the Sandy Bridge PRM, volume 2 part 1, page 274:
 147     *
 148     *     "A PIPE_CONTROL command, with only the Stall At Pixel Scoreboard
 149     *      field set (DW1 Bit 1), must be issued prior to any change to the
 150     *      value in this field (Maximum Number of Threads in 3DSTATE_WM)"
 151     */
 152    p->gen6_PIPE_CONTROL(p->dev,
 153          PIPE_CONTROL_STALL_AT_SCOREBOARD,
 154          NULL, 0, false, p->cp);
 155
 156 }
 157
 158 static void
 159 gen6_wa_pipe_control_vs_const_flush(struct ilo_3d_pipeline *p)
 160 {
 161    assert(p->dev->gen == ILO_GEN(6));
 162
 163    gen6_wa_pipe_control_post_sync(p, false);
 164
 165    /*
 166     * According to upload_vs_state() of classic i965, we need to emit
 167     * PIPE_CONTROL after 3DSTATE_CONSTANT_VS so that the command is kept being
 168     * buffered by VS FF, to the point that the FF dies.
 169     */
 170    p->gen6_PIPE_CONTROL(p->dev,
 171          PIPE_CONTROL_DEPTH_STALL |
 172          PIPE_CONTROL_INSTRUCTION_FLUSH |
 173          PIPE_CONTROL_STATE_CACHE_INVALIDATE,
 174          NULL, 0, false, p->cp);
 175 }
 176
 177 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
 178
 179 void
 180 gen6_pipeline_common_select(struct ilo_3d_pipeline *p,
 181                             const struct ilo_context *ilo,
 182                             struct gen6_pipeline_session *session)
 183 {
 184    /* PIPELINE_SELECT */
 185    if (session->hw_ctx_changed) {
 186       if (p->dev->gen == ILO_GEN(6))
 187          gen6_wa_pipe_control_post_sync(p, false);
 188
 189       p->gen6_PIPELINE_SELECT(p->dev, 0x0, p->cp);
 190    }
 191 }
 192
 193 void
 194 gen6_pipeline_common_sip(struct ilo_3d_pipeline *p,
 195                          const struct ilo_context *ilo,
 196                          struct gen6_pipeline_session *session)
 197 {
 198    /* STATE_SIP */
 199    if (session->hw_ctx_changed) {
 200       if (p->dev->gen == ILO_GEN(6))
 201          gen6_wa_pipe_control_post_sync(p, false);
 202
 203       p->gen6_STATE_SIP(p->dev, 0, p->cp);
 204    }
 205 }
 206
 207 void
 208 gen6_pipeline_common_base_address(struct ilo_3d_pipeline *p,
 209                                   const struct ilo_context *ilo,
 210                                   struct gen6_pipeline_session *session)
 211 {
 212    /* STATE_BASE_ADDRESS */
 213    if (session->state_bo_changed || session->instruction_bo_changed) {
 214       if (p->dev->gen == ILO_GEN(6))
 215          gen6_wa_pipe_control_post_sync(p, false);
 216
 217       p->gen6_STATE_BASE_ADDRESS(p->dev,
 218             NULL, p->cp->bo, p->cp->bo, NULL, ilo->shader_cache->bo,
 219             0, 0, 0, 0, p->cp);
 220
 221       /*
 222        * From the Sandy Bridge PRM, volume 1 part 1, page 28:
 223        *
 224        *     "The following commands must be reissued following any change to
 225        *      the base addresses:
 226        *
 227        *       * 3DSTATE_BINDING_TABLE_POINTERS
 228        *       * 3DSTATE_SAMPLER_STATE_POINTERS
 229        *       * 3DSTATE_VIEWPORT_STATE_POINTERS
 230        *       * 3DSTATE_CC_POINTERS
 231        *       * MEDIA_STATE_POINTERS"
 232        *
 233        * 3DSTATE_SCISSOR_STATE_POINTERS is not on the list, but it is
 234        * reasonable to also reissue the command.  Same to PCB.
 235        */
 236       session->viewport_state_changed = true;
 237
 238       session->cc_state_blend_changed = true;
 239       session->cc_state_dsa_changed = true;
 240       session->cc_state_cc_changed = true;
 241
 242       session->scissor_state_changed = true;
 243
 244       session->binding_table_vs_changed = true;
 245       session->binding_table_gs_changed = true;
 246       session->binding_table_fs_changed = true;
 247
 248       session->sampler_state_vs_changed = true;
 249       session->sampler_state_gs_changed = true;
 250       session->sampler_state_fs_changed = true;
 251
 252       session->pcb_state_vs_changed = true;
 253       session->pcb_state_gs_changed = true;
 254       session->pcb_state_fs_changed = true;
 255    }
 256 }
 257
 258 static void
 259 gen6_pipeline_common_urb(struct ilo_3d_pipeline *p,
 260                          const struct ilo_context *ilo,
 261                          struct gen6_pipeline_session *session)
 262 {
 263    /* 3DSTATE_URB */
 264    if (DIRTY(VERTEX_ELEMENTS) || DIRTY(VS) || DIRTY(GS)) {
 265       const struct ilo_shader *vs = (ilo->vs) ? ilo->vs->shader : NULL;
 266       const struct ilo_shader *gs = (ilo->gs) ? ilo->gs->shader : NULL;
 267       const bool gs_active = (gs || (vs && vs->stream_output));
 268       int vs_entry_size, gs_entry_size;
 269       int vs_total_size, gs_total_size;
 270
 271       vs_entry_size = (vs) ? vs->out.count : 0;
 272
 273       /*
 274        * As indicated by 2e712e41db0c0676e9f30fc73172c0e8de8d84d4, VF and VS
 275        * share VUE handles.  The VUE allocation size must be large enough to
 276        * store either VF outputs (number of VERTEX_ELEMENTs) and VS outputs.
 277        *
 278        * I am not sure if the PRM explicitly states that VF and VS share VUE
 279        * handles.  But here is a citation that implies so:
 280        *
 281        * From the Sandy Bridge PRM, volume 2 part 1, page 44:
 282        *
 283        *     "Once a FF stage that spawn threads has sufficient input to
 284        *      initiate a thread, it must guarantee that it is safe to request
 285        *      the thread initiation. For all these FF stages, this check is
 286        *      based on :
 287        *
 288        *      - The availability of output URB entries:
 289        *        - VS: As the input URB entries are overwritten with the
 290        *          VS-generated output data, output URB availability isn't a
 291        *          factor."
 292        */
 293       if (vs_entry_size < ilo->ve->count)
 294          vs_entry_size = ilo->ve->count;
 295
 296       gs_entry_size = (gs) ? gs->out.count :
 297          (vs && vs->stream_output) ? vs_entry_size : 0;
 298
 299       /* in bytes */
 300       vs_entry_size *= sizeof(float) * 4;
 301       gs_entry_size *= sizeof(float) * 4;
 302       vs_total_size = ilo->dev->urb_size;
 303
 304       if (gs_active) {
 305          vs_total_size /= 2;
 306          gs_total_size = vs_total_size;
 307       }
 308       else {
 309          gs_total_size = 0;
 310       }
 311
 312       p->gen6_3DSTATE_URB(p->dev, vs_total_size, gs_total_size,
 313             vs_entry_size, gs_entry_size, p->cp);
 314
 315       /*
 316        * From the Sandy Bridge PRM, volume 2 part 1, page 27:
 317        *
 318        *     "Because of a urb corruption caused by allocating a previous
 319        *      gsunit's urb entry to vsunit software is required to send a
 320        *      "GS NULL Fence" (Send URB fence with VS URB size == 1 and GS URB
 321        *      size == 0) plus a dummy DRAW call before any case where VS will
 322        *      be taking over GS URB space."
 323        */
 324       if (p->state.gs.active && !gs_active)
 325          ilo_3d_pipeline_emit_flush_gen6(p);
 326
 327       p->state.gs.active = gs_active;
 328    }
 329 }
 330
 331 static void
 332 gen6_pipeline_common_pointers_1(struct ilo_3d_pipeline *p,
 333                                 const struct ilo_context *ilo,
 334                                 struct gen6_pipeline_session *session)
 335 {
 336    /* 3DSTATE_VIEWPORT_STATE_POINTERS */
 337    if (session->viewport_state_changed) {
 338       p->gen6_3DSTATE_VIEWPORT_STATE_POINTERS(p->dev,
 339             p->state.CLIP_VIEWPORT,
 340             p->state.SF_VIEWPORT,
 341             p->state.CC_VIEWPORT, p->cp);
 342    }
 343 }
 344
 345 static void
 346 gen6_pipeline_common_pointers_2(struct ilo_3d_pipeline *p,
 347                                 const struct ilo_context *ilo,
 348                                 struct gen6_pipeline_session *session)
 349 {
 350    /* 3DSTATE_CC_STATE_POINTERS */
 351    if (session->cc_state_blend_changed ||
 352        session->cc_state_dsa_changed ||
 353        session->cc_state_cc_changed) {
 354       p->gen6_3DSTATE_CC_STATE_POINTERS(p->dev,
 355             p->state.BLEND_STATE,
 356             p->state.DEPTH_STENCIL_STATE,
 357             p->state.COLOR_CALC_STATE, p->cp);
 358    }
 359
 360    /* 3DSTATE_SAMPLER_STATE_POINTERS */
 361    if (session->sampler_state_vs_changed ||
 362        session->sampler_state_gs_changed ||
 363        session->sampler_state_fs_changed) {
 364       p->gen6_3DSTATE_SAMPLER_STATE_POINTERS(p->dev,
 365             p->state.vs.SAMPLER_STATE,
 366             0,
 367             p->state.wm.SAMPLER_STATE, p->cp);
 368    }
 369 }
 370
 371 static void
 372 gen6_pipeline_common_pointers_3(struct ilo_3d_pipeline *p,
 373                                 const struct ilo_context *ilo,
 374                                 struct gen6_pipeline_session *session)
 375 {
 376    /* 3DSTATE_SCISSOR_STATE_POINTERS */
 377    if (session->scissor_state_changed) {
 378       p->gen6_3DSTATE_SCISSOR_STATE_POINTERS(p->dev,
 379             p->state.SCISSOR_RECT, p->cp);
 380    }
 381
 382    /* 3DSTATE_BINDING_TABLE_POINTERS */
 383    if (session->binding_table_vs_changed ||
 384        session->binding_table_gs_changed ||
 385        session->binding_table_fs_changed) {
 386       p->gen6_3DSTATE_BINDING_TABLE_POINTERS(p->dev,
 387             p->state.vs.BINDING_TABLE_STATE,
 388             p->state.gs.BINDING_TABLE_STATE,
 389             p->state.wm.BINDING_TABLE_STATE, p->cp);
 390    }
 391 }
 392
 393 void
 394 gen6_pipeline_vf(struct ilo_3d_pipeline *p,
 395                  const struct ilo_context *ilo,
 396                  struct gen6_pipeline_session *session)
 397 {
 398    /* 3DSTATE_INDEX_BUFFER */
 399    if (DIRTY(INDEX_BUFFER)) {
 400       p->gen6_3DSTATE_INDEX_BUFFER(p->dev,
 401             &ilo->ib.state, session->info->primitive_restart, p->cp);
 402    }
 403
 404    /* 3DSTATE_VERTEX_BUFFERS */
 405    if (DIRTY(VERTEX_BUFFERS) || DIRTY(VERTEX_ELEMENTS)) {
 406       p->gen6_3DSTATE_VERTEX_BUFFERS(p->dev,
 407             ilo->vb.states, ilo->vb.enabled_mask, ilo->ve, p->cp);
 408    }
 409
 410    /* 3DSTATE_VERTEX_ELEMENTS */
 411    if (DIRTY(VERTEX_ELEMENTS) || DIRTY(VS)) {
 412       const struct ilo_ve_state *ve = ilo->ve;
 413       bool last_velement_edgeflag = false;
 414       bool prepend_generate_ids = false;
 415
 416       if (ilo->vs) {
 417          const struct ilo_shader_info *info = &ilo->vs->info;
 418
 419          if (info->edgeflag_in >= 0) {
 420             /* we rely on the state tracker here */
 421             assert(info->edgeflag_in == ve->count - 1);
 422             last_velement_edgeflag = true;
 423          }
 424
 425          prepend_generate_ids = (info->has_instanceid || info->has_vertexid);
 426       }
 427
 428       p->gen6_3DSTATE_VERTEX_ELEMENTS(p->dev, ve,
 429             last_velement_edgeflag, prepend_generate_ids, p->cp);
 430    }
 431 }
 432
 433 void
 434 gen6_pipeline_vf_statistics(struct ilo_3d_pipeline *p,
 435                             const struct ilo_context *ilo,
 436                             struct gen6_pipeline_session *session)
 437 {
 438    /* 3DSTATE_VF_STATISTICS */
 439    if (session->hw_ctx_changed)
 440       p->gen6_3DSTATE_VF_STATISTICS(p->dev, false, p->cp);
 441 }
 442
 443 void
 444 gen6_pipeline_vf_draw(struct ilo_3d_pipeline *p,
 445                       const struct ilo_context *ilo,
 446                       struct gen6_pipeline_session *session)
 447 {
 448    /* 3DPRIMITIVE */
 449    p->gen6_3DPRIMITIVE(p->dev, session->info, false, p->cp);
 450    p->state.has_gen6_wa_pipe_control = false;
 451 }
 452
 453 void
 454 gen6_pipeline_vs(struct ilo_3d_pipeline *p,
 455                  const struct ilo_context *ilo,
 456                  struct gen6_pipeline_session *session)
 457 {
 458    const bool emit_3dstate_vs = (DIRTY(VS) || DIRTY(VERTEX_SAMPLERS));
 459    const bool emit_3dstate_constant_vs = session->pcb_state_vs_changed;
 460
 461    /*
 462     * the classic i965 does this in upload_vs_state(), citing a spec that I
 463     * cannot find
 464     */
 465    if (emit_3dstate_vs && p->dev->gen == ILO_GEN(6))
 466       gen6_wa_pipe_control_post_sync(p, false);
 467
 468    /* 3DSTATE_CONSTANT_VS */
 469    if (emit_3dstate_constant_vs) {
 470       p->gen6_3DSTATE_CONSTANT_VS(p->dev,
 471             &p->state.vs.PUSH_CONSTANT_BUFFER,
 472             &p->state.vs.PUSH_CONSTANT_BUFFER_size,
 473             1, p->cp);
 474    }
 475
 476    /* 3DSTATE_VS */
 477    if (emit_3dstate_vs) {
 478       const struct ilo_shader *vs = (ilo->vs)? ilo->vs->shader : NULL;
 479       const int num_samplers = ilo->sampler[PIPE_SHADER_VERTEX].count;
 480
 481       p->gen6_3DSTATE_VS(p->dev, vs, num_samplers, p->cp);
 482    }
 483
 484    if (emit_3dstate_constant_vs && p->dev->gen == ILO_GEN(6))
 485       gen6_wa_pipe_control_vs_const_flush(p);
 486 }
 487
 488 static void
 489 gen6_pipeline_gs(struct ilo_3d_pipeline *p,
 490                  const struct ilo_context *ilo,
 491                  struct gen6_pipeline_session *session)
 492 {
 493    /* 3DSTATE_CONSTANT_GS */
 494    if (session->pcb_state_gs_changed)
 495       p->gen6_3DSTATE_CONSTANT_GS(p->dev, NULL, NULL, 0, p->cp);
 496
 497    /* 3DSTATE_GS */
 498    if (DIRTY(GS) || DIRTY(VS) || session->prim_changed) {
 499       const struct ilo_shader *gs = (ilo->gs)? ilo->gs->shader : NULL;
 500       const struct ilo_shader *vs = (ilo->vs)? ilo->vs->shader : NULL;
 501       const int num_vertices = u_vertices_per_prim(session->reduced_prim);
 502
 503       if (gs)
 504          assert(!gs->pcb.clip_state_size);
 505
 506       p->gen6_3DSTATE_GS(p->dev, gs, vs,
 507             (vs) ? vs->cache_offset + vs->gs_offsets[num_vertices - 1] : 0,
 508             p->cp);
 509    }
 510 }
 511
 512 bool
 513 gen6_pipeline_update_max_svbi(struct ilo_3d_pipeline *p,
 514                               const struct ilo_context *ilo,
 515                               struct gen6_pipeline_session *session)
 516 {
 517    if (DIRTY(VS) || DIRTY(GS) || DIRTY(STREAM_OUTPUT_TARGETS)) {
 518       const struct pipe_stream_output_info *so_info =
 519          (ilo->gs) ? &ilo->gs->info.stream_output :
 520          (ilo->vs) ? &ilo->vs->info.stream_output : NULL;
 521       unsigned max_svbi = 0xffffffff;
 522       int i;
 523
 524       for (i = 0; i < so_info->num_outputs; i++) {
 525          const int output_buffer = so_info->output[i].output_buffer;
 526          const struct pipe_stream_output_target *so =
 527             ilo->so.states[output_buffer];
 528          const int struct_size = so_info->stride[output_buffer] * 4;
 529          const int elem_size = so_info->output[i].num_components * 4;
 530          int buf_size, count;
 531
 532          if (!so) {
 533             max_svbi = 0;
 534             break;
 535          }
 536
 537          buf_size = so->buffer_size - so_info->output[i].dst_offset * 4;
 538
 539          count = buf_size / struct_size;
 540          if (buf_size % struct_size >= elem_size)
 541             count++;
 542
 543          if (count < max_svbi)
 544             max_svbi = count;
 545       }
 546
 547       if (p->state.so_max_vertices != max_svbi) {
 548          p->state.so_max_vertices = max_svbi;
 549          return true;
 550       }
 551    }
 552
 553    return false;
 554 }
 555
 556 static void
 557 gen6_pipeline_gs_svbi(struct ilo_3d_pipeline *p,
 558                       const struct ilo_context *ilo,
 559                       struct gen6_pipeline_session *session)
 560 {
 561    const bool emit = gen6_pipeline_update_max_svbi(p, ilo, session);
 562
 563    /* 3DSTATE_GS_SVB_INDEX */
 564    if (emit) {
 565       if (p->dev->gen == ILO_GEN(6))
 566          gen6_wa_pipe_control_post_sync(p, false);
 567
 568       p->gen6_3DSTATE_GS_SVB_INDEX(p->dev,
 569             0, p->state.so_num_vertices, p->state.so_max_vertices,
 570             false, p->cp);
 571
 572       if (session->hw_ctx_changed) {
 573          int i;
 574
 575          /*
 576           * From the Sandy Bridge PRM, volume 2 part 1, page 148:
 577           *
 578           *     "If a buffer is not enabled then the SVBI must be set to 0x0
 579           *      in order to not cause overflow in that SVBI."
 580           *
 581           *     "If a buffer is not enabled then the MaxSVBI must be set to
 582           *      0xFFFFFFFF in order to not cause overflow in that SVBI."
 583           */
 584          for (i = 1; i < 4; i++) {
 585             p->gen6_3DSTATE_GS_SVB_INDEX(p->dev,
 586                   i, 0, 0xffffffff, false, p->cp);
 587          }
 588       }
 589    }
 590 }
 591
 592 void
 593 gen6_pipeline_clip(struct ilo_3d_pipeline *p,
 594                    const struct ilo_context *ilo,
 595                    struct gen6_pipeline_session *session)
 596 {
 597    /* 3DSTATE_CLIP */
 598    if (DIRTY(RASTERIZER) || DIRTY(FS) ||
 599        DIRTY(VIEWPORT) || DIRTY(FRAMEBUFFER)) {
 600       bool enable_guardband = true;
 601       unsigned i;
 602
 603       /*
 604        * We do not do 2D clipping yet.  Guard band test should only be enabled
 605        * when the viewport is larger than the framebuffer.
 606        */
 607       for (i = 0; i < ilo->viewport.count; i++) {
 608          const struct ilo_viewport_cso *vp = &ilo->viewport.cso[i];
 609
 610          if (vp->min_x > 0.0f || vp->max_x < ilo->fb.state.width ||
 611              vp->min_y > 0.0f || vp->max_y < ilo->fb.state.height) {
 612             enable_guardband = false;
 613             break;
 614          }
 615       }
 616
 617       p->gen6_3DSTATE_CLIP(p->dev,
 618             &ilo->rasterizer->state,
 619             (ilo->fs && ilo->fs->shader->in.has_linear_interp),
 620             enable_guardband, 1, p->cp);
 621    }
 622 }
 623
 624 static void
 625 gen6_pipeline_sf(struct ilo_3d_pipeline *p,
 626                  const struct ilo_context *ilo,
 627                  struct gen6_pipeline_session *session)
 628 {
 629    /* 3DSTATE_SF */
 630    if (DIRTY(RASTERIZER) || DIRTY(VS) || DIRTY(GS) || DIRTY(FS)) {
 631       const struct ilo_shader *fs = (ilo->fs)? ilo->fs->shader : NULL;
 632       const struct ilo_shader *last_sh =
 633          (ilo->gs)? ilo->gs->shader :
 634          (ilo->vs)? ilo->vs->shader : NULL;
 635
 636       p->gen6_3DSTATE_SF(p->dev,
 637             &ilo->rasterizer->state, fs, last_sh, p->cp);
 638    }
 639 }
 640
 641 void
 642 gen6_pipeline_sf_rect(struct ilo_3d_pipeline *p,
 643                       const struct ilo_context *ilo,
 644                       struct gen6_pipeline_session *session)
 645 {
 646    /* 3DSTATE_DRAWING_RECTANGLE */
 647    if (DIRTY(FRAMEBUFFER)) {
 648       if (p->dev->gen == ILO_GEN(6))
 649          gen6_wa_pipe_control_post_sync(p, false);
 650
 651       p->gen6_3DSTATE_DRAWING_RECTANGLE(p->dev, 0, 0,
 652             ilo->fb.state.width, ilo->fb.state.height, p->cp);
 653    }
 654 }
 655
 656 static void
 657 gen6_pipeline_wm(struct ilo_3d_pipeline *p,
 658                  const struct ilo_context *ilo,
 659                  struct gen6_pipeline_session *session)
 660 {
 661    /* 3DSTATE_CONSTANT_PS */
 662    if (session->pcb_state_fs_changed)
 663       p->gen6_3DSTATE_CONSTANT_PS(p->dev, NULL, NULL, 0, p->cp);
 664
 665    /* 3DSTATE_WM */
 666    if (DIRTY(FS) || DIRTY(FRAGMENT_SAMPLERS) ||
 667        DIRTY(BLEND) || DIRTY(DEPTH_STENCIL_ALPHA) ||
 668        DIRTY(RASTERIZER)) {
 669       const struct ilo_shader *fs = (ilo->fs)? ilo->fs->shader : NULL;
 670       const int num_samplers = ilo->sampler[PIPE_SHADER_FRAGMENT].count;
 671       const bool dual_blend = ilo->blend->dual_blend;
 672       const bool cc_may_kill = (ilo->dsa->alpha.enabled ||
 673                                 ilo->blend->alpha_to_coverage);
 674
 675       if (fs)
 676          assert(!fs->pcb.clip_state_size);
 677
 678       if (p->dev->gen == ILO_GEN(6) && session->hw_ctx_changed)
 679          gen6_wa_pipe_control_wm_max_threads_stall(p);
 680
 681       p->gen6_3DSTATE_WM(p->dev, fs, num_samplers,
 682             &ilo->rasterizer->state, dual_blend, cc_may_kill, p->cp);
 683    }
 684 }
 685
 686 static void
 687 gen6_pipeline_wm_multisample(struct ilo_3d_pipeline *p,
 688                              const struct ilo_context *ilo,
 689                              struct gen6_pipeline_session *session)
 690 {
 691    /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
 692    if (DIRTY(SAMPLE_MASK) || DIRTY(FRAMEBUFFER)) {
 693       const uint32_t *packed_sample_pos;
 694
 695       packed_sample_pos = (ilo->fb.num_samples > 1) ?
 696          &p->packed_sample_position_4x : &p->packed_sample_position_1x;
 697
 698       if (p->dev->gen == ILO_GEN(6)) {
 699          gen6_wa_pipe_control_post_sync(p, false);
 700          gen6_wa_pipe_control_wm_multisample_flush(p);
 701       }
 702
 703       p->gen6_3DSTATE_MULTISAMPLE(p->dev,
 704             ilo->fb.num_samples, packed_sample_pos,
 705             ilo->rasterizer->state.half_pixel_center, p->cp);
 706
 707       p->gen6_3DSTATE_SAMPLE_MASK(p->dev,
 708             (ilo->fb.num_samples > 1) ? ilo->sample_mask : 0x1, p->cp);
 709    }
 710 }
 711
 712 static void
 713 gen6_pipeline_wm_depth(struct ilo_3d_pipeline *p,
 714                        const struct ilo_context *ilo,
 715                        struct gen6_pipeline_session *session)
 716 {
 717    /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
 718    if (DIRTY(FRAMEBUFFER)) {
 719       if (p->dev->gen == ILO_GEN(6)) {
 720          gen6_wa_pipe_control_post_sync(p, false);
 721          gen6_wa_pipe_control_wm_depth_flush(p);
 722       }
 723
 724       p->gen6_3DSTATE_DEPTH_BUFFER(p->dev, ilo->fb.state.zsbuf, p->cp);
 725
 726       /* TODO */
 727       p->gen6_3DSTATE_CLEAR_PARAMS(p->dev, 0, p->cp);
 728    }
 729 }
 730
 731 void
 732 gen6_pipeline_wm_raster(struct ilo_3d_pipeline *p,
 733                         const struct ilo_context *ilo,
 734                         struct gen6_pipeline_session *session)
 735 {
 736    /* 3DSTATE_POLY_STIPPLE_PATTERN and 3DSTATE_POLY_STIPPLE_OFFSET */
 737    if ((DIRTY(RASTERIZER) || DIRTY(POLY_STIPPLE)) &&
 738        ilo->rasterizer->state.poly_stipple_enable) {
 739       if (p->dev->gen == ILO_GEN(6))
 740          gen6_wa_pipe_control_post_sync(p, false);
 741
 742       p->gen6_3DSTATE_POLY_STIPPLE_PATTERN(p->dev,
 743             &ilo->poly_stipple, p->cp);
 744
 745       p->gen6_3DSTATE_POLY_STIPPLE_OFFSET(p->dev, 0, 0, p->cp);
 746    }
 747
 748    /* 3DSTATE_LINE_STIPPLE */
 749    if (DIRTY(RASTERIZER) && ilo->rasterizer->state.line_stipple_enable) {
 750       if (p->dev->gen == ILO_GEN(6))
 751          gen6_wa_pipe_control_post_sync(p, false);
 752
 753       p->gen6_3DSTATE_LINE_STIPPLE(p->dev,
 754             ilo->rasterizer->state.line_stipple_pattern,
 755             ilo->rasterizer->state.line_stipple_factor + 1, p->cp);
 756    }
 757
 758    /* 3DSTATE_AA_LINE_PARAMETERS */
 759    if (DIRTY(RASTERIZER) && ilo->rasterizer->state.line_smooth) {
 760       if (p->dev->gen == ILO_GEN(6))
 761          gen6_wa_pipe_control_post_sync(p, false);
 762
 763       p->gen6_3DSTATE_AA_LINE_PARAMETERS(p->dev, p->cp);
 764    }
 765 }
 766
 767 static void
 768 gen6_pipeline_state_viewports(struct ilo_3d_pipeline *p,
 769                               const struct ilo_context *ilo,
 770                               struct gen6_pipeline_session *session)
 771 {
 772    /* SF_CLIP_VIEWPORT and CC_VIEWPORT */
 773    if (p->dev->gen >= ILO_GEN(7) && DIRTY(VIEWPORT)) {
 774       p->state.SF_CLIP_VIEWPORT = p->gen7_SF_CLIP_VIEWPORT(p->dev,
 775             ilo->viewport.cso, ilo->viewport.count, p->cp);
 776
 777       p->state.CC_VIEWPORT = p->gen6_CC_VIEWPORT(p->dev,
 778             ilo->viewport.cso, ilo->viewport.count, p->cp);
 779
 780       session->viewport_state_changed = true;
 781    }
 782    /* SF_VIEWPORT, CLIP_VIEWPORT, and CC_VIEWPORT */
 783    else if (DIRTY(VIEWPORT)) {
 784       p->state.CLIP_VIEWPORT = p->gen6_CLIP_VIEWPORT(p->dev,
 785             ilo->viewport.cso, ilo->viewport.count, p->cp);
 786
 787       p->state.SF_VIEWPORT = p->gen6_SF_VIEWPORT(p->dev,
 788             ilo->viewport.cso, ilo->viewport.count, p->cp);
 789
 790       p->state.CC_VIEWPORT = p->gen6_CC_VIEWPORT(p->dev,
 791             ilo->viewport.cso, ilo->viewport.count, p->cp);
 792
 793       session->viewport_state_changed = true;
 794    }
 795 }
 796
 797 static void
 798 gen6_pipeline_state_cc(struct ilo_3d_pipeline *p,
 799                        const struct ilo_context *ilo,
 800                        struct gen6_pipeline_session *session)
 801 {
 802    /* BLEND_STATE */
 803    if (DIRTY(BLEND) || DIRTY(FRAMEBUFFER) || DIRTY(DEPTH_STENCIL_ALPHA)) {
 804       p->state.BLEND_STATE = p->gen6_BLEND_STATE(p->dev,
 805             ilo->blend, &ilo->fb, &ilo->dsa->alpha, p->cp);
 806
 807       session->cc_state_blend_changed = true;
 808    }
 809
 810    /* COLOR_CALC_STATE */
 811    if (DIRTY(DEPTH_STENCIL_ALPHA) || DIRTY(STENCIL_REF) || DIRTY(BLEND_COLOR)) {
 812       p->state.COLOR_CALC_STATE =
 813          p->gen6_COLOR_CALC_STATE(p->dev, &ilo->stencil_ref,
 814                ilo->dsa->alpha.ref_value, &ilo->blend_color, p->cp);
 815
 816       session->cc_state_cc_changed = true;
 817    }
 818
 819    /* DEPTH_STENCIL_STATE */
 820    if (DIRTY(DEPTH_STENCIL_ALPHA)) {
 821       p->state.DEPTH_STENCIL_STATE =
 822          p->gen6_DEPTH_STENCIL_STATE(p->dev, ilo->dsa, p->cp);
 823
 824       session->cc_state_dsa_changed = true;
 825    }
 826 }
 827
 828 static void
 829 gen6_pipeline_state_scissors(struct ilo_3d_pipeline *p,
 830                              const struct ilo_context *ilo,
 831                              struct gen6_pipeline_session *session)
 832 {
 833    /* SCISSOR_RECT */
 834    if (DIRTY(SCISSOR) || DIRTY(VIEWPORT)) {
 835       /* there should be as many scissors as there are viewports */
 836       p->state.SCISSOR_RECT = p->gen6_SCISSOR_RECT(p->dev,
 837             &ilo->scissor, ilo->viewport.count, p->cp);
 838
 839       session->scissor_state_changed = true;
 840    }
 841 }
 842
 843 static void
 844 gen6_pipeline_state_surfaces_rt(struct ilo_3d_pipeline *p,
 845                                 const struct ilo_context *ilo,
 846                                 struct gen6_pipeline_session *session)
 847 {
 848    /* SURFACE_STATEs for render targets */
 849    if (DIRTY(FRAMEBUFFER)) {
 850       const int offset = ILO_WM_DRAW_SURFACE(0);
 851       uint32_t *surface_state = &p->state.wm.SURFACE_STATE[offset];
 852       int i;
 853
 854       for (i = 0; i < ilo->fb.state.nr_cbufs; i++) {
 855          const struct ilo_surface_cso *surface =
 856             (const struct ilo_surface_cso *) ilo->fb.state.cbufs[i];
 857
 858          assert(surface && surface->is_rt);
 859          surface_state[i] =
 860             p->gen6_SURFACE_STATE(p->dev, &surface->u.rt, true, p->cp);
 861       }
 862
 863       /*
 864        * Upload at least one render target, as
 865        * brw_update_renderbuffer_surfaces() does.  I don't know why.
 866        */
 867       if (i == 0) {
 868          struct ilo_view_surface null_surface;
 869
 870          ilo_gpe_init_view_surface_null(p->dev,
 871                ilo->fb.state.width, ilo->fb.state.height,
 872                1, 0, &null_surface);
 873
 874          surface_state[i] =
 875             p->gen6_SURFACE_STATE(p->dev, &null_surface, true, p->cp);
 876
 877          i++;
 878       }
 879
 880       memset(&surface_state[i], 0, (ILO_MAX_DRAW_BUFFERS - i) * 4);
 881
 882       if (i && session->num_surfaces[PIPE_SHADER_FRAGMENT] < offset + i)
 883          session->num_surfaces[PIPE_SHADER_FRAGMENT] = offset + i;
 884
 885       session->binding_table_fs_changed = true;
 886    }
 887 }
 888
 889 static void
 890 gen6_pipeline_state_surfaces_so(struct ilo_3d_pipeline *p,
 891                                 const struct ilo_context *ilo,
 892                                 struct gen6_pipeline_session *session)
 893 {
 894    const struct ilo_shader_state *vs = ilo->vs;
 895    const struct ilo_shader_state *gs = ilo->gs;
 896    const struct pipe_stream_output_target **so_targets =
 897       (const struct pipe_stream_output_target **) ilo->so.states;
 898    const int num_so_targets = ilo->so.count;
 899
 900    if (p->dev->gen != ILO_GEN(6))
 901       return;
 902
 903    /* SURFACE_STATEs for stream output targets */
 904    if (DIRTY(VS) || DIRTY(GS) || DIRTY(STREAM_OUTPUT_TARGETS)) {
 905       const struct pipe_stream_output_info *so_info =
 906          (gs) ? &gs->info.stream_output :
 907          (vs) ? &vs->info.stream_output : NULL;
 908       const int offset = ILO_GS_SO_SURFACE(0);
 909       uint32_t *surface_state = &p->state.gs.SURFACE_STATE[offset];
 910       int i;
 911
 912       for (i = 0; so_info && i < so_info->num_outputs; i++) {
 913          const int target = so_info->output[i].output_buffer;
 914          const struct pipe_stream_output_target *so_target =
 915             (target < num_so_targets) ? so_targets[target] : NULL;
 916
 917          if (so_target) {
 918             surface_state[i] = p->gen6_so_SURFACE_STATE(p->dev,
 919                   so_target, so_info, i, p->cp);
 920          }
 921          else {
 922             surface_state[i] = 0;
 923          }
 924       }
 925
 926       memset(&surface_state[i], 0, (ILO_MAX_SO_BINDINGS - i) * 4);
 927
 928       if (i && session->num_surfaces[PIPE_SHADER_GEOMETRY] < offset + i)
 929          session->num_surfaces[PIPE_SHADER_GEOMETRY] = offset + i;
 930
 931       session->binding_table_gs_changed = true;
 932    }
 933 }
 934
 935 static void
 936 gen6_pipeline_state_surfaces_view(struct ilo_3d_pipeline *p,
 937                                   const struct ilo_context *ilo,
 938                                   int shader_type,
 939                                   struct gen6_pipeline_session *session)
 940 {
 941    const struct pipe_sampler_view * const *views =
 942       (const struct pipe_sampler_view **) ilo->view[shader_type].states;
 943    const int num_views = ilo->view[shader_type].count;
 944    uint32_t *surface_state;
 945    int offset, i;
 946    bool skip = false;
 947
 948    /* SURFACE_STATEs for sampler views */
 949    switch (shader_type) {
 950    case PIPE_SHADER_VERTEX:
 951       if (DIRTY(VERTEX_SAMPLER_VIEWS)) {
 952          offset = ILO_VS_TEXTURE_SURFACE(0);
 953          surface_state = &p->state.vs.SURFACE_STATE[offset];
 954
 955          session->binding_table_vs_changed = true;
 956       }
 957       else {
 958          skip = true;
 959       }
 960       break;
 961    case PIPE_SHADER_FRAGMENT:
 962       if (DIRTY(FRAGMENT_SAMPLER_VIEWS)) {
 963          offset = ILO_WM_TEXTURE_SURFACE(0);
 964          surface_state = &p->state.wm.SURFACE_STATE[offset];
 965
 966          session->binding_table_fs_changed = true;
 967       }
 968       else {
 969          skip = true;
 970       }
 971       break;
 972    default:
 973       skip = true;
 974       break;
 975    }
 976
 977    if (skip)
 978       return;
 979
 980    for (i = 0; i < num_views; i++) {
 981       if (views[i]) {
 982          const struct ilo_view_cso *cso =
 983             (const struct ilo_view_cso *) views[i];
 984
 985          surface_state[i] =
 986             p->gen6_SURFACE_STATE(p->dev, &cso->surface, false, p->cp);
 987       }
 988       else {
 989          surface_state[i] = 0;
 990       }
 991    }
 992
 993    memset(&surface_state[i], 0, (ILO_MAX_SAMPLER_VIEWS - i) * 4);
 994
 995    if (i && session->num_surfaces[shader_type] < offset + i)
 996       session->num_surfaces[shader_type] = offset + i;
 997 }
 998
 999 static void
1000 gen6_pipeline_state_surfaces_const(struct ilo_3d_pipeline *p,
1001                                    const struct ilo_context *ilo,
1002                                    int shader_type,
1003                                    struct gen6_pipeline_session *session)
1004 {
1005    const struct ilo_cbuf_cso *buffers = ilo->cbuf[shader_type].cso;
1006    const int num_buffers = ilo->cbuf[shader_type].count;
1007    uint32_t *surface_state;
1008    int offset, i;
1009    bool skip = false;
1010
1011    /* SURFACE_STATEs for constant buffers */
1012    switch (shader_type) {
1013    case PIPE_SHADER_VERTEX:
1014       if (DIRTY(CONSTANT_BUFFER)) {
1015          offset = ILO_VS_CONST_SURFACE(0);
1016          surface_state = &p->state.vs.SURFACE_STATE[offset];
1017
1018          session->binding_table_vs_changed = true;
1019       }
1020       else {
1021          skip = true;
1022       }
1023       break;
1024    case PIPE_SHADER_FRAGMENT:
1025       if (DIRTY(CONSTANT_BUFFER)) {
1026          offset = ILO_WM_CONST_SURFACE(0);
1027          surface_state = &p->state.wm.SURFACE_STATE[offset];
1028
1029          session->binding_table_fs_changed = true;
1030       }
1031       else {
1032          skip = true;
1033       }
1034       break;
1035    default:
1036       skip = true;
1037       break;
1038    }
1039
1040    if (skip)
1041       return;
1042
1043    for (i = 0; i < num_buffers; i++) {
1044       if (buffers[i].resource) {
1045          const struct ilo_view_surface *surf = &buffers[i].surface;
1046
1047          surface_state[i] =
1048             p->gen6_SURFACE_STATE(p->dev, surf, false, p->cp);
1049       }
1050       else {
1051          surface_state[i] = 0;
1052       }
1053    }
1054
1055    memset(&surface_state[i], 0, (ILO_MAX_CONST_BUFFERS - i) * 4);
1056
1057    if (i && session->num_surfaces[shader_type] < offset + i)
1058       session->num_surfaces[shader_type] = offset + i;
1059 }
1060
1061 static void
1062 gen6_pipeline_state_binding_tables(struct ilo_3d_pipeline *p,
1063                                    const struct ilo_context *ilo,
1064                                    int shader_type,
1065                                    struct gen6_pipeline_session *session)
1066 {
1067    uint32_t *binding_table_state, *surface_state;
1068    int *binding_table_state_size, size;
1069    bool skip = false;
1070
1071    /* BINDING_TABLE_STATE */
1072    switch (shader_type) {
1073    case PIPE_SHADER_VERTEX:
1074       surface_state = p->state.vs.SURFACE_STATE;
1075       binding_table_state = &p->state.vs.BINDING_TABLE_STATE;
1076       binding_table_state_size = &p->state.vs.BINDING_TABLE_STATE_size;
1077
1078       skip = !session->binding_table_vs_changed;
1079       break;
1080    case PIPE_SHADER_GEOMETRY:
1081       surface_state = p->state.gs.SURFACE_STATE;
1082       binding_table_state = &p->state.gs.BINDING_TABLE_STATE;
1083       binding_table_state_size = &p->state.gs.BINDING_TABLE_STATE_size;
1084
1085       skip = !session->binding_table_gs_changed;
1086       break;
1087    case PIPE_SHADER_FRAGMENT:
1088       surface_state = p->state.wm.SURFACE_STATE;
1089       binding_table_state = &p->state.wm.BINDING_TABLE_STATE;
1090       binding_table_state_size = &p->state.wm.BINDING_TABLE_STATE_size;
1091
1092       skip = !session->binding_table_fs_changed;
1093       break;
1094    default:
1095       skip = true;
1096       break;
1097    }
1098
1099    if (skip)
1100       return;
1101
1102    /*
1103     * If we have seemingly less SURFACE_STATEs than before, it could be that
1104     * we did not touch those reside at the tail in this upload.  Loop over
1105     * them to figure out the real number of SURFACE_STATEs.
1106     */
1107    for (size = *binding_table_state_size;
1108          size > session->num_surfaces[shader_type]; size--) {
1109       if (surface_state[size - 1])
1110          break;
1111    }
1112    if (size < session->num_surfaces[shader_type])
1113       size = session->num_surfaces[shader_type];
1114
1115    *binding_table_state = p->gen6_BINDING_TABLE_STATE(p->dev,
1116          surface_state, size, p->cp);
1117    *binding_table_state_size = size;
1118 }
1119
1120 static void
1121 gen6_pipeline_state_samplers(struct ilo_3d_pipeline *p,
1122                              const struct ilo_context *ilo,
1123                              int shader_type,
1124                              struct gen6_pipeline_session *session)
1125 {
1126    const struct ilo_sampler_cso * const *samplers =
1127       ilo->sampler[shader_type].cso;
1128    const struct pipe_sampler_view * const *views =
1129       (const struct pipe_sampler_view **) ilo->view[shader_type].states;
1130    const int num_samplers = ilo->sampler[shader_type].count;
1131    const int num_views = ilo->view[shader_type].count;
1132    uint32_t *sampler_state, *border_color_state;
1133    bool emit_border_color = false;
1134    bool skip = false;
1135
1136    /* SAMPLER_BORDER_COLOR_STATE and SAMPLER_STATE */
1137    switch (shader_type) {
1138    case PIPE_SHADER_VERTEX:
1139       if (DIRTY(VERTEX_SAMPLERS) || DIRTY(VERTEX_SAMPLER_VIEWS)) {
1140          sampler_state = &p->state.vs.SAMPLER_STATE;
1141          border_color_state = p->state.vs.SAMPLER_BORDER_COLOR_STATE;
1142
1143          if (DIRTY(VERTEX_SAMPLERS))
1144             emit_border_color = true;
1145
1146          session->sampler_state_vs_changed = true;
1147       }
1148       else {
1149          skip = true;
1150       }
1151       break;
1152    case PIPE_SHADER_FRAGMENT:
1153       if (DIRTY(FRAGMENT_SAMPLERS) || DIRTY(FRAGMENT_SAMPLER_VIEWS)) {
1154          sampler_state = &p->state.wm.SAMPLER_STATE;
1155          border_color_state = p->state.wm.SAMPLER_BORDER_COLOR_STATE;
1156
1157          if (DIRTY(FRAGMENT_SAMPLERS))
1158             emit_border_color = true;
1159
1160          session->sampler_state_fs_changed = true;
1161       }
1162       else {
1163          skip = true;
1164       }
1165       break;
1166    default:
1167       skip = true;
1168       break;
1169    }
1170
1171    if (skip)
1172       return;
1173
1174    if (emit_border_color) {
1175       int i;
1176
1177       for (i = 0; i < num_samplers; i++) {
1178          border_color_state[i] = (samplers[i]) ?
1179             p->gen6_SAMPLER_BORDER_COLOR_STATE(p->dev,
1180                   samplers[i], p->cp) : 0;
1181       }
1182    }
1183
1184    /* should we take the minimum of num_samplers and num_views? */
1185    *sampler_state = p->gen6_SAMPLER_STATE(p->dev,
1186          samplers, views,
1187          border_color_state,
1188          MIN2(num_samplers, num_views), p->cp);
1189 }
1190
1191 static void
1192 gen6_pipeline_state_pcb(struct ilo_3d_pipeline *p,
1193                         const struct ilo_context *ilo,
1194                         struct gen6_pipeline_session *session)
1195 {
1196    /* push constant buffer for VS */
1197    if (DIRTY(VS) || DIRTY(CLIP)) {
1198       const struct ilo_shader *vs = (ilo->vs)? ilo->vs->shader : NULL;
1199
1200       if (vs && vs->pcb.clip_state_size) {
1201          void *pcb;
1202
1203          p->state.vs.PUSH_CONSTANT_BUFFER_size = vs->pcb.clip_state_size;
1204          p->state.vs.PUSH_CONSTANT_BUFFER =
1205             p->gen6_push_constant_buffer(p->dev,
1206                   p->state.vs.PUSH_CONSTANT_BUFFER_size, &pcb, p->cp);
1207
1208          memcpy(pcb, &ilo->clip, vs->pcb.clip_state_size);
1209       }
1210       else {
1211          p->state.vs.PUSH_CONSTANT_BUFFER_size = 0;
1212          p->state.vs.PUSH_CONSTANT_BUFFER = 0;
1213       }
1214
1215       session->pcb_state_vs_changed = true;
1216    }
1217 }
1218
1219 #undef DIRTY
1220
1221 static void
1222 gen6_pipeline_commands(struct ilo_3d_pipeline *p,
1223                        const struct ilo_context *ilo,
1224                        struct gen6_pipeline_session *session)
1225 {
1226    /*
1227     * We try to keep the order of the commands match, as closely as possible,
1228     * that of the classic i965 driver.  It allows us to compare the command
1229     * streams easily.
1230     */
1231    gen6_pipeline_common_select(p, ilo, session);
1232    gen6_pipeline_gs_svbi(p, ilo, session);
1233    gen6_pipeline_common_sip(p, ilo, session);
1234    gen6_pipeline_vf_statistics(p, ilo, session);
1235    gen6_pipeline_common_base_address(p, ilo, session);
1236    gen6_pipeline_common_pointers_1(p, ilo, session);
1237    gen6_pipeline_common_urb(p, ilo, session);
1238    gen6_pipeline_common_pointers_2(p, ilo, session);
1239    gen6_pipeline_wm_multisample(p, ilo, session);
1240    gen6_pipeline_vs(p, ilo, session);
1241    gen6_pipeline_gs(p, ilo, session);
1242    gen6_pipeline_clip(p, ilo, session);
1243    gen6_pipeline_sf(p, ilo, session);
1244    gen6_pipeline_wm(p, ilo, session);
1245    gen6_pipeline_common_pointers_3(p, ilo, session);
1246    gen6_pipeline_wm_depth(p, ilo, session);
1247    gen6_pipeline_wm_raster(p, ilo, session);
1248    gen6_pipeline_sf_rect(p, ilo, session);
1249    gen6_pipeline_vf(p, ilo, session);
1250    gen6_pipeline_vf_draw(p, ilo, session);
1251 }
1252
1253 void
1254 gen6_pipeline_states(struct ilo_3d_pipeline *p,
1255                      const struct ilo_context *ilo,
1256                      struct gen6_pipeline_session *session)
1257 {
1258    int shader_type;
1259
1260    gen6_pipeline_state_viewports(p, ilo, session);
1261    gen6_pipeline_state_cc(p, ilo, session);
1262    gen6_pipeline_state_scissors(p, ilo, session);
1263    gen6_pipeline_state_pcb(p, ilo, session);
1264
1265    /*
1266     * upload all SURAFCE_STATEs together so that we know there are minimal
1267     * paddings
1268     */
1269    gen6_pipeline_state_surfaces_rt(p, ilo, session);
1270    gen6_pipeline_state_surfaces_so(p, ilo, session);
1271    for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
1272       gen6_pipeline_state_surfaces_view(p, ilo, shader_type, session);
1273       gen6_pipeline_state_surfaces_const(p, ilo, shader_type, session);
1274    }
1275
1276    for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
1277       gen6_pipeline_state_samplers(p, ilo, shader_type, session);
1278       /* this must be called after all SURFACE_STATEs are uploaded */
1279       gen6_pipeline_state_binding_tables(p, ilo, shader_type, session);
1280    }
1281 }
1282
1283 void
1284 gen6_pipeline_prepare(const struct ilo_3d_pipeline *p,
1285                       const struct ilo_context *ilo,
1286                       const struct pipe_draw_info *info,
1287                       struct gen6_pipeline_session *session)
1288 {
1289    memset(session, 0, sizeof(*session));
1290    session->info = info;
1291    session->pipe_dirty = ilo->dirty;
1292    session->reduced_prim = u_reduced_prim(info->mode);
1293
1294    /* available space before the session */
1295    session->init_cp_space = ilo_cp_space(p->cp);
1296
1297    session->hw_ctx_changed =
1298       (p->invalidate_flags & ILO_3D_PIPELINE_INVALIDATE_HW);
1299
1300    if (session->hw_ctx_changed) {
1301       /* these should be enough to make everything uploaded */
1302       session->state_bo_changed = true;
1303       session->instruction_bo_changed = true;
1304       session->prim_changed = true;
1305    }
1306    else {
1307       session->state_bo_changed =
1308          (p->invalidate_flags & ILO_3D_PIPELINE_INVALIDATE_STATE_BO);
1309       session->instruction_bo_changed =
1310          (p->invalidate_flags & ILO_3D_PIPELINE_INVALIDATE_KERNEL_BO);
1311       session->prim_changed = (p->state.reduced_prim != session->reduced_prim);
1312    }
1313 }
1314
1315 void
1316 gen6_pipeline_draw(struct ilo_3d_pipeline *p,
1317                    const struct ilo_context *ilo,
1318                    struct gen6_pipeline_session *session)
1319 {
1320    /* force all states to be uploaded if the state bo changed */
1321    if (session->state_bo_changed)
1322       session->pipe_dirty = ILO_DIRTY_ALL;
1323    else
1324       session->pipe_dirty = ilo->dirty;
1325
1326    session->emit_draw_states(p, ilo, session);
1327
1328    /* force all commands to be uploaded if the HW context changed */
1329    if (session->hw_ctx_changed)
1330       session->pipe_dirty = ILO_DIRTY_ALL;
1331    else
1332       session->pipe_dirty = ilo->dirty;
1333
1334    session->emit_draw_commands(p, ilo, session);
1335 }
1336
1337 void
1338 gen6_pipeline_end(struct ilo_3d_pipeline *p,
1339                   const struct ilo_context *ilo,
1340                   struct gen6_pipeline_session *session)
1341 {
1342    int used, estimate;
1343
1344    /* sanity check size estimation */
1345    used = session->init_cp_space - ilo_cp_space(p->cp);
1346    estimate = ilo_3d_pipeline_estimate_size(p, ILO_3D_PIPELINE_DRAW, ilo);
1347    assert(used <= estimate);
1348
1349    p->state.reduced_prim = session->reduced_prim;
1350 }
1351
1352 static void
1353 ilo_3d_pipeline_emit_draw_gen6(struct ilo_3d_pipeline *p,
1354                                const struct ilo_context *ilo,
1355                                const struct pipe_draw_info *info)
1356 {
1357    struct gen6_pipeline_session session;
1358
1359    gen6_pipeline_prepare(p, ilo, info, &session);
1360
1361    session.emit_draw_states = gen6_pipeline_states;
1362    session.emit_draw_commands = gen6_pipeline_commands;
1363
1364    gen6_pipeline_draw(p, ilo, &session);
1365    gen6_pipeline_end(p, ilo, &session);
1366 }
1367
1368 void
1369 ilo_3d_pipeline_emit_flush_gen6(struct ilo_3d_pipeline *p)
1370 {
1371    if (p->dev->gen == ILO_GEN(6))
1372       gen6_wa_pipe_control_post_sync(p, false);
1373
1374    p->gen6_PIPE_CONTROL(p->dev,
1375          PIPE_CONTROL_INSTRUCTION_FLUSH |
1376          PIPE_CONTROL_WRITE_FLUSH |
1377          PIPE_CONTROL_DEPTH_CACHE_FLUSH |
1378          PIPE_CONTROL_VF_CACHE_INVALIDATE |
1379          PIPE_CONTROL_TC_FLUSH |
1380          PIPE_CONTROL_NO_WRITE |
1381          PIPE_CONTROL_CS_STALL,
1382          0, 0, false, p->cp);
1383 }
1384
1385 void
1386 ilo_3d_pipeline_emit_write_timestamp_gen6(struct ilo_3d_pipeline *p,
1387                                           struct intel_bo *bo, int index)
1388 {
1389    if (p->dev->gen == ILO_GEN(6))
1390       gen6_wa_pipe_control_post_sync(p, true);
1391
1392    p->gen6_PIPE_CONTROL(p->dev,
1393          PIPE_CONTROL_WRITE_TIMESTAMP,
1394          bo, index * sizeof(uint64_t) | PIPE_CONTROL_GLOBAL_GTT_WRITE,
1395          true, p->cp);
1396 }
1397
1398 void
1399 ilo_3d_pipeline_emit_write_depth_count_gen6(struct ilo_3d_pipeline *p,
1400                                             struct intel_bo *bo, int index)
1401 {
1402    if (p->dev->gen == ILO_GEN(6))
1403       gen6_wa_pipe_control_post_sync(p, false);
1404
1405    p->gen6_PIPE_CONTROL(p->dev,
1406          PIPE_CONTROL_DEPTH_STALL |
1407          PIPE_CONTROL_WRITE_DEPTH_COUNT,
1408          bo, index * sizeof(uint64_t) | PIPE_CONTROL_GLOBAL_GTT_WRITE,
1409          true, p->cp);
1410 }
1411
1412 static int
1413 gen6_pipeline_estimate_commands(const struct ilo_3d_pipeline *p,
1414                                 const struct ilo_gpe_gen6 *gen6,
1415                                 const struct ilo_context *ilo)
1416 {
1417    static int size;
1418    enum ilo_gpe_gen6_command cmd;
1419
1420    if (size)
1421       return size;
1422
1423    for (cmd = 0; cmd < ILO_GPE_GEN6_COMMAND_COUNT; cmd++) {
1424       int count;
1425
1426       switch (cmd) {
1427       case ILO_GPE_GEN6_PIPE_CONTROL:
1428          /* for the workaround */
1429          count = 2;
1430          /* another one after 3DSTATE_URB */
1431          count += 1;
1432          /* and another one after 3DSTATE_CONSTANT_VS */
1433          count += 1;
1434          break;
1435       case ILO_GPE_GEN6_3DSTATE_GS_SVB_INDEX:
1436          /* there are 4 SVBIs */
1437          count = 4;
1438          break;
1439       case ILO_GPE_GEN6_3DSTATE_VERTEX_BUFFERS:
1440          count = 33;
1441          break;
1442       case ILO_GPE_GEN6_3DSTATE_VERTEX_ELEMENTS:
1443          count = 34;
1444          break;
1445       case ILO_GPE_GEN6_MEDIA_VFE_STATE:
1446       case ILO_GPE_GEN6_MEDIA_CURBE_LOAD:
1447       case ILO_GPE_GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD:
1448       case ILO_GPE_GEN6_MEDIA_GATEWAY_STATE:
1449       case ILO_GPE_GEN6_MEDIA_STATE_FLUSH:
1450       case ILO_GPE_GEN6_MEDIA_OBJECT_WALKER:
1451          /* media commands */
1452          count = 0;
1453          break;
1454       default:
1455          count = 1;
1456          break;
1457       }
1458
1459       if (count)
1460          size += gen6->estimate_command_size(p->dev, cmd, count);
1461    }
1462
1463    return size;
1464 }
1465
1466 static int
1467 gen6_pipeline_estimate_states(const struct ilo_3d_pipeline *p,
1468                               const struct ilo_gpe_gen6 *gen6,
1469                               const struct ilo_context *ilo)
1470 {
1471    static int static_size;
1472    int shader_type, count, size;
1473
1474    if (!static_size) {
1475       struct {
1476          enum ilo_gpe_gen6_state state;
1477          int count;
1478       } static_states[] = {
1479          /* viewports */
1480          { ILO_GPE_GEN6_SF_VIEWPORT,                 1 },
1481          { ILO_GPE_GEN6_CLIP_VIEWPORT,               1 },
1482          { ILO_GPE_GEN6_CC_VIEWPORT,                 1 },
1483          /* cc */
1484          { ILO_GPE_GEN6_COLOR_CALC_STATE,            1 },
1485          { ILO_GPE_GEN6_BLEND_STATE,                 ILO_MAX_DRAW_BUFFERS },
1486          { ILO_GPE_GEN6_DEPTH_STENCIL_STATE,         1 },
1487          /* scissors */
1488          { ILO_GPE_GEN6_SCISSOR_RECT,                1 },
1489          /* binding table (vs, gs, fs) */
1490          { ILO_GPE_GEN6_BINDING_TABLE_STATE,         ILO_MAX_VS_SURFACES },
1491          { ILO_GPE_GEN6_BINDING_TABLE_STATE,         ILO_MAX_GS_SURFACES },
1492          { ILO_GPE_GEN6_BINDING_TABLE_STATE,         ILO_MAX_WM_SURFACES },
1493       };
1494       int i;
1495
1496       for (i = 0; i < Elements(static_states); i++) {
1497          static_size += gen6->estimate_state_size(p->dev,
1498                static_states[i].state,
1499                static_states[i].count);
1500       }
1501    }
1502
1503    size = static_size;
1504
1505    /*
1506     * render targets (fs)
1507     * stream outputs (gs)
1508     * sampler views (vs, fs)
1509     * constant buffers (vs, fs)
1510     */
1511    count = ilo->fb.state.nr_cbufs;
1512
1513    if (ilo->gs)
1514       count += ilo->gs->info.stream_output.num_outputs;
1515    else if (ilo->vs)
1516       count += ilo->vs->info.stream_output.num_outputs;
1517
1518    for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
1519       count += ilo->view[shader_type].count;
1520       count += ilo->cbuf[shader_type].count;
1521    }
1522
1523    if (count) {
1524       size += gen6->estimate_state_size(p->dev,
1525             ILO_GPE_GEN6_SURFACE_STATE, count);
1526    }
1527
1528    /* samplers (vs, fs) */
1529    for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
1530       count = ilo->sampler[shader_type].count;
1531       if (count) {
1532          size += gen6->estimate_state_size(p->dev,
1533                ILO_GPE_GEN6_SAMPLER_BORDER_COLOR_STATE, count);
1534          size += gen6->estimate_state_size(p->dev,
1535                ILO_GPE_GEN6_SAMPLER_STATE, count);
1536       }
1537    }
1538
1539    /* pcb (vs) */
1540    if (ilo->vs && ilo->vs->shader->pcb.clip_state_size) {
1541       const int pcb_size = ilo->vs->shader->pcb.clip_state_size;
1542
1543       size += gen6->estimate_state_size(p->dev,
1544             ILO_GPE_GEN6_PUSH_CONSTANT_BUFFER, pcb_size);
1545    }
1546
1547    return size;
1548 }
1549
1550 static int
1551 ilo_3d_pipeline_estimate_size_gen6(struct ilo_3d_pipeline *p,
1552                                    enum ilo_3d_pipeline_action action,
1553                                    const void *arg)
1554 {
1555    const struct ilo_gpe_gen6 *gen6 = ilo_gpe_gen6_get();
1556    int size;
1557
1558    switch (action) {
1559    case ILO_3D_PIPELINE_DRAW:
1560       {
1561          const struct ilo_context *ilo = arg;
1562
1563          size = gen6_pipeline_estimate_commands(p, gen6, ilo) +
1564             gen6_pipeline_estimate_states(p, gen6, ilo);
1565       }
1566       break;
1567    case ILO_3D_PIPELINE_FLUSH:
1568       size = gen6->estimate_command_size(p->dev,
1569             ILO_GPE_GEN6_PIPE_CONTROL, 1) * 3;
1570       break;
1571    case ILO_3D_PIPELINE_WRITE_TIMESTAMP:
1572       size = gen6->estimate_command_size(p->dev,
1573             ILO_GPE_GEN6_PIPE_CONTROL, 1) * 2;
1574       break;
1575    case ILO_3D_PIPELINE_WRITE_DEPTH_COUNT:
1576       size = gen6->estimate_command_size(p->dev,
1577             ILO_GPE_GEN6_PIPE_CONTROL, 1) * 3;
1578       break;
1579    default:
1580       assert(!"unknown 3D pipeline action");
1581       size = 0;
1582       break;
1583    }
1584
1585    return size;
1586 }
1587
1588 void
1589 ilo_3d_pipeline_init_gen6(struct ilo_3d_pipeline *p)
1590 {
1591    const struct ilo_gpe_gen6 *gen6 = ilo_gpe_gen6_get();
1592
1593    p->estimate_size = ilo_3d_pipeline_estimate_size_gen6;
1594    p->emit_draw = ilo_3d_pipeline_emit_draw_gen6;
1595    p->emit_flush = ilo_3d_pipeline_emit_flush_gen6;
1596    p->emit_write_timestamp = ilo_3d_pipeline_emit_write_timestamp_gen6;
1597    p->emit_write_depth_count = ilo_3d_pipeline_emit_write_depth_count_gen6;
1598
1599 #define GEN6_USE(p, name, from) \
1600    p->gen6_ ## name = from->emit_ ## name
1601    GEN6_USE(p, STATE_BASE_ADDRESS, gen6);
1602    GEN6_USE(p, STATE_SIP, gen6);
1603    GEN6_USE(p, PIPELINE_SELECT, gen6);
1604    GEN6_USE(p, 3DSTATE_BINDING_TABLE_POINTERS, gen6);
1605    GEN6_USE(p, 3DSTATE_SAMPLER_STATE_POINTERS, gen6);
1606    GEN6_USE(p, 3DSTATE_URB, gen6);
1607    GEN6_USE(p, 3DSTATE_VERTEX_BUFFERS, gen6);
1608    GEN6_USE(p, 3DSTATE_VERTEX_ELEMENTS, gen6);
1609    GEN6_USE(p, 3DSTATE_INDEX_BUFFER, gen6);
1610    GEN6_USE(p, 3DSTATE_VF_STATISTICS, gen6);
1611    GEN6_USE(p, 3DSTATE_VIEWPORT_STATE_POINTERS, gen6);
1612    GEN6_USE(p, 3DSTATE_CC_STATE_POINTERS, gen6);
1613    GEN6_USE(p, 3DSTATE_SCISSOR_STATE_POINTERS, gen6);
1614    GEN6_USE(p, 3DSTATE_VS, gen6);
1615    GEN6_USE(p, 3DSTATE_GS, gen6);
1616    GEN6_USE(p, 3DSTATE_CLIP, gen6);
1617    GEN6_USE(p, 3DSTATE_SF, gen6);
1618    GEN6_USE(p, 3DSTATE_WM, gen6);
1619    GEN6_USE(p, 3DSTATE_CONSTANT_VS, gen6);
1620    GEN6_USE(p, 3DSTATE_CONSTANT_GS, gen6);
1621    GEN6_USE(p, 3DSTATE_CONSTANT_PS, gen6);
1622    GEN6_USE(p, 3DSTATE_SAMPLE_MASK, gen6);
1623    GEN6_USE(p, 3DSTATE_DRAWING_RECTANGLE, gen6);
1624    GEN6_USE(p, 3DSTATE_DEPTH_BUFFER, gen6);
1625    GEN6_USE(p, 3DSTATE_POLY_STIPPLE_OFFSET, gen6);
1626    GEN6_USE(p, 3DSTATE_POLY_STIPPLE_PATTERN, gen6);
1627    GEN6_USE(p, 3DSTATE_LINE_STIPPLE, gen6);
1628    GEN6_USE(p, 3DSTATE_AA_LINE_PARAMETERS, gen6);
1629    GEN6_USE(p, 3DSTATE_GS_SVB_INDEX, gen6);
1630    GEN6_USE(p, 3DSTATE_MULTISAMPLE, gen6);
1631    GEN6_USE(p, 3DSTATE_STENCIL_BUFFER, gen6);
1632    GEN6_USE(p, 3DSTATE_HIER_DEPTH_BUFFER, gen6);
1633    GEN6_USE(p, 3DSTATE_CLEAR_PARAMS, gen6);
1634    GEN6_USE(p, PIPE_CONTROL, gen6);
1635    GEN6_USE(p, 3DPRIMITIVE, gen6);
1636    GEN6_USE(p, INTERFACE_DESCRIPTOR_DATA, gen6);
1637    GEN6_USE(p, SF_VIEWPORT, gen6);
1638    GEN6_USE(p, CLIP_VIEWPORT, gen6);
1639    GEN6_USE(p, CC_VIEWPORT, gen6);
1640    GEN6_USE(p, COLOR_CALC_STATE, gen6);
1641    GEN6_USE(p, BLEND_STATE, gen6);
1642    GEN6_USE(p, DEPTH_STENCIL_STATE, gen6);
1643    GEN6_USE(p, SCISSOR_RECT, gen6);
1644    GEN6_USE(p, BINDING_TABLE_STATE, gen6);
1645    GEN6_USE(p, SURFACE_STATE, gen6);
1646    GEN6_USE(p, so_SURFACE_STATE, gen6);
1647    GEN6_USE(p, SAMPLER_STATE, gen6);
1648    GEN6_USE(p, SAMPLER_BORDER_COLOR_STATE, gen6);
1649    GEN6_USE(p, push_constant_buffer, gen6);
1650 #undef GEN6_USE
1651 }