src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c

   1 /*
   2  * Mesa 3-D graphics library
   3  *
   4  * Copyright (C) 2013 LunarG, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Chia-I Wu <olv@lunarg.com>
  26  */
  27
  28 #include "genhw/genhw.h"
  29 #include "util/u_dual_blend.h"
  30
  31 #include "ilo_blitter.h"
  32 #include "ilo_builder_3d.h"
  33 #include "ilo_builder_render.h"
  34 #include "ilo_cp.h"
  35 #include "ilo_shader.h"
  36 #include "ilo_state.h"
  37 #include "ilo_3d_pipeline.h"
  38 #include "ilo_3d_pipeline_gen6.h"
  39 #include "ilo_3d_pipeline_gen7.h"
  40
  41 static void
  42 gen7_wa_pipe_control_cs_stall(struct ilo_3d_pipeline *p,
  43                               bool change_multisample_state,
  44                               bool change_depth_state)
  45 {
  46    struct intel_bo *bo = NULL;
  47    uint32_t dw1 = GEN6_PIPE_CONTROL_CS_STALL;
  48
  49    assert(ilo_dev_gen(p->dev) == ILO_GEN(7) ||
  50           ilo_dev_gen(p->dev) == ILO_GEN(7.5));
  51
  52    /* emit once */
  53    if (p->state.has_gen6_wa_pipe_control)
  54       return;
  55    p->state.has_gen6_wa_pipe_control = true;
  56
  57    /*
  58     * From the Ivy Bridge PRM, volume 2 part 1, page 258:
  59     *
  60     *     "Due to an HW issue driver needs to send a pipe control with stall
  61     *      when ever there is state change in depth bias related state"
  62     *
  63     * From the Ivy Bridge PRM, volume 2 part 1, page 292:
  64     *
  65     *     "A PIPE_CONTOL command with the CS Stall bit set must be programmed
  66     *      in the ring after this instruction
  67     *      (3DSTATE_PUSH_CONSTANT_ALLOC_PS)."
  68     *
  69     * From the Ivy Bridge PRM, volume 2 part 1, page 304:
  70     *
  71     *     "Driver must ierarchi that all the caches in the depth pipe are
  72     *      flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
  73     *      requires driver to send a PIPE_CONTROL with a CS stall along with a
  74     *      Depth Flush prior to this command.
  75     *
  76     * From the Ivy Bridge PRM, volume 2 part 1, page 315:
  77     *
  78     *     "Driver must send a least one PIPE_CONTROL command with CS Stall and
  79     *      a post sync operation prior to the group of depth
  80     *      commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
  81     *      3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER)."
  82     */
  83
  84    if (change_multisample_state)
  85       dw1 |= GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH;
  86
  87    if (change_depth_state) {
  88       dw1 |= GEN6_PIPE_CONTROL_WRITE_IMM;
  89       bo = p->workaround_bo;
  90    }
  91
  92    gen6_PIPE_CONTROL(p->builder, dw1, bo, 0, false);
  93 }
  94
  95 static void
  96 gen7_wa_pipe_control_vs_depth_stall(struct ilo_3d_pipeline *p)
  97 {
  98    assert(ilo_dev_gen(p->dev) == ILO_GEN(7) ||
  99           ilo_dev_gen(p->dev) == ILO_GEN(7.5));
 100
 101    /*
 102     * From the Ivy Bridge PRM, volume 2 part 1, page 106:
 103     *
 104     *     "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
 105     *      needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS,
 106     *      3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS,
 107     *      3DSTATE_SAMPLER_STATE_POINTER_VS command.  Only one PIPE_CONTROL
 108     *      needs to be sent before any combination of VS associated 3DSTATE."
 109     */
 110    gen6_PIPE_CONTROL(p->builder,
 111          GEN6_PIPE_CONTROL_DEPTH_STALL |
 112          GEN6_PIPE_CONTROL_WRITE_IMM,
 113          p->workaround_bo, 0, false);
 114 }
 115
 116 static void
 117 gen7_wa_pipe_control_wm_depth_stall(struct ilo_3d_pipeline *p,
 118                                     bool change_depth_buffer)
 119 {
 120    assert(ilo_dev_gen(p->dev) == ILO_GEN(7) ||
 121           ilo_dev_gen(p->dev) == ILO_GEN(7.5));
 122
 123    /*
 124     * From the Ivy Bridge PRM, volume 2 part 1, page 276:
 125     *
 126     *     "The driver must make sure a PIPE_CONTROL with the Depth Stall
 127     *      Enable bit set after all the following states are programmed:
 128     *
 129     *       * 3DSTATE_PS
 130     *       * 3DSTATE_VIEWPORT_STATE_POINTERS_CC
 131     *       * 3DSTATE_CONSTANT_PS
 132     *       * 3DSTATE_BINDING_TABLE_POINTERS_PS
 133     *       * 3DSTATE_SAMPLER_STATE_POINTERS_PS
 134     *       * 3DSTATE_CC_STATE_POINTERS
 135     *       * 3DSTATE_BLEND_STATE_POINTERS
 136     *       * 3DSTATE_DEPTH_STENCIL_STATE_POINTERS"
 137     *
 138     * From the Ivy Bridge PRM, volume 2 part 1, page 315:
 139     *
 140     *     "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
 141     *      any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
 142     *      3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
 143     *      issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
 144     *      set), followed by a pipelined depth cache flush (PIPE_CONTROL with
 145     *      Depth Flush Bit set, followed by another pipelined depth stall
 146     *      (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
 147     *      guarantee that the pipeline from WM onwards is already flushed
 148     *      (e.g., via a preceding MI_FLUSH)."
 149     */
 150    gen6_PIPE_CONTROL(p->builder,
 151          GEN6_PIPE_CONTROL_DEPTH_STALL,
 152          NULL, 0, false);
 153
 154    if (!change_depth_buffer)
 155       return;
 156
 157    gen6_PIPE_CONTROL(p->builder,
 158          GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH,
 159          NULL, 0, false);
 160
 161    gen6_PIPE_CONTROL(p->builder,
 162          GEN6_PIPE_CONTROL_DEPTH_STALL,
 163          NULL, 0, false);
 164 }
 165
 166 static void
 167 gen7_wa_pipe_control_ps_max_threads_stall(struct ilo_3d_pipeline *p)
 168 {
 169    assert(ilo_dev_gen(p->dev) == ILO_GEN(7) ||
 170           ilo_dev_gen(p->dev) == ILO_GEN(7.5));
 171
 172    /*
 173     * From the Ivy Bridge PRM, volume 2 part 1, page 286:
 174     *
 175     *     "If this field (Maximum Number of Threads in 3DSTATE_PS) is changed
 176     *      between 3DPRIMITIVE commands, a PIPE_CONTROL command with Stall at
 177     *      Pixel Scoreboard set is required to be issued."
 178     */
 179    gen6_PIPE_CONTROL(p->builder,
 180          GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL,
 181          NULL, 0, false);
 182
 183 }
 184
 185 #define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
 186
 187 static void
 188 gen7_pipeline_common_urb(struct ilo_3d_pipeline *p,
 189                          const struct ilo_state_vector *vec,
 190                          struct gen6_pipeline_session *session)
 191 {
 192    /* 3DSTATE_URB_{VS,GS,HS,DS} */
 193    if (DIRTY(VE) || DIRTY(VS)) {
 194       /* the first 16KB are reserved for VS and PS PCBs */
 195       const int offset = (ilo_dev_gen(p->dev) == ILO_GEN(7.5) &&
 196             p->dev->gt == 3) ? 32768 : 16384;
 197       int vs_entry_size, vs_total_size;
 198
 199       vs_entry_size = (vec->vs) ?
 200          ilo_shader_get_kernel_param(vec->vs, ILO_KERNEL_OUTPUT_COUNT) : 0;
 201
 202       /*
 203        * From the Ivy Bridge PRM, volume 2 part 1, page 35:
 204        *
 205        *     "Programming Restriction: As the VS URB entry serves as both the
 206        *      per-vertex input and output of the VS shader, the VS URB
 207        *      Allocation Size must be sized to the maximum of the vertex input
 208        *      and output structures."
 209        */
 210       if (vs_entry_size < vec->ve->count)
 211          vs_entry_size = vec->ve->count;
 212
 213       vs_entry_size *= sizeof(float) * 4;
 214       vs_total_size = p->dev->urb_size - offset;
 215
 216       gen7_wa_pipe_control_vs_depth_stall(p);
 217
 218       gen7_3DSTATE_URB_VS(p->builder,
 219             offset, vs_total_size, vs_entry_size);
 220
 221       gen7_3DSTATE_URB_GS(p->builder, offset, 0, 0);
 222       gen7_3DSTATE_URB_HS(p->builder, offset, 0, 0);
 223       gen7_3DSTATE_URB_DS(p->builder, offset, 0, 0);
 224    }
 225 }
 226
 227 static void
 228 gen7_pipeline_common_pcb_alloc(struct ilo_3d_pipeline *p,
 229                                const struct ilo_state_vector *vec,
 230                                struct gen6_pipeline_session *session)
 231 {
 232    /* 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,PS} */
 233    if (session->hw_ctx_changed) {
 234       /*
 235        * Push constant buffers are only allowed to take up at most the first
 236        * 16KB of the URB.  Split the space evenly for VS and FS.
 237        */
 238       const int max_size = (ilo_dev_gen(p->dev) == ILO_GEN(7.5) &&
 239             p->dev->gt == 3) ? 32768 : 16384;
 240       const int size = max_size / 2;
 241       int offset = 0;
 242
 243       gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(p->builder, offset, size);
 244       offset += size;
 245
 246       gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(p->builder, offset, size);
 247
 248       if (ilo_dev_gen(p->dev) == ILO_GEN(7))
 249          gen7_wa_pipe_control_cs_stall(p, true, true);
 250    }
 251 }
 252
 253 static void
 254 gen7_pipeline_common_pointers_1(struct ilo_3d_pipeline *p,
 255                                 const struct ilo_state_vector *vec,
 256                                 struct gen6_pipeline_session *session)
 257 {
 258    /* 3DSTATE_VIEWPORT_STATE_POINTERS_{CC,SF_CLIP} */
 259    if (session->viewport_state_changed) {
 260       gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(p->builder,
 261             p->state.CC_VIEWPORT);
 262
 263       gen7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP(p->builder,
 264             p->state.SF_CLIP_VIEWPORT);
 265    }
 266 }
 267
 268 static void
 269 gen7_pipeline_common_pointers_2(struct ilo_3d_pipeline *p,
 270                                 const struct ilo_state_vector *vec,
 271                                 struct gen6_pipeline_session *session)
 272 {
 273    /* 3DSTATE_BLEND_STATE_POINTERS */
 274    if (session->cc_state_blend_changed) {
 275       gen7_3DSTATE_BLEND_STATE_POINTERS(p->builder,
 276             p->state.BLEND_STATE);
 277    }
 278
 279    /* 3DSTATE_CC_STATE_POINTERS */
 280    if (session->cc_state_cc_changed) {
 281       gen7_3DSTATE_CC_STATE_POINTERS(p->builder,
 282             p->state.COLOR_CALC_STATE);
 283    }
 284
 285    /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */
 286    if (session->cc_state_dsa_changed) {
 287       gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(p->builder,
 288             p->state.DEPTH_STENCIL_STATE);
 289    }
 290 }
 291
 292 static void
 293 gen7_pipeline_vs(struct ilo_3d_pipeline *p,
 294                  const struct ilo_state_vector *vec,
 295                  struct gen6_pipeline_session *session)
 296 {
 297    const bool emit_3dstate_binding_table = session->binding_table_vs_changed;
 298    const bool emit_3dstate_sampler_state = session->sampler_state_vs_changed;
 299    /* see gen6_pipeline_vs() */
 300    const bool emit_3dstate_constant_vs = session->pcb_state_vs_changed;
 301    const bool emit_3dstate_vs = (DIRTY(VS) || DIRTY(SAMPLER_VS) ||
 302            session->kernel_bo_changed);
 303
 304    /* emit depth stall before any of the VS commands */
 305    if (emit_3dstate_binding_table || emit_3dstate_sampler_state ||
 306            emit_3dstate_constant_vs || emit_3dstate_vs)
 307       gen7_wa_pipe_control_vs_depth_stall(p);
 308
 309    /* 3DSTATE_BINDING_TABLE_POINTERS_VS */
 310    if (emit_3dstate_binding_table) {
 311       gen7_3DSTATE_BINDING_TABLE_POINTERS_VS(p->builder,
 312               p->state.vs.BINDING_TABLE_STATE);
 313    }
 314
 315    /* 3DSTATE_SAMPLER_STATE_POINTERS_VS */
 316    if (emit_3dstate_sampler_state) {
 317       gen7_3DSTATE_SAMPLER_STATE_POINTERS_VS(p->builder,
 318               p->state.vs.SAMPLER_STATE);
 319    }
 320
 321    /* 3DSTATE_CONSTANT_VS */
 322    if (emit_3dstate_constant_vs) {
 323       gen7_3DSTATE_CONSTANT_VS(p->builder,
 324               &p->state.vs.PUSH_CONSTANT_BUFFER,
 325               &p->state.vs.PUSH_CONSTANT_BUFFER_size,
 326               1);
 327    }
 328
 329    /* 3DSTATE_VS */
 330    if (emit_3dstate_vs) {
 331       const int num_samplers = vec->sampler[PIPE_SHADER_VERTEX].count;
 332
 333       gen6_3DSTATE_VS(p->builder, vec->vs, num_samplers);
 334    }
 335 }
 336
 337 static void
 338 gen7_pipeline_hs(struct ilo_3d_pipeline *p,
 339                  const struct ilo_state_vector *vec,
 340                  struct gen6_pipeline_session *session)
 341 {
 342    /* 3DSTATE_CONSTANT_HS and 3DSTATE_HS */
 343    if (session->hw_ctx_changed) {
 344       gen7_3DSTATE_CONSTANT_HS(p->builder, 0, 0, 0);
 345       gen7_3DSTATE_HS(p->builder, NULL, 0);
 346    }
 347
 348    /* 3DSTATE_BINDING_TABLE_POINTERS_HS */
 349    if (session->hw_ctx_changed)
 350       gen7_3DSTATE_BINDING_TABLE_POINTERS_HS(p->builder, 0);
 351 }
 352
 353 static void
 354 gen7_pipeline_te(struct ilo_3d_pipeline *p,
 355                  const struct ilo_state_vector *vec,
 356                  struct gen6_pipeline_session *session)
 357 {
 358    /* 3DSTATE_TE */
 359    if (session->hw_ctx_changed)
 360       gen7_3DSTATE_TE(p->builder);
 361 }
 362
 363 static void
 364 gen7_pipeline_ds(struct ilo_3d_pipeline *p,
 365                  const struct ilo_state_vector *vec,
 366                  struct gen6_pipeline_session *session)
 367 {
 368    /* 3DSTATE_CONSTANT_DS and 3DSTATE_DS */
 369    if (session->hw_ctx_changed) {
 370       gen7_3DSTATE_CONSTANT_DS(p->builder, 0, 0, 0);
 371       gen7_3DSTATE_DS(p->builder, NULL, 0);
 372    }
 373
 374    /* 3DSTATE_BINDING_TABLE_POINTERS_DS */
 375    if (session->hw_ctx_changed)
 376       gen7_3DSTATE_BINDING_TABLE_POINTERS_DS(p->builder, 0);
 377
 378 }
 379
 380 static void
 381 gen7_pipeline_gs(struct ilo_3d_pipeline *p,
 382                  const struct ilo_state_vector *vec,
 383                  struct gen6_pipeline_session *session)
 384 {
 385    /* 3DSTATE_CONSTANT_GS and 3DSTATE_GS */
 386    if (session->hw_ctx_changed) {
 387       gen7_3DSTATE_CONSTANT_GS(p->builder, 0, 0, 0);
 388       gen7_3DSTATE_GS(p->builder, NULL, 0);
 389    }
 390
 391    /* 3DSTATE_BINDING_TABLE_POINTERS_GS */
 392    if (session->binding_table_gs_changed) {
 393       gen7_3DSTATE_BINDING_TABLE_POINTERS_GS(p->builder,
 394             p->state.gs.BINDING_TABLE_STATE);
 395    }
 396 }
 397
 398 static void
 399 gen7_pipeline_sol(struct ilo_3d_pipeline *p,
 400                   const struct ilo_state_vector *vec,
 401                   struct gen6_pipeline_session *session)
 402 {
 403    const struct pipe_stream_output_info *so_info;
 404    const struct ilo_shader_state *shader;
 405    bool dirty_sh = false;
 406
 407    if (vec->gs) {
 408       shader = vec->gs;
 409       dirty_sh = DIRTY(GS);
 410    }
 411    else {
 412       shader = vec->vs;
 413       dirty_sh = DIRTY(VS);
 414    }
 415
 416    so_info = ilo_shader_get_kernel_so_info(shader);
 417
 418    gen6_pipeline_update_max_svbi(p, vec, session);
 419
 420    /* 3DSTATE_SO_BUFFER */
 421    if ((DIRTY(SO) || dirty_sh || session->batch_bo_changed) &&
 422        vec->so.enabled) {
 423       int i;
 424
 425       for (i = 0; i < vec->so.count; i++) {
 426          const int stride = so_info->stride[i] * 4; /* in bytes */
 427          int base = 0;
 428
 429          gen7_3DSTATE_SO_BUFFER(p->builder, i, base, stride,
 430                vec->so.states[i]);
 431       }
 432
 433       for (; i < 4; i++)
 434          gen7_3DSTATE_SO_BUFFER(p->builder, i, 0, 0, NULL);
 435    }
 436
 437    /* 3DSTATE_SO_DECL_LIST */
 438    if (dirty_sh && vec->so.enabled)
 439       gen7_3DSTATE_SO_DECL_LIST(p->builder, so_info);
 440
 441    /* 3DSTATE_STREAMOUT */
 442    if (DIRTY(SO) || DIRTY(RASTERIZER) || dirty_sh) {
 443       const unsigned buffer_mask = (1 << vec->so.count) - 1;
 444       const int output_count = ilo_shader_get_kernel_param(shader,
 445             ILO_KERNEL_OUTPUT_COUNT);
 446
 447       gen7_3DSTATE_STREAMOUT(p->builder, buffer_mask, output_count,
 448             vec->rasterizer->state.rasterizer_discard);
 449    }
 450 }
 451
 452 static void
 453 gen7_pipeline_sf(struct ilo_3d_pipeline *p,
 454                  const struct ilo_state_vector *vec,
 455                  struct gen6_pipeline_session *session)
 456 {
 457    /* 3DSTATE_SBE */
 458    if (DIRTY(RASTERIZER) || DIRTY(FS))
 459       gen7_3DSTATE_SBE(p->builder, vec->rasterizer, vec->fs);
 460
 461    /* 3DSTATE_SF */
 462    if (DIRTY(RASTERIZER) || DIRTY(FB)) {
 463       struct pipe_surface *zs = vec->fb.state.zsbuf;
 464
 465       gen7_wa_pipe_control_cs_stall(p, true, true);
 466       gen7_3DSTATE_SF(p->builder, vec->rasterizer,
 467             (zs) ? zs->format : PIPE_FORMAT_NONE);
 468    }
 469 }
 470
 471 static void
 472 gen7_pipeline_wm(struct ilo_3d_pipeline *p,
 473                  const struct ilo_state_vector *vec,
 474                  struct gen6_pipeline_session *session)
 475 {
 476    /* 3DSTATE_WM */
 477    if (DIRTY(FS) || DIRTY(BLEND) || DIRTY(DSA) || DIRTY(RASTERIZER)) {
 478       const bool cc_may_kill = (vec->dsa->dw_alpha ||
 479                                 vec->blend->alpha_to_coverage);
 480
 481       gen7_3DSTATE_WM(p->builder, vec->fs,
 482             vec->rasterizer, cc_may_kill, 0);
 483    }
 484
 485    /* 3DSTATE_BINDING_TABLE_POINTERS_PS */
 486    if (session->binding_table_fs_changed) {
 487       gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(p->builder,
 488             p->state.wm.BINDING_TABLE_STATE);
 489    }
 490
 491    /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */
 492    if (session->sampler_state_fs_changed) {
 493       gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(p->builder,
 494             p->state.wm.SAMPLER_STATE);
 495    }
 496
 497    /* 3DSTATE_CONSTANT_PS */
 498    if (session->pcb_state_fs_changed) {
 499       gen7_3DSTATE_CONSTANT_PS(p->builder,
 500             &p->state.wm.PUSH_CONSTANT_BUFFER,
 501             &p->state.wm.PUSH_CONSTANT_BUFFER_size,
 502             1);
 503    }
 504
 505    /* 3DSTATE_PS */
 506    if (DIRTY(FS) || DIRTY(SAMPLER_FS) || DIRTY(BLEND) ||
 507        session->kernel_bo_changed) {
 508       const int num_samplers = vec->sampler[PIPE_SHADER_FRAGMENT].count;
 509       const bool dual_blend = vec->blend->dual_blend;
 510
 511       if ((ilo_dev_gen(p->dev) == ILO_GEN(7) ||
 512            ilo_dev_gen(p->dev) == ILO_GEN(7.5)) &&
 513           session->hw_ctx_changed)
 514          gen7_wa_pipe_control_ps_max_threads_stall(p);
 515
 516       gen7_3DSTATE_PS(p->builder, vec->fs, num_samplers, dual_blend);
 517    }
 518
 519    /* 3DSTATE_SCISSOR_STATE_POINTERS */
 520    if (session->scissor_state_changed) {
 521       gen6_3DSTATE_SCISSOR_STATE_POINTERS(p->builder,
 522             p->state.SCISSOR_RECT);
 523    }
 524
 525    /* XXX what is the best way to know if this workaround is needed? */
 526    {
 527       const bool emit_3dstate_ps =
 528          (DIRTY(FS) || DIRTY(SAMPLER_FS) || DIRTY(BLEND));
 529       const bool emit_3dstate_depth_buffer =
 530          (DIRTY(FB) || DIRTY(DSA) || session->state_bo_changed);
 531
 532       if (emit_3dstate_ps ||
 533           emit_3dstate_depth_buffer ||
 534           session->pcb_state_fs_changed ||
 535           session->viewport_state_changed ||
 536           session->binding_table_fs_changed ||
 537           session->sampler_state_fs_changed ||
 538           session->cc_state_cc_changed ||
 539           session->cc_state_blend_changed ||
 540           session->cc_state_dsa_changed)
 541          gen7_wa_pipe_control_wm_depth_stall(p, emit_3dstate_depth_buffer);
 542    }
 543
 544    /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
 545    if (DIRTY(FB) || session->batch_bo_changed) {
 546       const struct ilo_zs_surface *zs;
 547       uint32_t clear_params;
 548
 549       if (vec->fb.state.zsbuf) {
 550          const struct ilo_surface_cso *surface =
 551             (const struct ilo_surface_cso *) vec->fb.state.zsbuf;
 552          const struct ilo_texture_slice *slice =
 553             ilo_texture_get_slice(ilo_texture(surface->base.texture),
 554                   surface->base.u.tex.level, surface->base.u.tex.first_layer);
 555
 556          assert(!surface->is_rt);
 557          zs = &surface->u.zs;
 558          clear_params = slice->clear_value;
 559       }
 560       else {
 561          zs = &vec->fb.null_zs;
 562          clear_params = 0;
 563       }
 564
 565       gen6_3DSTATE_DEPTH_BUFFER(p->builder, zs);
 566       gen6_3DSTATE_HIER_DEPTH_BUFFER(p->builder, zs);
 567       gen6_3DSTATE_STENCIL_BUFFER(p->builder, zs);
 568       gen7_3DSTATE_CLEAR_PARAMS(p->builder, clear_params);
 569    }
 570 }
 571
 572 static void
 573 gen7_pipeline_wm_multisample(struct ilo_3d_pipeline *p,
 574                              const struct ilo_state_vector *vec,
 575                              struct gen6_pipeline_session *session)
 576 {
 577    /* 3DSTATE_MULTISAMPLE and 3DSTATE_SAMPLE_MASK */
 578    if (DIRTY(SAMPLE_MASK) || DIRTY(FB)) {
 579       const uint32_t *packed_sample_pos;
 580
 581       gen7_wa_pipe_control_cs_stall(p, true, true);
 582
 583       packed_sample_pos =
 584          (vec->fb.num_samples > 4) ? p->packed_sample_position_8x :
 585          (vec->fb.num_samples > 1) ? &p->packed_sample_position_4x :
 586          &p->packed_sample_position_1x;
 587
 588       gen6_3DSTATE_MULTISAMPLE(p->builder,
 589             vec->fb.num_samples, packed_sample_pos,
 590             vec->rasterizer->state.half_pixel_center);
 591
 592       gen7_3DSTATE_SAMPLE_MASK(p->builder,
 593             (vec->fb.num_samples > 1) ? vec->sample_mask : 0x1,
 594             vec->fb.num_samples);
 595    }
 596 }
 597
 598 static void
 599 gen7_pipeline_vf_draw(struct ilo_3d_pipeline *p,
 600                       const struct ilo_state_vector *vec,
 601                       struct gen6_pipeline_session *session)
 602 {
 603    /* 3DPRIMITIVE */
 604    gen7_3DPRIMITIVE(p->builder, vec->draw, &vec->ib);
 605    p->state.has_gen6_wa_pipe_control = false;
 606 }
 607
 608 static void
 609 gen7_pipeline_commands(struct ilo_3d_pipeline *p,
 610                        const struct ilo_state_vector *vec,
 611                        struct gen6_pipeline_session *session)
 612 {
 613    /*
 614     * We try to keep the order of the commands match, as closely as possible,
 615     * that of the classic i965 driver.  It allows us to compare the command
 616     * streams easily.
 617     */
 618    gen6_pipeline_common_select(p, vec, session);
 619    gen6_pipeline_common_sip(p, vec, session);
 620    gen6_pipeline_vf_statistics(p, vec, session);
 621    gen7_pipeline_common_pcb_alloc(p, vec, session);
 622    gen6_pipeline_common_base_address(p, vec, session);
 623    gen7_pipeline_common_pointers_1(p, vec, session);
 624    gen7_pipeline_common_urb(p, vec, session);
 625    gen7_pipeline_common_pointers_2(p, vec, session);
 626    gen7_pipeline_wm_multisample(p, vec, session);
 627    gen7_pipeline_gs(p, vec, session);
 628    gen7_pipeline_hs(p, vec, session);
 629    gen7_pipeline_te(p, vec, session);
 630    gen7_pipeline_ds(p, vec, session);
 631    gen7_pipeline_vs(p, vec, session);
 632    gen7_pipeline_sol(p, vec, session);
 633    gen6_pipeline_clip(p, vec, session);
 634    gen7_pipeline_sf(p, vec, session);
 635    gen7_pipeline_wm(p, vec, session);
 636    gen6_pipeline_wm_raster(p, vec, session);
 637    gen6_pipeline_sf_rect(p, vec, session);
 638    gen6_pipeline_vf(p, vec, session);
 639    gen7_pipeline_vf_draw(p, vec, session);
 640 }
 641
 642 static void
 643 ilo_3d_pipeline_emit_draw_gen7(struct ilo_3d_pipeline *p,
 644                                const struct ilo_state_vector *vec)
 645 {
 646    struct gen6_pipeline_session session;
 647
 648    gen6_pipeline_prepare(p, vec, &session);
 649
 650    session.emit_draw_states = gen6_pipeline_states;
 651    session.emit_draw_commands = gen7_pipeline_commands;
 652
 653    gen6_pipeline_draw(p, vec, &session);
 654    gen6_pipeline_end(p, vec, &session);
 655 }
 656
 657 static void
 658 gen7_rectlist_pcb_alloc(struct ilo_3d_pipeline *p,
 659                         const struct ilo_blitter *blitter,
 660                         struct gen6_rectlist_session *session)
 661 {
 662    /*
 663     * Push constant buffers are only allowed to take up at most the first
 664     * 16KB of the URB.  Split the space evenly for VS and FS.
 665     */
 666    const int max_size =
 667       (ilo_dev_gen(p->dev) == ILO_GEN(7.5) && p->dev->gt == 3) ? 32768 : 16384;
 668    const int size = max_size / 2;
 669    int offset = 0;
 670
 671    gen7_3DSTATE_PUSH_CONSTANT_ALLOC_VS(p->builder, offset, size);
 672    offset += size;
 673
 674    gen7_3DSTATE_PUSH_CONSTANT_ALLOC_PS(p->builder, offset, size);
 675
 676    gen7_wa_pipe_control_cs_stall(p, true, true);
 677 }
 678
 679 static void
 680 gen7_rectlist_urb(struct ilo_3d_pipeline *p,
 681                   const struct ilo_blitter *blitter,
 682                   struct gen6_rectlist_session *session)
 683 {
 684    /* the first 16KB are reserved for VS and PS PCBs */
 685    const int offset =
 686       (ilo_dev_gen(p->dev) == ILO_GEN(7.5) && p->dev->gt == 3) ? 32768 : 16384;
 687
 688    gen7_3DSTATE_URB_VS(p->builder, offset, p->dev->urb_size - offset,
 689          blitter->ve.count * 4 * sizeof(float));
 690
 691    gen7_3DSTATE_URB_GS(p->builder, offset, 0, 0);
 692    gen7_3DSTATE_URB_HS(p->builder, offset, 0, 0);
 693    gen7_3DSTATE_URB_DS(p->builder, offset, 0, 0);
 694 }
 695
 696 static void
 697 gen7_rectlist_vs_to_sf(struct ilo_3d_pipeline *p,
 698                        const struct ilo_blitter *blitter,
 699                        struct gen6_rectlist_session *session)
 700 {
 701    gen7_3DSTATE_CONSTANT_VS(p->builder, NULL, NULL, 0);
 702    gen6_3DSTATE_VS(p->builder, NULL, 0);
 703
 704    gen7_3DSTATE_CONSTANT_HS(p->builder, NULL, NULL, 0);
 705    gen7_3DSTATE_HS(p->builder, NULL, 0);
 706
 707    gen7_3DSTATE_TE(p->builder);
 708
 709    gen7_3DSTATE_CONSTANT_DS(p->builder, NULL, NULL, 0);
 710    gen7_3DSTATE_DS(p->builder, NULL, 0);
 711
 712    gen7_3DSTATE_CONSTANT_GS(p->builder, NULL, NULL, 0);
 713    gen7_3DSTATE_GS(p->builder, NULL, 0);
 714
 715    gen7_3DSTATE_STREAMOUT(p->builder, 0x0, 0, false);
 716
 717    gen6_3DSTATE_CLIP(p->builder, NULL, NULL, false, 0);
 718
 719    gen7_wa_pipe_control_cs_stall(p, true, true);
 720
 721    gen7_3DSTATE_SF(p->builder, NULL, blitter->fb.dst.base.format);
 722    gen7_3DSTATE_SBE(p->builder, NULL, NULL);
 723 }
 724
 725 static void
 726 gen7_rectlist_wm(struct ilo_3d_pipeline *p,
 727                  const struct ilo_blitter *blitter,
 728                  struct gen6_rectlist_session *session)
 729 {
 730    uint32_t hiz_op;
 731
 732    switch (blitter->op) {
 733    case ILO_BLITTER_RECTLIST_CLEAR_ZS:
 734       hiz_op = GEN7_WM_DW1_DEPTH_CLEAR;
 735       break;
 736    case ILO_BLITTER_RECTLIST_RESOLVE_Z:
 737       hiz_op = GEN7_WM_DW1_DEPTH_RESOLVE;
 738       break;
 739    case ILO_BLITTER_RECTLIST_RESOLVE_HIZ:
 740       hiz_op = GEN7_WM_DW1_HIZ_RESOLVE;
 741       break;
 742    default:
 743       hiz_op = 0;
 744       break;
 745    }
 746
 747    gen7_3DSTATE_WM(p->builder, NULL, NULL, false, hiz_op);
 748
 749    gen7_3DSTATE_CONSTANT_PS(p->builder, NULL, NULL, 0);
 750
 751    gen7_wa_pipe_control_ps_max_threads_stall(p);
 752    gen7_3DSTATE_PS(p->builder, NULL, 0, false);
 753 }
 754
 755 static void
 756 gen7_rectlist_wm_depth(struct ilo_3d_pipeline *p,
 757                        const struct ilo_blitter *blitter,
 758                        struct gen6_rectlist_session *session)
 759 {
 760    gen7_wa_pipe_control_wm_depth_stall(p, true);
 761
 762    if (blitter->uses & (ILO_BLITTER_USE_FB_DEPTH |
 763                         ILO_BLITTER_USE_FB_STENCIL)) {
 764       gen6_3DSTATE_DEPTH_BUFFER(p->builder,
 765             &blitter->fb.dst.u.zs);
 766    }
 767
 768    if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH) {
 769       gen6_3DSTATE_HIER_DEPTH_BUFFER(p->builder,
 770             &blitter->fb.dst.u.zs);
 771    }
 772
 773    if (blitter->uses & ILO_BLITTER_USE_FB_STENCIL) {
 774       gen6_3DSTATE_STENCIL_BUFFER(p->builder,
 775             &blitter->fb.dst.u.zs);
 776    }
 777
 778    gen7_3DSTATE_CLEAR_PARAMS(p->builder,
 779          blitter->depth_clear_value);
 780 }
 781
 782 static void
 783 gen7_rectlist_wm_multisample(struct ilo_3d_pipeline *p,
 784                              const struct ilo_blitter *blitter,
 785                              struct gen6_rectlist_session *session)
 786 {
 787    const uint32_t *packed_sample_pos =
 788       (blitter->fb.num_samples > 4) ? p->packed_sample_position_8x :
 789       (blitter->fb.num_samples > 1) ? &p->packed_sample_position_4x :
 790       &p->packed_sample_position_1x;
 791
 792    gen7_wa_pipe_control_cs_stall(p, true, true);
 793
 794    gen6_3DSTATE_MULTISAMPLE(p->builder, blitter->fb.num_samples,
 795          packed_sample_pos, true);
 796
 797    gen7_3DSTATE_SAMPLE_MASK(p->builder,
 798          (1 << blitter->fb.num_samples) - 1, blitter->fb.num_samples);
 799 }
 800
 801 static void
 802 gen7_rectlist_commands(struct ilo_3d_pipeline *p,
 803                        const struct ilo_blitter *blitter,
 804                        struct gen6_rectlist_session *session)
 805 {
 806    gen7_rectlist_wm_multisample(p, blitter, session);
 807
 808    gen6_state_base_address(p->builder, true);
 809
 810    gen6_3DSTATE_VERTEX_BUFFERS(p->builder,
 811          &blitter->ve, &blitter->vb);
 812
 813    gen6_3DSTATE_VERTEX_ELEMENTS(p->builder,
 814          &blitter->ve, false, false);
 815
 816    gen7_rectlist_pcb_alloc(p, blitter, session);
 817
 818    /* needed for any VS-related commands */
 819    gen7_wa_pipe_control_vs_depth_stall(p);
 820
 821    gen7_rectlist_urb(p, blitter, session);
 822
 823    if (blitter->uses & ILO_BLITTER_USE_DSA) {
 824       gen7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS(p->builder,
 825             session->DEPTH_STENCIL_STATE);
 826    }
 827
 828    if (blitter->uses & ILO_BLITTER_USE_CC) {
 829       gen7_3DSTATE_CC_STATE_POINTERS(p->builder,
 830             session->COLOR_CALC_STATE);
 831    }
 832
 833    gen7_rectlist_vs_to_sf(p, blitter, session);
 834    gen7_rectlist_wm(p, blitter, session);
 835
 836    if (blitter->uses & ILO_BLITTER_USE_VIEWPORT) {
 837       gen7_3DSTATE_VIEWPORT_STATE_POINTERS_CC(p->builder,
 838             session->CC_VIEWPORT);
 839    }
 840
 841    gen7_rectlist_wm_depth(p, blitter, session);
 842
 843    gen6_3DSTATE_DRAWING_RECTANGLE(p->builder, 0, 0,
 844          blitter->fb.width, blitter->fb.height);
 845
 846    gen7_3DPRIMITIVE(p->builder, &blitter->draw, NULL);
 847 }
 848
 849 static void
 850 gen7_rectlist_states(struct ilo_3d_pipeline *p,
 851                      const struct ilo_blitter *blitter,
 852                      struct gen6_rectlist_session *session)
 853 {
 854    if (blitter->uses & ILO_BLITTER_USE_DSA) {
 855       session->DEPTH_STENCIL_STATE =
 856          gen6_DEPTH_STENCIL_STATE(p->builder, &blitter->dsa);
 857    }
 858
 859    if (blitter->uses & ILO_BLITTER_USE_CC) {
 860       session->COLOR_CALC_STATE =
 861          gen6_COLOR_CALC_STATE(p->builder, &blitter->cc.stencil_ref,
 862                blitter->cc.alpha_ref, &blitter->cc.blend_color);
 863    }
 864
 865    if (blitter->uses & ILO_BLITTER_USE_VIEWPORT) {
 866       session->CC_VIEWPORT =
 867          gen6_CC_VIEWPORT(p->builder, &blitter->viewport, 1);
 868    }
 869 }
 870
 871 static void
 872 ilo_3d_pipeline_emit_rectlist_gen7(struct ilo_3d_pipeline *p,
 873                                    const struct ilo_blitter *blitter)
 874 {
 875    struct gen6_rectlist_session session;
 876
 877    memset(&session, 0, sizeof(session));
 878    gen7_rectlist_states(p, blitter, &session);
 879    gen7_rectlist_commands(p, blitter, &session);
 880 }
 881
 882 static int
 883 gen7_pipeline_max_command_size(const struct ilo_3d_pipeline *p)
 884 {
 885    static int size;
 886
 887    if (!size) {
 888       size += GEN7_3DSTATE_URB_ANY__SIZE * 4;
 889       size += GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE * 5;
 890       size += GEN6_3DSTATE_CONSTANT_ANY__SIZE * 5;
 891       size += GEN7_3DSTATE_POINTERS_ANY__SIZE * (5 + 5 + 4);
 892       size += GEN7_3DSTATE_SO_BUFFER__SIZE * 4;
 893       size += GEN6_PIPE_CONTROL__SIZE * 5;
 894
 895       size +=
 896          GEN6_STATE_BASE_ADDRESS__SIZE +
 897          GEN6_STATE_SIP__SIZE +
 898          GEN6_3DSTATE_VF_STATISTICS__SIZE +
 899          GEN6_PIPELINE_SELECT__SIZE +
 900          GEN6_3DSTATE_CLEAR_PARAMS__SIZE +
 901          GEN6_3DSTATE_DEPTH_BUFFER__SIZE +
 902          GEN6_3DSTATE_STENCIL_BUFFER__SIZE +
 903          GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE +
 904          GEN6_3DSTATE_VERTEX_BUFFERS__SIZE +
 905          GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE +
 906          GEN6_3DSTATE_INDEX_BUFFER__SIZE +
 907          GEN75_3DSTATE_VF__SIZE +
 908          GEN6_3DSTATE_VS__SIZE +
 909          GEN6_3DSTATE_GS__SIZE +
 910          GEN6_3DSTATE_CLIP__SIZE +
 911          GEN6_3DSTATE_SF__SIZE +
 912          GEN6_3DSTATE_WM__SIZE +
 913          GEN6_3DSTATE_SAMPLE_MASK__SIZE +
 914          GEN7_3DSTATE_HS__SIZE +
 915          GEN7_3DSTATE_TE__SIZE +
 916          GEN7_3DSTATE_DS__SIZE +
 917          GEN7_3DSTATE_STREAMOUT__SIZE +
 918          GEN7_3DSTATE_SBE__SIZE +
 919          GEN7_3DSTATE_PS__SIZE +
 920          GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE +
 921          GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE +
 922          GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE +
 923          GEN6_3DSTATE_LINE_STIPPLE__SIZE +
 924          GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE +
 925          GEN6_3DSTATE_MULTISAMPLE__SIZE +
 926          GEN7_3DSTATE_SO_DECL_LIST__SIZE +
 927          GEN6_3DPRIMITIVE__SIZE;
 928    }
 929
 930    return size;
 931 }
 932
 933 static int
 934 ilo_3d_pipeline_estimate_size_gen7(struct ilo_3d_pipeline *p,
 935                                    enum ilo_3d_pipeline_action action,
 936                                    const void *arg)
 937 {
 938    int size;
 939
 940    switch (action) {
 941    case ILO_3D_PIPELINE_DRAW:
 942       {
 943          const struct ilo_state_vector *ilo = arg;
 944
 945          size = gen7_pipeline_max_command_size(p) +
 946             gen6_pipeline_estimate_state_size(p, ilo);
 947       }
 948       break;
 949    case ILO_3D_PIPELINE_FLUSH:
 950    case ILO_3D_PIPELINE_WRITE_TIMESTAMP:
 951    case ILO_3D_PIPELINE_WRITE_DEPTH_COUNT:
 952       size = GEN6_PIPE_CONTROL__SIZE;
 953       break;
 954    case ILO_3D_PIPELINE_WRITE_STATISTICS:
 955       {
 956          const int num_regs = 10;
 957          const int num_pads = 1;
 958
 959          size = GEN6_PIPE_CONTROL__SIZE;
 960          size += GEN6_MI_STORE_REGISTER_MEM__SIZE * 2 * num_regs;
 961          size += GEN6_MI_STORE_DATA_IMM__SIZE * num_pads;
 962       }
 963       break;
 964    case ILO_3D_PIPELINE_RECTLIST:
 965       size = 64 + 256; /* states + commands */
 966       break;
 967    default:
 968       assert(!"unknown 3D pipeline action");
 969       size = 0;
 970       break;
 971    }
 972
 973    return size;
 974 }
 975
 976 void
 977 ilo_3d_pipeline_init_gen7(struct ilo_3d_pipeline *p)
 978 {
 979    p->estimate_size = ilo_3d_pipeline_estimate_size_gen7;
 980    p->emit_draw = ilo_3d_pipeline_emit_draw_gen7;
 981    p->emit_flush = ilo_3d_pipeline_emit_flush_gen6;
 982    p->emit_write_timestamp = ilo_3d_pipeline_emit_write_timestamp_gen6;
 983    p->emit_write_depth_count = ilo_3d_pipeline_emit_write_depth_count_gen6;
 984    p->emit_write_statistics = ilo_3d_pipeline_emit_write_statistics_gen6;
 985    p->emit_rectlist = ilo_3d_pipeline_emit_rectlist_gen7;
 986 }