2 * Mesa 3-D graphics library
4 * Copyright (C) 2012-2013 LunarG, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Chia-I Wu <olv@lunarg.com>
28 #include "util/u_format_s3tc.h"
29 #include "vl/vl_decoder.h"
30 #include "vl/vl_video_buffer.h"
31 #include "intel_chipset.h"
32 #include "intel_reg.h" /* for TIMESTAMP */
33 #include "intel_winsys.h"
35 #include "ilo_context.h"
36 #include "ilo_format.h"
37 #include "ilo_resource.h"
38 #include "ilo_public.h"
39 #include "ilo_screen.h"
43 static const struct debug_named_value ilo_debug_flags[] = {
44 { "3d", ILO_DEBUG_3D, "Dump 3D commands and states" },
45 { "vs", ILO_DEBUG_VS, "Dump vertex shaders" },
46 { "gs", ILO_DEBUG_GS, "Dump geometry shaders" },
47 { "fs", ILO_DEBUG_FS, "Dump fragment shaders" },
48 { "cs", ILO_DEBUG_CS, "Dump compute shaders" },
49 { "nohw", ILO_DEBUG_NOHW, "Do not send commands to HW" },
50 { "nocache", ILO_DEBUG_NOCACHE, "Always invalidate HW caches" },
55 ilo_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
58 case PIPE_CAPF_MAX_LINE_WIDTH:
59 /* in U3.7, defined in 3DSTATE_SF */
61 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
62 /* line width minus one, which is reserved for AA region */
64 case PIPE_CAPF_MAX_POINT_WIDTH:
65 /* in U8.3, defined in 3DSTATE_SF */
67 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
68 /* same as point width, as we ignore rasterizer->point_smooth */
70 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
71 /* [2.0, 16.0], defined in SAMPLER_STATE */
73 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
74 /* [-16.0, 16.0), defined in SAMPLER_STATE */
76 case PIPE_CAPF_GUARD_BAND_LEFT:
77 case PIPE_CAPF_GUARD_BAND_TOP:
78 case PIPE_CAPF_GUARD_BAND_RIGHT:
79 case PIPE_CAPF_GUARD_BAND_BOTTOM:
80 /* what are these for? */
89 ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
90 enum pipe_shader_cap param)
93 case PIPE_SHADER_FRAGMENT:
94 case PIPE_SHADER_VERTEX:
95 case PIPE_SHADER_GEOMETRY:
102 /* the limits are copied from the classic driver */
103 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
104 return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 16384;
105 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
106 return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
107 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
108 return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
109 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
110 return (shader == PIPE_SHADER_FRAGMENT) ? 1024 : 0;
111 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
113 case PIPE_SHADER_CAP_MAX_INPUTS:
114 /* this is limited by how many attributes SF can remap */
116 case PIPE_SHADER_CAP_MAX_CONSTS:
118 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
119 return ILO_MAX_CONST_BUFFERS;
120 case PIPE_SHADER_CAP_MAX_TEMPS:
122 case PIPE_SHADER_CAP_MAX_ADDRS:
123 return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
124 case PIPE_SHADER_CAP_MAX_PREDS:
126 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
128 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
130 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
132 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
133 return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
134 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
135 return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
136 case PIPE_SHADER_CAP_SUBROUTINES:
138 case PIPE_SHADER_CAP_INTEGERS:
140 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
141 return ILO_MAX_SAMPLERS;
142 case PIPE_SHADER_CAP_PREFERRED_IR:
143 return PIPE_SHADER_IR_TGSI;
144 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
153 ilo_get_video_param(struct pipe_screen *screen,
154 enum pipe_video_profile profile,
155 enum pipe_video_cap param)
158 case PIPE_VIDEO_CAP_SUPPORTED:
159 return vl_profile_supported(screen, profile);
160 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
162 case PIPE_VIDEO_CAP_MAX_WIDTH:
163 case PIPE_VIDEO_CAP_MAX_HEIGHT:
164 return vl_video_buffer_max_size(screen);
165 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
166 return PIPE_FORMAT_NV12;
167 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
169 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
171 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
180 ilo_get_compute_param(struct pipe_screen *screen,
181 enum pipe_compute_cap param,
185 const char *ir_target;
186 uint64_t grid_dimension;
187 uint64_t max_grid_size[3];
188 uint64_t max_block_size[3];
189 uint64_t max_threads_per_block;
190 uint64_t max_global_size;
191 uint64_t max_local_size;
192 uint64_t max_private_size;
193 uint64_t max_input_size;
194 uint64_t max_mem_alloc_size;
199 /* XXX some randomly chosen values */
201 case PIPE_COMPUTE_CAP_IR_TARGET:
202 val.ir_target = "ilog";
205 size = strlen(val.ir_target) + 1;
207 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
208 val.grid_dimension = Elements(val.max_grid_size);
210 ptr = &val.grid_dimension;
211 size = sizeof(val.grid_dimension);
213 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
214 val.max_grid_size[0] = 65535;
215 val.max_grid_size[1] = 65535;
216 val.max_grid_size[2] = 1;
218 ptr = &val.max_grid_size;
219 size = sizeof(val.max_grid_size);
221 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
222 val.max_block_size[0] = 512;
223 val.max_block_size[1] = 512;
224 val.max_block_size[2] = 512;
226 ptr = &val.max_block_size;
227 size = sizeof(val.max_block_size);
230 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
231 val.max_threads_per_block = 512;
233 ptr = &val.max_threads_per_block;
234 size = sizeof(val.max_threads_per_block);
236 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
237 val.max_global_size = 4;
239 ptr = &val.max_global_size;
240 size = sizeof(val.max_global_size);
242 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
243 val.max_local_size = 64 * 1024;
245 ptr = &val.max_local_size;
246 size = sizeof(val.max_local_size);
248 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
249 val.max_private_size = 32768;
251 ptr = &val.max_private_size;
252 size = sizeof(val.max_private_size);
254 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
255 val.max_input_size = 256;
257 ptr = &val.max_input_size;
258 size = sizeof(val.max_input_size);
260 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
261 val.max_mem_alloc_size = 128 * 1024 * 1024;
263 ptr = &val.max_mem_alloc_size;
264 size = sizeof(val.max_mem_alloc_size);
273 memcpy(ret, ptr, size);
279 ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
281 struct ilo_screen *is = ilo_screen(screen);
284 case PIPE_CAP_NPOT_TEXTURES:
285 case PIPE_CAP_TWO_SIDED_STENCIL:
287 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
289 case PIPE_CAP_ANISOTROPIC_FILTER:
290 case PIPE_CAP_POINT_SPRITE:
292 case PIPE_CAP_MAX_RENDER_TARGETS:
293 return ILO_MAX_DRAW_BUFFERS;
294 case PIPE_CAP_OCCLUSION_QUERY:
295 case PIPE_CAP_QUERY_TIME_ELAPSED:
296 case PIPE_CAP_TEXTURE_SHADOW_MAP:
297 case PIPE_CAP_TEXTURE_SWIZZLE: /* must be supported for shadow map */
299 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
301 * As defined in SURFACE_STATE, we have
303 * Max WxHxD for 2D and CUBE Max WxHxD for 3D
304 * GEN6 8192x8192x512 2048x2048x2048
305 * GEN7 16384x16384x2048 2048x2048x2048
307 * However, when the texutre size is large, things become unstable. We
308 * require the maximum texture size to be 2^30 bytes in
309 * screen->can_create_resource(). Since the maximum pixel size is 2^4
310 * bytes (PIPE_FORMAT_R32G32B32A32_FLOAT), textures should not have more
313 * For 3D textures, we have to set the maximum number of levels to 9,
314 * which has at most 2^24 pixels. For 2D textures, we set it to 14,
315 * which has at most 2^26 pixels.
318 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
320 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
322 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
324 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
327 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
328 if (is->dev.gen >= ILO_GEN(7) && !is->dev.has_gen7_sol_reset)
330 return ILO_MAX_SO_BUFFERS;
331 case PIPE_CAP_PRIMITIVE_RESTART:
332 return false; /* TODO */
333 case PIPE_CAP_MAX_COMBINED_SAMPLERS:
334 return ILO_MAX_SAMPLERS * 2;
335 case PIPE_CAP_INDEP_BLEND_ENABLE:
336 case PIPE_CAP_INDEP_BLEND_FUNC:
338 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
339 return (is->dev.gen >= ILO_GEN(7)) ? 2048 : 512;
340 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
341 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
342 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
343 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
344 case PIPE_CAP_DEPTH_CLIP_DISABLE:
346 case PIPE_CAP_SHADER_STENCIL_EXPORT:
348 case PIPE_CAP_TGSI_INSTANCEID:
349 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
350 return false; /* TODO */
351 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
353 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
355 case PIPE_CAP_SEAMLESS_CUBE_MAP:
356 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
357 case PIPE_CAP_SCALED_RESOLVE:
359 case PIPE_CAP_MIN_TEXEL_OFFSET:
361 case PIPE_CAP_MAX_TEXEL_OFFSET:
363 case PIPE_CAP_CONDITIONAL_RENDER:
364 case PIPE_CAP_TEXTURE_BARRIER:
366 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
367 return ILO_MAX_SO_BINDINGS / ILO_MAX_SO_BUFFERS;
368 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
369 return ILO_MAX_SO_BINDINGS;
370 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
371 if (is->dev.gen >= ILO_GEN(7))
372 return is->dev.has_gen7_sol_reset;
374 return false; /* TODO */
375 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
376 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
378 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
380 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
382 case PIPE_CAP_GLSL_FEATURE_LEVEL:
384 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
385 case PIPE_CAP_USER_VERTEX_BUFFERS:
387 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
388 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
389 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
391 case PIPE_CAP_COMPUTE:
392 return false; /* TODO */
393 case PIPE_CAP_USER_INDEX_BUFFERS:
395 case PIPE_CAP_USER_CONSTANT_BUFFERS:
396 return false; /* TODO push constants */
397 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
399 case PIPE_CAP_START_INSTANCE:
400 case PIPE_CAP_QUERY_TIMESTAMP:
402 case PIPE_CAP_TEXTURE_MULTISAMPLE:
403 return false; /* TODO */
404 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
406 case PIPE_CAP_CUBE_MAP_ARRAY:
407 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
408 return false; /* TODO */
409 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
411 case PIPE_CAP_TGSI_TEXCOORD:
413 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
415 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
416 return false; /* TODO */
417 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
426 ilo_get_vendor(struct pipe_screen *screen)
428 return "LunarG, Inc.";
432 ilo_get_name(struct pipe_screen *screen)
434 struct ilo_screen *is = ilo_screen(screen);
437 /* stolen from classic i965 */
438 switch (is->dev.devid) {
439 case PCI_CHIP_SANDYBRIDGE_GT1:
440 case PCI_CHIP_SANDYBRIDGE_GT2:
441 case PCI_CHIP_SANDYBRIDGE_GT2_PLUS:
442 chipset = "Intel(R) Sandybridge Desktop";
444 case PCI_CHIP_SANDYBRIDGE_M_GT1:
445 case PCI_CHIP_SANDYBRIDGE_M_GT2:
446 case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS:
447 chipset = "Intel(R) Sandybridge Mobile";
449 case PCI_CHIP_SANDYBRIDGE_S:
450 chipset = "Intel(R) Sandybridge Server";
452 case PCI_CHIP_IVYBRIDGE_GT1:
453 case PCI_CHIP_IVYBRIDGE_GT2:
454 chipset = "Intel(R) Ivybridge Desktop";
456 case PCI_CHIP_IVYBRIDGE_M_GT1:
457 case PCI_CHIP_IVYBRIDGE_M_GT2:
458 chipset = "Intel(R) Ivybridge Mobile";
460 case PCI_CHIP_IVYBRIDGE_S_GT1:
461 case PCI_CHIP_IVYBRIDGE_S_GT2:
462 chipset = "Intel(R) Ivybridge Server";
464 case PCI_CHIP_BAYTRAIL_M_1:
465 case PCI_CHIP_BAYTRAIL_M_2:
466 case PCI_CHIP_BAYTRAIL_M_3:
467 case PCI_CHIP_BAYTRAIL_M_4:
468 case PCI_CHIP_BAYTRAIL_D:
469 chipset = "Intel(R) Bay Trail";
471 case PCI_CHIP_HASWELL_GT1:
472 case PCI_CHIP_HASWELL_GT2:
473 case PCI_CHIP_HASWELL_GT2_PLUS:
474 case PCI_CHIP_HASWELL_SDV_GT1:
475 case PCI_CHIP_HASWELL_SDV_GT2:
476 case PCI_CHIP_HASWELL_SDV_GT2_PLUS:
477 case PCI_CHIP_HASWELL_ULT_GT1:
478 case PCI_CHIP_HASWELL_ULT_GT2:
479 case PCI_CHIP_HASWELL_ULT_GT2_PLUS:
480 case PCI_CHIP_HASWELL_CRW_GT1:
481 case PCI_CHIP_HASWELL_CRW_GT2:
482 case PCI_CHIP_HASWELL_CRW_GT2_PLUS:
483 chipset = "Intel(R) Haswell Desktop";
485 case PCI_CHIP_HASWELL_M_GT1:
486 case PCI_CHIP_HASWELL_M_GT2:
487 case PCI_CHIP_HASWELL_M_GT2_PLUS:
488 case PCI_CHIP_HASWELL_SDV_M_GT1:
489 case PCI_CHIP_HASWELL_SDV_M_GT2:
490 case PCI_CHIP_HASWELL_SDV_M_GT2_PLUS:
491 case PCI_CHIP_HASWELL_ULT_M_GT1:
492 case PCI_CHIP_HASWELL_ULT_M_GT2:
493 case PCI_CHIP_HASWELL_ULT_M_GT2_PLUS:
494 case PCI_CHIP_HASWELL_CRW_M_GT1:
495 case PCI_CHIP_HASWELL_CRW_M_GT2:
496 case PCI_CHIP_HASWELL_CRW_M_GT2_PLUS:
497 chipset = "Intel(R) Haswell Mobile";
499 case PCI_CHIP_HASWELL_S_GT1:
500 case PCI_CHIP_HASWELL_S_GT2:
501 case PCI_CHIP_HASWELL_S_GT2_PLUS:
502 case PCI_CHIP_HASWELL_SDV_S_GT1:
503 case PCI_CHIP_HASWELL_SDV_S_GT2:
504 case PCI_CHIP_HASWELL_SDV_S_GT2_PLUS:
505 case PCI_CHIP_HASWELL_ULT_S_GT1:
506 case PCI_CHIP_HASWELL_ULT_S_GT2:
507 case PCI_CHIP_HASWELL_ULT_S_GT2_PLUS:
508 case PCI_CHIP_HASWELL_CRW_S_GT1:
509 case PCI_CHIP_HASWELL_CRW_S_GT2:
510 case PCI_CHIP_HASWELL_CRW_S_GT2_PLUS:
511 chipset = "Intel(R) Haswell Server";
514 chipset = "Unknown Intel Chipset";
522 ilo_get_timestamp(struct pipe_screen *screen)
524 struct ilo_screen *is = ilo_screen(screen);
530 is->winsys->read_reg(is->winsys, TIMESTAMP, ×tamp.val);
533 * From the Ivy Bridge PRM, volume 1 part 3, page 107:
535 * "Note: This timestamp register reflects the value of the PCU TSC.
536 * The PCU TSC counts 10ns increments; this timestamp reflects bits
537 * 38:3 of the TSC (i.e. 80ns granularity, rolling over every 1.5
540 * However, it seems dw[0] is garbage and dw[1] contains the lower 32 bits
541 * of the timestamp. We will have to live with a timestamp that rolls over
542 * every ~343 seconds.
544 * See also brw_get_timestamp().
546 return (uint64_t) timestamp.dw[1] * 80;
550 ilo_fence_reference(struct pipe_screen *screen,
551 struct pipe_fence_handle **p,
552 struct pipe_fence_handle *f)
554 struct ilo_fence **ptr = (struct ilo_fence **) p;
555 struct ilo_fence *fence = ilo_fence(f);
558 /* still need to reference fence */
560 pipe_reference(NULL, &fence->reference);
564 /* reference fence and dereference the one pointed to by ptr */
565 if (*ptr && pipe_reference(&(*ptr)->reference, &fence->reference)) {
566 struct ilo_fence *old = *ptr;
569 old->bo->unreference(old->bo);
577 ilo_fence_signalled(struct pipe_screen *screen,
578 struct pipe_fence_handle *f)
580 struct ilo_fence *fence = ilo_fence(f);
582 /* mark signalled if the bo is idle */
583 if (fence->bo && !intel_bo_is_busy(fence->bo)) {
584 fence->bo->unreference(fence->bo);
588 return (fence->bo == NULL);
592 ilo_fence_finish(struct pipe_screen *screen,
593 struct pipe_fence_handle *f,
596 struct ilo_fence *fence = ilo_fence(f);
597 const int64_t wait_timeout = (timeout > INT64_MAX) ? -1 : timeout;
599 /* already signalled */
603 /* wait and see if it returns error */
604 if (fence->bo->wait(fence->bo, wait_timeout))
608 fence->bo->unreference(fence->bo);
615 ilo_screen_destroy(struct pipe_screen *screen)
617 struct ilo_screen *is = ilo_screen(screen);
619 /* as it seems, winsys is owned by the screen */
620 is->winsys->destroy(is->winsys);
626 init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
628 dev->devid = info->devid;
629 dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
630 dev->has_llc = info->has_llc;
633 * From the Sandy Bridge PRM, volume 4 part 2, page 18:
635 * "[DevSNB]: The GT1 product's URB provides 32KB of storage, arranged
636 * as 1024 256-bit rows. The GT2 product's URB provides 64KB of
637 * storage, arranged as 2048 256-bit rows. A row corresponds in size
638 * to an EU GRF register. Read/write access to the URB is generally
639 * supported on a row-granular basis."
641 * From the Ivy Bridge PRM, volume 4 part 2, page 17:
643 * "URB Size URB Rows URB Rows when SLM Enabled
648 if (IS_HASWELL(info->devid)) {
649 dev->gen = ILO_GEN(7.5);
651 if (IS_HSW_GT2(info->devid)) {
653 dev->urb_size = 256 * 1024;
657 dev->urb_size = 128 * 1024;
660 else if (IS_GEN7(info->devid)) {
661 dev->gen = ILO_GEN(7);
663 if (IS_IVB_GT2(info->devid)) {
665 dev->urb_size = 256 * 1024;
669 dev->urb_size = 128 * 1024;
672 else if (IS_GEN6(info->devid)) {
673 dev->gen = ILO_GEN(6);
675 if (IS_SNB_GT2(info->devid)) {
677 dev->urb_size = 64 * 1024;
681 dev->urb_size = 32 * 1024;
685 ilo_err("unknown GPU generation\n");
693 ilo_screen_create(struct intel_winsys *ws)
695 struct ilo_screen *is;
696 const struct intel_winsys_info *info;
698 ilo_debug = debug_get_flags_option("ILO_DEBUG", ilo_debug_flags, 0);
700 is = CALLOC_STRUCT(ilo_screen);
706 info = is->winsys->get_info(is->winsys);
707 if (!init_dev(&is->dev, info)) {
712 util_format_s3tc_init();
714 is->base.destroy = ilo_screen_destroy;
715 is->base.get_name = ilo_get_name;
716 is->base.get_vendor = ilo_get_vendor;
717 is->base.get_param = ilo_get_param;
718 is->base.get_paramf = ilo_get_paramf;
719 is->base.get_shader_param = ilo_get_shader_param;
720 is->base.get_video_param = ilo_get_video_param;
721 is->base.get_compute_param = ilo_get_compute_param;
723 is->base.get_timestamp = ilo_get_timestamp;
725 is->base.flush_frontbuffer = NULL;
727 is->base.fence_reference = ilo_fence_reference;
728 is->base.fence_signalled = ilo_fence_signalled;
729 is->base.fence_finish = ilo_fence_finish;
731 is->base.get_driver_query_info = NULL;
733 ilo_init_format_functions(is);
734 ilo_init_context_functions(is);
735 ilo_init_resource_functions(is);